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| september 2013 doc id 023520 rev 2 1/87 UM1556 user manual vipower m0-5 and m0-5enhanced high-side drivers introduction the aim of this document is to give the design engineer a comprehensive ?tool kit? to better understand the behavior of vipower high side switches, allowing easier design and saving time and money. today?s vipower high side switches represent the 5th generation of smart power drivers (the so called m0-5). in this latest generation of drivers, all the experience and know-how derived from previous generations have been implemented in order to improve robustness, increase functionality and raise package density while maintaining lower prices. the complexity of a modern high side driver (hsd) is still relatively low compared to many other logic ics. however, the combination of digital logic functions with analog power structures supplied by an unstabilized automotive battery system across a wide temperature range is very challenging for such a device. the m0-5 components today meet all the above criteria, providing an optimal price/performance ratio by offering the highest performance and robustness at excellent prices. www.st.com
contents UM1556 2/87 doc id 023520 rev 2 contents 1 general items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 application schematic (monolithic digital, monolithic and hybrid analogue hsd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.1 reverse battery protection of monolithic hsds . . . . . . . . . . . . . . . . . . . . 9 1.2.2 reverse battery protection of hybrid hsds . . . . . . . . . . . . . . . . . . . . . . 15 1.3 microcontroller protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 introduction of m0-5enhanced products . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4.1 new features overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.2 open load in off-state/short to vbat . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4.3 indication of power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4.4 indication of power limitation ? example for analogue driver . . . . . . . . . 19 1.4.5 indication of power limitation ? example for digital driver . . . . . . . . . . . 20 1.4.6 m0-5enhanced: analogue current sense truth table . . . . . . . . . . . . . . . 21 1.4.7 indication of power limitation, the advantages . . . . . . . . . . . . . . . . . . . . 22 2 analogue current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2 simplified principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3 normal operation (channel on, cs_dis low) . . . . . . . . . . . . . . . . . . . . . 24 2.4 overtemperature indication (channel on, cs_dis low) . . . . . . . . . . . . . 27 2.5 current sense esd and spikes protection . . . . . . . . . . . . . . . . . . . . . . . . 27 2.6 current sense resistor calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.7 diagnostics with different load configurations . . . . . . . . . . . . . . . . . . . . . 29 2.7.1 diagnostics with paralleled loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.7.2 diagnostics with different load options . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.7.3 k-factor calibration method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.8 analogue current sense diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.9 open load detection in off-state ? external circuitry for analogue m0-5 hsd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.10 open load detection in off-state ? m0-5enhanced hsd . . . . . . . . . . . . . 36 3 digital status output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 UM1556 contents doc id 023520 rev 2 3/87 3.1 digital hsd diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4 switching inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.1 turn-on phase behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2 turn-off phase behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2.1 calculation of energy dissipated in the hsd . . . . . . . . . . . . . . . . . . . . . 41 4.2.2 calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3 proper hsd selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.1 example of vnd5e160aj driving relays . . . . . . . . . . . . . . . . . . . . . . . . 44 4.4 external clamping selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.4.1 clamping circuitry examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.4.2 component selection guide for external transil-diode clamping . . . . . . 52 4.4.3 examples of vn5e025aj for dc motor driving with external clamp) . . 56 5 high side driver selection for lamp loads . . . . . . . . . . . . . . . . . . . . . . 66 6 paralleling of hsds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1 paralleling of cs_dis (current sense disable) and in (input) . . . . . . . . . 72 6.1.1 monolithic hsds supplied from different supply lines . . . . . . . . . . . . . . 72 6.1.2 hybrid hsds supplied from different supply lines . . . . . . . . . . . . . . . . . 73 6.1.3 mix of monolithic and hybrid hsds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.2 paralleling of cs pins (current sense) . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.2.1 monolithic hsds supplied from different supply lines . . . . . . . . . . . . . . 76 6.2.2 hybrid hsds supplied from different supply lines . . . . . . . . . . . . . . . . . 77 6.2.3 mix of monolithic and hybrid hsds supplied from different supply lines 78 7 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.1 esd protection of hsd ? calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.2 esd protection ? ecu level (layout consideration) . . . . . . . . . . . . . . . . . 84 8 robust design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.1 design suggestions for hsds and relays on the same pcb . . . . . . . . . . 85 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 list of tables UM1556 4/87 doc id 023520 rev 2 list of tables table 1. datasheet values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. reverse battery protection (of monolithic hsds only) ? comparison . . . . . . . . . . . . . . . . . 14 table 3. cs pin levels in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4. analogue driver-truth table (off-state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 5. analogue driver-truth table (on-state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. paralleling bulbs ? overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. v sense measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8. analogue hsd diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9. digital hsd diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 10. external clamping circuitry examples (1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 11. external clamping circuitry examples (2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 12. list of suggested bulb/driver combinations(1/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 13. list of suggested bulb/driver combinations(2/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 14. list of suggested bulb/driver combinations(3/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 15. list of suggested bulb/driver combinations(4/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 16. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 UM1556 list of figures doc id 023520 rev 2 5/87 list of figures figure 1. monolithic digital hsd - application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. monolithic analogue hsd - application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. hybrid analogue hsd ? application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. voltage levels during reverse battery ? resistor protection . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. logical levels check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. voltage levels during reverse battery using diode-resistor protection network. . . . . . . . . . 12 figure 7. positive iso pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. negative iso pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. voltage levels during reverse battery ? mosfet protection . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. hybrid hsd - reverse battery protection with self switch-on of the mosfet. . . . . . . . . . . 16 figure 11. example - self switch-on of mosfet eliminated by dgnd. . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. iso-pulse transfer to i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. open load/short to vcc condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14. open load/short to vcc condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15. m0-5 ? ?soft? short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. m0-5 ? ?hard? short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17. m0-5enhanced ? ?soft? short to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 figure 18. m0-5enhanced ? ?hard? short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 19. m0-5 ? ?soft? short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 20. m0-5 ? ?hard? short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 21. m0-5enhanced ? ?soft? short to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 figure 22. m0-5enhanced ? ?hard? short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 23. system reaction time comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 24. m0-5 high side driver with analogue current sense ? block diagram . . . . . . . . . . . . . . . . 23 figure 25. m0-5 current sense simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 26. v sense vs i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 27. v sense vs v out @ i out =i limh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 28. current sense resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 29. switchable current sense resistor ? example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 30. v sense measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 31. vnd5012a current sense voltage behavior ? hard short to gnd occurred (20 m ), thermal shutdown was reached 344 ms after short-circuit to gnd . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 32. analogue hsd ? circuit for open load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . 36 figure 33. analogue hsd ? open load detection in off-state (m0-5enhanced) . . . . . . . . . . . . . . . . . 36 figure 34. digital hsd diagnostics ? timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 figure 35. inductive load ? hsd turn-on phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 36. inductive load ? turn-on example: vnq5e050ak, l=260 mh, r=81 . . . . . . . . . . . . . . . 40 figure 37. inductive load ? hsd turn-off phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 38. inductive load ? turn off example: vnq5e050ak, l=260 mh, r=81 . . . . . . . . . . . . . . . 43 figure 39. maximum turn-off current versus inductance ? vnd5e160aj datasheet. . . . . . . . . . . . . . 46 figure 40. maximum demagnetization energy ? vnd5e160a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 41. demagnetization energy measurement ? vnd5e160aj, relay 260 mh . . . . . . . . . . . . . . 47 figure 42. external clamping - transil and diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 43. transil ? v/a characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 44. peak pulse power vs pulse time (for transil 600 w@10/1000 s series) . . . . . . . . . . . . . . 54 figure 45. equivalent pulses giving the same power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 46. maximum peak power as a function of initial temperature of the transil . . . . . . . . . . . . . . . 54 figure 47. maximum turn-off current versus inductance ? vn5e025aj datasheet . . . . . . . . . . . . . . . 57 list of figures UM1556 6/87 doc id 023520 rev 2 figure 48. external clamping circuitry ? border conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 49. energy sharing between hsd and external clamping circuitry . . . . . . . . . . . . . . . . . . . . . . 59 figure 50. appropriate protection circuitry for vn5e025a with dc motor . . . . . . . . . . . . . . . . . . . . . . 61 figure 51. demagnetization energy measurement ? vnd5e025ak, motor, smbj16a and 1n4002 . 63 figure 52. demagnetization phase ? vnd5e025ak, dc motor (blocked), freewheeling diode 1n5401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 53. repetitive demagnetization ? vnd5e025ak (tsd cycling), dc motor, 1n5401 . . . . . . . . 64 figure 54. principle of the setup used for the simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 55. direct connection of cs_dis pins (not recommended) ? monolithic hsd . . . . . . . . . . . . . 72 figure 56. proper connection of cs_dis pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 57. direct connection of cs_dis pins (not recommended) ? hybrid hsd . . . . . . . . . . . . . . . . 74 figure 58. direct connection of cs_dis pins (not recommended) ? mix of monolithic and hybrid hsd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 59. direct connection of cs pins (not recommended) ? monolithic hsd . . . . . . . . . . . . . . . . . 76 figure 60. safe solution for paralleling cs pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 61. direct connection of cs pins (not recommended) ? hybrid hsd . . . . . . . . . . . . . . . . . . . . 78 figure 62. direct connection of cs pins (not recommended) ? mix of monolithic and hybrid hsd . . . 79 UM1556 general items doc id 023520 rev 2 7/87 1 general items 1.1 application schematic (monolithic digital, monolithic and hybrid analogue hsd) figure 1. monolithic digital hs d - application schematic 1. if status disable function is not required, st_d is pin should be left open or connected to ground through a resistor (~10 k ). direct connection to ground is not safe (iso pulses clamped through st_dis pin can damage the device). 2. pull-up r5 is optional (for open load detection in off-state). 3. no pull-down resistors are necessary on in and st_d is pins due to the internal pull-down structure. 5 j q g n ' j q g * 1 ' 5 n 5 n 5 n 5 n 9 e d w * 1 ' 2 8 7 3 8 7 * 1 ' , 1 / r j l f 2 8 7 6 7 6 7 b ' , 6 * 1 ' 9 f f 8 9 9 g g * 1 ' r x w r x w l q 8 0 l f u r f r q w u r o o h u * 1 ' 9 * 1 ' 5 n 9 e d w b v z l w f k h g & q ) & q ) 9 & q ) 9 2 s w l r q d o 6 h h 1 r w h ' ! 0 ' - 3 general items UM1556 8/87 doc id 023520 rev 2 figure 2. monolithic analogue hsd - application schematic figure 3. hybrid analogue hsd ? application schematic 4. if current sense disable function is not required, cs_dis pin should be left open or connected to ground through a resistor (~10 k ). direct connection to ground is not safe (iso pulses clamped through cs_dis pin can damage the device). iso pulses refered to iso 7637-2: 2004(e). 5. pull-up r5 is optional (open load detection in off-state capability in case of m0-5enhanced). , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 8 5 j q g n ' j q g * 1 ' 5 n * 1 ' 5 v h q v h 5 n 5 n * 1 ' 9 e d w * 1 ' 2 8 7 3 8 7 * 1 ' * 1 ' 9 * 1 ' 9 g g * 1 ' r x w r x w $ ' & l q 8 0 l f u r f r q w u r o o h u & q ) & q ) & q ) 9 & q ) 9 5 n 9 e d w b v z l w f k h g 2 s w l r q d o i r u 0 ( q k d q f h g 6 h h 1 r w h ' ! 0 ' - 3 * 1 ' 5 n * 1 ' 5 v h q v h 5 n 5 n * 1 ' 9 e d w * 1 ' 2 8 7 3 8 7 * 1 ' * 1 ' 9 * 1 ' 9 g g * 1 ' r x w r x w $ ' & l q 8 0 l f u r f r q w u r o o h u & q ) & q ) & q ) 9 & q ) 9 5 n 9 e d w b v z l w f k h g 6 h h 1 r w h , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 5 h y h u v h % d w 3 u r w 3 z u & o d p s 8 2 s w l r q d o i r u 0 ( q k d q f h g ' ! 0 ' - 3 UM1556 general items doc id 023520 rev 2 9/87 1.2 reverse battery protection 1.2.1 reverse battery protection of monolithic hsds the reverse battery protection is inserted to the gnd terminal of the driver. there are three possible solutions: resistor only, resistor plus diode and mosfet. there is a relatively low current in the gnd path and therefore no high power components are needed. however, this protection circuit still must be able to handle the clamped iso pulse current, as well as the iso pulse voltage. we also have to consider the fact that this simple "ground" circuitry doesn't provide any protection to the connected load. if a reverse battery condition occurs, the load is supplied in reverse polarity through internal body diode of the hsd and the power dissipation on the hsd can become critical (depending on connected load and thermal connection of the hsd). with a typical voltage drop on the internal body diode of about 0.7 v, the resulting power dissipation = 0.7 i load [w]. reverse battery protection using resistor figure 4. voltage levels during reverse battery ? resistor protection a resistor r gnd in the gnd line prevents a short circuit through the internal substrate diode of the hsd during a reverse battery condition. the minimum resistor value is limited by the dc reverse ground pin current of the hsd. the maximum resistor value is limited by the drop voltage, caused by the on-state supply current (i s ) of the hsd. the voltage drop across this resistor elevates the minimum input high threshold and normally should not exceed 1 v (depending on microcontroller i/o levels). equation 1 equation 2 5 j q g * 1 ' n n n n , 1 / r j l f 2 8 7 6 7 6 7 b ' , 6 * 1 ' 9 f f 9 g g * 1 ' r x w r x w l q 0 l f u r f r q w u r o o h u * 1 ' * 1 ' b 9 * 1 ' 9 9 9 9 9 9 9 9 9 9 ' ! 0 ' - 3 r gnd v gnd i s(on)max ----------------------- - () ------------------------------------------ - general items UM1556 10/87 doc id 023520 rev 2 equation 3 this resistor can be shared amongst several different hsds. in this case, equation 1 i s(on)max becomes the sum of the maximum on-state currents of the different devices. when the microprocessor ground is not common with the device ground, the r gnd produces a shift (i s(on)max r gnd ) in the input thresholds and (in case of a digital hsd) also the status output values. this shift varies depending on how many devices are on in the case of several hsds sharing the same r gnd . this can lead to a very low value of r gnd (needed to comply with equation 1 and equation 2 ) not being fulfilled. to overcome this problem, st suggests the use of another solution with diode or mosfet. resistor calculation ? example (reverse battery requirement ? 14 v@60 s): 1. define maximum acceptable (safe) ground shift level v gnd : figure 5. logical levels check table 1. datasheet values symbol parameter value vn5050j v ih input high-side voltage (min) 2.1 v i ih high level input current (max) 10 a i gnd dc reverse gnd current (max) -200 ma i s(on) on-state supply current (max) 3 ma v stat low level status voltage (max) 0.5 v at 1.6 ma st72f561 v oh output high level voltage (min) 4.3 v at -2 ma v il input low level voltage (max) 0.3 v dd p d v bat () 2 r gnd ---------------------- = 5 j q g * 1 ' * 1 ' + 6 ' , 1 n x & , , , + 6 9 2 + 9 * 1 ' 9 , + n 6 7 $ 7 2 8 7 , 1 9 , / 9 6 7 $ 7 9 1 - 6 7 ) * 1 ' ' ! 0 ' - 3 UM1556 general items doc id 023520 rev 2 11/87 the maximum acceptable ground shift level is the maximum drop voltage on r gnd that does not influence the communication between hsd and c. status signal level check: as seen in tab le 1 , the microcontroller can safely recognize log. ?l? when the input voltage is below v il =0.3v dd =0.35=1.5v. the maximum low level voltage on the hsd status pin v stat = 0.5 v. this means there is a 1.5 v ? 0.5 v = 1 v safety margin for voltage drop on r gnd . input signal level check: as seen in table 1 , the microcontroller output high level (4.3 v) is clearly above the hsd minimum input high level (2.1 v). the voltage drop on the protection serial resistor is relatively small: r prot i ih =10k10a=0.1v. hence, there is a 4.3 v ? 0.1 v ? 2.1 v = 2.1 v safety margin. result: the maximum acceptable drop voltage on r gnd is 1 v. for safety reasons, we consider v gnd = 0.8 v for the following calculations. 2. calculate resistor value 3. check power dissipation in reverse mode => select resistor package power rating@70 c of 2512 is 1 w note: the device with only a resistor at the gnd terminal doesn't clamp iso pulses on the supply line. positive iso pulses (> 50 v) and negative iso pulses pass the gnd and logic terminals. therefore a serial protection resistor should be used between the c and hsd. resistor values should be calculated according to the maximum injected current to the i/o pin of the microcontroller used. r gnd v gnd i s(on)max ----------------------- - 0.8v 3ma ------------ - 266.67 = r gnd v bat i gnd -------------- 14v 200ma ------------------- 70 = ? ? ? ? ? ? ? r gnd ? 220 = p d v bat () 2 r gnd ---------------------- 14v 2 220 -------------- 0.89w package ? 2512 === = general items UM1556 12/87 doc id 023520 rev 2 reverse battery protection using diode plus resistor figure 6. voltage levels during reverse battery using diode-resistor protection network a diode at the gnd terminal prevents a short circuit through the internal substrate diode of the hsd during reverse mode. a resistor (1 k - package 0805) should be inserted in parallel to the diode if the device drives an inductive load (to clean up negative voltage peaks at gnd terminal in case of inductive load switch-off). this ground network can be safely shared amongst several different hsds. the presence of the ground networkalso produces a shift (~ 600 mv) in the input threshold and in the status output values. this shift does not vary if more than one hsd share the same diode/resistor. a diode at the gnd terminal allows the hsd to clamp positive iso pulses above 50 v (clamping voltage of the hsd). negative iso pulses still pass gnd and logic terminals. the diode should withstand clamped iso currents in case of positive iso pulses, and reverse voltages in case of negative iso pulses. dimensioning of the diode (a) : the most severe positive iso pulse to consider is test pulse 2 at level iv (50 v @ 50 s). this voltage is considered on top of the nominal supply voltage of 13.5 v, so total voltage is 63.5 v. the vipower has a clamping voltage of typ. 46 v (minimum 41 v/maximum 52 v). in a typical device, the remaining voltage is 63.5 v - 46 v - 0.7 v = 16.8 v. the iso pulse generator interior resistance is given with 2 . hence the resulting peak current through the diode is 8.4 a for a duration of 50 s. a. result: maximum peak forward current: 8.4 a @ 50 s maximum reverse voltage: -100 v n * 1 ' n n n n , 1 / r j l f 2 8 7 6 7 6 7 b ' , 6 * 1 ' 9 f f 9 g g * 1 ' r x w r x w l q 0 l f u r f r q w u r o o h u * 1 ' * 1 ' b 9 * 1 ' 9 9 9 9 9 9 9 9 9 9 ' ' ! 0 ' - 3 UM1556 general items doc id 023520 rev 2 13/87 figure 7. positive iso pulse the most severe negative iso pulse to consider is test pulse 1 at level iv (-100 v@2 ms). this pulse is directly transferred to the gnd pin. the maximum peak reverse voltage of the diode should therefore be at least 100 v. note: the diode works in avalanche mode if pulse level is above the rated reverse voltage. figure 8. negative iso pulse note: as seen from the above explanation, the hsd with diode protection in the gnd pin doesn?t clamp negative iso pulses at supply line. therefore an appropriate serial protection resistor should be used between the c and hsd.the resistor value should be calculated according to maximum injected current to the i/o pin of the used microcontroller. note: diode parameters can be lower if an external clamping circuitry is used (e.g. hsd module is supplied from a protected power supply line). * 1 ' , 1 / r j l f 2 8 7 6 7 6 7 b ' , 6 * 1 ' 9 f f 9 9 ' * 1 ' 9 , ' , $ ' 9 9 n ' ! 0 ' - 3 * 1 ' , 1 / r j l f 2 8 7 6 7 6 7 b ' , 6 * 1 ' 9 f f ' * 1 ' 9 n 9 9 9 9 9 ' ! 0 ' - 3 general items UM1556 14/87 doc id 023520 rev 2 reverse battery protection using mosfet figure 9. voltage levels during reverse battery ? mosfet protection the hsd is protected by a mosfet which is switched-off during reverse battery conditions. this mosfet circuitry also provides full iso pulse clamping at supply line and causes no ground level shift. a capacitor between gate and source keeps the gate charged during negative iso pulses as well. the time constant given by rc values should be longer than 2 ms (duration of reverse battery protection (monolithic hsds only) - comparison of negative iso7637 pulse 1). n n n n , 1 / r j l f 2 8 7 6 7 6 7 b ' , 6 * 1 ' 9 f f 9 g g * 1 ' r x w r x w l q 0 l f u r f r q w u r o o h u * 1 ' * 1 ' b 9 * 1 ' 9 9 9 9 9 9 9 9 9 9 * 1 ' = ' & 5 ' ! 0 ' - 3 table 2. reverse battery protection (of monolithic hsds only) ? comparison protection type (monolithic hsd) +- resistor ? any type of load. ? voltage drop fluctuation. ? calculation of r value necessary. ? positive and negative iso-pulse transfer to input and diagnostics pin (serial protection resistors necessary). ? relatively high power dissipation on the r gnd (~1 w) during reverse conditions ? higher price of the resistor ? device turns-off in case of positive iso pulses diode ? fixed voltage drop. ? positive iso-pulse clamping (> 50 v). ? resistive load only. ? negative iso-pulse transfer to input and diagnostics pin (serial protection resistors necessary). rgnd gnd gnd hsd d gnd gnd hsd UM1556 general items doc id 023520 rev 2 15/87 1.2.2 reverse battery protection of hybrid hsds in contrast to monolithic devices, all hybrid vipower hsd do not need any external components to protect the internal logic in case of a reverse battery condition. the protection is provided by internal structures (see "reverse battery protection" in the block diagram of figure 10 ). in addition, due to the fact that the output mosfet turns on even in reverse battery mode thus providing the same low ohmic path as in regular operating conditions, no additional power dissipation has to be considered. furthermore, if for example, a diode is connected to the gnd of a hybrid hsd, the output mosfet is unable to turn on and thus the unique feature of the driver is disabled (see figure 11 ). resistor and diode ? fixed voltage drop ? positive iso-pulse clamping (> 50 v). ? any type of load. ? negative iso-pulse transfer to input and diagnostics pin (serial protection resistors necessary). mosfet ? any type of load. ? no voltage drop. ? no iso-pulse transfer to input and diagnostics pin. ? higher cost (more external components needed). table 2. reverse battery protection (of monolithic hsds only) ? comparison (continued) protection type (monolithic hsd) +- 1k d gnd gnd hsd gnd zd c vbat gnd hsd r general items UM1556 16/87 doc id 023520 rev 2 figure 10. hybrid hsd - reverse battery protection with self switch-on of the mosfet figure 11. example - self switch-on of mosfet eliminated by dgnd 1.3 microcontroller protection if iso pulses or reverse battery conditions appear, the hsd control pins are pulled to dangerous voltage levels due to the internal hsd structure and ground protection network (see section 1.2: reverse battery protection for further details). * 1 ' 5 n * 1 ' 5 v h q v h 5 n 5 n * 1 ' * 1 ' * 1 ' * 1 ' * 1 ' 9 g g * 1 ' r x w r x w $ ' & l q 8 0 l f u r f r q w u r o o h u & q ) & q ) & q ) 9 & q ) 9 , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 5 h y h u v h % d w 3 u r w 3 z u & o d p s 8 9 b 9 * 1 ' * 1 ' / 2 $ ' $ 9 9 9 g v p 9 9 9 9 0 2 6 ) ( 7 v z l w f k h g 2 1 ' ! 0 ' - 3 * 1 ' 5 n * 1 ' 5 v h q v h 5 n 5 n * 1 ' * 1 ' * 1 ' * 1 ' * 1 ' 9 g g * 1 ' r x w r x w $ ' & l q 8 0 l f u r f r q w u r o o h u & q ) & q ) & q ) 9 & q ) 9 , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 5 h y h u v h % d w 3 u r w 3 z u & o d p s 8 9 b 9 * 1 ' * 1 ' / 2 $ ' $ 9 9 9 g v p 9 9 9 9 e r g \ ' l r g h 9 ' j q g 0 2 6 ) ( 7 v z l w f k h g 2 ) ) ' ! 0 ' - 3 UM1556 general items doc id 023520 rev 2 17/87 figure 12. iso-pulse transfer to i/o pin therefore, each microcontroller i/o pin connected to a hsd must be protected by a serial resistor to limit the injected current. the value of r prot must be high enough to ensure that injected current is always below the latch-up limit of the microcontroller i/o. we should also consider the voltage drop on r prot because the current required by the hsd input is typically 10 a. the following condition must be fulfilled: example: recommended r prot value is 10 k (safe value for most automotive microcontrollers). 1.4 introduction of m0-5enhanced products in addition to the established m0-5 drivers, stmicroelectronics has introduced a new set of products called m0-5enhanced. as the name indicates, these new drivers are based on the st proprietary m0-5 technology, but have some more sophisticated features. the new features of the m0-5enhanced family are aimed at improving the load handling as well as the overload diagnostics capabilities. 5 j q g * 1 ' * 1 ' + 6 ' , 1 5 s u r w n x & , , , + 6 9 2 + 9 * 1 ' 9 , + 2 8 7 * 1 ' ' 9 s h d n ' ! 0 ' - 3 v peak i ( c ) latchup --------------------------------------- - r prot v oh v ih v gnd + () ? i ih ------------------------------------------------------- ? --------------- - r prot 4.3v 2.1v 1v + () ? 10 a ------------------------------------------------- - ? 5k r prot 120k ? general items UM1556 18/87 doc id 023520 rev 2 1.4.1 new features overview improved diagnostics on analogue current sense devices: ? open load/short to vbat indication in off-state improved compatibility with higher variety of loads ? optimized current limitation range faster detection of overload and short to gnd through ? indication of power limitation analogue: stable indication by pulling the cs pin to v senseh (as for tsd) digital: stable indication by pulling low the status pin (as for tsd) 1.4.2 open load in off-state/short to vbat now also featured on analogue m0-5enhanced high side drivers (already implemented for digital high side drivers) open load detection in off-state through external pull up resistor differentiation between open load and short to vbat by disconnecting the optional pull up resistor figure 13. open load/short to vcc condition , 1 3 8 7 * 1 ' 9 f f 9 f f o l q h 2 8 7 3 8 7 / r j l f ' u l y h u 9 s x 5 s x 5 / 9 2 / & 6 5 6 & ' ! 0 ' - 3 UM1556 general items doc id 023520 rev 2 19/87 figure 14. open load/short to vcc condition 1.4.3 indication of power limitation the principle: diagnostics reacts as soon as power limitation is reached without waiting for thermal shut down (in digital as well as in analogue hsds) no ambiguity of diagnostics between open load and overload fast and secure detection of short circuit/overload also for intermittent loads (for example turn-indicator lamps or loads driven with pwm) intermittent short circuit detection covered as well 1.4.4 indication of power limitation ? example for analogue driver table 3. cs pin levels in off-state pull up cs open load yes vsenseh no 0 short to vcc yes vsenseh no vsenseh nominal yes 0 no 0 9 6 ( 1 6 ( + 9 6 ( 1 6 ( 9 6 ( 1 6 ( + w ' 6 7 . 2 1 9 6 ( 1 6 ( 9 6 ( 1 6 ( 9 , 1 3 x o o x s f r q q h f w h g 3 x o o x s g l v f r q q h f w h g 2 s h q o r d g 6 k r u w w r 9 & & * $ 3 * & ) 7 general items UM1556 20/87 doc id 023520 rev 2 1.4.5 indication of power limitation ? example for digital driver figure 15. m0-5 ? ?soft? short to gnd figure 16. m0-5 ? ?hard? short to gnd figure 17. m0-5enhanced ? ?soft? short to gnd figure 18. m0-5enhanced ? ?hard? short to gnd figure 19. m0-5 ? ?soft? short to gnd figure 20. m0-5 ? ?hard? short to gnd UM1556 general items doc id 023520 rev 2 21/87 1.4.6 m0-5enhanced: analogue current sense truth table figure 21. m0-5enhanced ? ?soft? short to gnd figure 22. m0-5enhanced ? ?hard? short to gnd table 4. analogue driver-truth table (off-state) operation mode input level output level current sense normal operation l l0v short to vbat vbat v senseh open load h (with external pull up) v senseh l (without external pull up) 0v short to gnd l 0 v overtemperature l 0 v general items UM1556 22/87 doc id 023520 rev 2 overtemperature, overload and short to gnd can be distinguished from an open load condition without the need of offstate diagnostics ? no switchable pull up resistor is required. detailed diagnostics without external components is possible. 1.4.7 indication of power limitation, the advantages the system reaction time on overload/short circuit events depends on various aspects. the most important one is the first link in the chain: the diagnostics feedback of the smart power device. figure 23. system reaction time comparison indication of power limitation as diagnostics feedback allows almost instantaneous overload/short circuit detection, as soon as the deltat exceeds 60 k. table 5. analogue driver-truth table (on-state) operation mode input level output level current sense normal operation h vbat i out /k short to vbat vbat nominal overtemperature l v senseh w > p v @ 2 y h u o r d g ( y h q w 5 h d f w l r q w l p h + 6 ' ? & ' l d j q r v l v i l o w h u l q j ? & h u u r u p h p r u \ l q f u h p h q w + 6 ' w x u q r i i 6 \ v w h p 3 u r w h f w l r q 6 \ v w h p 3 u r w h f w l r q + 6 ' ? & ' l d j q r v l v i l o w h u l q j ? & h u u r u p h p r u \ l q f u h p h q w + 6 ' w x u q r i i 6 \ v w h p 3 u r w h f w l r q 6 \ v w h p 3 u r w h f w l r q w > p v @ 5 h d f w l r q w l p h + 6 ' ? & g l d j q r v w l f v i l o w h u l q j ? & h u u r u p h p r u \ l q f u h p h q w + 6 ' w x u q r i i + 6 ' ? & g l d j q r v w l f v i l o w h u l q j ? & h u u r u p h p r u \ l q f u h p h q w + 6 ' w x u q r i i 6 \ v w h p 3 u r w h f w l r q 6 \ v w h p 3 u r w h f w l r q : l w k 3 r z h u / l p l w d w l r q l q g l f d w l r q : l w k r x w 3 r z h u / l p l w d w l r q l q g l f d w l r q ' ! 0 ' - 3 UM1556 analogue current sense doc id 023520 rev 2 23/87 2 analogue current sense 2.1 introduction with the introduction of the novel vipower m0-5 technology, important improvements have been introduced to the analog current sense operation. the block diagram of a m0-5 high side drive with analog current sense is reported in figure 24 . in line with the previous generations, the current sense block has a double function: current mirror of the load current in normal operation. this delivers a current proportional to the load current according to a known ratio named k diagnostics flag in fault conditions. this delivers a fixed voltage with a certain current capability in case of overtemperature conditions. the current delivered by the current sense circuit can be easily converted to a voltage by means of an external sense resistor, thus allowing continuous load monitoring and abnormal-condition detection. figure 24. m0-5 high side driver with analogue current sense ? block diagram 2.2 simplified principle of operation the simplified block diagram of the m0-5 analog current sense is shown in figure 25 . ' ! 0 ' - 3 analogue current sense UM1556 24/87 doc id 023520 rev 2 figure 25. m0-5 current sense simplified block diagram the sensemos is scaled down copy of the mainmos according to a defined geometric ratio, driven by the same gate control circuit as the mainmos. 2.3 normal operation (channel on, cs_dis low) the current flowing through the mainmos is mirrored by the sensemos. the current delivered by the current sense pin is regulated by the current sense amplifier through the p channel mosfet m1 so that: equation 4 and consequently equation 5 where gapgms00102 v ds_main v ds_sense = r ds_sense i sense ? r ds_main i out ? = v sense r sense i out k ? ? = UM1556 analogue current sense doc id 023520 rev 2 25/87 encloses the geometric ratio, the current sense amplifier offset and various process parameter spreads. care must be taken in order to ensure the i sense is proportional to i out . indeed, the maximum drop across the r sense is internally limited to approx. 7.5 v as specified in the datasheet by the parameter v sense ?maximum analog sense output voltage? (5 v minimum @ 8v analogue current sense UM1556 26/87 doc id 023520 rev 2 still compatible with the minimum i limh. with the selected r sense , the maximum v sense which can be developed to maintain linearity is approx. 4.3 v. however, the current sense operation for load current approaching the current limitation is neither guaranteed nor predictable. indeed, because of the intervention of the current limiter, the output voltage can drop significantly: up to approximately 0 v in the extreme case of a hard short circuit. as the whole circuit is referred to v out , ambiguous and unreliable current values can derive from the cs under such conditions. in order to bring the cs into a well defined state, a dedicated circuit section shuts down the current sense circuitry when v out drops below a certain threshold (6 v typ, see figure 27 ). figure 27. v sense vs v out @ i out =i limh once again, this value is consistent with the current sense operating range and current limitation value. example 3 : vnd5025ak at the edge of current limitation i out =i limh = 29 a, the maximum drop on the output mosfet is therefore, at vcc = 8 v, v out is still sufficient to ensure correct cs function up to the current limited region. i out i sense_max k ? 29a ? = 9 2 8 7 y v 9 6 ( 1 6 ( # , 2 8 7 , / , 0 + 9 2 8 7 9 9 6 ( 1 6 ( 9 ' ! 0 ' - 3 v ds r ds_max i limh ? 1.45v ? = UM1556 analogue current sense doc id 023520 rev 2 27/87 in conclusion, in normal operation the current sense works properly within the described border conditions. for a given device, the i sense is a single value monotonic function of the i out as long as the maximum i sense (1 st example) or the current sense saturation (2 nd example) are reached, i.e., there's no chance of having the same i sense for different i out within the given range. the current sense may still work above the current limited region depending on the v out . in this latter case, however, the intervention of protection mechanisms such as power limitation and saturation of the circuit (depending on the r sense choice) might cause the information provided by the current sense to not be processable. finally, the cs switch-off in case of a hard short circuit renders this latter condition indistinguishable from an open load triggered switch-off. 2.4 overtemperature indication (channel on, cs_dis low) in case of overtemperature, the fault is indicated by the cs pin which is switched to a "current limited" voltage souce. indeed, with reference to figure 25 , whenever an overtemperature condition is reached, the branch circuit on the left side is activated. the p channel mosfet m2 is controlled in such a way as to develop 9 v typ (v senseh in the datasheet) across the external sense resistor. in any case, the current sourced by the cs in this condition is limited to 8 ma typ (i senseh in the datasheet). example 4 vnd5025ak and minimum sense resistance for v senseh > 5 v considering typical i senseh =8ma r sense_min = 625 2.5 current sense esd and spikes protection an additional improvement brought to the current sense circuit with the m0-5 is related to the esd and voltage transient protection of the cs pin. with reference to figure 25 , this protection is now obtained thanks to the active clamping structure connected between vcc and the cs pad, represented in a simplified way by a zener. consequently, the absolute maximum rating on v csense now ranges from vcc - 41 v to vcc. this novel solution has removed the inaccuracy at very low v sense experienced by the m0- 3 drivers due to the offset caused by some leakage in the previous esd protection structure. this offset increases when v sense is lower than v gnd because of the ground network which protects against reverse battery. with m0-5, the current sense is able to function correctly with the accuracy given by the k factor spread for v sense up to -1 v (with reference to the device gnd). analogue current sense UM1556 28/87 doc id 023520 rev 2 2.6 current sense resistor calculation the analogue m0-5 hsds integrate a current sense which under normal circumstances provides a voltage across an external shunt resistor (r sense ), which is proportional to the load current with an n/n ratio (the so-called k factor): this allows monitoring of the current which flows through the load and the detection of fault conditions such as open load, overload and short-circuit to gnd leading to a thermal shutdown. in case of a thermal shutdown (m0-5, m0-5enhanced) or a power limitation (m0- 5enhanced), the c sense pin is switched to a voltage source v senseh (v senseh =9v typ, i sensehmax = 8 ma) for as long as the device remains in the thermal shutdown (power limitation) mode. the voltage from the current sense resistor is usually connected through a 10 k protection resistor to the adc input of the c. for the v senseh level, the voltage is limited by the c internal esd protection (~5.6 v) and the adc shows maximum value (0xff in case of 8 bit resolution). the capacitor cf is used to improve the accuracy of the adc. this capacitor plus a 10 k serial resistor function as a low pass filter (>10 khz) for potential hf noise on the c sense line (especially if there is a long wire route to the microcontroller). figure 28. current sense resistor the r sense value definition example : consider the vn5016aj (16 m ) with a nominal load current i n = 5 a@v sense = 2 v and typ k = 5000 (datasheet): v sense r sense i sense ? r sense i out k ------------- v [] ? == , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f + 6 ' 5 j q g n ' j q g * 1 ' * 1 ' 5 v h q v h 9 e d w * 1 ' / 2 $ ' , 6 ( 1 6 ( 9 6 ( 1 6 ( , 2 8 7 5 s u r w n & ) q ) * 1 ' x & $ ' & ' ! 0 ' - 3 r sense k v sense i out ---------------------- - ? 5000 2 5 -- - ? 2 ? === UM1556 analogue current sense doc id 023520 rev 2 29/87 2.7 diagnostics with different load configurations 2.7.1 diagnostics with paralleled loads a hsd with current sensing allows the detection of individual bulb failures when in a parallel arrangement. however, if we consider the bulb wattage spread, the hsd k-factor tolerance, variations of bulb currents vs. v bat and adc resolution, it is clear that accurate failure determination can be difficult in some cases. for example, if there is a largeand small bulb on the output, the detection limit for the lowest power bulb is lost in the tolerances. in order to achieve better current sense accuracy, one or both of the strategies listed below can be adopted: 1. current sense calibration (k-factor measurement) of each hsd 2. v bat measurement bulb current compensation by appropriate software 2.7.2 diagnostics with different load options in some cases, the requirement profile asks for alternative loads to be driven with one and the same high side driver. these load alternatives may be a bulb lamp alternating with an led (-cluster). in this case the driver: must handle the high inrush current of the bulb load must provide sufficiently low power dissipation during continuous operation must not indicate an open load in case an led (-cluster) is applied instead of a bulb. m0-5 drivers today offer an open load threshold (in case of drivers with digital status output) that is usually low enough to prevent an open load detection in case an led is connected. if an analog current sense device is used, different sense resistors have to be used in order to have the current sense band in the appropriate range matching the different load currents. an example of a current sense resistor switching circuit can be seen in the figure 29 . the measured scale can be extended by r sense1 , switched in parallel to r sense2 by mosfet q1. table 6. paralleling bulbs ? overview 5+5w ok without calibration 7+7w 21+21w 27+27w 21+5w calibration and v bat monitoring recommended 27+7w 21+21+5w calibration and v bat monitoring necessary 27+27+7w analogue current sense UM1556 30/87 doc id 023520 rev 2 figure 29. switchable current sense resistor ? example 2.7.3 k-factor calibration method in order to reduce the v sense spread, it is possible to reduce the k spread and eliminate the r sense variation by adding a simple test (calibration test) at the end of the module production line. how the calibration works ?to calibrate? on a specific device soldered in a module signifies measuring the k ratio at a given output current by a v sense reading. since the relation of i out =i sense k is known, it is straightforward to calculate the k ratio. however, even if the k ratio measured at a single point eliminates the parametric spread, it doesn't eliminate the v sense variation due to the k variation produced by the output current variation. this variation can be eliminated given the following considerations: ta ble 7 and figure 30 show a v sense measurement in a random vnd5e025ak with r sense =1.8k . , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 8 5 j q g n ' j q g * 1 ' 5 n * 1 ' 5 v h q v h 5 n 5 n * 1 ' 9 e d w * 1 ' * 1 ' * 1 ' 9 * 1 ' & q ) & q ) & q ) 9 & q ) 9 9 g g * 1 ' r x w r x w $ ' & l q r x w 8 0 l f u r f r q w u r o o h u 4 5 v h q v h * 1 ' 5 n * 1 ' * 1 ' : / ( ' & / 8 6 7 ( 5 ' ! 0 ' - 3 table 7. v sense measurement i out [a] v sense [v] 10.64 21.29 31.99 42.69 53.39 UM1556 analogue current sense doc id 023520 rev 2 31/87 figure 30. v sense measurement the trend is almost linear in the application range and so we can approximate the v sense trend with the following equation: equation 6 where m [ohm] is the rectangular coefficient and a is a constant. the output current can be calculated by inverting this equation: equation 7 instead of i out =i sense k, once m[s] and b are known, it is possible to evaluate the i out with a high accuracy, leaving only the spread due to temperature variation. the current sense fluctuation due temperature variation is expressed in the datasheet with the parameter dk/k. how to calculate m and b to calculate m and b two simple measurements performed at the end of the production line are required. chose two reference output currents (i ref1 and i ref2 ) and measure the respective v sense1 and v sense2 . these four values must thenbe stored in an eeprom in order to let the c use this information to calculate k and b using the simple formulas reported below. since we defined: it is also true that: 9 v h q v h 9 v , r x w , r x w $ 9 v h q v h 9 ' ! 0 ' - 3 v sense m*i out a + = i out m*v sense +b = i out m*v sense +b = analogue current sense UM1556 32/87 doc id 023520 rev 2 equation 8 and solving these two equations we get the following formulas: equation 9 example for the chosen device: setting i ref1 = 2 a and i ref2 = 4 a according to tab le 7 we get v sense1 = 1.29 v and v sense2 = 2.69 v then m = 1.43 [s] b = 0.16 [a] i out is then: equation 10 after calibration, the current sense variation is still affected by the device temperature. equation 10 remains affected by an error proportional to the sense current thermal drift. this drift is reported in the datasheet as dk/k. 2.8 analogue current sense diagnostics ta ble 8 summarizes all failure conditions, the v sense signal behavior and recommendations for diagnostics sampling for m0-5 in comparison with m0-5enhanced. dk 1 /k 1 (1) 1. the drift decreases when increasing the output current , e.g. in the vnd5e025ak datasheet the drift is +/- 13 % at 2 a and it decreases down to +/-6 % when the output current is 10 a. currente sense drift i out =2 a; v sense =4 v v csd =0 v; t j =-40c to 150 c -13 13 % i ref1 m*v sense1 +b = i ref2 m*v sense2 +b = mi ref1 i ref2 ? () v sense1 v sense2 ? () ? = bi ref2 ? v sense1 i ref1 ? v sense2 ? () v sense1 v sense2 ? () ? = i out 1.43 v sense ? 0.16 + = UM1556 analogue current sense doc id 023520 rev 2 33/87 table 8. analogue hsd diagnostics diagnostics symbol m0-5 m0-5 enhanced value value open load (without pull- up) v in hh v sense l ll condition 1 st sample after v in = h with a minimum delay of 600us, and wait to t1 (see sc to gnd) for 2 nd sample to distinguish between sc to gnd ? see (1) . delay response time from rising edge of input pin must be considered (minimum 300 s). waveform open load (with pull-up) v in hhl v sense l llv senseh condition same as open load without pull-up (no diagnostics in off-state) n/a waveform short circuit to v bat v in hhl v sense < nominal < nominal v senseh condition n/a n/a waveform 1 r p l q d o 9 v h q v h analogue current sense UM1556 34/87 doc id 023520 rev 2 sc to gnd v in hh v sense l v senseh (v senseh ? thermal shutdown) v senseh (v senseh ? power limitation or thermal shutdown) condition 1st sample after v in =h with a minimum delay of 600 s, and wait until thermal shutdown (t1) for 2nd sample to distinguish between open load. t1 depends on package, cooling area, sc resistance, ambient temperature, etc (range of 50 ? 1000 ms) ? see (1) . tj > t tsd (typ=175 c) waveform 1. v sense = 0 v condition explanation (m0-5 only): under normal conditions, the v sense is a mirror of the hsd output current, therefore just one sample gives us information about the hsd. however, we should consider the status signal delay response time from the rising edge of the input pin: t dsense2h = max 600 s (see datasheet). if the device is in a thermal shutdown condition the v sense is pulled to v senseh . if v sense = 0 v we have to be careful because there are two possible states: a) open load b) hard short to gnd, the device is still not in thermal shutdown if a hard short to gnd occurs, the v sense first goes to 0 v (the internal current mirror is not working because v out is close to 0v). after the device reaches thermal shutdown the v sense is pulled to v senseh . the time between sc to gnd and thermal shutdown depends on the package, cooling area, sc resistanc e, ambient temperature etc. normally this time is in the range of 50 - 1000 ms. see figure 31 . table 8. analogue hsd diagnostics (continued) diagnostics symbol m0-5 m0-5 enhanced value value 9 , 9 6 h q v h , 2 8 7 7 m 9 6 ( 1 6 ( + w 9 6 ( 1 6 ( + 9 , 9 6 h q v h , 2 8 7 UM1556 analogue current sense doc id 023520 rev 2 35/87 figure 31. vnd5012a current sense voltage behavior ? hard short to gnd occurred (20 m ), thermal shutdown was reached 344 ms after short-circuit to gnd 2.9 open load detection in off-state ? external circuitry for analogue m0-5 hsd the following schematic shows a simple way to perform an open-load diagnostics in off- state for analogue hsds. in case of a missing load in off-state the r sense resistor is supplied through r5, r6 and d1. then the voltage increase on r sense is about 2 v (divider r5, r6, r sense ), which can be recognized by a c as open-load in off-state. in on-state conditions (or if current sense disable signal is high) the influence of r5, r6 is suppressed by the conducting transistor t1 (anode of d1 is shorted to gnd). gapgms00108 analogue current sense UM1556 36/87 doc id 023520 rev 2 figure 32. analogue hsd ? circuit for open load detection in off-state 2.10 open load detection in off-state ? m0-5enhanced hsd figure 33. analogue hsd ? open load detection in off-state (m0-5enhanced) , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 8 5 j q g n ' j q g * 1 ' 5 n * 1 ' 5 v h q v h n 5 n 5 n * 1 ' 9 e d w * 1 ' 2 8 7 3 8 7 * 1 ' * 1 ' 9 * 1 ' 9 g g * 1 ' r x w r x w $ ' & l q 8 0 l f u r f r q w u r o o h u 5 n 9 e d w b v z l w f k h g 5 n 7 * 1 ' * 1 ' ' ' ' & q ) & q ) & q ) 9 & q ) 9 5 n 5 n ' ! 0 ' - 3 , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 8 5 j q g n ' j q g * 1 ' 5 n * 1 ' 5 v h q v h 5 n 5 n * 1 ' 9 e d w * 1 ' 2 8 7 3 8 7 * 1 ' * 1 ' 9 * 1 ' 9 g g * 1 ' r x w r x w $ ' & l q 8 0 l f u r f r q w u r o o h u & q ) & q ) & q ) 9 & q ) 9 5 n 9 e d w b v z l w f k h g ' ! 0 ' - 3 UM1556 digital status output doc id 023520 rev 2 37/87 3 digital status output 3.1 digital hsd diagnostics the diagnostics of digital m0-5 devices is based on a logical level on the status pin. the table below summarizes all failure conditions, the status signal behavior and recommendations for diagnostics sampling for m0-5 in comparison with m0-5enhanced. table 9. digital hsd diagnostics diagnostics symbol m0-5 m0-5 enhanced value value open load (without pull-up) v in hl h l v stat ll l l condition i out < i ol (see datasheet) v out > v ol (typ=3 v ) without external pull-up i out < i ol (see datasheet) v out > v ol (typ=3 v) without external pull-up waveform open load (with pull-up) v in hl h l v stat ll l l condition i out < i ol (see datasheet) v out > v ol (typ=3 v ) with external pull-up i out < i ol (see datasheet) v out > v ol (typ=3 v) with external pull-up waveform digital status output UM1556 38/87 doc id 023520 rev 2 figure 34. digital hsd diagnostics ? timing overview overtemp / overload v in hl h l v stat lh l h condition tj > t tsd (typ=175 c) ( thermal shutdown) ? active power limitation ?tj > t tsd (typ=175 c) (thermal shutdown) waveform short circuit to v bat v in hl h l v stat hl h l condition i out > i ol (see datasheet ) v out > v ol (typ = 3 v) i out > i ol (see datasheet) v out > v ol (typ = 3 v) waveform table 9. digital hsd diagnostics (continued) diagnostics symbol m0-5 m0-5 enhanced value value 9 9 w 3 2 / 6 ' / w 6 ' / w w ' 2 / r q w ' 6 7 . 2 1 , 1 6 7 $ 7 9 6 7 $ 7 9 6 7 $ 7 9 6 7 $ 7 2 1 v w d w h 2 3 / 2 7 2 ) ) v w d w h 2 3 ( 1 / 2 $ ' q r h [ w s x o o x s 2 3 ( 1 / 2 $ ' h [ w s x o o x s 2 9 ( 5 7 ( 0 3 0 0 ( q k d q f h g 6 + 2 5 7 w r 9 % $ 7 3 2 : ( 5 / , 0 , 7 $ 7 , 2 1 0 ( q k d q f h g r q o \ ' ! 0 ' - 3 UM1556 switching inductive loads doc id 023520 rev 2 39/87 4 switching inductive loads switching inductive loads such as relays, solenoids, motors etc. can generate transient voltages of many times the steady-state value. for example, turning off a 12 volt relay coil can easily create a negative spike of several hundred volts. the m0-5/m0-5e high side drivers are well designed to drive such loads, in most cases without any external protection. nevertheless, there are physical limits for each component that have to be respected in order to decide whether external protection is necessary or not. an attractive feature of the m0-5/m0-5e drivers is that a relatively high output voltage clamping leads to a fast demagnetization of the inductive load. the purpose of this chapter is to provide a simple guide on how to check the conditions during demagnetization and how to select a proper hsd (and the external clamping if necessary) according to the given load. 4.1 turn-on phase behaviour figure 35. inductive load ? hsd turn-on phase when an hsd turns on an inductive load, the current increases with a time constant given by l/r values, so the nominal load current is not reached immediately. this fact should be considered in diagnostics software (i.e. to avoid false open load detection). / 5 9 e d w * 1 ' 2 8 7 5 j q g ' j q g * 1 ' * 1 ' & o d p s 9 r x w , r x w / r d g ' ! 0 ' - 3 5 / w w 9 % $ 7 9 2 8 7 , 2 8 7 5 9 % $ 7 9 , 1 w w w switching inductive loads UM1556 40/87 doc id 023520 rev 2 figure 36. inductive load ? turn-on ex ample: vnq5e050ak, l=260 mh, r=81 4.2 turn-off phase behavior figure 37. inductive load ? hsd turn-off phase the hsd turn-off phase with inductive load is explained in figure 37 . the inductance reverses the output voltage in order to be able to continue driving the current in the same gapgms00113 / 5 9 e d w * 1 ' 2 8 7 5 j q g ' j q g * 1 ' * 1 ' & o d p s 9 r x w , r x w 9 9 9 w \ s ( ( ( / 2 $ ' b / 5 ( / ( 5 ( % $ 7 ( + 6 ' ( % $ 7 ( / 2 $ ' b 9 f o d p s 9 g h p d j 5 / w w 7 ' ( 0 $ * 9 ' ( 0 $ * 9 % $ 7 9 & / $ 0 3 , 9 2 8 7 , 2 8 7 5 9 ' ( 0 $ * 9 , 1 w w w ' ! 0 ' - 3 UM1556 switching inductive loads doc id 023520 rev 2 41/87 direction. this voltage (so called demagnetization voltage) is limited to the value given by the clamping voltage of the hsd and the battery voltage: equation 11 the load current decays exponentially (linearly if r 0) and reaches zero when all energy stored in the inductor is dissipated in the hsd and the load resistance. since the hsd output clamp is related to the v bat pin, the energy absorbed by the hsd increases with increasing battery voltage (the battery is in series with the high side switch and load so the energy contribution of the battery increases with the battery voltage). 4.2.1 calculation of energy dissipated in the hsd the energy dissipated in the high side driver is given by the integral of the actual power on the mosfet through the demagnetization time: to integrate the above formula we need to know the current response i out (t) and the demagnetization time t demag . the i out (t) can be obtained from the well known formula, r/l circuit current response using the initial current i 0 and the final current v demag /r considering i out >= 0 condition (see figure 37 ): (0 < t < t demag i out 0) inserting i(t) = 0 we can calculate the demagnetization time: equation 12 equation 13 v demag v bat v clamp = ? = 13v - 46v typ. = e hsd v clamp 0 t demag ? i out (t)dt ? = i out (t) i 0 i 0 v demag r --------------------------- + ?? ?? 1e tr ? l --------- ? ?? ?? ?? ? ?? ?? ?? ? = t demag l r --- - v demag i 0 r ? + v demag ----------------------------------------------- ?? ?? ?? log ? = t demag r0 lim l i 0 v demag ------------------------ ? = switching inductive loads UM1556 42/87 doc id 023520 rev 2 (simplified for r 0) substituting the t demag and i out (t) by the formulas above we can calculate the energy dissipated in the hsd: then equation 14 equation 15 (simplified for r 0) 4.2.2 calculation example this example shows how to use above equations to calculate the demagnetization time and energy dissipated in the hsd. conditions: step 1) demagnetization voltage calculation using equation 11 : step 2) demagnetization time calculation using equation 12 : e hsd v clamp 0 t demag ? i out (t)dt ? v bat v demag + () 0 t demag ? i out (t)dt ? == e hsd v bat v demag + r 2 ------------------------------------------------ lri 0 ? v demag ? v demag i 0 r ? + v demag ---------------------------------------------- - ?? ?? ?? log ? ?? = e hsd r0 lim 1 2 -- - li 0 2 v bat v demag + v demag ------------------------------------------------ ?? ? = ?battery voltage v bat = 13.5 v ? hsd vnq5e050ak-e ? clamping voltage v clamp = 46 v (typical for m0-5/m0-5e) ? load resistence r = 81 ? load inductance l = 260 mh ? load current (before turn-off event): i 0 =v bat /r = 167 ma v demag v bat v clamp ? 13.5 46 ? 32.5v ? === UM1556 switching inductive loads doc id 023520 rev 2 43/87 step 3) calculation of energy dissipated in the hsd using equation 14 : step 4) measurement (comparison with theory): (see figure 38 ) figure 38. inductive load ? turn off example: vnq5e050ak, l=260 mh, r=81 the demagnetization energy dissipated in the hsd was measured by an oscilloscope with mathematical functions. the first function (f1) shows the actual power dissipation on the hsd (v bat ?v out )i out , the second function (f4) shows the hsd energy (integral of f1) . as seen from the oscillogram the measured values are very close to the theoretical calculations. t demag l r --- - v demag i 0 r ? + v demag ---------------------------------------------- - log ?? ?? ?? ? 0.260 81 -------------- - 32.5 0.167 81 ? + 32.5 ------------------------------------------- - ?? ?? log ? 1.12ms == = e hsd v bat v demag + r 2 ------------------------------------------------ lri 0 v demag ? v demag i 0 r ? + v demag ---------------------------------------------- - ?? ?? ?? log ?? = ?? = 13.5 32.5 + 81 2 ----------------------------- 0.260 81 0.167 32.5 ? ? () 32.5 0.167 81 ? + 32.5 ------------------------------------------- - ?? ?? log ? 4.04mj = ?? = gapgms00115 switching inductive loads UM1556 44/87 doc id 023520 rev 2 4.3 proper hsd selection even if the device is internally protected against break down during the demagnetization phase, the energy capability is limited and has to be taken into account during the design of the application. it is possible to identify two main mechanisms that can lead to the device failure: 1. the temperature during the demagnetization rises quickly (depending on the inductance) and the uneven energy distribution on the power surface can cause the presence of a hot spot causing the device failure with a single shot. 2. as in normal operation, the life time of the device is affected by the fast thermal variation as described by the coffin-manson law. repetitive demagnetization energy causing temperature variations above 60 k causes a shorter life time. these considerations lead to two simple design rules: 1. the energy has to be below the energy the device can withstand at a given inductance. 2. in case of a repetitive pulse, the average temperature variation of the device should not exceed 60 k at turn-off. to fulfill these rules, the designer has to calculate the energy dissipated in the hsd at turn- off, and then compare this number with the datasheet values as shown in the following examples. 4.3.1 example of vnd5e160aj driving relays the purpose of this example is to evaluate if a vnd5e160aj device can safely drive a relay under following conditions: UM1556 switching inductive loads doc id 023520 rev 2 45/87 step 1) demagnetization voltage calculation using equation 11 : step 2) demagnetization time calculation using equation 12 : step 3) calculation of energy dissipated in hsd using equation 14 : step 4) hsd datasheet analysis: the maximum demagnetization energy is specified by i/l diagram in the datasheet. this diagram shows the maximum turn-off current versus inductance for r l = 0 and v bat = 13.5 v (see figure 39 ). these conditions are different from conditions considered in our example (r l = 62 , v bat = 16 v) and inductance 260 mh is not covered by the diagram. ? battery voltage: v bat = 16 v ? hsd: clamping voltage: vnd5e160aj v clamp = 46 v (typical for m0-5/m0-5e) ? relay: resistance : inductance (coil not powered): nvf4-4c-z60a r=62 @-40c (1) l=260mh (2) 1. the relay datasheet usually specifies a coil resistance at 20 c. for the worst case evaluation we should consider the resistance at -40 c which can be calculated as: 2. not every relay datasheet specifies the coil inductanc e. in this case it can be determined by measurement. the inductance value is different with armature seated (relay powered) than when unseated (relay not powered). the inductance measurement should be done with relay powered (armature seated) because this better represents the application conditions. the inductance of a typical 12 v automotive relay is in the range of 200-800 mh. ? load current (before turn-off event): i 0 =v bat /r = 258 ma r 40 ? r 20 1 0.0039 + 40 ? 20 ? () ? () ? = v demag v bat v clamp ? 16 46 ? 30v ? === t demag l r --- - v demag i 0 r ? + v demag ---------------------------------------------- - log ?? ?? ?? ? 0.260 62 -------------- - 30 0.258 62 ? + 30 -------------------------------------- - ?? ?? log ? 1.8ms == = e hsd v bat v demag + r 2 ------------------------------------------------ lri 0 v demag v demag i 0 r ? + v demag ---------------------------------------------- - ?? ?? ?? log ? ? ? ?? == 16 30 + 62 2 ------------------- 0.260 62 0.258 30 ? 30 0.258 + 62 ? 30 -------------------------------------- - ?? ?? log ?? 9.9mj = ?? = switching inductive loads UM1556 46/87 doc id 023520 rev 2 figure 39. maximum turn-off current versus inductance ? vnd5e160aj datasheet therefore it is convenient to translate i/l chart to e/l chart. this can be easily done using equation 15 for the calculation of energy on the hsd considering r l =0, v bat =13.5v (see figure 40 ). figure 40. maximum demagnetization energy ? vnd5e160a 9 % $ 7 9 5 / r k p ' ! 0 ' - 3 0 d [ l p x p g h p d j q h w l ] d w l r q h q h u j \ 9 1 ' ( $ - f d o f x o d w h g i u r p , / f x u y h l q g d w d v k h h w / > p + @ ( > p - @ $ 7 m v w d u w & v l q j o h s x o v h % 7 m v w d u w & u h s h w l w l y h s x o v h & 7 m v w d u w & u h s h w l w l y h s x o v h ? ? ? 0 $ ; 0 $ ; , / ( 5 h o d \ p - p + ' ! 0 ' - 3 UM1556 switching inductive loads doc id 023520 rev 2 47/87 waveform a represents the max energy the device can withstand in a single pulse. a second pulse with the same energy can destroy the part. waveforms b and c represent the max energy to ensure the junction temperature variation to stay below 60 k. putting the energy value of 9.9 mj @ 260 mh calculated in step 3) to this diagram we can see that we are clearly in the safe area. although the energy curve is introduced only up to 100 mh inductance, the calculated energy is below the limit even at 100 mh. step 5) measurement (calculation check): (see figure 41 ). figure 41. demagnetization energy measurement ? vnd5e160aj, relay 260 mh the measured energy is lower by a factor of two than calculated (4.6 mj measured versus 9.9 mj calculated). this difference can be explained by measurement at ambient temperature when the coil resistance is ~25 % higher than the resistance at -40 c used in the calculations. another factor is the coil inductance decrease due to the magnetic saturation (the inductance value used for calculation was measured at a low current). conclusion: the device can safely drive the load without additional protection. the worst case demagnetization energy is clearly below the device limit. 4.4 external clamping selection the main function of external clamping circuitry is to clamp the demagnetization voltage and dissipate the demagnetization energy in order to protect the hsd. it can be used as a cost gapgms00118 switching inductive loads UM1556 48/87 doc id 023520 rev 2 effective alternative in case the demagnetization energy exceeds the energy capability of a given hsd. a typical example is driving dc motors (high currents in combination with high inductance). during the selection of a suitable hsd for such an application, we usually end up in the situation that a given hsd fits perfectly in terms of current profile, but the worst case demagnetization energy is too high (turn-off from stall condition at 16 v, -40 c). rather than selecting a larger hsd, the use of an external clamp can be the more economical choice. external clamping circuitry ? requirements summary: proper negative output voltage clamping to protect the hsd no conduction at: ? normal operation (0-16 v) ? reverse battery condition (-16 v@60 s) ? jump start (27 v@60 s) ? load dump (36 v@400 ms) proper energy capability ? single demagnetization pulse ? repetitive demagnetization pulse 4.4.1 clamping circuitry examples 1) transil and diode protection circuitry (in parallel with the load): the transil (t) clamps the demagnetization voltage to a safe level. the clamping voltage of the transil should be selected in a way that the voltage across the hsd channel is below the minimum specified clamping voltage of the hsd (41 v). the diode (d) is included to protect the transil during normal operation (positive output voltage). 2) transil protection circuitry (in parallel with the hsd) l r vbat gnd out rgnd dgnd gnd gnd clamp vout iout t d gnd UM1556 switching inductive loads doc id 023520 rev 2 49/87 the hsd channel is protected directly by the parallel transil. the clamping voltage of the transil should be below the minimum clamping voltage of the hsd (41 v). such transils (v cl < 41 v) usually start conducting at 30 v, therefore there is a high probability that it is damaged during the clamped load dump pulse (36 v). for that reason it is usually better to use the previously described solution (1). 3) freewheeling diode and reverse battery diode a general purpose diode connected in parallel with the load provides a conductive path for proper demagnetization. relatively small demagnetization voltage (1 diode voltage drop in forward direction) leads to a very slow demagnetization. this can have a negative influence when driving the relay, for example. a slow movement of the armature (slow opening of contacts) can have a negative influence on the lifetime of the relay contacts (depending on the switching current). in order to protect the freewheeling diode against the reverse battery condition, there is an additional diode (dr) required in series with the output. this circuitry is suitable only for small loads because of permanent voltage drop ( power dissipation) on dr during normal operation. 4) freewheeling diode and reverse battery p-channel mos circuitry l r vbat gnd out rgnd dgnd gnd gnd clamp vout iout t l r vbat gnd out rgnd dgnd gnd gnd clamp vout iout gnd d dr switching inductive loads UM1556 50/87 doc id 023520 rev 2 this circuitry is an improvement of the previous example. the reverse battery protection of the freewheeling diode (and load) is solved by a pmos circuitry with negligible voltage drop at nominal current (to avoid undesired power dissipation in on-state) the peak power dissipation of the freewheeling diode during the demagnetization phase is very low in comparison with the transil protection because of low demagnetization voltage (1 diode voltage drop). furthermore, the average power dissipation is much lower, assuming non-zero load resistance (the part of demagnetization energy dissipated in the load resistance is higher at lower demagnetization voltage). therefore, this circuitry is suitable for high current inductive loads such as dc motors, where the transil protection is usually not able to handle the average power dissipation caused by repetitive turn-on/off cycles (the hsd usually goes in thermal cycling when the motor is blocked so there are a lot of demagnetization cycles in a short time). l r vbat gnd out rgnd dgnd gnd gnd clamp iout gnd d pmos 4k7 15v gnd UM1556 switching inductive loads doc id 023520 rev 2 51/87 external clamping circuitry examples : table 10. external clamping circuitry examples (1/2) external clamping circuitry + ? 1) transil and diode (in parallel with the load) fast demagnetization the peak voltage across the hsd channel depends also on v bat (maximum v bat should be considered) 2) transil (in parallel with the hsd) fast demagnetization direct (parallel) protection of the hsd - independent from v bat load dump pulse: (the transil with v cl < 41 v is starting to conduct already at ~30 v transil can be damaged during the load dump pulse) higher peak power dissipation on transil in comparison with circuitry 1) (contribution of power supply) 3) freewheeling diode and reverse battery diode low cost load is reverse battery protected only for small loads (voltage drop and power dissipation on reverse battery protection diode dr ) slow demagnetization l r vbat gnd out rgnd dgnd gnd gnd clamp vout iout t d gnd l r vbat gnd out rgnd dgnd gnd gnd clamp vout iout t l r vbat gnd out rgnd dgnd gnd gnd clamp vout iout gnd d dr switching inductive loads UM1556 52/87 doc id 023520 rev 2 4.4.2 component selection guide fo r external transil-diode clamping this chapter shows how to select proper a diode (d) and transil (t) for external clamping circuitry 1). figure 42. external clamping - transil and diode transil selection clamping voltage, v/a characteristic table 11. external clamping circuitry examples (2/2) external clamping circuitry + ? 4) freewheeling diode and reverse battery fet load is reverse battery protected low peak power dissipation on d during demag. phase (suitable for high current inductive loads such as dc motors) high number of ext. components (cost) slow demagnetization l r vbat gnd out rgnd dgnd gnd gnd clamp iout gnd d pmos 4k7 15v gnd l r vbat gnd out rgnd dgnd gnd gnd clamp vout iout t d gnd UM1556 switching inductive loads doc id 023520 rev 2 53/87 figure 43. transil ? v/a characteristic considering the worst case values (v bat = 16 v, v hsdclampmin = 41 v) the demagnetization voltage should be limited at least to 16 ? 41 = -25 v. assuming 1 v voltage drop on the protection diode (d) we need a transil with v cl < 24 v at the given current level (load current at switch-off event). the clamping voltage is usually specified only at the maximum peak power limit of the device. to determine the voltage at a given current level, apply a linear approximation using v br /i r and v cl /i pp data or estimate the value using v cl /i pp diagram in the datasheet. the transil must not conduct during a reverse battery condition. assuming v bat = -16 v, a 0.5 v drop on the hsd channel and a 0.5 v drop on the protection diode, we have -15 v across the transil. we can find the parameter v rm (stand-off voltage) in the transil specification. v rm is the maximum operation voltage with low leakage current (valid in the whole temperature range). single pulse energy capability the maximum nonrepetitive transient power and current capability of transils is specified mostly for 10/1000 s exponential pulse at 25 c. a real application condition is usually different. in our case, the pulse length is given by the demagnetization time, while the current waveform is close to the sawtooth shape (depending on l/r ratio of the load). to check if the transil can safely operate under the desired conditions we can use the translation diagrams in figure 44 , figure 45 and figure 46 . gapgms00119 v rm >15 v vcl<24 v (at given i 0 ) switching inductive loads UM1556 54/87 doc id 023520 rev 2 figure 44. peak pulse power vs pulse time (for transil 600 w@10/1000 s series) figure 45. equivalent pulses giving the same power dissipation figure 46. maximum peak power as a function of initial temperature of the transil repetitive pulse energy capability depending on the application (pwm, hsd thermal cycling), the transil should be able to withstand repetitive operation and the most important parameter is the average power dissipation: ' ! 0 ' - 3 ' ! 0 ' - 3 ' ! 0 ' - 3 UM1556 switching inductive loads doc id 023520 rev 2 55/87 equation 16 valid when f: switching frequency; e: energy dissipated in transil at each demag. pulse. equation 17 v cl : transil clamping voltage; r: load resistance; l: load inductance; i 0 : load current at turn-off event. the junction temperature t j calculated from p avg should never exceed the maximum specified junction temperature: equation 18 t amb : ambient temperature; r th(j-a) : thermal resistance between the junction and ambient; p avg : average power dissipation. transil selection summary: 1. determine the length of equivalent exponential pulse: (see figure 45 ? considering sawtooth demagnetization current) 2. determine maximum peak power (p p ) for t p (using figure 44 ) 3. correct p p value according to worst case t j (using figure 46 ) 4. check if corrected 5. check p avg and t j in repetitive operation ( equation 16 - equation 18 ) p avg fe ? = t demag 1 f -- - < ------------- - lri 0 v cl ? v cl i 0 r ? + v cl --------------------------------- - ?? ?? ?? log ?? ?? = t j t amb r th j a ? () p avg ? + = t p 0.5 t demag 1.4 ----------------------- - ? = p p v cl i 0 ? > switching inductive loads UM1556 56/87 doc id 023520 rev 2 diode selection: reverse voltage > 52 v (must not conduct during positive voltage on the hsd output maximum possible output voltage is limited by v hsdclampmax =52v) peak forward current > i 0 @ t demag (i 0 : load current at switch-off event, t demag : demagnetization time) 4.4.3 examples of vn5e025aj for dc motor driving with external clamp) the purpose of this example is to evaluate if a vn5e025aj can safely drive a specific dc motor in terms of demagnetization energy and to determine a suitable external clamping circuitry if needed. step 1) demagnetization voltage calculation using equation 11 : step 2) demagnetization time calculation using equation 12 : step 3) calculation of energy dissipated in hsd using equation 14 : step 4) hsd datasheet analysis: looking at the i/l diagram in the datasheet, the maximum turn-off current specified for 0.73 mh inductance is 16 a (single pulse, v bat = 13.5 v, r l = 0). the worst case current in battery voltage: v bat = 16 v hsd: ? clamping voltage: vn5e025aj v clamp = 46 v (typical for m0-5/m0-5e) dc motor: ? nominal current: ? resistance: ? inductance: ? stall current: i nom = 1.5 a r = 0.6 @-40 c l = 0.73 mh i 0 = 25 a@-40 c, 16 v v demag v bat v clamp ? 16 46 ? 30v ? === t demag l r --- - v demag i 0 r ? + v demag ---------------------------------------------- - ?? ?? ?? log ? 0.00073 0.6 --------------------- 30 25 0.6 ? + 30 -------------------------------- ?? ?? log ? 0.49ms == = e hsd v bat v demag + r 2 ------------------------------------------------ lri 0 ? v demag ? v demag i 0 r ? + v demag ---------------------------------------------- - ?? ?? ?? log ? ?? == 16 30 + 0.6 2 ------------------- 0.00073 0.6 25 30 ? 30 25 0.6 ? + 30 -------------------------------- ?? ?? log ?? 264.5mj = ?? ? = UM1556 switching inductive loads doc id 023520 rev 2 57/87 our example (a motor stall condition 25 a@16 v/-40 c) is much higher. for better comparison of the calculated energy (264.5 mj) with the device limits, it is useful to translate the current values at 0.73 mh (i max_a = 16 a, i max_b = 12 a, i max_c = 11 a) to energy values using equation 15 : e max_b =74mj e max_c =62.5mj single pulse @ t jstart = 150 c repetitive pulse @ t jstart = 100 c repetitive pulse @ t jstart = 125 c figure 47. maximum turn-off current versus inductance ? vn5e025aj datasheet the demagnetization energy is by a factor of 2 higher than the device is able to withstand, therefore additional protection/clamping is necessary. the evaluation of an appropriate protection/clamping is described in the following step 5). step 5) external clamping selection (transil and diode): the external circuitry is selected according to tab le 10 . we start with the evaluation of the circuitry with transil and diode as shown in figure 48 : e max a ? 1 2 -- - li 2 max v bat v demag + v demag ------------------------------------------------ ?? ? 1 2 -- - 0.00073 16 2 13.5 32.5 + 32.5 ----------------------------- 132mj = ??? == ( 0 $ ; b $ p - ( 0 $ ; b % p - ( 0 $ ; b & p - 9 % $ 7 9 5 / 9 % $ 7 9 5 / r k p ' & p r w r u ( + 6 ' p - 9 % $ 7 9 5 / r k p ' ! 0 ' - 3 switching inductive loads UM1556 58/87 doc id 023520 rev 2 figure 48. external clamping circuitry ? border conditions the diode (d) selection: reverse voltage > 52 v (must not conduct during positive voltage on the output maximum possible output voltage is limited by v hsdclampmax = 52 v) peak forward current > 25 a @ 0.49 ms (i 0 @ t demag ) 1n4002 (v rrm = 100 v, i fsm = 30 a @ 8.3 ms) the transil (t) selection: stand-off voltage > 15 v (must not conduct during the reverse battery condition at 16 v v batreverse ?v hsddrop ?v ddrop = 16 v?0.5 v?0.5 v = 15 v) clamping voltage < 24 v@25 a (to be sure that the hsd clamp is not activated v hsdclampmin ?v bat ?v ddrop = 41 v?16 v?1 v = 24 v) energy capability requirement (single pulse): peak power: 600 w (considering v cl = 24 v 24 v*25a = 600 w) pulse duration: 0.49 ms (considering v cl = 24 v) pulse waveform: sawtooth demag. current considered equivalent exponential pulse duration: 0.175 ms (see figure 45 ) choice 1) single pulse consideration: according to required energy capability (600 w@0.175 ms), we can find a suitable transil in the smbj series (st devices 600 w@10/1000 s). maximum peak power of these devices is ~ 825 w@0.175 ms considering 105 c initial temperature (see figure 44 and figure 46 ). 9 e d w * 1 ' 2 8 7 5 j q g ' j q g * 1 ' * 1 ' & o d p s 9 r x w , r x w 7 ' * 1 ' 0 9 9 b 9 9 $ 9 e d w * 1 ' 2 8 7 5 j q g ' j q g * 1 ' * 1 ' & o d p s 9 r x w , r x w 7 ' * 1 ' 0 9 9 b 9 9 ' h p d j q h w l ] d w l r q h [ w f o d p s l q j d f w l y h 5 h y h u v h e d w w h u \ h [ w f o d p s l q j l q d f w l y h ' ! 0 ' - 3 0.5 0.49ms 1.4 ------------------- - ? 0.175ms = UM1556 switching inductive loads doc id 023520 rev 2 59/87 the first device closest to the reverse battery requirement (stand-off voltage v rm > 15 v) is smbj16a: v cl = 24 v@18 a (estimated from v cl /i pp diagram) v cl = 27 v@25 a (estimated from v cl /i pp diagram) then we check the v cl /i pp parameters. as seen from the v cl /i pp characteristics, this transil does not fit with our 24 v@25 a requirement. nevertheless, we can decide to use this device given that the hsd can also go in clamp to safely dissipate the remaining energy (see figure 49 ): figure 49. energy sharing between hsd and external clamping circuitry the output voltage during the demagnetization phase is -25 v (considering a worst case hsd v clampmin = 41 v, v bat = 16 v). under these conditions, the external clamping circuitry provides 18 a according to the transil characteristics at 24 v (1 v drop on the protection diode), so the hsd is loaded by the remaining current (25-18 = 7 a). looking at the i/l diagram, we are clearly in the safe area. in addition to single pulse energy considerations, the ?repetitive energy capability? also needs to be checked ? see choice 2) single pulse consideration . type i rm @v rm v br @ir min (1) v cl @i pp 10/1000 s v cl @i pp 8/20 s t (2) max min max max max a v v ma v a v a 10-4/c smbj16a/ca 1 16 17.8 1 26 23.1 34.4 116 8.8 1. pulse test : t p <50 ms. 2. to calculate v br or v cl versus junction temperature, use the following formulas: v br @t j =v br @25 c x (1 + t x (t j -25)) vcl@tj=v cl @25 cx (1 + t x (t j -25)) vbat gnd out rgnd dgnd gnd gnd clamp t smbj16a d 1n4002 gnd m 16v -25v + _ 41v (vclamp min) 25a 18a 7a (24v@18a) (ext. clamping active, hsd clamping active) demagnetization: (1v@18a) -24v switching inductive loads UM1556 60/87 doc id 023520 rev 2 choice 2) single pulse consideration in the second choice, we select a more powerful transil from the smcj series (st devices 1500 w@10/1000 s) with a more flat v cl /i pp characteristics: smcj18a: v cl = 23 v@25 a (estimated from v cl /i pp diagram) as seen in the datasheet, the selected device is able to fulfill the 24 v/25 a clamping requirement together with a safe stand-off voltage of 18 v (no conduction at reverse battery condition). it means that the hsd is fully protected and does not see any demagnetization energy. in addition to single pulse energy considerations, the ?repetitive energy capability? also needs to be checked. repetitive energy capability check (hsd cycling): assuming that the hsd is in a thermal shutdown condition with autorestart (frequency assumed to be ~500 hz) and i 0 = i liml 15 a. one pulse energy ? according to equation 17 : demagnetization time check equation 12 : average power dissipation on transil during hsd cycling ? equation 16 ): type i rm @v rm v br @ir min (1) v cl @i pp 10/1000 s v cl @i pp 8/20 s t (2) max min max max max a v v ma v a v a 10-4/c smcj18a/ca 1 18 20.0 1 29.2 53 39.3 254 9.2 1. pulse test : t p <50 ms. 2. to calculate v br or v cl versus junction temperature, use the following formulas: v br @t j =v br @25 c x (1 + t x (t j -25)) vcl@tj=v cl @25 cx (1 + t x (t j -25)) e v cl r 2 ------------- - lri 0 v cl ? v cl i 0 r ? + v cl --------------------------------- - ?? ?? ?? log ?? ?? == 23 0.6 2 ---------- - 0.00073 0.6 15 23 ? 23 15 0.6 ? + 23 -------------------------------- ?? ?? log ?? 65.5mj = ?? = t demag l r --- - v demag i 0 r ? + v demag ---------------------------------------------- - ?? ?? ?? log ? 0.00073 0.6 --------------------- 25 15 0.6 ? + 23 -------------------------------- ?? ?? log ? 0.4ms == = UM1556 switching inductive loads doc id 023520 rev 2 61/87 500*0.0655 = 32.8 w the calculated average power dissipation of 32.8 w is very high - clearly above the capability of standard transil diodes. therefore this protection can be used only if no pwm control is used and proper diagnostics is implemented to switch-off the hsd in case of overload. step 5 ? continued) external clamping selection (freewheeling diode) the following evaluation is conducted on circuitry with a freewheeling diode, as shown in figure 50 . in this case, the average power dissipation on the freewheeling diode is not so high. the demagnetization voltage is about -1 v, therefore most of the energy stored in the load inductance is dissipated in the load resistance (0.6 ). relatively slow demagnetization does not cause any problems when driving motors. figure 50. appropriate protection circuitry for vn5e025a with dc motor demagnetization time - equation 12 (assuming v demag = -1 v) : the freewheeling diode selection: ? reverse voltage > 52 v (must not conduct during positive voltage on the output maximum possible output voltage is limited by v hsdclampmax = 52 v) peak forward current: > 25 a @ 3.37 ms (i 0 @ t demag ) average power dissipation (repetitive turn-off) assuming that the hsd is in a thermal shutdown condition, with autorestart (frequency assumed to be ~500 hz) and i 0 = i liml ? 15 a. p avg fe ? = vbat out rgnd dgnd gnd gnd clamp iout gnd d pmos 4k7 15v gnd gnd m + _ 25a demag. phase - starting conditions: -1v 16v 0v t demag l r --- - v demag i 0 r ? + v demag ---------------------------------------------- - ?? ?? ?? log ? 0.00073 0.6 --------------------- 1250.6 ? + 1 ---------------------------- - ?? ?? log ? 3.37ms === switching inductive loads UM1556 62/87 doc id 023520 rev 2 energy dissipated in the freewheeling diode - equation 17 : (hsd turn off: i 0 = i liml = 15 a): demagnetization time for i 0 = i liml = 15 a - equation 12 : the demagnetization time (2.8 ms) is higher than the assumed hsd cycling frequency period (2 ms). therefore the average power dissipation on the freewheeling diode cannot be easily calculated using equation 16 : p avg =f.e ? 500 0.0136 = 6.8 w (real value is significantly lower). as a rough estimation, we can use the average power dissipation during one demagnetization pulse: 1n5401 (v rrm =100 v, i fsm =200 a@8.3 ms, p d = 6.25 w) step 6) measurement (confirmation of theoretical analysis) transil diode protection circuitry: smbj16a + 1n4002 the measurement was done at room temperature on vnd5e025ak loaded with a blocked dc motor (as specified in the beginning) and with external protection regarding choice 1) smbj16a + 1n4002: e v cl r 2 ------------- - lri 0 v cl ? v cl i 0 r ? + v cl --------------------------------- - log ?? ?? ?? ?? = ?? = 1 0.6 2 ----------- 0.00073 0.6 15 1 ? 1150.6 ? + 1 ---------------------------- - ?? ?? log ?? 13.6mj = ?? = t demag l r --- - v demag i 0 r ? + v demag ----------------------------------------------- ?? ?? ?? 0.00073 0.6 --------------------- 1150.6 ? + 1 ---------------------------- - ?? ?? log ? 2.8ms = = log ? = p avg e t demag ----------------------- - 0.0136 0.0028 ----------------- - 4.9w === UM1556 switching inductive loads doc id 023520 rev 2 63/87 figure 51. demagnetization energy measurement ? vnd5e025ak, motor, smbj16a and 1n4002 the measured energy is significantly lower than the calculated one (200 mj measured versus 260 mj calculated), while the demagnetization time fits well. this difference can be explained by measurement at ambient temperature when coil resistance is ~25 % higher than the resistance at -40 c used in the calculations. measured stall current was 19 a (versus 25 a specification at -40 c). as seen from the screenshot, the external clamping circuitry (smbj16a + 1n4002) limits the demagnetization voltage to -24 v, so the voltage across the hsd is maximum 39 v (below internal clamp activation). reverse battery test : the measured break down voltage of the external clamping circuitry is: -19 v@-1 ma fitting the -16 v@60 s reverse battery requirement. the transil diode failed (overheating) during hsd thermal shutdown cycling (as expected in theoretical calculation). freewheeling diode protection circuitry: 1n5401 the measurement was done at room temperature on vnd5e025ak loaded with a blocked dc motor (as specified in the beginning) and with external freewheeling diode 1n5401. gapgms00125 switching inductive loads UM1556 64/87 doc id 023520 rev 2 figure 52. demagnetization phase ? vnd5e025ak, dc motor (blocked), freewheeling diode 1n5401 the measured demagnetization time of 3.2 ms is very close to the calculated value (3.37 ms). due to the measurement at room temperature, the stall current was only 20 a (versus 25 a specified at -40 c). figure 53. repetitive demagnetization ? vnd5e025ak (tsd cycling), dc motor, 1n5401 i out v out v bat t demag = 3.2ms v demag = -1v gapgms00126 . i diode v out v bat p diode average power dissipation on freewheeling diode gapgms00127 UM1556 switching inductive loads doc id 023520 rev 2 65/87 the average power dissipation measured on the freewheeling diode is 3.2 w, while the hsd thermal shutdown cycling frequency was 188 hz. these values are below theoretical calculations. real hsd cycling frequency is much lower than the frequency assumed in the calculation (500 hz ? based on simulation with resistive load). conclusion: the demagnetization energy is two times higher than the device is able to withstand, therefore additional protection/clamping is necessary. two different external protection circuits were analyzed: transil and diode (smbj16a or smcj18a and 1n4002) the transil is not able to withstand the repetitive energy when the hsd is in a thermal cycling condition. therefore this protection can by used only if no pwm control is used and proper diagnostics is implemented to switch-off the hsd in case of overload. freewheeling diode (1n5401) and reverse battery protection circuitry with mosfet with this external protection circuitry, the repetitive energy capability requirement is also fulfilled. vbat gnd out rgnd dgnd gnd gnd clamp vout iout t d gnd m 16v -25v + _ 41v -24v 25a vbat out rgnd dgnd gnd gnd clamp iout gnd d pmos 4k7 15v gnd gnd m + _ 25a demag. phase - starting conditions: -1v 16v 0v high side driver selection for lamp loads UM1556 66/87 doc id 023520 rev 2 5 high side driver selection for lamp loads this chapter proposes drivers that can be used for typical automotive lamp loads or typical combinations of lamps. a properly selected driver should allow the safe turning on of the bulb without any restrictions under normal conditions. under worst case conditions, the driver should still be able to turn on the bulb even if some protection of the driver may be triggered temporarily. however, the driver?s long term integrity should not be jeopardized. in order to decide which driver is suitable to turn on a lamp, three conditions are first defined - see a), b) and c) below. afterwards a simulation is performed with the pre-selected bulb/driver combination, in order to verify the driver matches the requirements under the defined conditions. the tool used for this simulation is based on matlab/simulink. figure 54. principle of the setup used for the simulations the prerequisite to appear in ta ble 12 , tab le 13 , table 14 , ta ble 15 is that the driver has to fulfill all of the following three requirements: a) normal condition v batt = 13.5 v; t c = 25 c; t bulb = 25 c requirement: none of the protection functions must be triggered . gapgms00128 UM1556 high side driver selection for lamp loads doc id 023520 rev 2 67/87 b) cold condition v batt = 16 v; t c = 25 c; t bulb = -40 c requirement: power limitation allowed for durations of less than 20 ms. c) hot condition v batt = 16 v; t c = 105 c; t bulb = 25 c requirement: driver must not run into thermal shutdown. high side driver selection for lamp loads UM1556 68/87 doc id 023520 rev 2 note: the mentioned criteria only refer to the inrush current at turn-on of a cold bulb. the steady state power dissipation and, in case pwm is applied, the additional switching losses of the driver also have to be considered in order not to exceed the maximum possible power dissipation. this obviously becomes more important with a larger number of channels per package (i.e. dual or quad channel drivers) and high power loads applied to more than one channel. table 12. list of suggested bulb/driver combinations(1/4) bulb load [w] driver ron [m ] single channel part # dual channel part # quad channel part # 65 10 12 16 vn5010ak vn5e010ah vn5012ak vn5016aj vn5e016ah vnd5012ak vnd5e012ay UM1556 high side driver selection for lamp loads doc id 023520 rev 2 69/87 60 10 12 16 vn5010ak vn5e010ah vn5012ak vn5016aj vn5e016ah vnd5012ak vnd5e012ay 55 10 12 16 vn5010ak vn5e010ah vn5012ak vn5016aj vn5e016ah vnd5012ak vnd5e012ay table 12. list of suggested bulb/driver combinations(1/4) (continued) bulb load [w] driver ron [m ] single channel part # dual channel part # quad channel part # table 13. list of suggested bulb/driver combinations(2/4) bulb load [w] driver ron [m ] single channel part # dual channel part # quad channel part # 3x27 + 7 10 12 16 vn5010ak vn5e010ah vn5012ak vn5016aj vn5e016ah vnd5012ak vnd5e012ay 2x27 + 7 12 16 25 27 vn5012ak vn5016aj vn5e016ah vn5025aj vn5e025aj vnd5012ak vnd5e012ay vnd5025ak vnd5e025ak vnq5027ak high side driver selection for lamp loads UM1556 70/87 doc id 023520 rev 2 27 + 7 25 27 vn5025aj vn5e025aj vnd5025ak vnd5e025ak vnq5027ak 27 25 27 50 vn5025aj vn5e025aj vn5e050aj vnd5025ak vnd5e025ak vnd5e050j/aj vnd5e050k/ak vnq5027ak vnq5e050k/ak table 13. list of suggested bulb/driver combinations(2/4) (continued) bulb load [w] driver ron [m ] single channel part # dual channel part # quad channel part # table 14. list of suggested bulb/driver combinations(3/4) bulb load [w] driver ron [m ] single channel part # dual channel part # quad channel part # 3x21 + 5 10 12 16 25 27 vn5010ak vn5e010ah vn5012ak vn5016aj vn5e016ah vn5025aj vn5e025aj vnd5012ak vnd5e012ay vnd5025ak vnd5e025ak vnq5027ak 2x21 + 5 16 25 27 vn5016aj vn5e016ah vn5025aj vn5e025aj vnd5025ak vnd5e025ak vnq5027ak UM1556 high side driver selection for lamp loads doc id 023520 rev 2 71/87 21 + 5 25 27 50 vn5025aj vn5e025aj vn5e050j/aj vnd5025ak vnd5e025ak vnd5e050j/aj vnd5e050k/ak vnq5027ak vnq5e050k/ak 21 25 27 50 vn5025aj vn5e025aj vn5050j/aj vn5e050j/aj vnd5025ak vnd5e025ak vnd5050j/aj vnd5050k/ak vnd5e050j/aj vnd5e050k/ak vnq5027ak vnq5050k/ak vnq5e050k/ak table 14. list of suggested bulb/driver combinations(3/4) (continued) bulb load [w] driver ron [m ] single channel part # dual channel part # quad channel part # table 15. list of suggested bulb/driver combinations(4/4) bulb load [w] driver ron [m ] single channel part # dual channel part # quad channel part # 10 50 160 vn5050j/aj vn5e050j/aj vn5e160s/as vnd5050j/aj vnd5050k/ak vnd5e050j/aj vnd5e050k/ak vnd5e160j/aj vnq5050k/ak vnq5e050k/ak vnq5e160k/ak 7160 vn5160s vn5e160s/as vnd5160j/aj vnd5e160j/aj vnq5160k/ak vnq5e160k/ak 5160 vn5160s vn5e160s/as vnd5160j/aj vnd5e160j/aj vnq5160k/ak vnq5e160k/ak paralleling of hsds UM1556 72/87 doc id 023520 rev 2 6 paralleling of hsds 6.1 paralleling of cs_dis (current sense disable) and in (input) the following chapters describe the paralleling of cs_dis and in pins of hsds, taking into account device technology (monolithic hsds or hybrid hsds) and supply line configuration (either the same or separate supply lines for each hsd). direct connection of cs_dis or in pins is generally allowed with devices designed with the same technology (monolithic or hybrid) supplied from one supply line. in all other cases (like the combination of monolithic with hybrid technology or different supply lines, or both), we should use additional components to ensure safe operation under conditions in automotive environments (iso pulses, reverse battery ?). the clamp structure on the cs_dis pin is the same as on the in pin, therefore all the explanations related to the paralleling of the cs_dis pins are also applicable to paralleling of in pins. 6.1.1 monolithic hsds supplied from different supply lines paralleling cs_dis pins of monolithic hsds is possible, however some precautions in schematics should be applied if the hsds are supplied from different supply lines. in this case, the direct connection of cs_dis pins (as shown in figure 55 ) is not safe. figure 55. direct connection of cs_dis pi ns (not recommended) ? monolithic hsd direct connection of cs_dis pins is not safe in following cases: negative voltage surge on either on vbat1 or vbat2 positive voltage surge either on vbat1 or vbat2 while: ? device gnd pin disconnected; ? dgnd not used (resistor protection only); ? positive pulse energy higher than hsd (or d gnd ) capability - all paralleled devices can be damaged 1 h j d w l y h , 6 2 s x o v h 9 e d w 9 & / $ 0 3 9 & 6 & / ' ! 0 ' - 3 UM1556 paralleling of hsds doc id 023520 rev 2 73/87 a negative voltage surge (iso7637-2 pulse 1, 3a) either on vbat1 or vbat2 is directly coupled to the hsd gnd pin through the involved vcc-gnd clamp structure. as soon as this occurs and the negative voltage on gnd pin is large enough to activate all involved clamp structures, there may be an unlimited current flow through both cs_dis pins (supported by current from vcc through the associated parasitic bipolar structure). this current can lead to malfunction or even failure of one or both of the hsds. a positive voltage surge (iso7637-2 pulse 2a, 3b) either on vbat1 or vbat2 may lead to the hsd gnd pin to rise in voltage (in case of missing dgnd, dgnd failure or gnd pin disconnected). as soon as this occurs, the voltage on cs_dis pin also rises (the cs_dis pin clamp structure is linked with the gnd). if the voltage on the cs_dis line reaches ~6.3 v (clamp voltage on cs_dis pin) there may be an unlimited current flow through both cs_dis pins (supported by current from vcc through the associated parasitic bipolar structure). this current can lead to malfunction or even failure of one or both of the hsds. in order to avoid such failures add a 10 k resistor in series to each cs_dis pin (see figure 56 ). in principle, the same applies to the input pins (the clamp structure is the same as on the cs_dis pin). figure 56. proper connection of cs_dis pins 6.1.2 hybrid hsds supplied from different supply lines paralleling of cs_dis pins of hybrid hsds is possible, however some precautions in schematic should be applied if the hsds are supplied from different supply lines. direct connection of cs_dis pins (as shown in figure 57 ) is not safe. gapgms00133 paralleling of hsds UM1556 74/87 doc id 023520 rev 2 figure 57. direct connection of cs_dis pins (not recommended) ? hybrid hsd direct connection of cs pins is not safe in the following cases: loss of gnd connection if the gnd connection of one device is lost, positive as well as negative iso pulses on the associated supply line are no longer clamped (considering no other devices are connected to this supply line). if the transient voltage is large enough to activate involved clamp structures, there may be unlimited current flow between both supply lines through the cs_dis pins. this current can lead to malfunction or even failure of one or both of the hsds. in order to avoid such failures, add a 10 k resistor in series to each cs_dis pin (as already described in case of monolithic devices ? see figure 6.1.1: monolithic hsds supplied from different supply lines on page 72 ). in principle, the same applies to the input pins (the clamp structure is the same as on the cs_dis pin). 6.1.3 mix of monolithic and hybrid hsds paralleling of cs_dis pins of monolithic and hybrid hsd is possible, however some precautions in schematics must be applied. the direct connection of cs_dis pins (as shown in figure 58 ) is not safe (even if we consider the same power supply for both devices). , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 5 h y h u v h % d w 3 u r w 3 z u & o d p s 8 , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 5 h y h u v h % d w 3 u r w 3 z u & o d p s 8 * 1 ' * 1 ' 9 e d w * 1 ' q ) 9 9 e d w * 1 ' q ) 9 * 1 ' 5 v h q v h n q ) * 1 ' * 1 ' 5 v h q v h n q ) * 1 ' n x & b , 2 / r v v r i * 1 ' 3 r v l w l y h , 6 2 s x o v h ! 9 & / $ 0 3 9 & 6 & / ' ! 0 ' - 3 UM1556 paralleling of hsds doc id 023520 rev 2 75/87 figure 58. direct connection of cs_dis pins (not recommended) ? mix of monolithic and hybrid hsd direct connection of cs pins is not safe in the following cases (single supply line considered): reverse battery negative iso pulse due to the different concepts of reverse battery protection of hybrid and monolithic devices, there is a way for unlimited current flow between both devices in case of reverse battery conditions. the hybrid device has an integrated reverse battery protection in the vcc line, while the monolithic device needs an external diode/resistor in series with the gnd pin (refer to section 1.2: reverse battery protection ). the different potential on each gnd pin (hybrid: ~ 0 v, monolithic: vbat - 0.7 v) leads to the activation of both cs_dis clamp structures when v bat is below ~ -7.5 v (v cscl and two diode voltage drop). the resulting current can lead to malfunction or even failure of one or both of the hsds. in order to avoid such failure, add a 10 k resistor in series to each cs_dis pin (as already described in case of paralleling of monolithic devices ? see figure 6.1.1: monolithic hsds supplied from different supply lines on page 72 ). in principle, the same applies to the input pins (the clamp structure is the same as on cs_dis pin). 6.2 paralleling of cs pins (current sense) the following chapters describe the paralleling of cs pins of hsds, taking into account device technology (monolithic hsds or hybrid hsds) and supply line configuration (either the same or separate supply line for each hsd). direct connection of cs pins is generally allowed when the devices are supplied from one supply line. in case of separated supply lines, we should use additional components to ensure a safe operation under conditions in automotive environments (iso pulses, reverse battery ?). , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 5 h y h u v h % d w 3 u r w 3 z u & o d p s 8 * 1 ' 9 e d w * 1 ' q ) 9 * 1 ' q ) 9 * 1 ' 5 v h q v h n q ) * 1 ' * 1 ' 5 v h q v h n q ) * 1 ' n x & b , 2 5 j q g n ' j q g * 1 ' , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 8 5 h y h u v h e d w w h u \ f r q g l w l r q r u q h j d w l y h , 6 2 s x o v h ' ! 0 ' - 3 paralleling of hsds UM1556 76/87 doc id 023520 rev 2 6.2.1 monolithic hsds supplied from different supply lines paralleling cs pins of monolithic hsds is possible, however some precautions in schematics should be applied if the hsds are supplied from different supply lines. direct connection of cs pins (as shown in the next picture) is not safe. figure 59. direct connection of cs pins (not recommended) ? monolithic hsd direct connection of cs pins is not safe in following cases: negative voltage surge on either on vbat1 or vbat2 positive voltage surge either on vbat1 or vbat2 while: ? device gnd pin disconnected; ? dgnd not used (resistor protection only); ? positive pulse energy higher than the hsd (or dgnd) capability - all paralleled devices can be damaged loss of vbat1 or vbat2 a negative voltage surge (iso7637-2 pulse 1, 3a) either on vbat1 or vbat2 is directly coupled to the cs pin through the internal vcc-cs clamp structure. if the negative voltage on the cs line is high enough to activate the vcc-cs clamp structure, there may be an unlimited current flow through both cs pins. this current can lead to malfunction or even failure of one or both of the hsds. a positive voltage surge (iso7637-2 pulse 2a, 3b) either on vbat1 or vbat2 together with missing dgnd (dgnd not used, dgnd failure or gnd pin disconnected) can activate the vcc- cs clamp structure (clamp voltage similar to vcc-gnd clamp). as soon as this occurs there may be an unlimited current flow through both cs pins. this current can lead to malfunction or even failure of one or both of the hsds. loss of either vbat1 or vbat2 leads to an incorrect current sense signal. if vbat2 is lost, u2 (and other components connected to vbat2) is supplied by u1 current sense signal through the internal vcc-cs clamp structure. therefore, the voltage on cs bus drops to almost 0v resulting in an invalid v sense reading. ' ! 0 ' - 3 UM1556 paralleling of hsds doc id 023520 rev 2 77/87 in order to protect the devices during iso pulses and to ensure a valid current sense signal, we can add a diode in series to each cs pin (as shown in the following schematics). in order to suppress the rectification of noise injected to the sense line, add a ceramic filter capacitor between each cs pin and ground. however, the voltage drop on diodes in series with the cs pin can have an influence on the dynamic range of current sense, temperature and current sense accuracy. figure 60. safe solution for paralleling cs pins 6.2.2 hybrid hsds supplied from different supply lines paralleling cs pins of hybrid hsds is possible, however some precautions in schematics should be applied if the hsds are supplied from different supply lines. direct connection of cs pins (as shown in the next picture) is not safe. in logic out cs cs_dis gnd vcc u2 rgnd 1k dgnd gnd gnd rsense vbat2 gnd 100nf/50v in logic out cs cs_dis gnd vcc u1 vbat1 gnd 100nf/50v rgnd 1k dgnd gnd 100..470pf 100..470pf gnd gnd gnd adc_in paralleling of hsds UM1556 78/87 doc id 023520 rev 2 figure 61. direct connection of cs pins (not recommended) ? hybrid hsd direct connection of cs pins is not safe in following cases: loss of vbat1 or vbat2 loss of gnd connection loss of either vbat1 or vbat2 leads to an incorrect current sense signal. if vbat2 is lost, u2 logic part is supplied by u1 current sense signal through the internal vcc-cs clamp structure. therefore the voltage on cs bus drops and we no longer have an accurate v sense reading. if the gnd connection of one device is lost, positive as well as negative iso pulses on the associated supply line are no longer clamped (considering no other devices connected on this supply line). if the transient voltage is high enough to activate involved clamp structures, there may be an unlimited current flow between both supply lines through the cs pins. this current can lead to malfunction or even failure of one or both of the hsds. in order to ensure a valid current sense signal and to protect devices in all previously described cases, we can add a diode in series to each cs pin (as previously described in the case of monolithic devices ? see section 6.2.1: monolithic hsds supplied from different supply lines ). 6.2.3 mix of monolithic and hybrid hsds supplied from different supply lines paralleling cs pins of monolithic and hybrid hsds is possible, however some precautions in schematics should be applied if the hsds are supplied from different supply lines. direct connection of cs pins (as shown in figure 62 ) is not safe. in logic out cs cs_dis gnd vcc reverse bat. prot. pwr clamp u2 in logic out cs cs_dis gnd vcc reverse bat. prot. pwr clamp u1 gnd gnd vbat1 gnd 100nf/50v vbat2 gnd 100nf/50v gnd rsense gnd adc_in UM1556 paralleling of hsds doc id 023520 rev 2 79/87 figure 62. direct connection of cs pins (not r ecommended) ? mix of monolithic and hybrid hsd direct connection of cs pins is not safe in following cases: negative iso pulse on vbat2 loss of vbat1 or vbat2 loss of gnd connection a negative voltage surge (iso7637-2 pulse 1, 3a) on vbat2 is directly coupled to the cs pin through the internal vcc-cs clamp structure. if the negative voltage on the cs line is high enough to activate the vcc-cs clamp structure, there may be an unlimited current flow through both cs pins. this current can lead to malfunction or even failure of one or both of the hsds. loss of either vbat1 or vbat2 leads to an incorrect current sense signal. if vbat2 is lost, u2 logic part is supplied by u1 current sense signal through the internal vcc-cs clamp structure. therefore the voltage on cs bus drops, resulting in an inaccurate v sense reading. if the gnd connection of one device is lost, positive as well as negative iso pulses on the associated supply line are no longer clamped (considering no other devices connected to this supply line). if the transient voltage is high enough to activate the involved clamp structures, there can be an unlimited current flow between both supply lines through the cs pins. this current can lead to malfunction or even failure of one or both of the hsds. in order to ensure a valid current sense signal and to protect devices in all previously described cases, we can add a diode in series to each cs pin (as previously described in the case of monolithic devices ? see previous section 6.2.1: monolithic hsds supplied from different supply lines ). , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 8 5 j q g n ' j q g * 1 ' * 1 ' 5 v h q v h 9 e d w * 1 ' q ) 9 9 e d w * 1 ' q ) 9 * 1 ' * 1 ' $ ' & b , 1 , 1 / r j l f 2 8 7 & 6 & 6 b ' , 6 * 1 ' 9 f f 5 h y h u v h % d w 3 u r w 3 z u & o d p s 8 / r v v r i 9 e d w , v h q v h 9 v h q v h l q i o x h q f h g ' ! 0 ' - 3 esd protection UM1556 80/87 doc id 023520 rev 2 7 esd protection 7.1 esd protection of hsd ? calculations the esd robustness of a typical m0-5 hsd is rated at 5000 v on the output- as well as vcc- pin according to the human body model (100 pf, 1.5 k ). this applies to positive as well as negative esd pulses. for any esd pulse beyond these values, external protection is required. calculation of the energy capability of the hsd output without external protection (negative esd pulse) the energy content of the esd pulse is: equation 19 the energy dissipated by the resistance is: equation 20 the energy dissipated by the hsd is: equation 21 the maximum esd pulse energy capability of the hsd can be calculated using equation 21 and the data sheet parameters (typical example): esd discharge resistance clam ping structur e in hsd v eds 1 2 -- - c esd v 2 esd ?? = w r 1 2 -- - c esd v esd v demag ? () 2 ?? = w hsd v ( esd v demag ) v clamp c esd ?? ? = w hsdmax 4954v 46v 100pf 23 ? j ?? = UM1556 esd protection doc id 023520 rev 2 81/87 calculation of external protection (negative esd pulse) when the esd pulse amplitude or the esd capacitance is increased or the discharging resistance is decreased, the hsd needs external protection because the energy discharged in the hsd exceeds the limit calculated in equation 21 . if we add a ceramic capacitor on the output, the esd pulse initially only charges the capacitor without impacting the hsd until the voltage reaches the hsd active clamping voltage. then the voltage stays constant (without further impact on the capacitor), and excessive energy is absorbed by the esd discharge resistance and by the hsd. if in the first step we neglect the hsd, the final voltage becomes: equation 22 with v esd =8 kv, c esd =330 pf and f final =50 v, c ext should be >53 nf. since the hsd can absorb some esd energy on its own, the external capacitor can actually be smaller. the time t 1 defines the point in time when the external capacitor reaches the demagnetisation voltage of the hsd and does not charge further. the time constant for discharging the esd capacitor is: equation 23 with c ext >>c esd esd discharge cap esd discharge resistance esd capacitor on hsd output esd discharge resistance clamping str ucture in hsd v final v esd c esd c esd c ext + ------------------------------------- ?? ?? ?? ? = r esd c esd c ext c ext c esd + ------------------------------------- ?? = r esd c esd ? esd protection UM1556 82/87 doc id 023520 rev 2 equation 24 equation 25 equation 26 equation 27 the residual voltage at the esd capacitor when the external capacitor is charged to the hsd clamping voltage becomes: equation 28 therefore the energy absorbed by the hsd becomes: equation 29 once we know the maximum esd energy capability of the hsd (calculated with equation 21 ), we can calculate the necessary external capacitor: equation 30 it () v esd r esd --------------- e t ? ---- ? = v c esd t () v esd e t ? ---- ? v final + 1e t ? ---- ? ?? ?? ?? ? = v c ext t () v final 1e t ? ---- ? ?? ?? ?? ? = t 1 ? 1 v demag v final ------------------------ ? ?? ?? ?? log ? = v c esd (t1) v esd v demag c ext c esd --------------- ? ? = w hsd v esd v demag ? 1 c ext c esd --------------- + ?? ?? ?? ? ?? ?? ?? v clamp c esd ?? = c ext v esd v demag ? v demag --------------------------------------------- - c esd w hsdmax v demag v clamp ? ------------------------------------------------ ? ? > UM1556 esd protection doc id 023520 rev 2 83/87 of course, the external capacitor needs a voltage capability larger than the maximum clamping voltage of the hsd. in addition, it must be ensured that the esd discharge current cannot exceed the maximum current capability of the hsd: equation 31 and therefore equation 32 example 1: contact discharge 8 kv, 330 pf, 2 kw, i limh max =14 a (vnx5e160 hsd), battery not supplied (vcc=0 v) according to equation 30 c ext > 46 nf according to equation 32 c ext > -143 nf c ext > 46 nf fulfils both requirements. example 2: contact discharge 6 kv, 150 pf, 330 , battery not supplied (vcc=0 v) according to equation 30 : c ext > 9 nf according to equation 32 : c ext > 4.4 nf c ext > 9 nf fulfils both requirements. positive esd pulses without external protection a positive esd pulse on the output is transferred through the body diode of the power mosfet to the vcc pin of the hsd, stressing the vcc-gnd clamping structure. the esd ratings of the vcc-gnd clamping structure is the same for the output clamping structure. it 1 () i limhmax < ? ? () v demag ------------------------------------------------------------------------ 1 ? ?? ?? ?? ? > esd protection UM1556 84/87 doc id 023520 rev 2 therefore the same considerations and calculations apply for negative esd pulses on the output. positive esd pulses with external protection a positive esd pulse on the output is transferred through the body diode of the power mosfet to the vcc pin of the hsd,so the same requirements to dimension the external capacitor apply as the negative esd pulses on the output. 7.2 esd protection ? ecu level (layout consideration) an esd pulse on a powered ecu output connector is an expected event during the life of a car. typically, contact and air discharge tests are performed during module qualification. (ref. iec61000-4-2). the possible risk at application level is an early failure of the hsd with a following resistive short circuit between vcc and out. the esd pulse destruction value strongly depends on the module layout. to make the module pass the required stress level, add a 100 v ceramic capacitor with a value in the order of tens of nf to the output close to the connector. this capacitor decreases both the applied dv/dt and the maximum output voltage seen by the hsd. esd dischar ge r esistance clamping structure in hsd esd dischar ge capacitor body diode of power moseft vcc UM1556 robust design doc id 023520 rev 2 85/87 8 robust design 8.1 design suggestions for hsds and relays on the same pcb a typical ecu today still employs, along with the smart power hsds and lsds, a certain number of electromechanical relays. the activation of these relays, being on the same pcb and supplied by the same battery line as the hsds, may lead to fast dv/dt on the battery line due to bouncing of the contacts when inductive loads are driven. even a standard high frequency capacitor (typ. value 100 nf) across the local battery and ground is not enough to smoothen these pulses. the possible risk at application level is an early failure of the hsd with a following resistive short between vcc and out. in order to avoid this, add a free- wheeling diode across the inductive load terminals (see below diagram) in order to minimize the effects of the relay bouncing. some suggestions above those already mentioned to help render the hsds less sensitive when used with relays on the same board are: a) the usage of four-layer pcbs where the inner layers are used as low resistance shields (one should be connected to module gnd, the other to the battery connector); b) the cs pin circuitry as recommended in the datasheet; c) the use of separate connectors to supply the hsds. revision history UM1556 86/87 doc id 023520 rev 2 9 revision history table 16. document revision history date revision changes 01-aug-2012 1 initial release. 18-sep-2013 2 updated disclaimer UM1556 doc id 023520 rev 2 87/87 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com |
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