. ,. analog w devices preliminary technical data features 3.4tls acquisition time short 35ns aperture delay :to.005% maximum linearity error high input impedance: >107q dtl/ttl compatible compact module: 1 1/8" x 2" x 0.4" (29 x 51 x 10mm) 8 general description the sha1134 is a moderately fast, general purpose sample- and-hold amplifier which has been optimized for use in data acquisition applications with lz-bit analog-to-digital converters when in the "sample" mode, the module appears as a fast amp- lifier with a 3 .ztls settling time to :to.o 1 % accuracy. when switched to the "hold" mode, the output is held at a level corresponding to the input signal voltage at the instant of swit- ching. the operating mode of the shall 34 is controlled by a ttl/dtl compatible logic input. the sha1l34 features an aperture delay time of 35ns and an aperture delay time uncertainty, or "jitter", of zns. the droop rate of 50mv/s makes it suitabl~ for operation with virtually all successive approximation aid converters. package size for this compact module is liz" x z" x 0.4" (z9 x 51 x 10mm). it needs no adjustments and requires only :t15v external power for operation. principle of operation the shaii34 consists basically of two high speed operational amplifiers, a storage capacitor, and a digitally controlled switch connected in a feedback loop as shown below. 'n~'~ a1 - i + mode i a2 "'""oc 0-- - - - - - - - - ~ 00,,"," figure 1. sha 1134 basic configuration 8 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implica- tion or otherwise under any patent or patent rights of analog devices. general purpose sample-and-hold amplifier when the mode control input is shifted to logic" 1", the switch closes, causing the capacitor voltage and output voltage to match the input voltage. in addition to providing input buffer- ing, amplifier al supplies the current needed to quickly char~ the storage capacitor in this mode of operation. the high gain feedback loop contributes to high tracking accuracy. when the mode control is shifted back to logic "0", the switch opens and the output remains fixed at a voltage equal to the voltage "stored" across the capacitor. the low input current of amplifier a2 and the low "off" leakage current of the field- effect-transistor switch minimize the leakage of the capacitor's charge and, thus, the "droop" in the output voltage. amplifier az provides the sha1134 with low output impedance and good current drive capabil ity. route 1 industrial park; p.o. box 280; norwood, mass. 02062 tel: 617/329-4700 twx: 710/394.6577 west coast mid-west texas 213/595-1783 312/894-3300 214/231-5094 - - ~___n obsolete
specifications (typical @+25c and :t15v, unless otherwise noted) 0 o' sha1134 model accuracy gain gain error gain temperature coefficient gain nonlinearity . static input characteristics voltage range for rated accuracy impedance bias current input offset voltage temperature coefficient supply coefficient output characteristics voltage current resistance capacitive load noise @ 100khz bandwidth @ imhz bandwidth sample mode dynamics frequency response small signal (-3db) full power slew rate settling time to :to.oi % (20v step) overload recovery (50% overload) +1 :to.036% (0.04% max) 6.5ppm/c (10ppm/c max) :to.ooi % (:to.005% max) :tiov max >1o7q 0.5p.a max 0.5mv (1.5mv max) 135p.v/c (200p.v/oc max) 20p.v/%b.vs oop.v/%b.vs) :tiov :t5ma max 0.05q 1o0pf max o.3mv (0.5mv max) 1.8mv (2.2mv max) 800khz 600khz 15v/p.s 3.2p.s (4.0p.s max) 0.6p.s (ip.s max) sample-to-hold switching aperture delay time aperture uncertainty offset step offset linearity switching transient amplitude settling time to :to.oi % hold mode dynamics droop rate variation with temperature feedthrough (for :tiov input @ 1khz) hold-to-sample switching acquisition time to :to.oi % 35ns (sons max) 2ns (5ns max) 3.3mv (5.5mv max) :t3mv :t70m v ip.s :t50mv/s (:t200mv/s max) doubles every looc 1.0mv (2.0mv max) digit at input sample mode (logic "i") 3.4p.s (4.ip.s max) hold mode (logic "0") power required +2v ~ logic "1" ~ +5.5v @ lsna max ov ~ logic "0" ~ +0.8v @ 5p.a (20p.a max) +i5v :t3% @ +20ma -i5v :t3% @ -i7ma temperature range operating storage price (1-9) 0 to +70oc -55 to +85c $99 $75 specifications subject to change without notice. -2- outline dimensions and pin connections dimensions shown in inches and (mm). t ~ 0.41 max (10.4~ --- ~min (6.35) ' 1.15 max ~ (29.21) -10.26 t "~' 2.03 max (51.56) 1.80 (45.72) bottom view i i 0.1 grid --1 t- (2.54) notes: 1. pins: 0.019 to.001 (0.48mm 1:0.02mm) dia. half-hard brass, gold plated per mil-g-45204b, class i, type ii. 2. mating socket ac4102 @ $15, or pin sockets pin 2-330808-8 (7 required). $.20 ea. pin designations 1. analog ground 2. -15v 3. +15v 4. n.c. 5. n.c. 6. signal in 7. control in 8. logic ground 9. n.c. 10. n.c. 11. no pin 12. analog output 13. no pin 14. n.c. block diagram . 8 11~ 21~ 310-- 4 [ 0 5 0 .---- 0 14 0 12 0 10 0 9 8 8 obsolete
. data acquisition application successive-approximation aid converters can generate substan- tiallinearity errors if the analog input varies during the period of conversion; even the fastest 12-bit models available cannot tolerate input signal frequencies of greater than 10hz. for this reason, sample-and-hold amplifiers like the shaii34 are often connected between the aid and its signal source to hold the analog input constant during conversion. when the shaii34 is connected to an aid, its aperture time uncertainty, rather than the aid's conversion time, is the fac- tor which limits the allowable input signal slew rate. the shaii34, with a typical aperture delay time of 35ns and an uncertainty of 2ns, will change from the sample mode to the hold mode b to 35ns after the "1" to "0" transition of the mode control input. if the system timing is so arranged as to initiate the mode control signal bns early, thenswitching will actually occur within 2ns of the desired time as shown below. v - sha input signal -- sha output signal analog input/output signals t_--- =- -~ =-1-= -=-_-:- output uncertainty aperture uncertainty (2n51 sha1134 mode ii ;////// sa~~~e. 'i/// ~ hold ~"\: ~~ i 33n5 1 ~ desired switching point e sha1134 mode control input figure 2. aperture uncertainty the maximum allowable slew rate will thus equal the quotient of the maximum allowable vdltage uncertainty and the 2ns aperture uncertainty. for sinewave inputs, the corresponding maximum frequency is expressed by: 6e 1 6e fmax = (-) (~) == 8 x 107 (-) efs 21tut efs where: 6e = the allowable voltage uncertainty e fs = the sinewave magnitude for a system containing a shaii34 and a 12-bit aid with :tiov input signals and an allowable input uncertainty of :t\l2lsb (:t2.44mv), the maximum allowable slew rate will be :t1.22 v i~s. this corresponds to the maximum rate of change of a 19.5 khz sinewave signal. 8 . operation with an aid converter figure 3 below shows the appropriate connections between the shaii34 and a successive approximation aid converter in block diagram form. sha1134 analog to oigital input converter } oigital output input input output mode control status convert cdmmand convert jl.. command figure 3. sha 1134 and aid connections the resulting timing sequence at the start of conversion is illus- trated in figure 4. sha1134 input/ output signals i ~/'/i """"""""""----- ~ ii i '/. sample ~ '\""""~ """\:' h'o'ld ~"""""""""""""""""\: ii i n l i i i 1 --1 ~ "':f d"'" - ". switching transient settling ~ 1115 -- input - output sha1134 mode convert command status output/ mode control input 1 0 1 0 figure 4. aid and sha timing at start of conversion note that the leading edge of the convert command pulse causes the converter's status output to go to logic "0" which in turn switches the shaii34 from sample to hold. as discussed previously, the typical shall 34 actually changes modes b to 35ns after the "1" to "0" transition of the mode control input. t:his mode switching causes a transient on the output terminal which decays to within 0.01 % of the final value in approx- imately i~s. once the transient has settled, the convert com- mand input is returned to logic "0" and the conversion proceeds. as shown in figure 5, the status signal returns to logic" 1 " and the shai134 returns to the sample mode at the end of conversion. within 3 .4~s, it will have acquired the input signal to 0.01 % accuracy and a new conversion cycle may be started. sha1134 input/ output signals -- input - output sha1134 mode i i 1 i i ~ hold w////~ sample /?// ////4 i~_-l- acquisition ~ time ~ 3.4115 f status output/ 1 mode control input 0 figure 5. aid and sha timing at end of conversion .3- ~ obsolete
operation with an aid and multiplexer the subsystem of figure 3 may also be connected to a multi- plexer like analog devices' model mpx-8a as shown below: channel 1 input i i i i i i i i i channel "nput convert commano input mpx'a sha1134 a!o converter ] oigital output output input output input mooe control status status figure 6. aid, sha, and mpx connections the leading edge of the convert command pulse sets the status output to logic "0" thereby switching the shai134 to "hold"; the corresponding change to logic "1" of the st atus output increments the binary counter and changes the multiplexer address. since the sha1134's aperture time is small with respect to the multiplexer switching time, it will have switched to the hold mode before the mpx-8a actually changes channels. the multiplexer switching transients will settle out long before the sha returns to "sample" at the end of conversion. the timing sequence described above is illustra- ted in figure 7. multiplexer output! sha input sha ,,34 mode sha output! aid input channel being digitized ",:!. t ow.. -iov f :v. channel i channel 2 - channel 3 - figure 7. aid, sha, and mpx timing this method of sequencing the multiplexer may be altered to permit random addressing or addressing in a preset pattern. the timing of multiplexer address changes may also be altered but consideration should be given to the effects of feed through in the sha1134. feedthrough is the coupling of analog input sig- nals to the output terminal while the sha is in "hold". for the shaii34, a 20v pop input signal will typically produce a imv signal at the output. if large multiplexer switching trans- ients occur while the aid conversion is in progress, errors can be introduced. throughput rate the rate at which the systems of figures 3 and 6 can perform conversions will, of course, depend on the conversion time of the aid converter used. the table below lists the minimum system throughput rates achievable with several of analog devices' 12-bit successive approximation aid converters. aid converter minimum system throughput rate adc12qz adc12qm adc12qu adcll02 adcl1o3-003 22.1khz 33.1khz 49.6khz 74.0khz 115.6khz power supply and grounding connections the proper power supply and grounding connections are shown bel()w in figure 8. ct15v +5v +15 com -15 +5 com to digital logic 10l1f 35v '+ 10l1f .+35v figure 8. power supply and grounding connections the :t15v power supplies must be externally bypassed as shown. the capacitors should be tantalum types and should be installed as close to the, module pins as possible. the analog and digital ground lines should be run separately to their respective power supply commons to prevent coupling of digital switching noise to the sensitive analog circuit section. -4- - ~~ ~ . l!) ,.... ~ 0 m "" m u 8 z 0 w f- z cc cl. 8 convert ---1l n n command 6a;eug;;!'nput ---, n n r mul tiplexer chi' +8v i ch2, -iov i ch 3, +3v i ch4, ov channel analog gnd 2 0 -15v 3 8 +15v dig gnd obsolete
|
