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| AS3953 14443 high speed passive tag interface www.ams.com revision 1.0 1 - 42 1 general description the AS3953 nfc interface ic (nfic) delivers low cost, ultra low power nfc forum functionality to multiple different applications. the AS3953 is a analog front-end with integrated 14443a data framing and spi interface. it is designed to create a fast data link between an iso 14443a reader device (pcd) and a microcontroller. the AS3953 is passively powered meaning that it can be supplied from the pcd magnetic field, eliminating the need of a continual external supply. this makes the AS3953 perfect for wireless communication to a low- power battery powered device. the AS3953 is used with an appropriate antenna coil connected to the terminals lc1 and lc2, and behaves as a normal passive iso 144443a tag (picc). after the anti-collision protocol is passed, the pcd sends a wake-up command, which wakes up the microcontroller by sending an interrupt. from this point onwards, the AS3953 serves as a data link between the microcontroller and the pcd. AS3953 can also operate as nfcip-1 target at 106 kb/s. the AS3953 includes an onboard eeprom that can be accessed either from the pcd or from the microcontroller via the spi interface. this built-in flexibility makes it ideal for two types of applications: ?? where personalization data is programmed by the pcd (even in case the spi side is not powered) and it is later read by microcontroller through spi interface. ?? where log data is stored periodically by the microcontroller and can then be read by the pcd even when the microcontroller is not powered. a regulated power supply voltage extracted from the pcd field is also available on a pin and can be used as power supply for external circuitry. for example, an external microcontroller and a sensor could be powered from the pcd field combined with pass through data rates up to 848kbps, which means the AS3953 is ideal for contactless passive programming of mcu systems. the AS3953 can also operate as a stand-alone iso 14443a tag. the AS3953 supports iso 14443a up to level-4, meaning a contactless smart card or an nfc forum compatible tag (tag type 4) can be built. having a nfc forum compatible tag interface allows the AS3953 to be used in an application where a standard nfc enabled phone is used as a pcd. 2 key features ?? iso 14443a compliant to level-4 ?? nfcip-1 target at 106 kb/s ?? 1k bit eeprom (928 bits of user memory) ?? configurable wake-up interrupt (after tag is selected or using proprietary command) ?? powered from external magnetic field with the possibility to draw up to 5ma ?? 7 byte uid ?? user configurable regulated voltage extracted from external magnetic field ?? bit rates from 106 kbps till 848 kbps ?? integrated resonant capacitor ?? integrated buffer capacitor ?? 4-wire serial peripheral interface (spi) with 32 byte fifo ?? wide spi power supply range (1.65v to 3.6v) ?? wide temperature range: -40oc to 85oc ?? available as wlcsp 10-bumps (future delivery options: 10-pin mlpd (3x3mm) and gold bumped dies) 3 applications the device is ideal for applications like passive wake-up, multipurpose hf interface to a controller, low power or passive programming, ultra low power data logger, rfid programmable configuration eeprom, iso 14443a smart card, nfc forum tag type 4, and bluetooth and wi-fi pairing. figure 1. AS3953 block diagram lc1 lc2 vss vp_spi spi power manager eeprom por level shifters vp_reg vdd AS3953 afe vp_int irq logic
www.ams.com revision 1.0 2 - 42 AS3953 datasheet - contents contents 1 general description ......................................................................................................... ......................................................... 1 2 key features................................................................................................................ ............................................................. 1 3 applications................................................................................................................ ............................................................... 1 4 pin assignments ............................................................................................................. .......................................................... 4 4.1 pin descriptions.......................................................................................................... .......................................................................... 5 5 absolute maximum ratings .................................................................................................... .................................................. 6 6 electrical characteristics.................................................................................................. ......................................................... 7 6.1 operating conditions...................................................................................................... ...................................................................... 7 6.2 dc/ac characteristics for digital inputs and outputs...................................................................... .................................................... 7 6.3 electrical specification.................................................................................................. ........................................................................ 8 7 detailed description........................................................................................................ .......................................................... 9 7.1 circuit ................................................................................................................... ................................................................................ 9 7.2 picc afe.................................................................................................................. ........................................................................... 9 7.3 power manager ............................................................................................................. ..................................................................... 11 7.4 iso 14443a framing mode................................................................................................... ............................................................. 11 7.5 iso 14443a level-4 protocol mode.......................................................................................... ......................................................... 12 7.5.1 coding of uid ........................................................................................................... ................................................................. 12 7.5.2 coding of atqa, sak and ats ............................................................................................. ................................................... 13 7.6 proprietary commands...................................................................................................... ................................................................. 15 7.6.1 passing of block data to controller ..................................................................................... ...................................................... 17 7.6.2 use of cid .............................................................................................................. ................................................................... 17 7.7 iso 14443a level-3 protocol mode.......................................................................................... ......................................................... 17 7.8 transparent mode .......................................................................................................... .................................................................... 18 7.9 eeprom.................................................................................................................... ........................................................................ 18 7.9.1 uid word ................................................................................................................ ................................................................... 18 7.9.2 fabrication data word................................................................................................... ............................................................ 18 7.9.3 configuration word...................................................................................................... .............................................................. 19 7.9.4 otp words .............................................................................................................. ................................................................. 21 7.9.5 write lock word ......................................................................................................... ............................................................... 21 7.9.6 read lock word .......................................................................................................... .............................................................. 21 8 application information ..................................................................................................... ...................................................... 22 8.1 spi interface............................................................................................................. .......................................................................... 22 8.1.1 writing of data to addressable registers (register write mode).......................................................... .................................... 23 8.1.2 reading of data from addressable registers (register read mode) ......................................................... .............................. 24 8.1.3 writing and reading of eeprom through spi ............................................................................... ......................................... 24 8.1.4 loading transmitting data into fifo..................................................................................... .................................................... 25 8.1.5 reading received data from fifo ......................................................................................... .................................................. 25 8.1.6 direct command mode..................................................................................................... ......................................................... 26 8.1.7 spi timing .............................................................................................................. ................................................................... 26 8.1.8 interrupt interface ..................................................................................................... ................................................................. 28 8.1.9 fifo water level and fifo status register............................................................................... .............................................. 28 8.1.10 iso 14443a frame data in fifo .......................................................................................... .................................................. 29 8.2 direct commands........................................................................................................... .................................................................... 29 8.2.1 set default ............................................................................................................. .................................................................... 29 8.2.2 clear ................................................................................................................... ....................................................................... 29 www.ams.com revision 1.0 3 - 42 AS3953 datasheet - contents 8.2.3 transmit................................................................................................................ ..................................................................... 29 8.2.4 go2halt ................................................................................................................. ..................................................................... 29 8.3 registers ................................................................................................................. ........................................................................... 30 8.3.1 overview of registers................................................................................................... ............................................................. 30 8.3.2 io definition register.................................................................................................. ............................................................... 30 8.3.3 mode definition registers............................................................................................... ........................................................... 31 8.3.4 display registers....................................................................................................... ................................................................ 32 8.3.5 interrupt register and associated registers ............................................................................. ................................................ 33 8.3.6 definition of number of transmitted bytes ............................................................................... ................................................. 36 9 package drawings and markings ............................................................................................... ............................................ 37 10 ordering information....................................................................................................... ...................................................... 41 www.ams.com revision 1.0 4 - 42 AS3953 datasheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) miso vp_reg sclk vss lc2 mosi lc1 vp_spi irq /ss 10 9 8 7 6 12 34 5 0 test AS3953 gold bumped die (bottom view) irq lc2 mosi sclk /ss vp_spi vp_reg lc1 miso vss a3 b3 a2 b2 a1 b1 c1 b4 c4 a4 AS3953 wl-csp (top view) AS3953 mlpd (top view) 10 9 8 7 6 5 4 3 2 1 irq miso mosi sclk /ss vp_spi vp_reg lc1 lc2 vss gnd www.ams.com revision 1.0 5 - 42 AS3953 datasheet - pin assignments 4.1 pin descriptions table 1. pin descriptions pin number pin name pin type description mlpd wl-csp gold bumped die - - 0 test internal use no connection 1 c4 1 vp_spi supply pad positive supply of spi interface 2 b4 2 vp_reg analog output regulator output 3b3 3 lc1 analog i/o connection to tag coil 4b2 4 lc2 5 c1 5 vss supply pad ground, die substrate potential 6a1 6 /ss digital input serial peripheral interface enable (active low) 7b1 7 sclk serial peripheral interface clock 8a2 8 mosi serial peripheral interface data input 9 a3 9 miso digital output / tristate serial peripheral interface data output 10 a4 10 irq digital output interrupt request output (active high) 11 - - exposed pad supply exposed pad to be connected to ground (optional) www.ams.com revision 1.0 6 - 42 AS3953 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 7 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings symbol parameter min max units comments electrical parameters v dd dc supply voltage -0.5 5 v v in input pin voltage except lc1 and lc2 -0.5 5 v input pin voltage pins lc1 and lc2 -0.5 6.5 v peak current induced on pins lc1 and lc2 100 ma i scr input current (latchup immunity) -100 100 ma norm: jedec 78 electrostatic discharge esd electrostatic discharge 2 kv norm: mil 883 e method 3015 (human body model) temperature ranges and storage conditions t strg storage temperature -55 125 oc t body package body temperature 260 oc norm: ipc/jedec j-std-020 the reflow peak soldering temperature (body temperature) is specified according ipc/jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is ?matte tin? (100% sn) humidity non-condensing 585% msl moisture sensitivity level for mlpd 3 moisture sensitivity level for wl-csp 1 t strg_dof storage time for dof/dies or wafers on foil 3 months refer to indicated date of packing t strg_dof storage temperature for dof/dies or wafers on foil 18 24 oc rh open_dof relative humidity for dof/dies or wafers on foil in open package 15 % opened package rh unopen_dof relative humidity for dof/dies or wafers on foil in closed package 40 60 % unopened package www.ams.com revision 1.0 7 - 42 AS3953 datasheet - electrical characteristics 6 electrical characteristics all in this specification defined tolerances for external components need to be assured over the whole operation conditions ran ge and also over lifetime. 6.1 operating conditions 6.2 dc/ac characteristics for digital inputs and outputs cmos inputs. valid for input pins /ss, mosi, sclk cmos outputs. valid for output pins miso, irq symbol parameter min typ max units note i lim limiter current 30 ma till this current limiter clamps vlc1-lc2 to 5.0v v vp_spi spi power supply 1.65 3.6 v when logic powered from rfid interface 1.8 3.6 v when logic powered from vp_spi interface t amb ambient temperature -40 85 oc symbol parameter min typ max units note v ih high level input voltage 0.7 * vp_spi v v il low level input voltage 0.3 * vp_spi v i leak input leakage current 1 a symbol parameter min typ max units note v oh high level output voltage 0.9 * vp_spi v i source = 1ma vp_spi = 3v v ol low level output voltage 0.1 * vp_spi v c l capacitive load 50 pf r o output resistance 200 400 r pd pull-down resistance pad mosi 10 k pull-down can be enabled while miso output is in tristate. the activation is controlled by register setting www.ams.com revision 1.0 8 - 42 AS3953 datasheet - electrical characteristics 6.3 electrical specification vp_spi = 3.0 v, temperature 25oc unless noted otherwise symbol parameter min typ max units note i sb_spi standby consumption on vp_spi 100 na @ 25oc v lim limiter voltage 5.2 5.8 v i lc = 30ma (dc) i s supply current 250 a internal supply current measured in test mode on vrec, 13.56 mhz alternative pulses with amplitude 2vpp, negative peak at vss, forced to lc1 and lc2 v vp_reg regulated supply voltage 1.65 1.8 2.01 v set to 1.8v in eeprom configuration word v hf_pon hf_pon threshold (rising vreg) 2.3 v guaranteed by design only v por_hy hf_pon hysteresis 0.8 v v mod modulator on voltage drop 1.2 v i lc = 1ma 2.6 i lc = 30ma c r resonance capacitor for die 25.2 28 30.8 pf measured at 10mhz, 3.0vpp (2.5vpp) guaranteed by design resonance capacitor for mlpd package 38.2 31.3 34.4 resonance capacitor for wl-csp package 27 30 33 ee en eeprom endurance 100 000 cycles @ 125oc ee ret eeprom retention 10 years www.ams.com revision 1.0 9 - 42 AS3953 datasheet - detailed description 7 detailed description figure 3. system block diagram 7.1 circuit the AS3953 is composed of iso 14443a picc analog front-end (pic c afe), the iso 14443a picc logic (picc logic), eeprom, spi interface, level shifters and power supply manager block (power manager). the picc afe is connected to an external tag coil, which forms together with integrated resonant capacitor an lc tank with a re sonance at the external electromagnetic field frequency of 13.56 mhz. the picc afe has a built in rectifier and regulators. output of internal regulator is called vp_int. it is used to supply the picc afe and usually also the logic and eeprom (through power supply manager). output of exter nal regulator vp_reg is available on a pin to supply some external circuitry. power manager is controlling power supply of logic and eeprom. th e two blocks can be supplied either from vp_int or from vp_spi (spi power supply). in order to save current on vp_spi, vp_int is used as power supply whenever it is available. vp_spi is only used when some activity is started over the spi and the vp_reg is too low to be used as a power supply. the picc logic is responsible for picc-to-pcd communication up to the level-4 (block transmission) of iso 14443a. this means th at anti- collision and other low-level functionality are implemented there. the spi interface logic contains a 32 byte fifo for block transmission data which is exchanged on level-4 of iso 14443a communi cation. it also contains some control and display registers. the eeprom is used to store the uid, the housekeeping data (c onfiguration and control bits) and user data. it can be accessed f rom both sides (rfid and spi). 7.2 picc afe figure 4 depicts main picc afe building blocks. the picc afe is connected to external tag coil, which together with the integrated resonant capacitor forms an lc tank with res onance at external electromagnetic field frequency (13.56 mhz). figure 4 depicts the main picc afe building blocks. rectifier: extracts dc power supply from ac voltage induced on coil terminals. limiter: limits the maximum voltage on coil terminals to protect picc afe from destruction. at voltages that exceed limiter voltage it s tarts to absorb current (acts as some sort of shunt regulator). modulator switch: is used for communication picc-to-pcd. when switched on, it will draw current from coil terminals. this mechanism is called load modulation. variation of current in the modulator switch (on and off state) is seen as modulation by the pcd. demodulator: is used for communication picc-to-pcd. it detects am modulation of the pcd magnetic field. the demodulator is designed to accept modulation according to iso 14443a; all standard bit rates from 106 kb/s to 848 kb/s are supported. the modulation for b it rate 106 kb/s is 100%, whereas for other bit rates it may be less. iso 14443a reader AS3953 microcontroller spi www.ams.com revision 1.0 10 - 42 AS3953 datasheet - detailed description clock extractor: the clock extractor extracts a digital clock signal from the pcd carrier field frequency which is used as clock signal by logic blocks. hf_pon: observes rectified regulated voltage vrec. when the supply voltage is sufficiently high it enables operation of the picc afe an d the digital tag logic. a buffer capacitor and hf_pon hysteresis guarantees that there is no reset during reader (pcd) modulatio n. internal regulator: provides regulated voltage vp_int to the picc afe and in most cases also to eeprom and logic blocks. typical regulated voltage vp_int is 2.0v. a buffer capacitor is also integrated. external regulator: provides regulated voltage on external pin vp_reg where it can be used to supply some external circuitry. the regulated voltage and output resistance c an be adjusted using eeprom settings (see table 6) . appropriate external buffer capacitor is needed in case vp_reg is used in the application. the current to be provided depends on reader field strength, antenna size and q fact or, but it is limited to maximum 5ma. bias: provides bias currents and reference voltages to picc afe analog blocks. figure 4. picc afe block diagram hf pon rectifier modulator switch limiter demodulator clock extractor lc1 lc2 iso 14443 a logic external regulator bias vp_reg internal regulator vp_int vrec AS3953 www.ams.com revision 1.0 11 - 42 AS3953 datasheet - detailed description 7.3 power manager power manager is controlling the positive supply voltage of the picc logic, eeprom and spi interface (vdd). its inputs are vp_i nt (rectified and regulated supply extracted from pcd field) and the vp_spi (spi power supply from external). in standby mode, when the AS3953 is not in a pcd field (condition is that rectified supply voltage is below hf_pon threshold) a nd the spi is not active (/ss is high) the vdd supply is disconnected not to consume on vp_spi. the only consumption on vp_spi is leakage of leve l shifters and spi pins. when the AS3953 is placed in a pcd field the vdd is connected to vp_int. this happens once the vp_int level is above the hf_pon threshold. vp_spi is connected to vdd only when the AS3953 is not in the pcd field (rectified supply voltage is below hf_pon threshold) an d the spi interface is activated by pulling /ss signal low. the switch to vp_spi is controlled by /ss signal. the deactivation is delayed by 0.7ms min., thus the switch stays on in case the time between successive spi acti vations shorter. during eeprom wr iting, which is activated over the spi, the switch is also active. at activation of the switch the time between the falling edge of /ss signal and rising edge of sclk has to be at least 50s to allow charging of internal vdd buffer capacitor and expiration of por signal. please note that the only spi operations, which are allowed in this mode, are reading and writing of the eeprom and registers. figure 5. power manager concept 7.4 iso 14443a framing mode when framing mode is selected the picc logic performs receive and transmit framing according to the selected iso 14443a bit rat e. during reception it recognizes the sof, eof and data bits, performs parity and crc check, organizes the received data in bytes and places them in the fifo. during transmit, it operates inversely, it takes bytes from fifo, generates parity and crc bits, adds sof and eof and performs data encoding. default bit rate in the framing mode is fc/128 (~106 kb/s). higher data rates may be configured by controller by writing the bit rate definition register . in order to respect the pcd-to-picc frame delay according to iso14443-3 at data rate fc/128 bit the picc logic synchronizes the response to the beginning of the next response window, but not earlier than window with n=9. in this mode the eeprom can be accessed via spi when the rf field is active. delay vp_int vp_spi vdd pon /ss eeprom write www.ams.com revision 1.0 12 - 42 AS3953 datasheet - detailed description 7.5 iso 14443a level-4 protocol mode when level-4 protocol mode is selected the picc logic autonomously execute complete iso 14443a level-3 communication and certai n commands of level-4. this also includes the anti-collision sequence during which the AS3953 uid number is read by the pcd (7 by tes uid is supported), the AS3953 is brought in the selected state (iso14443-4) in which data exchange between the AS3953 and the pcd can start. on this level also a reading and writing of the AS3953 eeprom is possible. in case the configuration bit irq_l4 is set an interrupt is automatically sent to controller once the picc logic enters in active(*) state (after sending sak on cascade level 2). support of iso 14443a level-4. iso 14443a-4 commands rats , pps and deselect are implemented in the picc logic. rats and pps define communication parameters, which are going to be used in the following data exchange by using the block transmission protocol. the advantage of implementi ng pps that defines the bit rate used for communication, is that all bit rate issues are handled by the picc logic. the mcu gets the inform ation about the actual receive and transmit bit rate by reading a dedicated display register. it has to be fast enough to serve receive and tra nsmit at the maximum bit rate. execution of the block transmission protocol is left to the controller. in case of receiving the block data from the pcd the pi cc logic provides support by detecting and removing start bit, stop bit, parity bits and crc. parity bits and crc are also checked. when the bloc k data is sent to the pcd the picc logic calculates and inserts start bit, parity bits, crc and stop bit. deselect puts the picc logic in halt state. an interrupt is sent to controller upon reception of deselect command to inform it that pcd stopped the level-4 communication. additionally to supporting the iso14443-4 transmitting protocol t he picc logic accepts also proprietary commands. proprietary c ommands are identified by setting the two msb bits of first transmitted byte to ?01? (this combination is not used by iso 14443a level-4 pr otocol). the following custom commands are implemented: ?? wake-up: sends a wake-up interrupt to controller ?? read eeprom: reads data from eeprom ?? write eeprom: writes data to eeprom support of iso 14443a optional features. ?? cid is supported ?? nad is not supported ?? historical bytes are not supported ?? power level indication is not supported 7.5.1 coding of uid anti-collision procedure is based on unique identification number (uid). the AS3953 supports double uid size (7 bytes). first t hree bytes of uid are hard-wired inputs to the picc logic ( uid<23:0> ). last 4 bytes of uid are stored in eeprom uid word. first byte of uid (uid0). first byte of uid is according to [iso3] iso/iec 7816-6 ic manufacturer id. it is coded on bits uid<7:0> . ams ic manufacturer id is 3f(hex). second byte of uid (uid1). second byte of uid ? uid<15:8> is reserved for ams chip type (ic type). every ams rfid tag ic has its own chip type attributed. therefore pcd which has read the rfid tag uid knows to which tag ic it is talking. the AS3953 ic type is 10(hex). www.ams.com revision 1.0 13 - 42 AS3953 datasheet - detailed description third byte of uid (uid2). third byte of uid ? uid<23:16> is set to 00(hex). table below defines the coding of the first three bytes of uid. the last 4 bytes of uid are read from eeprom (uid word ). table below defines the last four bytes of uid. 7.5.2 coding of atqa, sak and ats several bits of responses atqa, sak and at s are defined as ?don?t care? in the iso 14443a standard. some others are defined by optional choices in standard protocol. this section defines how these bits are set by the AS3953. atqa. atqa is response to reqa and wupa commands. table below defines the atqa coding. bits b16 to b13 are rfu bits which must be set to ?0?. bits b12 to b9 are proprietary coding and are set to ?0?. bits b8 and b7 indicate double size uid. bit b6 is ?rfu? bit and is set to ?0?. for bit frame anti-collision, the code 00100 is chosen. sak. sak is response to select command. AS3953 uid has double size, which defines sak responses for cascade level 1 and cascade level 2. ?? cascade level 1: according to iso 14443-3, all bits except b3 are ?don?t care? for cascade level 1. table below defines cascade level 1 coding. ?? cascade level 2: according to iso 14443-3 all bits except b6 and b3 are ?don?t care? for cascade level 2. if configuration bit16 [nl4] is set to logic ?0? (default state), the sak on cascade level 2 reports that tag is compliant to level4 (see table below). if configuration bit16 [nl4] is set to logic ?1?, the sak on cascade level 2 reports that tag is not compliant to level-4 (s ee table below). uid byte fl signal name value (hex) uid0 uid<7:0> 3f uid1 uid<15:8> 10 uid2 uid<23:16> 00 uid byte uid word bits uid3 b7-b0 uid4 b15-b8 uid5 b23-b16 uid6 b31-b24 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0000000001000100 uid size bit frame anti-collision b8 msb b7 b6 b5 b4 b3 b2 b1 lsb description 00000100casc ade bit set: uid not complete b8 msb b7 b6 b5 b4 b3 b2 b1 lsb description 00100000 uid complete, tag is compliant to iso/iec14443-4 b8 msb b7 b6 b5 b4 b3 b2 b1 lsb description 00000000 uid complete, tag is not compliant to iso/iec14443-4 www.ams.com revision 1.0 14 - 42 AS3953 datasheet - detailed description if configuration bit15 [nfc] is set to logic ?1?, the sak on cascade level 2 reports that tag is nfc passive target (see table below). ats. ats is response to iso 14443-4 command rats . the content of the ats is used to inform the pcd about picc capability (like the maximum frame size, support of higher bit rates, etc.) several response fields of ats are stored in eeprom configurati on word. the AS3953 ats is composed of following 5 bytes accordi ng to [iso4]: tl, t0, ta(1), tb(1) and tc(1). ?? tl: this is the length byte. since ats is composed of 5 bytes, its content is 0x05. table below defines the coding of the tl byte. ?? t0: this is the format byte. table below defines the coding of the t0 byte. bit b8 is set to ?0?. bits b7 to b5 indicate presence of bytes ta(1), tb(1) and tc(1) and hence are all set to ?1?. bits b4 to b1 are called fcsi and codes fcs. the fcs is maximum size of a frame defined by picc. it is defined by configuration bits fsci<3:0> . ?? ta(1): this codes the bit rate capability of picc. supported higher bit rates of AS3953 are 212, 424 and 848 kb/s. however in specifi c applications, it is advised to report lower capability to pcd (for example, due to the usage of slow controller or low power ap plication). due to this reason the ta(1) response is configurable using configuration bits. bit b8 set to ?0? codes possibility of having different data rates for each direction. ?? tb(1): the interface byte tb(1) conveys information to define the frame waiting time and the start-up frame guard time. the interface byte tb(1) consists of two parts: - the most significant half-byte b8 to b5 is called fwi and codes frame waiting time (fwt). - the least significant half byte b4 to b1 is called sfgi and codes a multiplier value used to define the sfgt. the sfgt defines a specific guard time needed by the picc before it is ready to receive the next frame after it has sent the ats. sfgi is coded in the rang e from 0 to 14. the value of ?0? indicates ?no sfgt needed?. the sfgt bits are fixed to default value which is 0x0, while the fwi bits are defined by configuration bits fwi<3:0> . table below defines the coding of the tb(1) byte. b8 msb b7 b6 b5 b4 b3 b2 b1 lsb description 01000000 uid complete, tag is compliant to nfcip-1 transport protocol b8 msb b7 b6 b5 b4 b3 b2 b1 lsb description 0 0 0 0 0 1 0 1 coding of ats byte tl b8 msb b7 b6 b5 b4 b3 b2 b1 lsb description 0 1 1 1 fsci<3> fsci<2> fsci<1> fsci<0> coding of ats byte t0 tc(1) tb(1) ta(1) fcsi b8 msb b7 b6 b5 b4 b3 b2 b1 lsb description dr_sdr dr_picc_8 dr_picc_4 dr_picc_2 0 dr_pcd_8 dr_pcd_4 dr_pcd_2 coding of ats byte ta(1) ds (picc to pcd) dr (pcd to picc) b8 msb b7 b6 b5 b4 b3 b2 b1 lsb description fwi<3> fwi<2> fwi<1> fwi<0> 0 0 0 0 coding of ats byte tb(1) fwi sfgi www.ams.com revision 1.0 15 - 42 AS3953 datasheet - detailed description ?? tc(1): the interface byte tc(1) specifies a parameter of the protocol. the interface byte tc(1) consists of two parts: - the most significant bits b8 to b3 are set to 000000, all other values are ?rfu?. - the bits b2 and b1 define which optional fields in the prologue field are supported by the picc. the pcd is allowed to skip fields that are supported by the picc. bit b2 indicates support of cid and b1 indicates support of nad. the AS3953 value is ?10? indicating ?cid supported? and ?nad not supported?. table below defines the coding of the tc(1) byte. 7.6 proprietary commands proprietary commands have the same format as blocks defined in iso 14443-4 with the difference that optional nad field is aband oned since nad is not supported by the AS3953. the same format is used for commands sent by pcd and AS3953 responses. table below defines the coding of the proprietary commands. prologue field consists of the mandatory protocol control byte and an optional card identifier byte. card identifier byte is ac cording to iso 14443-4 definition. epilogue field contains crc over transmitted block. prologue field for proprietary commands. table below defines the coding of prologue field for proprietary commands. the following proprietary commands are implemented: ?? wake-up: sends a wake-up interrupt to controller ?? read eeprom: reads data from eeprom ?? write eeprom: writes data to eeprom wake-up command. information field of wake-up command consists of one byte only (see table below). the AS3953 echoes back the same information field. table below defines the coding of the AS3953 reply inf to wake-up command. b8 msb b7 b6 b5 b4 b3 b2 b1 lsb description 0 0 0 0 0 0 1 0 coding of ats byte tc(1) cid nad prologue field information field epilogue field pcb [cid] inf edc 1 byte 1 byte 2 bytes bit value function b8 0 01 indicates proprietary command b7 1 b6 0 shall be set to this value, other values are ?rfu? b5 1 b4 cid following if bit is set to ?1? b3 1 shall be set to this value, other values are ?rfu? b2 0 b1 1 01h 1byte 01h 1byte www.ams.com revision 1.0 16 - 42 AS3953 datasheet - detailed description word address byte. both proprietary commands related to eeprom (read and write) use word address byte to define the address of eeprom word that is accessed. seven msb bits of the address byte are used to define the address, while the last bit is ?don?t care?. note: the valid range for the word address byte is from 0000 000xb to 0011 111xb (eeprom words from 00h to 1fh). read eeprom. the read eeprom command is used to read data from the eeprom. the reques t information field contains the following three bytes ? - command code byte (02h) - address of the first word to be read - number of words to be read table below defines coding of read eeprom command information field. if the request is normally processed, the reply information field contains the status word 90h followed by the data. in case of error, the information field only contains the error status byte. the following rules apply: ?? in case the number of words to be read is higher than 8, first eight words are read. ?? in case the read protected word (its read lock bit is set) is accessed, an all ?0? data is sent out. ?? in case the reading starts at valid address and the number of words to read is such that the reading would be done beyond the e eprom addressing space, all ?0? data is returned for non-existing addresses. ?? in case the reading starts at non-existing address, error information field is returned. table below defines the coding of the AS3953 reply information field to read eeprom command, if command is normally processed. table below defines the coding of the AS3953 reply information field to read eeprom command, in case of an error. write eeprom. the write eeprom command is used to write one eeprom word (32 bits). the request information fi eld contains 6 bytes ? - command code byte (04h) - address of the word to be written - four bytes (32 bits) of data to be written table below defines coding of write eeprom command information field . the AS3953 reply contains one byte informing whether the writi ng of eeprom was executed or whether there was an error. prior to actual programming of data in eeprom, the control logic checks whether there is enough power available. this is done by performing so called power check during which a dummy eeprom programming is started. if t he power check fails, eeprom programming is not performed and an error code is sent. the eeprom programming is a ti me consuming operation. therefore, if the eeprom programming is executed, the as395 3 reply comes after 8ms typical. table below defines the coding of the AS3953 reply to write eeprom command. 02h address of first word to be read number of words ( 8) to be read 1byte 1byte 1byte 90h data 1byte 4 to 32 bytes information field comment 61h error (no diagnostic) 04h address of word to be written data 1 byte 1 byte 4 bytes information field comment 90h writing is normally processed 61h writing is not done due to coding error (error in parity, crc, nonexistent address?) 62h writing is not done since the word is locked 64h writing is not done due to power check fail www.ams.com revision 1.0 17 - 42 AS3953 datasheet - detailed description 7.6.1 passing of block data to controller after the picc logic has passed the anti-collision procedure and re plied with sak on cascade level 2 it passes in active(*) sta te. on this level it expects that blocks received from the pcd have the format according to iso 14443a-4. the iso 144443a logic recognizes the co mmand by observing the first received byte. based on content of this byte command is either processed by the AS3953 or the complete bloc k data is put in the fifo for further processing by the controller. the table below displays the decision criteria. as shown in table 3 , the block data is put in the fifo whenever the two msb bits are 00 or 10 and also in the case when the four msb bits are 1111. therefore the implemented communication between the pcd and a tag implemented by the AS3953 and a controller does not nee d to follow the block transmission protocol defined in the iso 14443-4. 7.6.2 use of cid as mentioned above the AS3953 decides depending on content of the first byte of received message to either execute received mes sage as a command or to put it in the fifo. the second byte of the message comprises a cid number which is attributed by pcd. pcd will us e cid number in case more piccs are brought to level-4 of communication at the same time. cid is only checked for messages (commands) that are executed by the AS3953. in case cid does not match such a command is rejec ted (no action is taken). messages that are based on first byte are put in fifo and are not filtered by cid. it is left to controller to check for the ci d and decide whether or not to reply (cid number is stored in the rats register ). 7.7 iso 14443a level-3 protocol mode level-3 protocol mode is intended for implementation of custom protocols for which coding on level-4 of iso 14443a communicatio n according to table 3 is not appropriate. in this mode level-2 and level-3 behavior of the picc logic is identical to iso 14443a level-4 protocol mo de, while on level-4 all received data blocks are put in fifo. in case the configuration bit irq_l4 is set an interrupt is automatically sent to controller once the picc logic enters in active(*) state (after sending sak on cascade level 2). in this mode the eeprom can be accessed via spi when the rf field is active. table 3. first byte of the iso 14443-4 pcd block first byte comment action of picc logic 1110 0000 rats replies with ats 1 1. rats and pps are only processed by the AS3953 logic in case they are sent according to the iso 14443-4 specification ( rats is first command sent after entry in active(*) state, optionally followed by pps ). in case rats or pps are sent once the AS3953 logic is in protocol state the information received is saved into fifo and not acted upon. 1110 not(0000) block is put in fifo 1101 xxxx pps replies with pps response (second character is cid) 1 1100 x 010 deselect replies and go to halt 1100 x not(010) (see footnote 2) block is put in fifo 1111 xxxx wtx, s(parameters), rfu 2 2. compatible with old and new s(parameters) definition: old: 1100 x000 is s(parameters) block according to the iso 14443-4/ am2. new: 1111 x000 is s(parameters) block according to the modification sc17/wg8. block is put in fifo since controller needs it to implement chaining 01xx xxxx proprietary command proprietary command is processed 00xx xxxx i-block block is put in fifo 10xx xxxx r-block www.ams.com revision 1.0 18 - 42 AS3953 datasheet - detailed description 7.8 transparent mode in the transparent mode the AS3953 logic is bypassed, afe input and output signals are directly available on spi interface pins when /ss signal is high. ?? modulator switch is controlled by pin mosi (high is modulator on) ?? clock extractor output is sent to pin miso ?? demodulator output is sent to pin irq when /ss signal is low the spi interface pins resume its normal functionality. in this mode the eeprom can be accessed via spi when the rf field is active. 7.9 eeprom the AS3953 contains an eeprom bl ock which can be accessed from both rfid and spi interface. eeprom cont ains 1024 bits (128 byte s) organized in 32 words of 32 bits. words in eeprom are number from 0 to 31(1f[hex]). bits in a word are numbered from 0 to 31. most of the eeprom is used to store user data (27 words ? 864 bits), five words are used to store some housekeeping information (part of the AS3953 uid, configuration bits which define the AS3953 operating options, lock bits, which control the possibility to write eep rom words). access properties: ro: read only, writing to this word is not possible rw: reading and writing to this word is possible, writing is disabled once the lock bit is set otp: one time programmable. a bit of this word once set to ?1? cannot be set back to ?0?. 7.9.1 uid word the uid word contains four lsb bytes of 7 byte uid which is used during anti-collision and selection process. every ic is progr ammed by a unique number during fabrication process at ams . for details on uid, please refer to coding of uid on page 12 . 7.9.2 fabrication data word this word stores some ic manufacturer data which is programmed and locked during fabrication process at ams . table 4. eeprom organization word address [hex] content access properties 0uid ro 1 fabrication data ro 2 configuration word rw 3 write lock word otp 4 read lock word otp 5 : : : : : : 1f user data rw www.ams.com revision 1.0 19 - 42 AS3953 datasheet - detailed description 7.9.3 configuration word the configuration word is used to define the AS3953 operating options. it is delivered by ams with default setting. notes: 1. configuration bits b31 to b15 define AS3953 response to sak and ats command in iso 14443a protocol modes, while bits b14 to b0 actually change performance. 2. incase both nl4 and nfc are set, the nl4 setting prevails. table 5. configuration word (bits 31 to 16) configuration bit name default function b31 fsci<3> 0 fsci. default value (2h) codes maximum size of frame accepted by picc to 32 bytes which is the size of the fifo. please note that the AS3953 can support larger frame sizes in case fifo is read during the receiving. b30 fsci<2> 0 b29 fsci<1> 1 b28 fsci<0> 0 b27 fwi<3> 0 fwi (default value (6h) defines frame waiting time of ~19.3ms) b26 fwi<2> 1 b25 fwi<1> 1 b24 fwi<0> 0 b23 dr_sdr 0 1: only the same bit rate for both directions supported (ta(1) of ats) b22 dr_picc_8 0 1: dr=8 picc-to-pcd supported (848kb/s) (ta(1) of ats) b21 dr_picc_4 0 1: dr=4 picc-to-pcd supported (424kb/s) (ta(1) of ats) b20 dr_picc_2 0 1: dr=2 picc-to-pcd supported (212kb/s) (ta(1) of ats) b19 dr_pcd_8 0 1: dr=8 pcd-to-picc supported (848kb/s) (ta(1) of ats) b18 dr_pcd_4 0 1: dr=4 pcd-to-picc supported (424kb/s) (ta(1) of ats) b17 dr_pcd_2 0 1: dr=2 pcd-to-picc supported (212kb/s) (ta(1) of ats) b16 nl4 0 1: sak on cascade level 2 reports that tag is not iso 14443-4 compatible b15 nfc 0 1: sak on cascade level 2 reports t hat tag is nfc passive target www.ams.com revision 1.0 20 - 42 AS3953 datasheet - detailed description notes: 1. configuration bits b31 to b15 define AS3953 response to sak and ats command in iso 14443a protocol mode, while bits b14 to b0 actually change performance. 2. applicable in iso 14443a level-3 and level-4 protocol modes. 3. applicable in iso 14443a level-3 protocol mode and framing mode, in protocol mode applicable for frames which are put in fi fo. 4. configuration bits fdel<1:0> are used to adjust frame delay time pcd-to-picc. delays caused by reader and tag resonant tanks and afe processing are compensated by picc logic.table below defines pcd-to-picc frame delay compensation using fdel bits. table 6. configuration word (bits 14 to 0) configuration bit name default function b14 irq_pu 0 1: send a power-up irq (after power-up initialization is finished) b13 irq_l4 0 1: send an irq at entry in active(*) state (after sending sak on cascade level 2) (see note 2) b12 mod_1 0 00: iso 14443a level-4 protocol mode 01: iso 14443a level-3 protocol mode 10: framing mode 11: transparent mode b11 mod_0 0 b10 rxncrc 0 1: rx ? crc is not checked, crc part of message is also put in fifo (see note 3) b9 rxbs 0 1: rx ? bit stream mode, received bits are put in fifo (no parity and crc check) (see note 3) b8 txncrc 0 1: tx ? do not generate crc (see note 3) b7 txbs 0 1: tx ? bit stream mode, bits put in fifo are sent without parity and crc generation (see note 3) b6 fdel<1> 0 pcd-to-picc delay adjustment (see note 4) b5 fdel<0> 0 b4 vreg<1> 0 00: 1.8v 10: 2.7v 01: 2.0v 11: 3.3v external regulated voltage (vp_reg) setting b3 vreg<0> 0 b2 rreg<1> 0 00: disabled 10: 50 01: 100 11: 25 external regulator enable and output resistance setting b1 rreg<0> 0 b0 dr8 0 reserved for internal use fdel<1:0> delay [ns] delay [number of 13.56 mhz periods] 00 442.5 6 01 295.0 4 10 147.5 2 11 590.0 8 www.ams.com revision 1.0 21 - 42 AS3953 datasheet - detailed description 7.9.4 otp words write and read lock words are otp (one time programmable). this means that once they are set to ?1?, they cannot be reset back to ?0?. since setting of otp bits is an irreversible operation, it is strongly recommended to perform it in controlled environment. 7.9.5 write lock word the write lock word contains write lock bits. each eeprom word has a corresponding lock bit in the write lock word. once a cert ain lock bit is set to ?1?, the content of corresponding word cannot be m odified any more (it becomes read only), eeprom write commands issu ed either through picc interface or through spi interface are rejected. the lock bit of a certain number protects the word with the same number (e.g. b5 of lock word protects word 5). since lock bits are otp they cannot be reset back to ?0? once they are set to ?1?.therefore once a certain word is locked it cannot be unlocked any more. the lock bits for page 0 is ?don?t care? since word 0 is always read only. please note t hat setting lock bit b2 locks the lock word itself, therefore once this bit is set the lock configuration cannot be modified any more. 7.9.6 read lock word the read lock word contains read lock bits . each eeprom word has a corresponding lock bit in the read lock word. once a certain lock bit is set to ?1?, the content of corresponding word cannot be read through picc interface, it can only be read through spi interfa ce. the lock bit of a certain number protects the word with the same number (e.g. b5 of lock word protects word 5). since lock bits are otp they cannot be reset back to ?0? once they are set to ?1?. therefore once a certain word is locked it cannot be unlocked any more. the lock bits for page s 0 to 4 are ?don?t care?; these pages can be read through picc interface even in case their corresponding lock bits are set. www.ams.com revision 1.0 22 - 42 AS3953 datasheet - application information 8 application information 8.1 spi interface communication between the AS3953 and controller is done through a 4-wire serial peripheral interface (spi) and additional inter rupt signal. the AS3953 is an spi slave device; it requests controller attention by sending an interrupt (irq pin). while signal /ss is high the spi interface is in reset, while it is low the spi interface is enabled. it is recommended to keep signal /ss high whenever the spi interface is not in use. mosi is sampled at the falling edge of sclk. all communication is done in blocks of 8 bits (bytes). first three bits of first byte transmitted after high to low transition of /ss define spi operation mode. msb bit is always transmitt ed first (valid for address and data). read and write modes support address auto incrementing, which means that in case after the address and first data byte some additional data bytes are sent (read), they are written to (read from) addresses incremented by ?1?. spi interface supports the following modes: ?? read and write of the spi interface internal registers ?? read and write of the eeprom ?? read and write of the fifo ?? sending direct commands please note that the only spi operations , which are allowed when logic and eeprom ar e supplied from vp_spi, are reading and wri ting of eeprom and registers (see also power manager on page 11 ). miso output is usually in tristate, it is only driven when output data is available. due to this the mosi and the miso can be e xternally shorted to create a bidirectional signal. during the time the miso output is in tristate, it is possible to switch on a 10 k pull-down by activating option bits miso_pd1 and miso_pd2 in io configuration register . table 7. spi and interrupt signals name signal signal level description /ss digital input with pull-up cmos spi enable (active low) mosi digital input cmos serial data input miso digital output with tristate cmos serial data output sclk digital input cmos clock for serial communication irq digital output cmos interrupt output pin table 8. spi modes mode mode pattern (communication bits) mode related data mode trailer m2 m1 m0 c4 c3 c2 c1 c0 register write 0 0 0 a4 a3 a2 a1 a0 data byte (or more bytes in case of auto incrementing) register read 0 0 1 a4 a3 a2 a1 a0 data byte (or more bytes in case of auto incrementing) eeprom write 0 1 0 00000word address byte 4 bytes of word data eeprom read 0 1 1 11111word address byte 4 bytes of word data (or multiple words in case of auto incrementing fifo load10000000one or more bytes of fifo data fifo read10111111one or more bytes of fifo data command mode 1 1 c5 c4 c3 c2 c1 c0 www.ams.com revision 1.0 23 - 42 AS3953 datasheet - application information figure 6. signal to controller 8.1.1 writing of data to addressable registers (register write mode) following figures show cases of writing a single byte and writing multiple bytes with auto-incrementing address. after the spi operation mode bits, the address of register to be written is provided. then one or more data bytes are transferred from the spi, always from the msb to the lsb. the data byte is written in register on falling edge of its last clock. in case the communication is terminated by putting /ss high before a packet of 8 bits composing one byte is sent, writing of this register is not performed. in case the register on the defined address does not exist or it is a read only register no write is performed. note: when the AS3953 is powered via vp_spi and not via field; the regist ers and eeprom can be readout. when cs is set to low, after 50us of the falling edge, the registers and the eeprom can be readout. nevertheless, if there is no activity for 1ms, there is a timeout and the logic goes to sleep, hence losing the values in the registers. (eeprom values are retained). figure 7. writing of a single register figure 8. writing of register data with auto-incrementing address mosi miso miso mosi AS3953 mosi miso i/o AS3953 c c separate spi input and output signals to controller bi-directional data io signal to controller 0 0 0 a4 a3 a2 a1 a0 d5 d4 d3 d2 d1 d0 d7 d6 x x sclk rising edge data is transfered from c sclk falling edge data is sampled data is moved to address a4-a0 /ss rising edge signals end of write mode three leading bits indicate mode /ss sclk mosi 000 a 4 a 3 a 2 a 1 a 0 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 x x data is moved to address www.ams.com revision 1.0 24 - 42 AS3953 datasheet - application information 8.1.2 reading of data from addressab le registers (register read mode) after the spi operation mode bits the address of register to be read has to be provided from the msb to the lsb. then one or mo re data bytes are transferred to miso output, always from the msb to the lsb. as in case of the write mode also the read mode supports auto-i ncrementing address. mosi is sampled at the falling edge of sclk (like shown in the following diagrams); data to be read from the AS3953 internal re gister is driven to miso pin on rising edge of sclk and is sampled by the master at the falling edge of sclk. in case the register on defined address does not exist all ?0? data is sent to miso. in the following figure example for reading of single byte is given. figure 9. reading of a single register 8.1.3 writing and reading of eeprom through spi eeprom data can be read and written also through spi interface. due to possible conflict with rfid interface trying to access t he eeprom in iso 14443a - level4 mode, access is granted to spi only in case the picc afe is not active. in all other modes defined in mode definition registers on page 31 , the eeprom can be accessed via spi when the rf fi eld is active. activity of the picc afe can be checked by observing hf_pon bit of rfid status display register . in case picc afe is activated while the eeprom writing or reading operation is goi ng on, this operation is interrupted, and l_ee_spi irq is sent. word address byte. both eeprom modes (read and write) use word address by te to define the address of eeprom word which is accessed. 7 msb bits of the address byte are used to define the address; while the last bit is ?don?t care? (utilized to synchr onize eeprom access). note: the valid range for the word address byte is from 0000 000xb to 0011 111xb (eeprom words from 00h to 1fh). table below defines the eeprom word address byte. eeprom write. in order to program an eeprom word six bytes have to be sent (mode byte, word address byte and 4 bytes of word data, all of them msb first)). actual programming of eeprom is start ed with rising edge of /ss signal which terminated the eeprom write c ommand. during eeprom programming the controller is not allowed to star t another spi activity. controller is informed about the end of eeprom programming by sending an interrupt (an interrupt flag is set in the auxiliary interrupt register ). i_eew flag is set in case eeprom programming is normally finished; in case of an error (writing to write protected word, writing to non-existent address) an err or flag ( i_er_eew ) is set. typical eeprom programing time for one word is 8ms. note: word data is sent msb first which is opposite to rfid eeprom programming where lsb is sent first. b7 b6 b5 b4 b3 b2 b1 b0 eeprom word address wa6wa5wa4wa3wa2wa1wa0 x 001a4a3a2a1a0 x x sclk rising edge data is moved from address www.ams.com revision 1.0 25 - 42 AS3953 datasheet - application information eeprom read. in order to read data from eeprom first a mode byte is sent, followed by the word address byte (msb first). then one or more words of data with address auto incrementing (packets of 4 bytes) are transferred to miso output, always from the msb to t he lsb. mosi is sampled at the falling edge of sclk; data to be read from the AS3953 eeprom is driven to miso pin on rising edge of sclk and is sampled by the master at the falling edge of sclk. in case the word on defined address does not exist all ?0? data is sent to miso. please note that sclk frequenc y should not exceed 1mhz during eeprom r ead (limited by eeprom read access time). figure 10. reading of eeprom page 8.1.4 loading transmitting data into fifo loading the transmitting data into the fifo is similar to writing data into an addressable registers. difference is that in cas e of loading more bytes all bytes go to the fifo. the command mode code 10 indicates fifo operations. in case of loading transmitting data into fifo al l bits www.ams.com revision 1.0 26 - 42 AS3953 datasheet - application information 8.1.6 direct command mode direct command mode has no arguments, so a single byte is sent. spi operation mode bits 11 indicate direct command mode. the fo llowing six bits define command code, sent msb to the lsb. the command is executed on falling edge of last clock. figure 12. sending of a direct command 8.1.7 spi timing table 9. timing parameters symbol parameter min typ max units note general timing (vdd = vdd_io = vdd_d = 3.3v, temperature 25c) t sclk sclk period 200 ns t sclk =t sclkl +t sclkh, during eeprom read the sclk period has to be increased to 1s (this limitation is imposed by eeprom read access time) t sclkl sclk low 80 ns t sclkh sclk high 80 ns t ssh spi reset (/ss high) 50 ns t ncsl /ss falling to sclk rising 25 ns first sclk pulse t ncsh sclk falling to /ss rising 80 ns last sclk pulse t dis data in setup time 10 ns t dih data in hold time 10 ns read timing (vdd = vdd_io = vdd_d = 3.3v, temperature 25c, c load 50pf) t dod data out delay 20 ns t dohz data out to high impedance delay 20 ns 1 1 c5 c4 c3 c2 c1 c0 x x sclk rising edge data is transfered from c sclk falling edge data is sampled /ss rising edge signals start of command execution two leading one indicate command mode /ss sclk mosi www.ams.com revision 1.0 27 - 42 AS3953 datasheet - application information figure 13. spi general timing figure 14. spi read timing ... ... ... t dis t dih datai datai datai ... t ncsh t sclkh t sclkl /ss mosi miso sclk t ncsl ... ... ... datai ... t dohz /ss mosi miso sclk t dod datao datao www.ams.com revision 1.0 28 - 42 AS3953 datasheet - application information 8.1.8 interrupt interface there are two interrupt registers implemented in the AS3953 ( main interrupt register and auxiliary interrupt register ). main interrupt register contains information about seven interrupt sources, while one bit references to interrupt sources detailed in auxiliary interrupt register . when an interrupt condition is met the source of interrupt bit is set in the main interrupt register and the irq pin transitions to high. the controller then reads the main interrupt register to distinguish between different interrupt sources. in case the bit l_aux is pointing to the auxiliary interrupt register , this register also needs to be read. after an interrupt register (main or auxiliary) is read its content is reset to ?0?. exception to this rule is the bit pointing to auxiliary register. this bit is only cleared when the auxiliary interrupt registe r is read. irq pin transitions to high after the interrupt bit(s) which caused its transition to high has been read. please note that there may be more than o ne interrupt register bit set in case the controller did not immediately read the interrupt registers after the irq signal is set and another event c ausing interrupt occurred. 8.1.9 fifo water level and fifo status register the AS3953 contains a 32 byte fifo. in case of transmitting the control logic shifts data which was previously loaded by the ex ternal controller to the framing block and further to the transmitter. during reception, the demodulated data is stored in the fifo and the exter nal controller can download received data. transmit and receive capability of the AS3953 is not limited by of the fifo size due to a fifo water level interrupt system. du ring transmission an interrupt is sent (interrupt due to fifo water level in the main interrupt register ) when the content of data in the fifo which still need to be sent is lower than the fifo water level for transmit. the external controller can now add more data in the fifo. the same stand s for receive mode. in case the number of received bytes increases over the fifo water level for receive an interrupt is sent to inform the e xternal controller that data has to be downloaded from fifo. the external controller has to serve the fifo faster than data is transmitted or received. a general rule is that the sclk freq uency has to be at least double than the actual data rate in receive or transmit. fifo water level is set to ? of fifo for reception and to ? of fifo for transmission. this means that in case of getting an int errupt during reception there are already 24 bytes in the fifo, which have to be read out to liberate space for following data bytes. same st ands for transmission, water level interrupt is sent when there are 8 bytes left in fifo, therefore up to 24 additional bytes can be loa ded. during fifo operation (fifo read or fifo load) the water level detection system is blocked to avoid spurious water level interr upts (these might occur when for example number of bytes has increased above water level during loading and immediately after that dropped again below water level due to tx process which runs in parallel). due to this the fifo loading/reading rate has to be higher than tx / rx bit ra te, once fifo loading/reading is finished the /ss pin has to be pulled to vdd (logic remains in fifo load/read mode as long as /ss remains lo w). in case loading/reading of fifo is not much faster than tx / rx processes low the following two cases have to be considered: ?? fifo underflow irq is not blocked, in case loading in fifo is slower than transmission process the fifo underflow irq is produc ed. ?? in case of slow fifo loading it is possible that the content of fifo is increased above water level but it is below when fifo l oading is fin- ished. in such case a water level irq is issued after termination of fifo loading. same stands for fifo reading. ?? in case of slow fifo loading it is possible that the content of fifo stays below water level during complete fifo loading opera tion. in such case water level irq is not issued after termination of fifo loading. same stands for fifo reading. in case it is known that the receive data frame is smaller than the fifo size the water level interrupt does not have to be ser ved. in such case the water level interrupt can be masked. after data is received the external controller needs to know how long the receive data string was before downloading data from the fifo: this information is available in the fifo status register 1 and fifo status register 2 which display number of bytes in the fifo which were not read out. the fifo status register 2 additionally contains two bits which indicate that the fifo was not correctly served during reception or transmission process (fifo overflow and fifo underflow). fifo overflow is set when too much data is written in fifo. in case this bit is set during reception the external controller di d not react on time on water level irq and more than 32 bytes were written in the fifo. the received data is corrupted in such a case. during transmis sion this means that controller has written more data than fifo size. the data to be transmitted is corrupted. fifo underflow is set when data was read from empty fifo. in case this bit is set during reception the external controller read more data than was actually received. during transmission this means that controller has failed to provide the quantity of data defined in num ber of transmitted bytes registers on time. www.ams.com revision 1.0 29 - 42 AS3953 datasheet - application information 8.1.10 iso 14443a frame data in fifo data in iso 14443a frames is organized in bytes; each byte is terminated by parity bit. data bits in a byte are numbered from b1 to b8 where b1 is lsb bit, lsb is sent first. data sent over spi is also organized in bytes, bits in a byte are marked d0 to d7 , where d0 is lsb bit, msb is sent first. during receive the framing engine checks the parity bit and removes it from data frame, only the data bytes are put in fifo. du ring transmission the process is inversed, only the data bytes are put in fifo, while the framing engine adds the parity bits. the iso 14443a data bits b1 to b8 are mapped to fifo data bits d0 to d7 , which means that the order of receiving/transmitting bits in a byte is inversed (the iso 14443a bytes are sent lsb first while the spi bytes are sent msb first). the only exceptions to this rule are the rx and tx bit stream modes. in these modes the meaning of byte is lost. in order to si mplify processing the order of bits is the same on iso 14443a and fifo side. this means that during reception with bit rxbs set the first received bit is also the first bit read out of fifo. in case the last fifo byte is not complete the bits which are not part of received data are padded with ?0?. the same stands for transmission with bit txbs set: the first bit written in fifo is also the first bit sent. 8.2 direct commands 8.2.1 set default this direct command puts the AS3953 in the same state as power-up initialization. all registers are initialized to the default state. 8.2.2 clear this direct command stops all current activities (transmission or reception) and clears fifo. 8.2.3 transmit this direct command transmits the data stored in the fifo. in protocol modes it is only accepted on level-4 of communication. b efore triggering transmission using transmit command direct command clear has to be sent, followed by definition of number of transmitted bytes and writing data to be transmitted in fifo. execution of this direct command is only enabled when the AS3953 antenna coil is in a pcd field (vp_int is above hf_pon thresho ld). 8.2.4 go2halt puts picc logic in halt state. execution of this direct command is only enabled when the AS3953 antenna coil is in a pcd field (vp_int is above hf_pon thresho ld) and picc logic is in one of the two iso 14443a protocol modes. table 10. list of direct commands command byte value [hex] command comments c2, c3 set default puts the AS3953 in default state c4, c5 clear stops all activities and clears fifo c8 transmit starts a transmit sequence d0 go2halt puts picc logic in halt state www.ams.com revision 1.0 30 - 42 AS3953 datasheet - application information 8.3 registers the 6-bit register addresses below are defined in the hexadecim al notation. the possible address range is from 00h to 3fh. there are two types of registers implemented in the AS3953: configuration registers and display registers. the configuration re gisters are used to configure the AS3953. they can be written and read through the spi (rw). the display registers are read only (ro); they cont ain information about the AS3953 internal state, which can be accessed through the spi. 8.3.1 overview of registers 8.3.2 io definition register io configuration register. note: this register is directly supplied by vp_spi. its initial state is unknown. table 11. list of the spi interface internal registers address [hex] content type 00 io configuration register rw 01 mode definition register rw 02 bit rate definition register rw 04 rfid status display register ro 05 rats register ro 08 mask main interrupt register rw 09 mask auxiliary interrupt register rw 0a main interrupt register ro 0b auxiliary interrupt register ro 0c fifo status register 1 ro 0d fifo status register 2 ro 10 number of transmitted bytes register 1 rw 11 number of transmitted bytes register 2 rw address# 00h : io configuration type: rw bit name default function comments 7 miso_pd2 x 1: pull-down on miso, when \ss is low and miso is not driven by the AS3953 6 miso_pd1 x 1: pull-down on miso when \ss is high 5 rfu 4 rfu 3 rfu 2 rfu 1 rfu 0 rfu www.ams.com revision 1.0 31 - 42 AS3953 datasheet - application information 8.3.3 mode definition registers mode definition register. note: default value is loaded from eeprom configuration word bits b12 to b7 during power-up initialization. bit rate definition register. note: default setting is set at power-up and after set default command. in iso 14443a level-4 protocol mode, this value is rewritten after receiving pps command. table below defines the coding of the bit rate note: in case a bit rate which is not supported is selected, the tx / rx operation is disabled. address# 01h : mode definition type: rw bit name default function comments 7 rfu 6 rfu 5 r_mod_1 see note 00: iso 14443a level-4 protocol mode 01: iso 14443a level-3 protocol mode 10: framing mode 11: transparent mode iso mode in case of register control; if iso 14443a protocol mode is selected through registers, logic is forced in level-4 mode. 4 r_mod_2 see note 3 r_rxncrc see note 1: rx ? crc is not checked, crc part of message is also put in fifo applicable in iso 14443a level-3 protocol mode and framing mode. in protocol mode, applicable for frames which are put in fifo. 2 r_rxbs see note 1: rx ? bit stream mode, received bits are put in fifo (no parity and crc check) 1 r_txncrc see note 1: tx ? do not generate crc 0 r_txbs see note 1: tx ? bit stream mode, bits put in fifo are sent without parity and crc generation address# 02h : bit rate definition type: rw bit name default function comments 7 tx_rate3 0 bit rate for tx for coding see table below 6 tx_rate2 0 5 tx_rate1 0 4 tx_rate0 0 3 rx_rate3 0 bit rate for rx for coding see table below 2 rx_rate2 0 1 rx_rate1 0 0 rx_rate0 0 rate3 rate2 rate1 rate0 bit rate [kbps] comments 0 0 0 0 fc/128 (~106) 0 0 0 1 fc/64 (~212) 0 0 1 0 fc/32 (~424) 0 0 1 1 fc/16 (~848) other combinations rfu www.ams.com revision 1.0 32 - 42 AS3953 datasheet - application information 8.3.4 display registers rfid status display register. notes: 1. the information read from this register can be false during reception (the logic state change during reception and the read out of status can be done just at the moment when the status is changing). 2. the rfid status display register is not a real register. by reading this register, controller has access to specific rfid logic internal signals in order to observe its internal state. rats register. notes: 1. at power-up and after set default , content of this register is set to ?0?. 2. the rats register is used only in iso 14443a-4 protocol mode. it contains information sent by pcd in rats command. the register informs the controller about maximum frame size that the pcd can handle and the attributed cid number. address# 04h : rfid status display type: r bit name function comments 7 hf_pon 1: picc afe is active afe power-on signal 6 state<2> 000: power off 001: idle 010: ready 011 ? active 101: halt 110: readyx 111: activex 100: l4 picc logic state 5 state<1> 4 state<0> 3 rfu 2 rfu 1 rfu 0 rfu address# 05h : rats type: r bit name function comments 7 fsdi3 rats fsdi bits displays maximum frame size that pcd can handle (set by pcd in rats command) 6 fsdi2 5 fsdi1 4 fsdi0 3 cid3 rats cid bits displays attributed cid number (set by pcd in rats command) 2 cid2 1 cid1 0 cid0 www.ams.com revision 1.0 33 - 42 AS3953 datasheet - application information 8.3.5 interrupt register and associated registers mask main interrupt register. note: default setting is set at power-up and after set default command. mask auxiliary interrupt register. note: default setting is set at power-up and after set default command. address# 08h : mask main interrupt type: rw bit name default function comments 7 m_pu 1 mask power-up irq this bit is set to ?0? during power-up initialization in case eeprom configuration bit irq_pu is set to ?1? 6 m_wu_l4 1 mask wake-up irq at entry in active(*) state this bit is set to ?0? during power-up initialization in case eeprom configuration bit irq_l4 is set to ?1? 5 m_wu 0 mask wake-up irq triggered by sending wake-up command 4 m_rxs 0 mask irq due to start of receive 3 m_rxe 0 mask irq due to end of receive 2 m_txe 0 mask irq due to end of transmission 1 m_wl 0 mask irq due to fifo water level 00 rfu address# 09h : mask auxiliary interrupt type: rw bit name default function comments 7 m_des 0 mask irq due to reception of deselect command 6 m_er_fr 0 mask framing error irq 5 m_er_par 0 mask parity error irq 4 m_er_crc 0 mask crc error irq 3 m_er_fifo 0 mask fifo error irq 2 m_eew 0 mask irq due to successful termination of eeprom programming 1 m_er_eew 0 mask error during eeprom programming irq 0 m_ee_spi 0 mask irq due to interruption of eeprom access due to picc interface activation www.ams.com revision 1.0 34 - 42 AS3953 datasheet - application information main interrupt register. notes: 1. at power-up and after set default command, content of this register is set to ?0?. 2. after main interrupt register is read, with the exception of bit0, the register content is set to ?0?. the bit0 is set to ?0? only after the corresponding interrupt register is read. auxiliary interrupt register. notes: 1. at power-up and after set default command content of this register is set to 0. 2. after auxiliary interrupt register has been read its content is set to 0. address# 0ah : main interrupt type: r bit name function comments 7 i_pu power-up irq 6 i_wu_l4 wake-up irq at entry in active(*) state 5 i_wu wake-up irq triggered by sending wake-up command 4 i_rxs irq due to start of receive applicable when receive frame is put in fifo 3 i_rxe irq due to end of receive applicable when receive frame is put in fifo 2 i_txe irq due to end of transmission applicable when data from fifo is sent 1 i_wl irq due to fifo water level during receive informing that fifo is almost full and has to be read out. during transmit informing that fifo is almost empty and that additional data has to be send 0 i_aux irq due to event displayed in the auxiliary interrupt register address# 0bh : auxiliary interrupt type: r bit name function comments 7 i_des irq due to reception of deselect command 6 i_er_fr framing error 5 i_er_par parity error in case of parity or/and crc error the receive data is still put in fifo, error irq is additionally send. 4 i_er_crc crc error 3 i_er_fifo fifo error (overflow/underflow) see fifo status register 2 2 i_eew irq due to successful termination of eeprom programming in case eeprom write command was sent through spi 1 i_er_eew error during eeprom programming (writing to write protected word, writing to nonexistent address) in case eeprom write command was sent through spi 0 i_ee_spi irq due to interruption of eeprom access due to picc interface activation www.ams.com revision 1.0 35 - 42 AS3953 datasheet - application information fifo status register 1. note: at power-up and after direct commands set default and clear content of this register is set to 0. fifo status register 2. note: at power-up and after direct commands set default and clear content of this register is set to 0 address# 0ch : fifo status 1 type: r bit name function comments 7 rfu 6 rfu 5 fifo_b5 number of data bytes (binary coded) in the fifo which were not read out valid range is from 000000 to 100000 000000 means that there are no data bytes to be read out 4 fifo_b4 3 fifo_b3 2 fifo_b2 1 fifo_b1 0 fifo_b0 address# 0dh : fifo status 2 type: r bit name function comments 7 rfu 6 fifo_unf fifo underflow set when more bytes than the actual content of fifo are read 5 fifo_ovr fifo overflow 4 fifo_ncp last fifo byte is not complete 3 fifo_lb2 number of bits in last fifo byte in case it was not complete (fifo_npc=1) msb bits valid 2 fifo_lb1 1 fifo_lb0 0 np_lb parity bit is missing in last byte this is a framing error www.ams.com revision 1.0 36 - 42 AS3953 datasheet - application information 8.3.6 definition of number of transmitted bytes number of transmitted bytes register 1. note: default setting is set at power-up and after set default command. number of transmitted bytes register 2. note: default setting is set at power-up and after set default command. address# 10h : number of transmitted bytes 1 type: rw bit name default function comments 7rfu number of full bytes to be transmitted in one command, msb bits maximum supported number of bytes is 1023 6rfu 5 rfu 4 ntx9 0 3 ntx8 0 2 ntx7 0 1 ntx6 0 0 ntx5 0 address# 11h : number of transmitted bytes 2 type: rw bit name default function comments 7 ntx4 0 number of full bytes to be transmitted in one command, lsb bits maximum supported number of bytes is 1023 6 ntx3 0 5 ntx2 0 4 ntx1 0 3 ntx0 0 2 nbtx2 number of bits in the split byte 000 means that all bytes all full applicable in - level-3 protocol mode in case configuration bit txbs is set (bit stream tx) - framing mode 1 nbtx1 0 nbtx0 www.ams.com revision 1.0 37 - 42 AS3953 datasheet - package drawings and markings 9 package drawings and markings the device is available in a mlpd (3x3x0.9mm) 10-pin, wl-csp 10-bumps package. gold bumped dies are also available. figure 15. mlpd (3x3x0.9mm) 10-pin package diagram marking: xxxx - encoded date code. xxxx as39 notes: 1. dimensions and tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters. angles are in degrees. 3. coplanarity applies to the exposed heat slug as well as the terminal. 4. radius on terminal is optional. 5. n is the total number of terminals. symbol min nom max a 0.80 0.90 1.00 a1 0 0.02 0.05 a3 0.20 ref l 0.30 0.40 0.50 b 0.18 0.25 0.30 d 3.00 bsc e 3.00 bsc e 0.50 bsc d2 2.23 2.38 2.48 e2 1.49 1.64 1.74 aaa - 0.15 - bbb - 0.10 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - n10 53a www.ams.com revision 1.0 38 - 42 AS3953 datasheet - package drawings and markings figure 16. wl-csp 10-bumps package diagram notes: 1. ccc coplanarity 2. all dimensions are in m www.ams.com revision 1.0 39 - 42 AS3953 datasheet - package drawings and markings figure 17. gold bumped dies 11-pins table 12. specification for gold bumps item min max unit backgrinded wafer height (excl bimp height) 100 m bump height 13 17 m height coplanarity for within wafer < 4 m height coplanarity for within die < 2 m surface roughness <= 3 m hardness 35 65 hv shear force 8 >= mg/m 2 www.ams.com revision 1.0 40 - 42 AS3953 datasheet - delivery frame drawing 10 delivery frame drawing figure 18. delivery frame drawing for ?8? cut dies on foil in 12? frame? (see ordering information (page 41) ) www.ams.com revision 1.0 41 - 42 AS3953 datasheet - ordering information 11 ordering information the devices are available as standard products shown in table below. note: all products are rohs compliant and ams green. buy our products or get free samples online at www.ams.com/icdirect technical support is available at www.ams.com/technical-support for further information and requests, please contact us at sales@ams.com or find your local distributor at www.ams.com/distributor table 13. ordering information ordering code type marking delivery form AS3953a-bwlt wafer level chip scale AS3953a tape & reel AS3953a-bwlm wafer level chip scale AS3953a mini reels AS3953a-bswb 1 1. future delivery options. sorted wafer na wafer box AS3953a-bswf-au 1 sorted wafer with gold bumps na foil AS3953a-bdft 1 mpld package AS3953a tape & reel AS3953a-bdfm 1 mpld package AS3953a mini reels www.ams.com revision 1.0 42 - 42 AS3953 datasheet - copyrights copyrights copyright ? 1997-2013, ams ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registered ?. all right s reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written con sent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by ams ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. ams ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with ams ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliabi lity applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without addi tional processing by ams ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the stan dard production flow, such as test flow or test location. the information furnished here by ams ag is believed to be correct and accurate. however, ams ag shall not be liable to recipien t or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruptio n of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, perfo rmance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of ams ag rendering of technical or other services. contact information headquarters ams ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel : +43 (0) 3136 500 0 fax : +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.ams.com/contact |
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