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1 datasheet caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. pwm doubler with output monitoring feature ISL6617A the ISL6617A utilizes intersil?s proprietary phase doubler scheme to modulate two-phase power trains with single pwm input. it doubles the number of phases that 3.3v multiphase controllers can support. the ISL6617A is designed to minimize the number of analog signals that interface between the controller and drivers in high phase count scalable applicatio ns. the common comp signal, which is usually seen in conventional cascaded configurations, is not required; this improves noise immunity and simplifies the layout. furthermore, the ISL6617A provides low part count and low cost advantage over the co nventional cascaded technique. by cascading the ISL6617A with another isl6617 or isl6611a, it can quadruple the number of ph ases that 3.3v multiphase controllers can support. the ISL6617A also features tr i-state input and outputs that recognize a high-impedance state, working together with intersil multiphase pwm controllers an d driver stages to prevent negative transients on the controlled output voltage when operation is suspended. this feature eliminates the need for the schottky diode that may be utilized in a power system to protect the load from excessive negative output voltage damage. applications ? high current low voltage dc/dc converters ? high frequency and high efficiency vrm and vrd ? high phase count and phase shedding applications ? 3.3v pwm input integrated power stage or drmos features ? proprietary phase doubler scheme ? enhanced light to full load efficiency ? double or quadruple phase count ? patented current balancing with dcr current sensing and adjustable gain ? current monitoring output (i out ) to simplify system interface and layout ? triple-level enable input for mode selection ? dual pwm output drives for tw o synchronous rectified bridges with single pwm input ? channel synchronization and two interleaving options ? support 3.3v pwm input ? support 5v pwm output ? tri-state pwm input and outputs for output stage shutdown ? overvoltage protection ? dual flat no-lead (dfn) package - near chip-scale package footprint; improves pcb utilization, thinner profile - pb-free (rohs compliant) related literature ? tb363 , ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? phase doubler selection guide part number pwm input pwm output integrated driver cascaded devices compatible controllers isl6617 5.0v 5.0v n/a 5.0v pwm drmos; isl6617, isl6611a isl6336g, isl6372/3/4/5/6, isl6364/67/67h; isl6388/98 with 5v pwm option ISL6617A 3.3v 5.0v n/a 5.0v pwm drmos; isl6617, isl6611a 3.3v pwm digital controllers with phase doubler compatibility; isl6388/98 with 3.3v pwm option isl6611a 5v n/a 5.0v discrete mosfet; dual fets isl6336g, isl6372/3/4/5/6, isl6364/67/67h; isl6388/98 with 5v pwm option december 19, 2014 fn7844.0
ISL6617A 2 fn7844.0 december 19, 2014 submit document feedback internal block diagram vcc pwmin 10k 5.5k csrtna pwma gnd pwmb csenb csrtnb channel a channel b en_sync current balance block csena control logic iout ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL6617Afrz 17af -40 to +125 10 ld 3x3 dfn l10.3x3 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for information on msl please see techbrief tb363 .
ISL6617A 3 fn7844.0 december 19, 2014 submit document feedback pin configuration ISL6617A (10 ld dfn) top view 1 3 4 pwmin csena vcc csrtna 2 10 8 7 9 pwma iout en_sync gnd 11 5 6pwmb csenb csrtnb functional pin descriptions pin # pin symbol function 1 csrtna output of the differential amplifier for channel a. connec t a resistor on this pin to the negative rail of the sensed vo ltage to set the current gain. 2 csena input of the differential amplifier for channel a. typicall y, the positive rail of sensed voltage via dcr sensing network connects to this node. 3 pwmin the pwm input signal (3.3v) triggers the j-k flip flop an d alternates its input to channel a and b. both channels are effectively modulated. the pwm signal can ente r three distinct states during operation; see ? operation ? on page 8 for further details. connect this pin to the pwm output of the controller. 4 csrtnb output of the differential amplifier for channel b. connect a resistor on this pin to the negative rail of the sensed vo ltage to set the current gain. 5 csenb input of the differential amplifier for channel b. typicall y, the positive rail of sensed voltage via dcr sensing network connects to this node. 6 pwmb pwm output of channel b with 5v pwm tri-state compatibility. 7 en_sync driver enable and mode selection input. see ? en_sync operation ? on page 8 for more details. 8 iout current monitoring output. it sources out the average current of both channel a and b. 9 vcc connect this pin to a +5v bias supply. it supplies power to internal analog circuits. place a high quality low esr ceramic capacitor from this pin to gnd. 10 pwma pwm output of channel a with 5v pwm tri-state compatibility. 11 gnd bias and reference ground. all signals are referenced to th is node. place a high quality lo w esr ceramic capacitor from th is pin to vcc. connect this pad to the power ground plane (gnd) via thermally enhanced connection.
ISL6617A 4 fn7844.0 december 19, 2014 submit document feedback typical application (2-phase co ntroller for 4-phase operation) main control isl69xxx +5v vsen gnd v cc vr_rdy cs0 en ISL6617A gnd vcc en_sync iout pwm0 +v core csrtn0 pwmin +3.3v cs1 pwm1 csrtn1 +5v +12v gnd vin phase pwm +12v gnd vin phase pwm pwmb pwma csena csrtna csrtnb csenb +5v ISL6617A gnd vcc en_sync iout pwmin +5v +12v gnd vin phase pwm +12v gnd vin phase pwm pwmb pwma csena csrtna csrtnb csenb power stage power stage power stage power stage
ISL6617A 5 fn7844.0 december 19, 2014 submit document feedback typical application ii (2-phase co ntroller to 8-phase operation) main control isl69xxx vsen gnd v cc cs0 pwm0 +v core csrtn0 +3.3v cs1 pwm1 csrtn1 +5v isl6617 gnd vcc en_sync iout pwmin +5v +12v gnd vin phase pwm +12v gnd vin phase pwm pwmb pwma isena- isena+ isenb+ isenb- +5v isl6617 gnd vcc en_sync iout pwmin +5v +12v gnd vin phase pwm +12v gnd vin phase pwm pwmb pwma isena- isena+ isenb+ isenb- +5v ISL6617A gnd vcc en_sync iout pwmin +5v pwmb pwma csena csrtna csenb csrtnb power stage power stage +5v isl6617 gnd vcc en_sync iout pwmin +5v +12v gnd vin phase pwm +12v gnd vin phase pwm pwmb pwma isena- isena+ isenb+ isenb- +5v isl6617 gnd vcc en_sync iout pwmin +5v +12v gnd vin phase pwm +12v gnd vin phase pwm pwmb pwma isena- isena+ isenb+ isenb- +5v ISL6617A gnd vcc en_sync iout pwmin +5v pwmb pwma csena csrtna csenb csrtnb power stage power stage power stage power stage power stage power stage
ISL6617A 6 fn7844.0 december 19, 2014 submit document feedback absolute maximum rating s thermal information supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.7v input voltage (v enx , v pwmin, i senx ). . . . . . . . . . . . . . . -0.3v to vcc + 0.3v ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c esd rating human body model (jedec class 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv machine model (jedec class b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200v charged device model (jedec class iv) . . . . . . . . . . . . . . . . . . . . . . . 2kv latch-up (jedec class ii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+85c thermal resistance (typical) ? ja (c/w) ? jc (c/w) 10 ld dfn ( notes 4 , 5 ) . . . . . . . . . . . . . . 48 7 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c maximum operating junction temperature . . . . . . . . . . . . . . . . . . +125c supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v ? 10% caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. ? jc , ?case temperature? location is at the ce nter of the package underside exposed pad. electrical specifications these specifications apply for recommended ambient temperature, unless otherwise noted. boldface limits apply over the operating temperature range. parameter symbol test conditions min ( note 6 )typ max ( note 6 )units supply current bias supply current i vcc pwm pin floating, v vcc = 5v, en_sync = 5v 5 6.5 ma pwm pin floating, v vcc = 5v, en_sync = 0v 5 6.5 ma f pwm = 600khz, v vcc = 5v, en_sync = 5v 6 7.5 ma f pwm = 600khz, v vcc = 5v, en_sync = 4.25v 6 7.5 ma f pwm = 300khz, v vcc = 5v, en_sync = 3.25v 6 7.5 ma power-on reset por rising 3.4 4.2 v por falling 2.3 3.0 v hysteresis 350 mv en_sync input enx minimum low threshold v enx 0.8 v enx maximum high threshold v enx 2.0 v sync and interleaving mode interleaving mode 1 window v enx 97% vcc interleaving mode 2 window v enx 78% 85% vcc synchronous mode window v enx 54% 64% vcc typical threshold hysteresis -5% vcc minimum sync pulse 40 ns maximum synchronization delay 50 ns interleaving mode phase shift sync = 5v, pwm = 300khz, 10% width 180 synchronization mode phase shift sync = 0v, pwm = 300khz, 10% width 0 pwm input (pwmin) sinking impedance r pwm_snk 5.5 k source impedance r pwm_src 10 k
ISL6617A 7 fn7844.0 december 19, 2014 submit document feedback tri-state to pwm high rising threshold v vcc = 5v 2.50 2.70 v tri-state to pwm high falling threshold v vcc = 5v 2.00 2.25 v tri-state to pwm low rising threshold v vcc = 5v 0.95 1.15 v tri-state to pwm low falling threshold v vcc = 5v 0.50 0.75 v current sense (csena, csenb, iout) and protection (iout) sensed current tolerance i out csena = csenb = 0a -6 0 6 a csena = csenb = 20a 14 20 26 a csena = csenb = 50a 43 50 57 a csena = csenb = 100a 90 100 110 a un-tri state trip for ovp i out enx = low to high, pwm = low 40 60 90 a pwm output (pwma and pwmb) sourcing impedance r pwm_src vcc = 5v, pwmin = high 30 100 200 sink impedance r pwm_snk vcc = 5v, pwmin = low 30 100 150 pwm output high level v pwma/b vcc = 5v, pwmin = high, 2.5ma load 4.5 v pwm output low level v pwma/b vcc = 5v, pwmin = low, 2.5ma load 0.4 v pwm tri-state level v pwma/b vcc = 5v, en_ph = low, 0.5ma load 1.65 2.00 2.6 v switching time (see figure 1 on page 8 ) pwma/b low to high rise time t r1 unloaded, 10% to 90% 4.5 ns pwma/b tri-state to high rise time t r2 unloaded, 10% to 90% 4.5 ns pwma/b high to low fall time t f1 unloaded, 90% to 10% 4.0 ns pwma/b high to tri-state fall time t f2 100% to 60% (3v), assume equivalent loading of rc = 50k *10pf = 500ns 255 ns pwma/b turn-on propagation delay t pdh outputs unloaded 35 ns pwma/b turn-off propagation delay t pdl outputs unloaded, excluding extension 35 ns pwma/b extension t ext enx = vcc, i pwma > i pwmb 70 ns enx = vcc, i pwma < i pwmb 70 ns enx = 80%*vcc, i pwma > i pwmb 190 ns enx = 80%*vcc, i pwma < i pwmb 190 ns tri-state to high or low propagation delay t pts outputs unloaded, excluding extension 10 ns tri-state shutdown hold-off time t tsshd including propagation delay 65 ns note: 6. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications these specifications apply for recommended ambient temperature, unless otherwise noted. boldface limits apply over the operating temperature range. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )units
ISL6617A 8 fn7844.0 december 19, 2014 submit document feedback timing diagram operation designed for high phase count an d phase shedding applications, the ISL6617A driverless phase doubler is meant to double or quadruple (cascaded with two isl6617s) the number of phases that 3.3v multiphase controllers can support. a rising transition on pwmin initiates the turn-on of the pwma/b (see figure 1 ). after a short pr opagation delay [t pdh ], the pwma/b begins to rise . typical rise times [t r1 ] are provided in the ?electrical specifications? table on page 7 . a falling transition on pwmin indicates the turn-off of the pwma/b. the pwma/b begins to fall [t f1 ] after a propagation delay [t pdl ], which is modulated by the current balance circuits. when the pwmin stays in the tri- state window for longer than [t tsshd ], both pwma/b will pull to 40% of vcc so that the cascaded 5v pwm input mosfet driver or integrated power stage can recognize tri-state. en_sync operation the en_sync pin features multiple functions. it is the enable input of the device and the input to select various operational modes. enable operation as shown in figure 2 , the ISL6617A disables the doubler operation when the en_sync pin is pulled to ground. when the en_sync returns high, the phase doubler will pull the pwm line into the tri-state window, and then will be enabled only at the leading edge of the pwm input. prior to the first pwmin rising edge, both the pwma and pwmb output will remain in tri-state unless an overvoltage fault is detected. this fault is defined as when a phase is detected to have more than 60% of the maximum i out current. this provides additional protection to the load if the upper mosfet experiences a short while the doubler is enabled. the en_sync pin should remain high if driving the pwm line high is prohibited for the associated controller. for proper system interface, please refer to the respective device datasheet. synchronous operation the ISL6617A can be set in inte rleaving mode or synchronous mode by pulling the en_sync pin to the respective level, as shown in table 1 . a synchronous pulse can be sent to the phase doubler during the load application to improve the voltage droop and current balance while still ma intaining interleaving operation at dc load conditions. however, excessive ringback can occur; hence, the synchronous mode op eration should be carefully investigated. figure 3 shows how to generate a synchronous pulse when a transient load is a pplied. the comparator should be a fast comparator with a minimum delay. various operational modes the ISL6617A has three distin ct operating modes depending upon the voltage level of the en_sync pin. to ensure that the ISL6617A is in operation, the pin must be above 2v. when the en_sync pin is set to above 97% of v cc , the ISL6617A will operate in interleaving mode with a maximum extension of 70ns. when v cc is between 78% and 85% of v cc , the ISL6617A operates in interleaving mode with a fixed extension of 120ns and a variable extension of up to 70ns. this results in a minimum extension of 120ns and a max of 190ns. to enter this 2nd interleaving mode, the pin must remain in the 78% to 85% range for at least 4 cycles. between 54% and 64% of v cc , the device operates in synchronous mode. figures 4 and 5 show simplified synchronous and interleaving mo des? operational waveforms, respectively. figure 1. timing diagram pwmin pwma/b t pdh t r1 t pdl 10% 1.7v t f2 t f1 t pts t tsshd t tsshd 90% 10% 90% t pts 60% 15ns t r2 10% 90% 3.3v 5v figure 2. typical enable operation timing diagram en_sync pwmin pwma/b figure 3. typical sync pulse generator + - comp sync 1.0nf 2k 20k 49.9k 1k vcc 0 dnp
ISL6617A 9 fn7844.0 december 19, 2014 submit document feedback to transition between two different modes, the en_sync pin voltage level needs to be set accordingly. figures 6 and 7 show an example of external circuits for mode transition between synchronous mode and interleaving #1 or #2 mode, respectively. the r should be less than 50k to improve transition time. table 1. ISL6617A operational modes mode min typ max extension enable low 0.8v enable high 2v interleaving#1 97%*vcc vcc 0ns to 70ns interleaving#2 78%*vcc 81%*vcc 85%*vcc 120ns + (0ns to 70ns) synchronous 54%*vcc 60%*vcc 64%*vcc 0ns to 70ns not used from 0.8v to 2v or 54% of vcc is not recommended region figure 4. interleaving mode?s operational waveforms (enx = vcc, or 81%*vcc) pwm pwma pwmb figure 5. synchronous mode ?s operational waveforms (en_sync = 60%*vcc) pwm pwma pwmb figure 6. configuration for transition betw een synchronous and interleaving #1 modes vcc sync - + sync 0ns to 70ns interleaving 0ns to 70ns en ttl - + - + - + interleaving +120+(0ns to 70ns) 40%*r 60%*r 4 cycles blanking ISL6617A en_sync figure 7. configuration for transition betw een synchronous and interleaving #2 modes vcc sync - + sync 0ns to 70ns interleaving 0ns to 70ns en ttl - + - + - + interleaving +120+(0ns to 70ns) 19%*r 28.5%*r 4 cycles blanking 52.5%*r ISL6617A en_sync
ISL6617A 10 fn7844.0 december 19, 2014 submit document feedback the ISL6617A can further be cascaded with isl6617 or isl6611a (phase doubler with integrated 5v drivers), as shown in figure 8 . this can quadruple the number of phases each pwm line can support. figure 9 shows the operational waveforms of the cascaded doublers. the pwmin pin of isl6617 or isl6611a will be pulled to vcc when it is disabled (en_x = low). to avoid driving the pwm outputs of the 1st stage ISL6617A by the 2nd stage?s pwmin, the 2nd stage doubler?s enable input should remain high, i.e, tied to vcc, as shown in figure 8 . note that ISL6617A cannot cascade with itself and its pwmin will not be pulled to vcc when en_x is disabled (low). to operate each phase at the switching frequency of f sw , the operational frequency of the co ntroller needs to be scaled accordingly for different modes, as shown in table 2 . when the doubler operates in interleaving mode, the pwm controller frequency should be set at two times the desired phase frequency (f sw ). since the input pwm pulse is divided into half to feed into each phase of the doubler, the operational duty cycle of each phase should be less than 50%. in synchronous mode, the pwm controller should be operated at the same frequency as the desired phase frequency. in this mode, the allowable duty cycle is up to 100%. for cascaded interleaving, the controller switching frequency needs to be set at four times the phase frequency. during cascaded operation, the maximum allowable duty cycle will be less than 25%. all of the maximum allowable duty cycle numbers referenced assume that the pwm controller can send out a 100% duty cycle pulse. in many cases, this is not achievable because th e controller needs time to reset its internal sawtooth ramp or internal max duty limit. however, the fixed 120ns extension of interleaving mode 2 helps recover the typical 1% duty cycle loss associated with the ramp reset time. to properly compensate the system that uses phase doublers, the effective system sawtooth to calculate the modulator gain should factor in the duty cycle limitation (d max ) as equation 1 . for instance, when using ISL6617A and isl6617 in cascaded interleaving mode, the effective sawtooth amplitude should be scaled as 3v/22.5% = 13.33v. figure 8. cascaded phase doubler simplified diagram power stage power stage power stage power stage vout pwma pwmb isena isenb pwma pwmb isena isenb pwma pwmb csena csenb iout iout iout pwmin pwmin pwmin to controller ISL6617A phase1a phase1b phase1c phase1d pwma pwmb pwm1 isl6617/isl6611a isl6617/isl6611a pwm1a pwm1b pwm1c pwm1d vcc en_x vcc en_x table 2. controller frequency and maximum duty cycle operational modes f controller ISL6617A maximum duty cycle per phase interleaving 2 x f sw 50% synchronous f sw 100% cascaded interleaving 4 x f sw 25% figure 9. cascaded doubler operational waveforms pwm1 pwma pwmb pwm1a pwm1b pwm1c pwm1d doubler #1 doubler #2 v ramp_effective v ramp d max ------------------ = (eq. 1)
ISL6617A 11 fn7844.0 december 19, 2014 submit document feedback current sensing the ISL6617A senses current continuously for fast response. the ISL6617A supports inductor dcr sensing, or resistive sensing techniques. the associated channel current sense amplifier uses the isen inputs to reproduce a sign al proportional to the inductor current, i l . the sensed current, i sen , is proportional to the inductor current. the sensed current is used for current balance and load-line regulation. the internal circuitry (shown in figures 10 and 11 ) represents one channel. this circuitry is repeated for each channel in the doubler. the input bias current of the current sensing amplifier is typically 60na; less than 5k input impedance is preferred to minimize the offset error. in addition, the common mode input voltage to the amplifier should be less than vcc-3v. inductor dcr sensing an inductor?s winding is characteri stic of a distributed resistance, as measured by the dcr (direct current resistance) parameter. consider the inductor dcr as a separate lumped quantity, as shown in figure 10 . the channel current i l , flowing through the inductor, will also pass through the dcr. equation 2 shows the s-domain equivalent voltage across the inductor v l . a simple r-c network across the inductor extracts the dcr voltage, as shown in figure 10 . the voltage on the capacitor v c , can be shown to be proportional to the channel current i l . see equation 3 . if the r-c network components ar e selected such that the rc time constant matches the induct or time constant (rc = l/dcr), the voltage across the capacitor v c is equal to the voltage drop across the dcr, i.e., proporti onal to the channel current. with the internal low-offset current amplifier, the capacitor voltage v c is replicated across the sense resistor r isen . therefore, the current out of isen+ pin, i sen , is proportional to the inductor current. because of the internal filter at isen- pin, one capacitor, c t , is needed to match the time delay between the isen- and isen+ signals. select the proper c t to keep the time constant of r isen and c t (r isen x c t ) close to 27ns. equation 4 shows that the ratio of the channel current to the sensed current, i sen , is driven by the value of the sense resistor and the dcr of the inductor. resistive sensing for more accurate current sensing, a dedicated resistor r sense in series with each output inductor can serve as the current sense element (see figure 11 ). this technique reduces overall converter efficiency due to the additional power loss on the current sense element r sense . the same capacitor c t is needed to match the time delay between isen- and isen+ signals. select the proper c t to keep the time constant of r isen and c t (r isen x c t ) close to 27ns. equation 5 shows the ratio of the channel current to the sensed current i sen . figure 10. dcr sensing configuration i a/b i sen i l dcr r isen --------------- = - + csen(a/b) current sense v in csrtn(a/b) pwma/b power r isen(a/b) dcr l inductor r v out c out - + v c (s) c i l s ?? - + v l c t ISL6617A stage v l s ?? i l sl dcr + ? ?? ? = (eq. 2) v c s ?? s l dcr ----------- - ? 1 + ?? ?? dcr i l ? ?? ? src 1 + ? ?? ----------------------------------------------------------------- = (eq. 3) i sen i l dcr r isen --------------- ? = (eq. 4) figure 11. sense resistor in series with inductors i a/b i sen i l r sense r isen -------------------------- = csen(a/b) current sense csrt(a/b) r isen(a/b) r sense l v out c out i l c t ISL6617A - + i sen i l r sense r isen -------------------- ? = (eq. 5)
ISL6617A 12 fn7844.0 december 19, 2014 submit document feedback current balance and current monitoring the sensed currents i a and i b from each respective channel are summed together and divided by 2. the resulting average current i avg provides a measure of the total load current. channel current balance is achieved by comparing the sensed current of each channel to the average cu rrent to make an appropriate adjustment to the pwma and pwmb duty cycle with intersil?s patented current-balance method. channel current balance is essential in achieving the thermal advantage of multiphase operatio n. with good current balance, the power loss is equally dissipated over multiple devices and a greater area. the resulting average current i avg also goes out from the iout pin for current monitoring and can also be fed back to the controller?s isen lines for current balance, load-line regulation, and overcurrent protection. for fast response to the current information, the iout pin should have minimum decoupling; no more than 50ns filter is recommended. the full scale of iout is 100a; it typically should set re sistor gain around 50a to 80a at the full load to ensure that it will not hit the full scale prior to the overcurrent trip point. at the same time, the current signal accuracy is maximized. benefits of a high phase count system at heavy load condition, efficiency can be improved by spreading the load across many phases. th is is primarily because the resistive loss becomes the dominant component of total loss budget at high current levels. since the load is carried by more phases, each power device handles less current. in addition, the devices are likely to be spread over a larger area on the printed circuit board (pcb). both these factors result in improved heat dissipation for higher phase count systems. by reducing the system?s operating temperature, the reliability of the co mponents is improved. furthermore, increasing the phase count also reduces the size of ripple on both the input and output currents. it reduces emi and improves the efficiency. figures 12 and 13 show the ripple values for a 24-phase voltage regulator with the following parameters: ?input voltage: 12v ?output voltage: 1.6v ? duty cycle: 13.3% ? load current: 200a ? output phase inductor: 500nh ? phase switching frequency: 200khz in this example, the 24-phase voltage regulator (vr) can run in 6-phase, 8-phase, 12-phase or 24-phase interleaving mode. in 6-phase interleaving mode, every 4 phases runs synchronously, which yields 18.73a and 12. 93a input and output ripple currents, respectively. the 24-phase interleaving regulator significantly drops these values to 4.05a and 0.78a, respectively. as shown in table 3 , both input and output ripple currents are reduced when more phases are running in interleaving mode. note that the 8-phase vr has lowe r output ripple current than the 12-phase vr since the 8-phase vr has better output ripple cancellation factor close to the duty cycle of 1/8. figure 14 shows the efficiency of a 12-phase vr design, which runs the doubler in interleaving and synchronous modes. for comparison, a 6-phase vr with the same number of mosfets and inductors is also plotted, clearly demonstrating the efficiency improvement of a high-phase co unt system and interleaving mode over synchronous mode resulting from the better ripple cancellation. table 3. ripple current (unit: a) interleaved phases 6 8 12 24 input ripple current 18.73 11.64 8.79 4.05 output ripple current 12.93 2.70 4.83 0.78
ISL6617A 13 fn7844.0 december 19, 2014 submit document feedback figure 12. input current ripple vs duty cycle, phase count figure 13. output current ripp le vs duty cycle, phase count figure 14. efficiency comparison in 12-phase design 24 channels, 6 interleaving 24 channels, 12 interleaving 24 interleaving phases 24 channels, 8 interleaving 20 15 10 5 0 input ripple current (a) 20 15 10 5 0 duty cycle (%) 01020 304050 24 channels, 6 interleaving 24 channels, 8 interleaving 24 channels, 12 interleaving 24 interleaving phases 010 20 3040 50 output current ripple (a) duty cycle (%) 80 60 40 20 0 6-phase, same amount of mosfets and inductors phase doubler in synchronous mode phase doubler in interleaving mode 0 20 40 60 80 100 120 140 160 180 load (a) 93 92 91 90 89 88 87 86 85 efficiency (%)
ISL6617A 14 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7844.0 december 19, 2014 for additional products, see www.intersil.com/product_tree submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change december 19, 2014 fn7844.0 initial release
ISL6617A 15 fn7844.0 december 19, 2014 submit document feedback package outline drawing l10.3x3 10 lead dual flat package (dfn) rev 10, 7/14 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 5. either a mold or mark feature. 3. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.10 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 4 5 5 a b 0.10 c 1 1.00 0.20 8x 0.50 2.00 3.00 (10x 0.23) (8x 0.50) 2.00 1.60 (10 x 0.55) 3.00 0.05 0.20 ref 10 x 0.23 10x 0.35 1.60 max (4x) 0.10 ab c m 0.415 0.23 0.35 0.200 2 2.85 typ 0.415

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