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4986o-auto-10/14 features master and slave operation possible supply voltage up to 40v operating voltage v s = 5v to 27v typically 10a supply current during sleep mode typically 57a supply current in silent mode linear low-drop voltage regulator, 85ma current capability: normal, fail-safe, and silent mode atmel ata6622c vcc = 3.3v 2% atmel ata6624c vcc = 5.0v 2% atmel ata6626c vcc = 5.0v 2%, txd time-out timer disabled in sleep mode vcc is switched off vcc- undervoltage detection (4ms reset time) and watchdog reset logical combined at open drain output nres negative trigger input for watchdog boosting the voltage regulator possible with an external npn transistor lin physical layer according to lin 2.0, 2.1 and saej2602-2 wake-up capability via lin-bus, wake pin, or kl_15 pin inh output to control an external voltage regulator or to switch off the master pull up resistor txd time-out timer; atmel ata6626c: txd time-out timer is disabled bus pin is overtemperature and short circuit protected versus gnd and battery adjustable watchdog time via external resistor advanced emc and esd performance fulfills the oem ?hardware requirement s for lin in automotive applications rev.1.0? interference and damage protection according to iso7637 qualified according to aec-q100 package: qfn 5mm x 5mm with 20 pins (moisture sensitivity level 1) ata6622c/ata6624c/ata6626c lin bus transceiver with 3.3v (5v) regulator and watchdog datasheet
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 2 1. description the atmel ? ata6622c is a fully integrated lin transceiver, which complies with the lin 2.0, 2.1 and saej2602-2 specifications. it has a low- drop voltage regulator for 3.3v/85ma output and a window watchdog. the atmel ata6624c has the same functionality as the atmel at a6622c; however, it uses a 5v/85ma re gulator. the atmel ata6626c has the same functionality as atmel ata6624c without a tx d time-out timer. the voltage regulator is able to source 85ma, but the output current can be boosted by using an external npn transistor. this chip combination makes it possible to develop inexpensive, simple, yet powerful slave and master nodes for lin-bus systems. atmel ata6622c/ata6624c/ata6626c are designed to handle the low-speed data communication in vehicles, e.g., in convenience electron ics. improved slope control at the lin- driver ensures secure data communic ation up to 20kbaud. sleep mode and si lent mode guarantee very low current consumption. the atmel ata662 6c is able to switch the lin unlimited to dominant level via txd for low data rates. figure 1-1. block diagram adjustable watchdog oscillator short circuit and overtemperature protection txd time-out timer edge detection internal testing unit control unit slew rate control wake-up bus timer undervoltage reset normal/silent/ fail-safe mode 3.3/5v rf filter watchdog out 14 1 5 11 rxd gnd ntrig pvcc pvcc pvcc tm mode en txd kl_15 16 wake receiver - + 9 4 15 13 3 normal mode normal and fail-safe mode 18 19 12 7 20 lin wd_osc nres pvcc vcc vs inh 10 *) *) not in ata6626
3 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 2. pin configuration figure 2-1. pinning qfn20 table 2-1. pin description pin symbol function 1 en enables the device in normal mode 2 gnd system ground (optional) 3 ntrig low-level watchdog trigger input from microcontroller 4 wake high-voltage input for local wake-up request; if not needed, connect directly to vs 5 gnd system ground (mandatory) 6 gnd system ground (optional) 7 lin lin-bus line input/output 8 gnd system ground (optional) 9 rxd receive data output 10 inh battery related output for controlling an external voltage regulator 11 txd transmit data input; active low output (strong pull down) after a local wake-up request 12 nres output undervoltage and watchdog reset (open drain) 13 wd_osc external resistor for adjustable watchdog timing 14 tm for factory testing only (tie to ground) 15 mode low, watchdog is on; high, watchdog is off 16 kl_15 ignition detection (edge sensitive) 17 gnd system ground (optional) 18 pvcc 3.3v/5v regulator sense input pin 19 vcc 3.3v/5v regulator output/driver pin 20 vs battery supply backside heat slug is connected to all gnd pins 67 8 10 9 20 19 18 qfn 5mm x 5mm 0.65mm pitch 20 lead ata6622c ata6624c ata6626c 16 11 12 13 14 15 txd nres wd_osc tm mode kl15 gnd pvcc vcc vs inh rxd gnd lin gnd gnd wake ntrig gnd en 5 4 3 2 1 17
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 4 3. functional description 3.1 physical layer compatibility since the lin physical layer is independent from higher lin laye rs (e.g., the lin protocol layer), all nodes with a lin physica l layer according to revision 2.x can be mixe d with lin physical layer nodes, which, acco rding to older versions (i.e., lin 1.0, lin 1.1, lin 1.2, lin 1.3), are without any restrictions. 3.2 supply pin (vs) the lin operating voltage is v s = 5v to 27v. an undervoltage detection is implemented to disable data transmission if v s falls below vs th < 4v in order to avoid false bus messages. after swit ching on vs, the ic starts in fail-safe mode, and the voltage regulator is switched on. the supply current is typically 10a in sleep mode and 57a in silent mode. 3.3 ground pin (gnd) the ic does not affect the lin bus in th e event of gnd disconnection. it is able to handle a ground shift up to 11.5% of vs. the mandatory system ground is pin 5. 3.4 voltage regulator output pin (vcc) the internal 3.3v/5v voltage regulator is capable of driving l oads up to 85ma. it is able to supply the microcontroller and other ics on the pcb and is protected against overloads by means of current limitation and overtemperatur e shut-down. furthermore, the output voltage is monitored and will cause a reset signal at th e nres output pin if it drops below a defined threshold v thun . to boost up the maximum load current, an external np n transistor may be used, with its base connected to the vcc pin and its emitter connected to pvcc. 3.5 voltage regulator sense pin (pvcc) the pvcc is the sense input pin of the 3. 3v/5v voltage regulator. for normal applicati ons (i.e., when only using the internal output transistor), this pin is connected to the vcc pin. if an external boosting transistor is used, the pvcc pin must be connected to the output of this tr ansistor, i.e., its emitter terminal. 3.6 bus pin (lin) a low-side driver with internal current lim itation and thermal shutdown and an internal pull-up resistor compliant with the lin 2.x specification are implement ed. the allowed voltage range is between ?27v and +40v. reverse currents from the lin bus to vs are suppressed, even in the event of gnd shifts or battery disconnection. lin receiver thresholds are compatible with the lin protocol specification. the fa ll time from recessive to dominant bus st ate and the rise time from dominant to recessive bus state are slope controlled. 3.7 input/output pin (txd) in normal mode the txd pin is the microc ontroller interface used to control the state of the lin output. txd must be pulled to ground in order to have a low lin-bus. if txd is high or unconnected (internal pull-up resistor), the lin output transistor is turned off, and the bus is in recessive state. during fail-saf e mode, this pin is used as output. it is current-limited to < 8m a. and is latched to low if the last wa ke-up event was from pin wake or kl_15. 3.8 txd dominant time-out function the txd input has an internal pull-up resistor. an internal timer prevents the bus line from being driven permanently in dominant state. if txd is forc ed to low for longer than t dom > 6ms, the lin-bus driver is switched to recessive state. to reactivate the lin bus driv er, switch txd to high (> 10s). the time-out function is disabled in the ata6626c. switchin g to dominant level on the lin bus occurs without any time limitations.
5 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 3.9 output pin (rxd) this output pin reports the state of the lin-bus to the microcontro ller. lin high (recessive state) is reported by a high level at rxd; lin low (dominant state) is reported by a low level at rx d. the output has an internal pull-up resistor with typically 5k to vcc. the ac characteristics can be defined with an external load capacitor of 20pf. the output is short-circuit pr otected. rxd is switched off in unpowered mode (i.e., v s = 0v). 3.10 enable input pin (en) the enable input pin controls th e operation mode of the device. if en is high, the circuit is in normal mode, with transmission paths from txd to lin and from lin to rxd both active. t he vcc voltage regulator operat es with 3.3v/5v/85ma output capability. if en is switched to low while txd is still high, the device is forced to silent mode. no data tr ansmission is then possible, a nd the current consumptio n is reduced to i vs typ. 57a. the vcc regulator has its full functionality. if en is switched to low while txd is low, the device is fo rced to sleep mode. no data transmission is possible, and the voltage regulator is switched off. 3.11 wake input pin (wake) the wake input pin is a high-voltage input used to wake up the device from sleep mode or silent mode. it is usually connected to an external switch in the application to generate a local wake-up. a pull-up current source, typically 10a, is implemented. if a local wake-up is not needed in the applicatio n, connect the wake pin directly to the vs pin. 3.12 mode input pin (mode) connect the mode pin directly or via an external resistor to gnd for normal watc hdog operation. to debug the software of the connected microcontroller, connect mode pi n to 3.3v/5v and the watchdog is switched off. 3.13 tm input pin the tm pin is used for final production measurements at atmel ? . in normal application, it has to be always connected to gnd. 3.14 kl_15 pin the kl_15 pin is a high-voltage input used to wake up the device from sleep or silent mode. it is an edge sensitive pin (low- to-high transition). it is usually connected to ignition to gen erate a local wake-up in the application when the ignition is switched on. although kl_15 pin is at high voltage (v batt ), it is possible to switch the ic into sleep or silent mode. connect the kl_15 pin directly to gnd if you do not need it. a debounce timer with a typical tdb kl_15 of 160s is implemented. the input voltage threshold can be adjusted by varyin g the external resistor due to the input current i kl_15 . to protect this pin against voltage transients, a serial resistor of 47k and a ceramic capacitor of 100nf are recommended. with this rc combination you can increase the wake-up time tw kl_15 and, therefore, the sensitivit y against transients on the ignition kl.15. you can also increase the wake-up time usi ng external capacitors with higher values. 3.15 inh output pin the inh output pin is used to switch an external voltage regulator on dur ing normal or fail-safe mode. the inh pin is switched off in sleep or silent mode. it is possible to switch off the external 1k master resistor via the inh pin for master node applications. the inh pin is switch ed off during vcc undervoltage reset. 3.16 reset output pin (nres) the reset output pin, an open drain output, switches to low during v cc undervoltage or a watchdog failure.
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 6 3.17 wd_osc output pin the wd_osc output pin provides a typical voltage of 1.2v, wh ich supplies an external resistor with values between 34k and 120k to adjust the watchdog oscillator time. 3.18 ntrig input pin the ntrig input pin is the trigger input for the window watchdog . a pull-up resistor is implemented. a negative edge triggers the watchdog. the trigger signal (low) must exceed a minimum time t trigmin to generate a watchdog trigger. 3.19 wake-up events from sleep or silent mode lin-bus wake pin en pin kl_15
7 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 4. modes of operation figure 4-1. modes of operation 4.1 normal mode this is the normal transmitting and receiving mode of the lin in terface in accordance with the lin specification lin 2.x. the voltage regulator is active and can source up to 85ma. th e undervoltage detection is ac tivated. the watchdog needs a trigger signal from ntrig to avoid resets at nres. if nres is switched to low, the ic cha nges its state to fail-safe mode. table 4-1. table of modes mode of operation transceiver vcc watchdog wd_osc inh rxd lin fail-safe off 3.3v/5v on 1.23v on high, except after wake-up recessive normal on 3.3v/5v on 1.23v on lin depending txd depending silent off 3.3v/5v off 0v off high recessive sleep off 0v off 0v off 0v recessive unpowered mode v batt = 0v a: v s > 5v b: v s < 3.7v c: bus wake-up event d: wake up from wake or kl_15 pin fail-safe mode normal mode vcc: 3.3v/5v with undervoltage monitoring communication: on watchdog: on vcc: 3.3v/5v with undervoltage monitoring communication: off watchdog: on silent mode vcc: 3.3v/5v with undervoltage monitoring communication: off watchdog: off sleep mode vcc: switched off communication: off watchdog: off go to silent command a txd = 0 en = 0 txd = 1 en = 0 en = 1 en = 1 en = 1 b b b c + d + e e c + d b local wake-up event go to sleep command e: nres switches to low
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 8 4.2 silent mode a falling edge at en when txd is high switches the ic into silent mode. the txd signal has to be logic high during the mode select window (see figure 4-2 ). the transmission path is disabled in s ilent mode. the overall supply current from v batt is a combination of the i vssi = 57a plus the vcc regulator output current i vcc . the internal slave termination between the lin pin and the vs pi n is disabled in silent mode, only a weak pull-up current (typically 10a) between the lin pin and the vs pin is present . silent mode can be activated independently from the actual level on the lin, wake, or kl_15 pins. if an undervoltage condition occurs, nres is switched to low, and the ic changes its state to fail-safe mode. a voltage less than the lin pre_wake detection vlinl at the lin pin activates the internal lin receiver and switches on the internal slave termination between the lin pin and the v s pin. figure 4-2. switch to silent mode delay time silent mode t d _silent maximum 20s mode select window lin switches directly to recessive mode t d = 3.2s lin vcc nres txd en normal mode silent mode
9 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (> t bus ) and the following rising edge at the lin pin (see figure 4-3 on page 9 ) results in a remote wake-up request. the device switches from silent mode to fail-safe mode. the remote wake-up request is in dicated by a low level at the rxd pin to interrupt the microcontroller (see figure 4-3 on page 9 ). en high can be used to switch directly to normal mode. figure 4-3. lin wake up from silent mode watchdog off start watchdog lead time t d watchdog undervoltage detection active silent mode 3.3v/5v fail safe mode 3.3v/5v normal mode low fail-safe mode normal mode en high node in silent mode high high nres en vcc voltage regulator rxd lin bus bus wake-up filtering time t bus txd
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 10 4.3 sleep mode a falling edge at en when txd is low switches the ic into sleep mode. the txd signal has to be logic low during the mode select window ( figure 4-4 on page 10 ). in order to avoid any influence to the li n-pin during switching into sleep mode it is possible to switch the en up to 3.2 s earlier to low than the txd. therefore, the best and easiest way are two falling edges at txd and en at the same time.the transmission path is disabled in sleep mode. the supply current i vssleep from v batt is typically 10a. the vcc regulator is switched off. nres and rxd are low. the in ternal slave termination betwe en the lin pin and vs pin is disabled, only a weak pull-up current (t ypically 10a) between the lin pin and the vs pin is present. sleep mode can be activated independently from the current level on the lin, wake, or kl_15 pin. a voltage less than the lin pre_wake detection vlinl at the lin pin activates the internal lin receiver and switches on the internal slave termination between the lin pin and the v s pin. a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (> t bus ) and a following rising edge at pin lin results in a remote wake-up request. the device switches from sleep mode to fail-safe mode. the vcc regulator is activated, and the remote wake-up request is indicated by a low level at the rxd pin to interrupt the microcontroller (see figure 4-5 on page 11 ). en high can be used to switch directly from sleep/silent to fail-safe mode. if en is st ill high after vcc ramp up and undervoltage reset time, the ic switches to the normal mode. figure 4-4. switch to sleep mode delay time sleep mode t d_sleep = maximum 20s lin switches directly to recessive mode t d = 3.2s lin vcc nres txd en sleep mode normal mode mode select window
11 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 4.4 fail-safe mode the device automatically switches to fail-safe mode at system power-up. the voltage regulator is switched on (see figure 5-1 on page 13 ). the nres output switches to low for t res = 4ms and gives a reset to the micr ocontroller. lin communication is switched off. the ic stays in this mode until en is switc hed to high. the ic then changes to normal mode. a power down of v batt (v s < 3.7v) during silent or sleep mode switches the ic into fail-safe mode after power up. a low at nres switches into fail-safe mode directly. during fail-safe mode the txd pin is an output and signals the last wake-up source. 4.5 unpowered mode if you connect battery voltage to the application circuit, the vo ltage at the vs pin increases according to the block capacitor (see figure 5-1 on page 13 ). after vs is higher than the vs undervoltage threshold vs th , the ic mode changes from unpowered mode to fail-safe mode. the vcc out put voltage reaches its nominal value after t vcc . this time, t vcc , depends on the vcc capacitor and the load. the nres is low for the reset time delay t reset . during this time, t reset , no mode change is possible. figure 4-5. lin wake up from sleep mode regulator wake-up time off state on state low fail-safe mode normal mode en high microcontroller start-up time delay reset time low low watchdog nres en vcc voltage regulator rxd lin bus bus wake-up filtering time t bus txd watchdog off start watchdog lead time t d
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 12 5. wake-up scenarios from silent or sleep mode 5.1 remote wake-up via dominant bus state a voltage less than the lin pre_wake detection v linl at the lin pin activates the internal lin receiver. a falling edge at the lin pin followed by a dominant bus level v busdom maintained for a certain time period (> t bus ) and a rising edge at pin lin result in a remote wake-up request. th e device switches from silent or sleep mode to fail-safe mode. the vcc voltage regulator is/remains activated, the inh pi n is switched to high, and the remote wake-up request is indicated by a low level at the rxd pin to generate an interrupt for the microcontro ller. a low level at the lin pin in the normal mode starts the bus wake-up filtering time, and if the ic is switched to silent or sleep mode, it will receive a wake-up after a positive edge at the lin pin. 5.2 local wake-up via pin wake a falling edge at the wake pin fo llowed by a low level maintained for a certain time period (> t wake ) results in a local wake- up request. the device switches to fail-saf e mode. the local wake-up request is indicated by a low level at the rxd pin to generate an interrupt in the microcontroller and a strong pull down at txd. when the wake pin is low, it is possible to switch to silent or sleep mode via pin en. in this case, the wake- up signal has to be switched to high > 10s before the negative edge at wake starts a new local wake-up request. 5.3 local wake-up via pin kl_15 a positive edge at pin kl_15 followed by a high voltage level for a certain time period (> t kl_15 ) results in a local wake-up request. the device switches into the fail-safe mode. the ex tra long wake-up time ensures that no transients at kl_15 create a wake up. the local wake-up reques t is indicated by a low level at the rxd pin to generate an interrupt for the microcontroller and a strong pull down at txd. during high-level voltage at pin kl_15, it is possible to switch to silent or sleep mode via pin en. in this case, the wake-up signal has to be switched to low > 250s before the positive edge at kl_15 starts a new local wake-up request. with exte rnal rc combination, the time is even longer. 5.4 wake-up source recognition the device can distinguish between a local wake-up request (wake or kl_15 pins) and a remote wake-up request (dominant lin bus state). the wa ke-up source can be read on the txd pin in fail-safe mode. a high level indicates a remote wake-up request (weak pull up at the txd pin); a low level indicates a local wake-up request (strong pull down at the txd pin). the wake-up request flag (signalled on the rxd pin), as we ll as the wake-up source flag (signalled on the txd pin), is immediately reset if the microcontroller sets the en pin to high (see figure 4-2 on page 8 and figure 4-3 on page 9 ) and the ic is in normal mode. the last wake-up source flag is stored and signalled in fail-safe mode at the txd pin. 5.5 fail-safe features during a short-circuit at lin to v battery , the output limits the output current to i bus_lim . due to the power dissipation, the chip temperature exceeds t linoff , and the lin output is switched off. the chip cools down and after a hysteresis of t hys , switches the output on again. rxd stays on high bec ause lin is high. during lin overtemperature switch-off, the vcc regulator works independently. during a short-circuit from lin to gnd the ic can be s witched into sleep or silent mode. if the short-circuit disappears, the ic starts with a remote wake-up. the reverse current is very low < 2 a at the lin pin during loss of v batt . this is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. during a short circuit at vcc, the ou tput limits the output current to i vcclim . because of undervoltage, nres switches to low and sends a reset to the microcontroller. the ic swit ches into fail-safe mode. if the chip temperature exceeds the value t vccoff , the vcc output switches off. the chip cools down and after a hysteresis of t hys , switches the output on again. because of the fail-safe mode, the vcc voltage will switch on again although en is switched off from the microcontroller. the microcontroller ca n start with its normal operation. en pin provides a pull-down resistor to force the tr ansceiver into recessive mode if en is disconnected. rxd pin is set floating if v batt is disconnected. txd pin provides a pull-up resistor to force the tr ansceiver into recessive mode if txd is disconnected.
13 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 if txd is short-circuited to gn d, it is possible to switch to sleep mode via enable after t dom > 20ms (only for atmel ? ata6622c/ata6624c). if the wd_osc pin has a short-circuit to gnd and the nt rig signal has a period time > 27ms, the watchdog runs with an internal oscillator and guarantees a reset after the second ntrig signal at the latest. if the resistor at wo_osc pin is disconnect ed, the watchdog runs with an internal oscillator and guarantees a reseet after the second ntrig signal at the latest. 5.6 voltage regulator the voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the microcontroller. it is recommended to use an electrolythic c apacitor with c > 1.8f and a ceramic capacitor with c = 100nf. the values of these capacitors can be vari ed by the customer, depending on the application. the main power dissipation of the ic is created from the vcc output current i vcc , which is needed for the application. in figure 5-2 on page 13 the safe operating area of the atmel ata6624c/ata6626c is shown. figure 5-1. vcc voltage regulator: ramp-up and undervoltage detection figure 5-2. power dissipation: safe operating area: vcc output current versus supply voltage v s at different ambient temperatures due to r thja = 35k/w for programming purposes of the microcontroller it is potentially nece ssary to supply the v cc output via an external power supply while the v s pin of the system basis chip is disconnected. this will not affect the system basis chip. nres 5v/3.3v t t t vs vcc 5v/3.3v v thun t res_f t reset t vcc 5.5v/3.8v 12v 5 6 7 8 9 10 1112 1314 15161718 v s (v) 90 80 70 60 50 40 30 20 10 0 i vcc (ma) t amb = 105c t amb = 115c t amb = 125c
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 14 6. watchdog the watchdog anticipates a trigger signal from the microcon troller at the ntrig (negative edge) input within a time window of t wd . the trigger signal must exceed a minimum time t trigmin > 200ns. if a triggering signal is not received, a reset signal will be generated at output nres. the timing basis of the watchdog is provided by the internal o scillator. its time period, t osc , is adjustable via the external resistor r wd_osc (34k to 120k ). during silent or sleep mode the watchdog is switched off to reduce current consumption. the minimum time for the first watchdog pulse is required afte r the undervoltage reset at nres disappears. it is defined as lead time t d . after wake up from sleep or silent mode, the lead time t d starts with the negativ e edge of the rxd output. 6.1 typical timing sequence with r wd_osc = 51k the trigger signal t wd is adjustable between 20ms and 64ms using the external resistor r wd_osc . for example, with an ex ternal resistor of r wd_osc = 51k 1%, the typical parameters of the watchdog are as follows: t osc = 0.405 r wd_osc ? 0.0004 (r wd_osc ) 2 (r wd_osc in k ; t osc in s) t osc = 19.6s due to 51k t d = 7895 19.6s = 155ms t 1 = 1053 19.6s = 20.6ms t 2 = 1105 19.6s = 21.6ms t nres = constant = 4ms after ramping up the battery voltage, the 3.3v/5v regulator is switched on. the re set output nres stays low for the time t reset (typically 4ms), then it switc hes to high, and the watchdog waits for the trigge r sequence from the microcontroller. the lead time, t d , follows the reset and is t d = 155ms. in this time, the first watchdog pulse from the microcontroller is required. if the trigger pulse ntrig occurs during this time, the time t 1 starts immediately. if no trigger signal occurs during the time t d , a watchdog reset with t nres = 4ms will reset the mi crocontroller after t d = 155ms. the times t 1 and t 2 have a fixed relationship between each other. a triggering signal from the microc ontroller is anticipated within the time frame of t 2 = 21.6ms. to avoid false triggering from glitches, the tr igger pulse must be longer than t trig,min > 200ns. this slope serves to restart the watchdog sequence. if the triggering signal fails in this open window t 2 , the nres output will be drawn to ground. a triggering signal during the closed window t 1 immediately switches nres to low. figure 6-1. timing sequence with r wd_osc = 51k t nres = 4ms undervoltage reset watchdog reset t reset = 4ms t trig > 200ns t 1 = 20.6ms t 2 = 21ms t 2 t 1 t wd t d = 155ms vcc 3.3v/5v ntrig nres
15 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 6.2 worst case calculation with r wd_osc = 51k the internal oscillator has a tolerance of 20%. this means that t 1 and t 2 can also vary by 20%. the worst case calculation for the watchdog period t wd is calculated as follows. the ideal watchdog time t wd is between the maximum t 1 and the minimum t 1 plus the minimum t 2 . t 1,min = 0.8 t 1 = 16.5ms, t 1,max = 1.2 t 1 = 24.8ms t 2,min = 0.8 t 2 = 17.3ms, t 2,max = 1.2 t 2 = 26ms t wdmax = t 1min + t 2min = 16.5ms + 17.3ms = 33.8ms t wdmin = t 1max = 24.8ms t wd = 29.3ms 4.5ms (15%) a microcontroller with an oscillator tolerance of 15% is sufficient to supply the trigger inputs correctly. table 6-1. typical watchdog timings r wd_osc k oscillator period t osc /s lead time t d /ms closed window t 1 /ms open window t 2 /ms trigger period from microcontroller t wd /ms reset time t nres /ms 34 13.3 105 14.0 14.7 19.9 4 51 19.61 154.8 20.64 21.67 29.32 4 91 33.54 264.80 35.32 37.06 50.14 4 120 42.84 338.22 45.11 47.34 64.05 4
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 16 7. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit supply voltage v s v s ?0.3 +40 v pulse time 500ms; t a = 25c output current i vcc 85ma v s +40 v pulse time 2min; t a =25c output current i vcc 85ma v s 27 v wake (with 33k serial resistor) kl_15 (with 47k /100nf) dc voltage transient voltage due to iso7637 (coupling 1nf) ?1 ?150 +40 +100 v v inh - dc voltage ?0.3 v s + 0.3 v lin - dc voltage ?27 +40 v logic pins (rxd, txd, en, nres, ntrig, wd_osc, mode, tm) ?0.3 +5.5 v output current nres i nres +2 ma pvcc dc voltage vcc dc voltage ?0.3 ?0.3 +5.5 +6.5 v v esd according to ibee lin emc test spec. 1.0 following iec 61000-4-2 - pin vs, lin, kl_15 (47k /100nf) to gnd - pin wake (33k serial resistor) to gnd 6 5 kv kv esd hbm following stm5.1 with 1.5k 100pf - pin vs, lin, kl_15, wake to gnd 6 kv hbm esd ansi/esd-stm5.1 jesd22-a114 aec-q100 (002) 3 kv cdm esd stm 5.3.1 750 v machine model esd aec-q100-revf(003) 200 v junction temperature t j ?40 +150 c storage temperature t s ?55 +150 c 8. thermal characteristics parameters symbol min. typ. max. unit thermal resistance junction to heat slug r thjc 10 k/w thermal resistance junction to ambient, where heat slug is soldered to pcb r thja 35 k/w thermal shutdown of vcc regulator 150 165 170 c thermal shutdown of lin output 150 165 170 c thermal shutdown hysteresis 10 c
17 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 9. electrical characteristics 5v < v s < 27v, -40c < tj < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* 1 vs pin 1.1 nominal dc voltage range vs v s 5 27 v a 1.2 supply current in sleep mode sleep mode v lin > v s ? 0.5v v s < 14v (t j = 25c) vs i vssleep 3 10 14 a b sleep mode v lin > v s ? 0.5v v s < 14v (t j = 125c) vs i vssleep 5 11 16 a a 1.3 supply current in silent mode bus recessive v s < 14v (t j = 25c) without load at vcc vs i vssi 47 57 67 a b bus recessive v s < 14v (t j = 125c) without load at vcc vs i vssi 56 66 76 a a 1.4 supply current in normal mode bus recessive v s < 14v without load at vcc vs i vsrec 0.3 0.8 ma a 1.5 supply current in normal mode bus dominant v s < 14v v cc load current 50 ma vs i vsdom 50 53 ma a 1.6 supply current in fail- safe mode bus recessive v s < 14v without load at vcc vs i vsfail 250 550 a a 1.7 v s undervoltage threshold vs v sth 3.7 4.4 5 v a 1.8 vs undervoltage threshold hysteresis vs v sth_hys 0.2 v a 2 rxd output pin 2.1 low-level output sink current normal mode v lin =0v v rxd =0.4v rxd i rxd 1.3 2.5 8 ma a 2.2 low-level output voltage i rxd = 1ma rxd v rxdl 0.4 v a 2.3 internal resistor to v cc rxd r rxd 3 5 7 k a 3 txd input/output pin 3.1 low-level voltage input txd v txdl ?0.3 +0.8 v a 3.2 high-level voltage input txd v txdh 2 v cc + 0.3v v a 3.3 pull-up resistor v txd =0v txd r txd 125 250 400 k a 3.4 high-level leakage current v txd =vcc txd i txd ?3 +3 a a 3.5 low-level output sink current at local wake-up request fail-safe mode v lin = v s v wake = 0v v txd = 0.4v txd i txdwake 2 2.5 8 ma a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 18 4 en input pin 4.1 low-level voltage input en v enl ?0.3 +0.8 v a 4.2 high-level voltage input en v enh 2 v cc + 0.3v v a 4.3 pull-down resistor v en = v cc en r en 50 125 200 k a 4.4 low-level input current v en = 0v en i en ?3 +3 a a 5 ntrig watchdog input pin 5.1 low-level voltage input ntrig v ntrigl ?0.3 +0.8 v a 5.2 high-level voltage input ntrig v ntrigh 2 v cc + 0.3v v a 5.3 pull-up resistor v ntrig = 0v ntrig r ntrig 125 250 400 k a 5.4 high-level leakage current v ntrig = v cc ntrig i ntrig ?3 +3 a a 6 mode input pin 6.1 low-level voltage input mode v model ?0.3 +0.8 v a 6.2 high-level voltage input mode v modeh 2 v cc + 0.3v v a 6.3 leakage current v mode = v cc or v mode = 0v mode i mode ?3 +3 a a 7 inh output pin 7.1 high-level voltage i inh = ?15ma inh v inhh v s ? 0.75 v s v a 7.2 switch-on resistance between vs and inh inh r inh 30 50 a 7.3 leakage current sleep mode v inh = 0v/27v, v s = 27v inh i inhl ?3 +3 a a 8 lin bus driver: bus load conditions: load 1 (small): 1nf, 1k ; load 2 (large): 10nf, 500 ; internal pull-up r rxd = 5k ; c rxd = 20pf load 3 (medium): 6.8nf, 660 , characterized on samples 10.6 and 10.7 specifies the timing parameters for proper operation at 20kbit/s and 10.8 and 10.9 at 10.4kbit/s 8.1 driver recessive output voltage load1/load2 lin v busrec 0.9 v s v s v a 8.2 driver dominant voltage v vs = 7v r load = 500 lin v _losup 1.2 v a 8.3 driver dominant voltage v vs = 18v r load = 500 lin v _hisup 2 v a 8.4 driver dominant voltage v vs = 7.0v r load = 1000 lin v _losup_1k 0.6 v a 8.5 driver dominant voltage v vs = 18v r load = 1000 lin v _hisup_1k 0.8 v a 8.6 pull-up resistor to v s the serial diode is mandatory lin r lin 20 30 60 k a 8.7 voltage drop at the serial diodes in pull-up path with r slave i serdiode = 10ma lin v serdiode 0.4 1.0 v d 9. electrical characteristics (continued) 5v < v s < 27v, -40c < tj < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
19 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 8.8 lin current limitation v bus = v batt_max lin i bus_lim 40 120 200 ma a 8.9 input leakage current at the receiver including pull-up resistor as specified input leakage current driver off v bus = 0v v batt = 12v lin i bus_pas_dom ?1 ?0.35 ma a 8.10 leakage current lin recessive driver off 8v < v batt < 18v 8v < v bus < 18v v bus v batt lin i bus_pas_rec 10 20 a a 8.11 leakage current when control unit disconnected from ground. loss of local ground must not affect communication in the residual network. gnd device = v s v batt = 12v 0v < v bus < 18v lin i bus_no_gnd ?10 +0.5 +10 a a 8.12 leakage current at a disconnected battery. node has to sustain the current that can flow under this condition. bus must remain operational under this condition. v batt disconnected v sup_device = gnd 0v < v bus < 18v lin i bus_no_bat 0.1 2 a a 8.13 capacitance on pin lin to gnd lin c lin 20 pf d 9 lin bus receiver 9.1 center of receiver threshold v bus_cnt = (v th_dom + v th_rec )/2 lin v bus_cnt 0.475 v s 0.5 v s 0.525 v s v a 9.2 receiver dominant state v en = 5v lin v busdom 0.4 v s v a 9.3 receiver recessive state v en = 5v lin v busrec 0.6 v s v a 9.4 receiver input hysteresis v hys = v th_rec ? v th_dom lin v bushys 0.028 v s 0.1 v s 0.175 v s v a 9.5 pre_wake detection lin high-level input voltage lin v linh v s ? 2v v s + 0.3v v a 9.6 pre_wake detection lin low-level input voltage activates the lin receiver lin v linl ?27 v s ? 3.3v v a 9. electrical characteristics (continued) 5v < v s < 27v, -40c < tj < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 20 10 internal timers 10.1 dominant time for wake-up via lin bus v lin = 0v lin t bus 30 90 150 s a 10.2 time delay for mode change from fail-safe into normal mode via en pin v en = 5v en t norm 5 15 20 s a 10.3 time delay for mode change from normal mode to sleep mode via en pin v en = 0v en t sleep 2 7 12 s a 10.4 txd dominant time-out time (ata6626c disabled) v txd = 0v txd t dom 6 13 20 ms a 10.5 time delay for mode change from silent mode into normal mode via en v en = 5v en t s_n 5 15 40 s a 10.6 duty cycle 1 th rec(max) = 0.744 v s th dom(max) = 0.581 v s v s = 7.0v to 18v t bit = 50s d1 = t bus_rec(min) /(2 t bit ) lin d1 0.396 a 10.7 duty cycle 2 th rec(min) = 0.422 v s th dom(min) = 0.284 v s v s = 7.6v to 18v t bit = 50s d2 = t bus_rec(max) /(2 t bit ) lin d2 0.581 a 10.8 duty cycle 3 th rec(max) = 0.778 v s th dom(max) = 0.616 v s v s = 7.0v to 18v t bit = 96s d3 = t bus_rec(min) /(2 t bit ) lin d3 0.417 a 10.9 duty cycle 4 th rec(min) = 0.389 v s th dom(min) = 0.251 v s v s = 7.6v to 18v t bit = 96s d4 = t bus_rec(max) /(2 t bit ) lin d4 0.590 a 10.10 slope time falling and rising edge at lin v s = 7.0v to 18v lin t slope_fall t slope_rise 3.5 22.5 s a 11 receiver electrical ac parameters of the lin physical layer lin receiver, rxd load conditions: c rxd = 20pf 11.1 propagation delay of receiver ( figure 9-1 on page 23 ) v s = 7.0v to 18v t rx_pd = max(t rx_pdr , t rx_pdf ) rxd t rx_pd 6 s a 11.2 symmetry of receiver propagation delay rising edge minus falling edge v s = 7.0v to 18v t rx_sym = t rx_pdr ? t rx_pdf rxd t rx_sym ?2 +2 s a 9. electrical characteristics (continued) 5v < v s < 27v, -40c < tj < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
21 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 12 nres open drain output pin 12.1 low-level output voltage v s 5.5v i nres = 1ma nres v nresl 0.14 v a 12.2 low-level output low 10k to 5v v cc = 0v nres v nresll 0.14 v a 12.3 undervoltage reset time v s 5.5v c nres = 20pf nres t reset 2 4 6 ms a 12.4 reset debounce time for falling edge v s 5.5v c nres = 20pf nres t res_f 1.5 10 s a 13 watchdog oscillator 13.1 voltage at wd_osc in normal mode i wd_osc = ?200a v vs 4v wd_ osc v wd_osc 1.13 1.23 1.33 v a 13.2 possible values of resistor wd_ osc r osc 34 120 k a 13.3 oscillator period r osc = 34k t osc 10.65 13.3 15.97 s a 13.4 oscillator period r osc = 51k t osc 15.68 19.6 23.52 s a 13.5 oscillator period r osc = 91k t osc 26.83 33.5 40.24 s a 13.6 oscillator period r osc = 120k t osc 34.2 42.8 51.4 s a 14 watchdog timing relative to t osc 14.1 watchdog lead time after reset t d 7895 cycles a 14.2 watchdog closed window t 1 1053 cycles a 14.3 watchdog open window t 2 1105 cycles a 14.4 watchdog reset time nres nres t nres 3.2 4 4.8 ms a 15 kl_15 pin 15.1 high-level input voltage r v = 47k positive edge initializes a wake-up kl_15 v kl_15h 4 v s + 0.3v v a 15.2 low-level input voltage r v = 47k kl_15 v kl_15l ?1 +2 v a 15.3 kl_15 pull-down current v s < 27v v kl_15 = 27v kl_15 i kl_15 50 65 a a 15.4 internal debounce time without external capacitor kl_15 tdb kl_15 80 160 250 s a 15.5 kl_15 wake-up time r v = 47k , c = 100nf kl_15 tw kl_15 0.4 2 4.5 ms c 16 wake pin 16.1 high-level input voltage wake v wakeh v s ? 1v v s + 0.3v v a 16.2 low-level input voltage initializes a wake-up signal wake v wakel ?1 v s ? 3.3v v a 16.3 wake pull-up current v s < 27v v wake = 0v wake i wake ?30 ?10 a a 16.4 high-level leakage current v s = 27v v wake = 27v wake i wakel ?5 +5 a a 9. electrical characteristics (continued) 5v < v s < 27v, -40c < tj < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 22 16.5 time of low pulse for wake-up via wake pin v wake = 0v wake i wakel 30 70 150 s a 17 vcc voltage regulator ata6622c, pvcc = vcc 17.1 output voltage vcc 4v < v s < 18v (0ma to 50ma) vcc vcc nor 3.234 3.366 v a 4.5v < v s < 18v (0ma to 85ma) vcc vcc nor 3.234 3.366 v c 17.2 output voltage vcc at low vs 3v < v s < 4v vcc vcc low v s ? v d 3.366 v a 17.3 regulator drop voltage v s > 3v i vcc = ?15ma vs, vcc v d1 200 mv a 17.4 regulator drop voltage v s > 3v i vcc = ?50ma vs, vcc v d2 500 700 mv a 17.5 line regulation 4v < v s < 18v vcc vcc line 0.1 0.2 % a 17.6 load regulation 5ma < i vcc < 50ma vcc vcc load 0.1 0.5 % a 17.7 power supply ripple rejection 10hz to 100khz c vcc = 10f v s = 14v, i vcc = ?15ma vcc 50 db d 17.8 output current limitation v s > 4v vcc i vcclim ?240 ?160 ?85 ma a 17.9 external load capacity 0.2 < esr < 5 at 100khz for phase margin 60 vcc c load 1.8 10 f d esr < 0.2 at 100khz for phase margin 30 17.10 vcc undervoltage threshold referred to vcc v s > 4v vcc v thunn 2.8 3.2 v a 17.11 hysteresis of undervoltage threshold referred to vcc v s > 4v vcc vhys thun 150 mv a 17.12 ramp-up time v s > 4v to v cc = 3.3v c vcc = 2.2f i load = ?5ma at vcc vcc t vcc 100 250 s a 18 vcc voltage regulator ata6624c/ata6626c, pvcc = vcc 18.1 output voltage vcc 5.5v < v s < 18v (0ma to 50ma) vcc vcc nor 4.9 5.1 v a 6v < v s < 18v (0ma to 85ma) vcc vcc nor 4.9 5.1 v c 18.2 output voltage vcc at low vs 4v < v s < 5.5v vcc vcc low v s ? v d 5.1 v a 18.3 regulator drop voltage v s > 4v i vcc = ?20ma vs, vcc v d1 250 mv a 18.4 regulator drop voltage v s > 4v i vcc = ?50ma vs, vcc v d2 400 600 mv a 18.5 regulator drop voltage v s > 3.3v i vcc = ?15ma vs, vcc v d3 200 mv a 18.6 line regulation 5.5v < v s < 18v vcc vcc line 0.1 0.2 % a 18.7 load regulation 5ma < i vcc < 50ma vcc vcc load 0.1 0.5 % a 9. electrical characteristics (continued) 5v < v s < 27v, -40c < tj < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
23 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 figure 9-1. definition of bus timing characteristics 18.8 power supply ripple rejection 10hz to 100khz c vcc = 10f v s = 14v, i vcc = ?15ma vcc 50 db d 18.9 output current limitation v s > 5.5v vcc i vcclim ?240 ?130 ?85 ma a 18.10 external load capacity 0.2 < esr < 5 at 100khz for phase margin 60 vcc c load 1.8 10 f d esr < 0.2 at 100khz for phase margin 30 18.11 vcc undervoltage threshold referred to vcc v s > 5.5v vcc v thunn 4.2 4.8 v a 18.12 hysteresis of undervoltage threshold referred to vcc v s > 5.5v vcc vhys thun 250 mv a 18.13 ramp-up time v s > 5.5v to v cc = 5v c vcc = 2.2f i load = ?5ma at vcc vcc t vcc 130 300 s a 9. electrical characteristics (continued) 5v < v s < 27v, -40c < tj < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter txd (input to transmitting node) vs (transceiver supply of transmitting node) rxd (output of receiving node1) rxd (output of receiving node2) lin bus signal thresholds of receiving node1 thresholds of receiving node2 t bus_rec(max) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) t rx_pdf(1) t bus_dom(min) t bus_dom(max) th rec(max) th dom(max) th rec(min) th dom(min) t bus_rec(min) t bit t bit t bit
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 24 figure 9-2. typical application circuit 67 8 10 9 20 19 18 mlp 5mm x 5mm 0.65mm pitch 20 lead ata6622c ata6624c ata6626c 16 11 12 13 14 15 txd nres lin sub bus wd_osc tm mode master node pull-up debug kl_15 pvcc vcc vs rxd lin gnd wake wake switch 51k 10k 1k 33k 10k 47k 10k ntrig ntrig microcontroller reset txd gnd rxd en v cc kl15 inh ignition kl30 v battery en 5 4 3 2 1 17 220pf 100nf 22f + 100nf 10f 100nf +
25 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 figure 9-3. application circuit with external npn-transistor 67 8 10 9 20 19 18 mlp 5mm x 5mm 0.65mm pitch 20 lead ata6622c ata6624c ata6626c 16 11 12 13 14 15 txd nres lin sub bus wd_osc tm mode master node pull-up debug kl_15 pvcc vcc vs rxd lin gnd wake wake switch 51k 10k 1k 33k 10k 47k 10k ntrig ntrig microcontroller reset gnd txd rxd en v cc kl15 inh ignition kl30 v battery en 5 4 3 2 1 17 220pf 100nf 22f + 100nf 10f 100nf + + 2.2f 3.3 mjd31c *) *) note that the output voltage pvcc is no longer short-ciruit protected when boosting the output current by an external npn-tr ansistor.
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 26 figure 9-4. lin slave applicatio n with minimum external devices 67 8 10 9 20 19 18 ata6622c ata6624c ata6626c 16 11 12 13 14 15 txd nres lin sub bus wd_osc tm mode kl_15 pvcc vcc gnd vs rxd inh gnd lin gnd gnd gnd wake ntrig ntrig microcontroller reset txd gnd rxd en vbat en 5 4 3 2 1 17 220pf 100nf vcc vcc vcc c1 c3 c5 c4 c2 22f/50v + 100nf 10f + 10k r9 note: no watchdog, inh output not used, no local wake-up vcc
27 ata6622c/ata6624c/at a6626c [datasheet] 4986o?auto?10/14 11. package information 10. ordering information extended type number package remarks ata6622c-pgqw-1 qfn20 3.3v lin system-basis-chip, pb-free, 6k, taped and reeled ata6624c-pgqw-1 qfn20 5v lin system-basis-chip, pb-free, 6k, taped and reeled ata6626c-pgqw-1 qfn20 5v lin system-basis-chip, pb-free, 6k, taped and reeled common dimensions (unit of measure = mm) package drawing contact: packagedrawings@atmel.com gpc symbol min nom max note 0.8 a 0.85 0.9 0 a1 0.035 0.05 0.16 a3 0.21 0.26 4.9 d 5 5.1 3.0 d2 3.1 3.2 4.9 e 5 5.1 3.0 e2 3.1 3.2 0.55 l 0.6 0.65 0.25 b 0.3 0.35 e 0.65 drawing no. rev. title 6.543-5129.02-4 1 10/18/13 package: vqfn_5x5_20l exposed pad 3.1x3.1 dimensions in mm specifications according to din technical drawings 20 d 1 5 pin 1 id e a3 a a1 b l z 10:1 top view side view bottom view e d2 6 1 5 15 11 10 20 16 e2 z
ata6622c/ata6 624c/ata6626c [datasheet] 4986o?auto?10/14 28 12. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 4986o-auto-10/14 ? section 10 ?ordering information? on page 27 updated ? section 11 ?package information? on page 27 updated 4986n-auto-07/14 ? put datasheet in the latest template 4986m-auto-02/13 ? section 10 ?ordering information? on page 27 updated 4986l-auto-11/12 ? section 10 ?ordering information? on page 27 updated 4986k-auto-01/12 ? table 2-1 ?pin description? on page 3 changed 4986j-auto-03/11 ? features on page 1 changed ? section 1 ?description? on pages 1 to 2 changed ? table 2-1 ?pin description? on page 3 changed ? section 3 ?functional description? on pages 4 to 6 changed ? section 4 ?modes of operation? on pages 7 to 11 changed ? section 5 ?wake-up scenarios from silent to sleep mode? on pages 12 to 14 changed ? section 7 ?absolute maximum ratings? on page 17 changed ? section 9 ?electrical characteristics? on pages 18 to 26 changed 4986i-auto-07/10 ? section 6 ?watchdog? on pages 15 to 16 changed 4986h-auto-05/10 ? new part numbers ata6622c, ata6624c and ata6626c added ? features on page 1 changed ? pin description table: rows pin 4 and pin 15 changed ? text under headings 3.3, 3.9, 3.11, 5.5 and 6 changed ? figures 4-5, 6-1 and 9-3 changed ? abs.max.rat.table -> values in row ?esd hbm following....? changed ? el.char.table -> rows changed: 7.1, 12.1, 12 .2, 17.5, 17.6, 17.7, 17 .8, 18.6, 18.7, 18.8, 18.9 ? el.char.table -> row 8.13 added ? figures 9-2 and 9-3 figure title changed ? figure 9-4 on page 27 added ? ord.info.table -> new part numbers added 4986g-auto-08/09 ? complete datasheet: ?lin 2.0 specificatio n? changed in ?lin 2.1 specification? ? figures changed: 1-1, 4-2, 4-3, 4-4, 4-5, 5-1, 9-2, 9-3 ? sections changed: 3.1, 3.6, 3.8, 3.9, 3.10, 3. 14, 4.1, 4.2, 4,3, 5.1, 5.2, 5.3, 5.5, 5.6 ? features and description changed ? table 4-1 changed ? abs. max. ratings table changed ? thermal characteristics table inserted ? el. characteristics table changed 4986f-auto-05/08 ? section 3.15 ?inh output pin? on page 6 changed ? section 5.5 ?fail-safe features? on page 13 changed ? section 6.1 ?typical timing sequence with r wd_osc = 51 k ? on page 15 changed ? section 8 ?electrical characteristics? numbers 1.6 to 1.8 on page 18 changed
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