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| this is information on a product in full production. april 2014 docid025146 rev 1 1/130 stm32f301x6/x8 arm ? -cortex ? -m4 32-bit mcu+fpu, up to 64 kb flash, 16 kb sram, adc, dac, comp, op-amp, 2.0 ? 3.6 v datasheet - production data features ? core: arm ? 32-bit cortex ? -m4 cpu with fpu (72 mhz max.), single-cycle multiplication and hw division, dsp instruction ? memories ? 32 to 64 kbyte of flash memory ?1 6 kbyte of sram on data bus ? crc calculation unit ? reset and power management ? vdd, vdda voltage range: 2.0 to 3.6 v ? power-on/power down reset (por/pdr) ? programmable voltage detector (pvd) ? low-power: sleep, stop, and standby ?v ba t supply for r tc and backup registers ? clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for r tc with calibration ? internal 8 mhz rc with x 16 pll option ? internal 40 khz oscillator ? up to 51 fast i/o ports, all mappable on external interrupt vectors, several 5 v-tolerant ? 7-channel dma controller supporting timers, adcs, spis, i 2 cs, usarts and dac ? 1 adc 0.20 s (up to 15 channels) with selectable resolution of 12/10/8/6 bits, 0 to 3.6 v conversion range, single ended/differential mode, separate analog supply from 2.0 to 3.6 v ? temperature sensor ? 1 x 12-bit dac channel with analog supply from 2.4 to 3.6 v ? three fast rail-to-rail analog comparators with analog supply from 2.0 to 3.6 v ? 1 x operational amplifier that can be used in pga mode, all terminal accessible with analog supply from 2.4 to 3.6 v ? up to 18 capacitive sensing channels supporting touchkey, linear and rotary sensors ? up to 9 timers ? one 32-bit timer with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? one 16-bit 6-channel advanced-control timer , with up to 6 pwm channels, deadtime generation and emergency stop ? three 16-bit timers with ic/oc/ocn or pwm, deadtime gen. and emergency stop ? one 16-bit basic timer to drive the dac ? 2 watchdog timers (independent, window) ? syst ick timer: 24-bit downcounter ? calendar rtc with alarm, periodic wakeup from stop/standby ? communication interfaces ? three i2cs with 20 ma current sink to support fast mode plus ? up to 3 usar t s, 1 with iso 7816 i/f , autobaudrate detect and dual clock domain ? up to two spis with multiplexed full duplex i2s ? infrared transmitter ? serial wire debug (swd), jtag ? 96-bit unique id t able 1. device summary reference part number stm32f301x6 stm32f301r6, stm32f301c6, stm32f301k6 stm32f301x8 stm32f301r8, stm32f301c8, stm32f301k8 lqfp48 (7 x 7 mm) lqfp64 (10 x 10 mm) ufqfpn32 (5 x 5 mm) wlcsp49 (3.4 x 3.4 mm) www .st.com http://
contents stm32f301x6/x8 2/130 docid025146 rev 1 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 arm ? cortex ? -m4 core with fpu, embedded flash and sram . . . . . . . 12 3.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.1 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.2 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 13 3.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.3 v oltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 17 3.1 1 fast analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 1.1 t emperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 1.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 1.3 v ba t battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13 operational amplifier (op amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14 ultra-fast comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.15 t imers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.15.1 advanced timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.15.2 general-purpose timers (tim2, tim15, tim16, tim17) . . . . . . . . . . . . . 21 3.15.3 basic timer (tim6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 docid025146 rev 1 3/130 stm32f301x6/x8 contents 4 3.15.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15.5 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15.6 syst ick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 real-time clock (r tc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 22 3.17 inter-integrated circuit interfaces (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.18 universal synchronous/asynchronous receiver transmitter (usar t) . . . 24 3.19 serial peripheral interfaces (spi)/inter-integrated sound interfaces (i2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.20 t ouch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.21 infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.22 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.22.1 serial wire jt ag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 m emory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.2 t ypical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.3 t ypical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 55 6.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 55 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.6 w akeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.8 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 contents stm32f301x6/x8 4/130 docid025146 rev 1 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.1 1 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.16 t imer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.17 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.18 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.19 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3.20 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3.21 operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.3.22 t emperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 10 6.3.23 v ba t monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 10 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 126 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 docid025146 rev 1 5/130 stm32f301x6/x8 list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f301x6/x8 device features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. stm32f301x6/x8 peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. stm32f301x6/x8 i 2 c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. usart features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. stm32f301x6/x8 spi/i2s implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9. capacitive sensing gpios available on stm32f301x6/x8 devices . . . . . . . . . . . . . . . . . . 26 table 10. no. of capacitive sensing channels available on stm32f301x6/x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. stm32f301x6/x8 pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3 table 13. alternate functions for port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 14. alternate functions for port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15. alternate functions for port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 16. alternate functions for port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 17. alternate functions for port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 18. stm32f301x6/x8 peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . 47 table 19. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 20. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 21. thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 22. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 23. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 24. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 25. programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 26. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 27. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 28. typical and maximum current consumption from vdd supply at vdd = 3.6v . . . . . . . . . . 58 table 29. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 60 table 30. typical and maximum v dd consumption in stop and standby modes . . . . . . . . . . . . . . . . 60 table 31. typical and maximum v dda consumption in stop and standby modes . . . . . . . . . . . . . . . 61 table 32. typical and maximum current consumption from v bat supply . . . . . . . . . . . . . . . . . . . . . . 61 table 33. typical current consumption in run mode, code with data processing running from flash 63 table 34. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 64 table 35. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 36. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 8 table 37. low-power mode wakeup timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 38. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 39. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 40. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 41. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 42. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 43. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 44. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 45. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 46. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 47. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 list of tables stm32f301x6/x8 6/130 docid025146 rev 1 table 48. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 49. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 50. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 51. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 52. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 53. output voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 54. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 55. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 56. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 57. iwdg min/max timeout period at 40 khz (lsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 58. wwdg min-max timeout value @72 mhz (pclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 59. i2c analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 60. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 61. i2s characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 62. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 63. maximum adc rain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 64. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 table 65. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 66. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 67. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 68. comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 69. operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 70. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 71. temperature sensor calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 72. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 73. wlcsp49 wafer level chip size package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 113 table 74. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 116 table 75. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 119 table 76. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . 122 table 77. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 78. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 79. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 docid025146 rev 1 7/130 stm32f301x6/x8 list of figures 7 list of figures figure 1. stm32f301x6/x8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3. infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 4. stm32f301x6/x8 ufqfn32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5. stm32f301x6/x8 lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 6. stm32f301x6/x8 lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 7. stm32f301x6/x8 wlcsp49 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 8. stm32f301x6/x8 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 9. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 10. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 11. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 12. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 13. typical v bat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) . . . . . . . . . . . 62 figure 14. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 15. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 16. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 figure 17. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 18. hsi oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 19. tc and tta i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 20. tc and tta i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 21. five volt tolerant (ft and ftf) i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . 84 figure 22. five volt tolerant (ft and ftf) i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . 84 figure 23. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 24. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 25. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 26. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 27. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 28. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 29. i 2 s master timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 30. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 31. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 32. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 33. opamp voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 34. wlcsp49 wafer level chip size package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 35. wlcsp49 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 14 figure 36. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . 115 figure 37. lqfp64 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 figure 38. lqfp64 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 39. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 118 figure 40. lqfp48 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 0 figure 41. lqfp48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 42. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) . . . . . . . . . . . . . . . . . . . . 122 figure 43. ufqfpn32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 44. ufqfpn32 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 introduction stm32f301x6/x8 8/130 docid025146 rev 1 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f301x6/x8 microcontrollers. this datasheet should be read in conjunction with the stm32f302xx advanced arm-based 32-bit mcus reference manual (rm0366). the reference manual is available from the stmicroelectronics website www.st.com . for information on the arm ? cortex ? -m4 core, please refer to the cortex ? -m4 technical reference manual, available from arm website www.arm.com. docid025146 rev 1 9/130 stm32f301x6/x8 description 48 2 description the stm32f301x6/x8 family is based on the high-performance arm ? cortex ? -m4 32-bit risc core operating at a frequency of up to 72 mhz and embedding a floating point unit (fpu). the family incorporates high-speed embedded memories (up to 64 kbyte of flash memory, 16 kbytes of sram), and an extensive range of enhanced i/os and peripherals connected to two apb buses. the devices offer a fast 12-bit adc (5 msps), three comparators, an operational amplifier , up to 18 capacitive sensing channels, one dac channel, a low-power r tc, one general- purpose 32-bit timer , one timer dedicated to motor control, and up to three general-purpose 16-bit timers, and one timer to drive the dac. they also feature standard and advanced communication interfaces: three i 2 cs, up to three usarts, up to two spis with multiplexed full-duplex i2ss, and an infrared transmitter. the stm32f301x6/x8 family operates in the ?40 to +85c and ?40 to +105c temperature ranges from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f301x6/x8 family offers devices in 32-, 48-, 49- and 64-pin packages. the set of included peripherals changes with the device chosen. description stm32f301x6/x8 10/130 docid025146 rev 1 t able 2. stm32f301x6/x8 device features and peripheral counts peripheral stm32f301kx stm32f301cx STM32F301RX flash (kbytes) 32 64 32 64 32 64 sram (kbytes) 16 t imers advanced control 1 (16-bit) general purpose 3 (16-bit) 1 (32 bit) basic 1 syst ick timer 1 w atchdog timers (independent, window) 2 comm. interfaces spi/i2s 2 i 2 c3 usar t 2 3 dma channels 7 capacitive sensing channels 18 12-bit adc number of channels 1 8 1 11 1 15 12-bit dac channels 1 analog comparator 3 operational amplifier 1 cpu frequency 72 mhz operating voltage 2.0 to 3.6 v operating temperature ambient operating temperature: - 40 to 85c / - 40 to 105c junction temperature: - 40 to 125c packages ufqfpn32 lqfp48, wlcsp49 lqfp64 docid025146 rev 1 11/130 stm32f301x6/x8 description 48 figure 1. stm32f301x6/x8 block diagram 1. af: alternate function on i/o pins. 0 6 y 9 7 r x f k 6 h q v l q j & r q w u r o o h u $ + % g h f r g h u 7 , 0 ( 5 & k d q q h o v & r p s & k d q q h o % 5 . d v $ ) 7 , 0 ( 5 7 , 0 ( 5 3 : 0 8 6 $ 5 7 5 ; 7 ; & 7 6 5 7 6 6 p d u w & d u g d v $ ) : l q : $ 7 & + ' 2 * % x v 0 d w u l [ ) 3 8 & r u w h [ 0 & 3 8 ) p d [ 0 + ] 1 9 , & * 3 ' 0 $ f k d q q h o v ) o d v k l q w h u i d f h 2 % / ) / $ 6 + . % e l w v - 7 5 6 7 - 7 ' , - 7 & . 6 : & / . - 7 0 6 6 : ' , 2 - 7 ' 2 $ v $ ) 3 r z h u 9 r o w d j h u h j 9 w r 9 9 ' ' 6 x s s o \ 6 x s h u y l v l r q 3 2 5 3 ' 5 3 9 ' 3 2 5 5 h v h w , q w 9 ' ' , 2 w r 9 9 6 6 1 5 ( 6 ( 7 9 ' ' $ 9 6 6 $ , q g : ' * . 6 w d q g e \ l q w h u i d f h 3 / / # 9 ' ' , 2 # 9 ' ' $ ; 7 $ / 2 6 & 0 + ] 5 h v h w f o r f n f r q w u r o $ + % 3 & / . $ 3 % 3 & / . $ 3 % 3 & / . $ + % $ 3 % $ + % $ 3 % & 5 & $ 3 % ) p d [ 0 + ] $ 3 % i p d [ 0 + ] * 3 , 2 3 2 5 7 $ * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 & * 3 , 2 3 2 5 7 ' 2 6 & b , 1 2 6 & b 2 8 7 6 3 , , 6 6 & / 6 ' $ 6 0 % $ d v $ ) 8 6 $ 5 7 6 & / 6 ' $ 6 0 % $ d v $ ) 8 6 $ 5 7 5 & / 6 7 , 0 ( 5 6 3 , , 6 e l w ' $ & , ) # 9 ' ' $ 7 , 0 ( 5 e l w 3 : 0 3 $ > @ 3 % > @ 3 & > @ 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) & k d q q h o v ( 7 5 d v $ ) ' $ & b & + d v $ ) + & / . ) & / . 8 6 $ 5 7 & / . 5 & + 6 0 + ] 6 5 $ 0 . % 6 : - 7 $ * 7 3 , 8 , e x v 7 5 $ ' ( & / . 7 5 $ & ( ' > @ d v $ ) ' e x v 6 \ v w h p e l w $ ' & 7 h p s v h q v r u 9 5 ( ) 9 5 ( ) 7 , 0 ( 5 ( ; 7 , 7 : . 8 3 ; ; $ ) & k d q q h o & r p s & k d q q h o % 5 . d v $ ) & k d q q h o & r p s & k d q q h o % 5 . d v $ ) & k d q q h o v & r p s f k d q q h o v ( 7 5 % 5 . d v $ ) * 3 , 2 3 2 5 7 ) 3 ' > @ 3 ) > @ , ) , & & / . $ ' & 6 $ 5 & / . # 9 ' ' , 2 # 9 ' ' $ # 9 6 : ; 7 $ / n + ] 2 6 & b , 1 2 6 & b 2 8 7 9 % $ 7 9 w r 9 5 7 & $ : 8 % d f n x s 5 h j % \ w h % d f n x s l q w h u i d f h $ 1 7 , 7 $ 0 3 , & , & 2 s $ p s # 9 ' ' $ , 1 [ [ 2 8 7 [ [ , 1 7 ( 5 ) $ & ( 6 < 6 & ) * & 7 / * 3 & r p s d u d w r u * 3 & r p s d u d w r u * 3 & r p s d u d w r u 5 ; 7 ; & 7 6 5 7 6 d v $ ) 5 ; 7 ; & 7 6 5 7 6 d v $ ) # 9 ' ' $ ; [ , q v 2 8 7 v d v $ ) * u r x s v r i f k d q q h o v d v $ ) 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) 6 & / 6 ' $ 6 0 % $ d v $ ) , & functional overview stm32f301x6/x8 12/130 docid025146 rev 1 3 functional overview 3.1 arm ? cortex ? -m4 core with fpu, embedded flash and sram the arm ? cortex ? -m4 processor with fpu is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 32-bit risc processor with fpu features exceptional code- efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single-precision fpu speeds up software development by using metalanguage development tools while avoiding saturation. with its embedded arm core, the stm32f301x6/x8 family is compatible with all arm tools and software. figure 1 shows the general block diagram of the stm32f301x6/x8 family devices. 3.2 memories 3.2.1 embedded flash memory all stm32f301x6/x8 devices feature up to 64 kbytes of embedded flash memory available for storing programs and data. the flash memory access time is adjusted to the cpu clock frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above). 3.2.2 embedded sram stm32f301x6/x8 devices feature 16 kbytes of embedded sram. 3.3 boot modes at startup, boot0 pin and boot1 option bit are used to select one of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 (pa9/pa10) and usart2 (pa2/pa3). docid025146 rev 1 13/130 stm32f301x6/x8 functional overview 48 3.4 cyclic redundancy check calculation unit (crc) the crc (cyclic redundancy check) calculation unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.5 power management 3.5.1 power supply schemes ? v ss , v dd = 2.0 to 3.6 v : external power supply for i/os and the internal regulator . it is provided externally through v dd pins. ? v ssa , v dda = 2.0 to 3.6 v : external analog power supply for adc, dac, comparators, operational amplifier , reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the dac and operational amplifier are used). the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. ? v ba t = 1.65 to 3.6 v : power supply for r tc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. 3.5.2 power supply supervisor the device has an integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . ? the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the application design ensures that v dda is higher than or equal to v dd . the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. functional overview stm32f301x6/x8 14/130 docid025146 rev 1 3.5.3 voltage regulator the regulator has three operation modes: main (mr), low-power (lpr), and power-down. ? the mr mode is used in the nominal regulation mode (run) ? the lpr mode is used in stop mode. ? the power-down mode is used in standby mode: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. the voltage regulator is always enabled after reset. it is disabled in standby mode. 3.5.4 low-power modes the stm32f301x6/x8 supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output, the r tc alarm, compx, i2c or usar tx. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched of f so that the entire 1.8 v domain is powered of f. the pll, the hsi rc and the hse crystal oscillators are also switched of f. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry . the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 3.6 interconnect matrix several peripherals have direct connections between them. this allows autonomous communication between peripherals, saving cpu resources thus power supply consumption. in addition, these hardware connections allow fast and predictable latency. docid025146 rev 1 15/130 stm32f301x6/x8 functional overview 48 note: for more details about the interconnect actions, please refer to the corresponding sections in the f301xx reference manual rm0366. 3.7 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillator. a software interrupt is generated if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example with failure of an indirectly used external oscillator). several prescalers allow to configure the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domains. the maximum frequency of the ahb and the high speed apb domains is 72 mhz, while the maximum allowed frequency of the low speed apb domain is 36 mhz. the advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. to achieve audio class performance, an audio crystal can be used. t able 3. stm32f301x6/x8 peripheral interconnect matrix interconnect source interconnect destination interconnect action timx timx t imers synchronization or chaining adc1 dac1 conversion triggers dma memory to memory transfer trigger compx comparator output blanking compx timx t imer input: ocrefclear input, input capture adc1 tim1 t imer triggered by analog watchdog gpio r tcclk hse/32 mc0 tim16 clock source used as input channel for hsi and lsi calibration css cpu (hard fault) compx pvd gpio tim1 tim15, 16, 17 t imer break gpio timx external trigger , timer break adc1 dac1 conversion external trigger dac1 compx comparator inverting input functional overview stm32f301x6/x8 16/130 docid025146 rev 1 figure 2. clock tree 0 + ] + 6 ( 2 6 & 2 6 & b , 1 2 6 & b 2 8 7 2 6 & b , 1 2 6 & b 2 8 7 0 + ] + 6 , 5 & , : ' * & / . w r , : ' * 3 / / [ [ [ 3 / / 0 8 / 0 & 2 $ + % $ 3 % s u h v f d o h u + & / . 3 / / & / . w r $ + % e x v f r u h p h p r u \ d q g ' 0 $ / 6 ( / 6 , + 6 , + 6 , + 6 ( w r 5 7 & 3 / / 6 5 & 6 : 6 < 6 & / . 5 7 & & / . 5 7 & 6 ( / > @ w r 7 , 0 , i $ 3 % s u h v f d o h u [ h o v h [ ) / , 7 ) & / . w r ) o d v k s u r j u d p p l q j l q w h u i d f h w r , & [ [ w r 8 6 $ 5 7 [ / 6 ( + 6 , 6 < 6 & / . 3 & / . 6 < 6 & / . + 6 , 3 & / . 0 6 9 w r , 6 [ [ w r f r u w h [ 6 \ v w h p w l p h u ) + & / . & r u w h [ i u h h u x q q l q j f o r f n w r $ 3 % s h u l s k h u d o v $ + % s u h v f d o h u & 6 6 / 6 ( 2 6 & n + ] / 6 , 5 & n + ] $ 3 % s u h v f d o h u , i $ 3 % s u h v f d o h u [ h o v h [ 3 & / . w r $ 3 % s h u l s k h u d o v 7 , 0 $ ' & 3 u h v f d o h u w r $ ' & $ ' & 3 u h v f d o h u , 6 6 5 & 6 < 6 & / . ( [ w f o r f n , 6 b & . , 1 [ 0 d l q f o r f n r x w s x w 3 / / & / . + 6 , + 6 ( 0 & 2 6 < 6 & / . / 6 , 3 / / 1 2 ' , 9 0 & 2 3 5 ( docid025146 rev 1 17/130 stm32f301x6/x8 functional overview 48 3.8 general-purpose inputs/outputs (gpios) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current capable except for analog inputs. the i/os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling allows i/o toggling up to 36 mhz. 3.9 direct memory access (dma) the flexible general-purpose dma is able to manage memory-to-memory, peripheral-to- memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. each of the 7 dma channels is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, timers, dac and adc. 3.10 interrupts and events 3.10.1 nested vectored interrupt controller (nvic) the stm32f301x6/x8 devices embed a nested vectored interrupt controller (nvic) able to handle up to 60 maskable interrupt channels and 16 priority levels. the nvic benefits are the following: ? closely coupled nvic gives low latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead the nvic hardware block provides flexible interrupt management features with minimal interrupt latency. functional overview stm32f301x6/x8 18/130 docid025146 rev 1 3.11 fast analog-to-digital converter (adc) an analog-to-digital converter, with selectable resolution between 12 and 6 bit, is embedded in the stm32f301x6/x8 family devices. the adc has up to 15 external channels performing conversions in single-shot or scan modes. channels can be configured to be either single-ended input or differential input. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? single-shunt phase current reading techniques. the adc can be served by the dma controller. three analog watchdogs are available. the analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers (timx) and the advanced-control timer (tim1) can be internally connected to the adc start trigger and injection trigger , respectively, to allow the application to synchronize a/d conversion and timers. 3.11.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connected to the adc1_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the of fset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. t o improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st . the temperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.11.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally connected to the adc1_in18 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is accessible in read-only mode. docid025146 rev 1 19/130 stm32f301x6/x8 functional overview 48 3.11.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc1_in17. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the v bat pin is internally connected to a bridge divider by 2. as a consequence, the converted digital value is half the v bat voltage. 3.12 digital-to-analog converter (dac) one 12-bit buffered dac channel (dac1_out1) can be used to convert digital signals into analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. this digital interface supports the following features: ? one dac output channel ? 8-bit or 12-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? t riangular-wave generation ? dma capability ? external triggers for conversion 3.13 operational amplifier (opamp) the stm32f301x6/x8 embeds one operational amplifier with external or internal follower routing and pga capability (or even amplifier and filter capability with external components). when the operational amplifier is selected, an external adc channel is used to enable output measurement. the operational amplifier features: ? 8.2 mhz bandwidth ? 0.5 ma output capability ? rail-to-rail input/output ? in pga mode, the gain can be programmed to be 2, 4, 8 or 16. 3.14 ultra-fast comparators (comp) the stm32f301x6/x8 devices embed three ultra-fast rail-to-rail comparators which offer the features below: ? programmable internal or external reference voltage ? selectable output polarity. functional overview stm32f301x6/x8 20/130 docid025146 rev 1 the reference voltage can be one of the following: ? external i/o ? dac output ? internal reference voltage or submultiple (1/4, 1/2, 3/4). refer to t able 26: embedded internal reference voltage for the value and precision of the internal reference voltage. all comparators can wake up from st op mode, and also generate interrupts and breaks for the timers. 3.15 timers and watchdogs the stm32f301x6/x8 includes advanced control timer, up to general-purpose timers, basic timer, two watchdog timers and a systick timer. the table below compares the features of the advanced control, general purpose and basic timers. 3.15.1 advanced timer (tim1) the advanced-control timer can each be seen as a three-phase pwm multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead- times. they can also be seen as complete general-purpose timers. the 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or center-aligned modes) with full modulation capability (0- 100%) ? one-pulse mode output t able 4. t imer feature comparison t imer type t imer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs advanced control tim1 (1) 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 ye s general- purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 ye s 4 no tim15 (1) 16-bit up any integer between 1 and 65536 ye s 2 1 tim16 (1) , tim17 (1) 16-bit up any integer between 1 and 65536 ye s 1 1 basic tim6 16-bit up any integer between 1 and 65536 ye s 0 no 1. tim1/15/16/17 can be clocked from the pll running at 144 mhz when the system clock source is the pll and ahb or apb2 subsystem clocks are not divided by more than 2 cumulatively . docid025146 rev 1 21/130 stm32f301x6/x8 functional overview 48 in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switches driven by these outputs. many features are shared with those of the general-purpose tim timers (described in section 3.15.2 using the same architecture, so the advanced-control timers can work together with the tim timers via the timer link feature for synchronization or event chaining. 3.15.2 general-purpose timers (tim2, tim15, tim16, tim17) there are up to four synchronizable general-purpose timers embedded in the stm32f301x6/x8 (see t able 4 for differences). each general-purpose timer can be used to generate pwm outputs, or act as a simple time base. tim2 tim2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler it features 4 independent channels for input capture/output compare, pwm or one-pulse mode output. it can work together, or with the other general-purpose timers via the timer link feature for synchronization or event chaining. the counter can be frozen in debug mode. it has independent dma request generation and supports quadrature encoders. tim15, tim16 and tim 17 these three timers general-purpose timers with mid-range features: they have 16-bit auto-reload upcounters and 16-bit prescalers. ? tim15 has 2 channels and 1 complementary channel ? tim16 and tim17 have 1 channel and 1 complementary channel all channels can be used for input capture/output compare, pwm or one-pulse mode output. the timers can work together via the timer link feature for synchronization or event chaining. the timers have independent dma request generation. the counters can be frozen in debug mode. 3.15.3 basic timer (tim6) this timer is mainly used for dac trigger generation. it can also be used as a generic 16-bit time base. 3.15.4 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. functional overview stm32f301x6/x8 22/130 docid025146 rev 1 3.15.5 window watchdog (wwdg) the window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capability and the counter can be frozen in debug mode. 3.15.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0. ? programmable clock source 3.16 real-time clock (rtc) and backup registers the rtc and the 20 backup registers are supplied through a switch that takes power from either the v dd supply when present or the vbat pin. the backup registers are five 32-bit registers used to store 20 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, or when the device wakes up from standby mode. the rtc is an independent bcd timer/counter. it supports the following features: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day , date, month, year , in bcd (binary-coded decimal) format. ? automatic correction for 28, 29 (leap year), 30, and 31 days of the month. ? t wo programmable alarms with wake up from stop and standby mode capability . ? on-the-fly correction from 1 to 32767 r tc clock pulses. this can be used to synchronize it with a master clock. ? digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy . ? t wo anti-tamper detection pins with programmable filter . the mcu can be woken up from stop and standby modes on tamper event detection. ? t imestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. ? 17-bit auto-reload counter for periodic interrupt with wakeup from stop/standby capability. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 40 khz) ? the high-speed external clock divided by 32. docid025146 rev 1 23/130 stm32f301x6/x8 functional overview 48 3.17 inter-integrated circuit interfaces (i 2 c) the devices feature three i 2 c bus interfaces which can operate in multimaster and slave mode. each i2c interface can support standard (up to 100 khz), fast (up to 400 khz) and fast mode + (up to 1 mhz) modes. all i 2 c interfaces support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). they also include programmable analog and digital noise filters. in addition, it provides hardware support for smbus 2.0 and pmbus 1.1: arp capability , host notify protocol, hardware crc (pec) generation/verification, timeouts verifications and aler t protocol management. it also has a clock domain independent from the cpu clock, allowing the i2cx (x=1,3) to wake up the mcu from stop mode on address match. the i2c interfaces can be served by the dma controller. refer to t able 6 for the features available in i2c1, i2c2 and i2c3. t able 5. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes ? 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits a vailable in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks v ariations depending on temperature, voltage, process w akeup from stop on address match is not available when digital filter is enabled. t able 6. stm32f301x6/x8 i 2 c implementation i2c features (1) 1. x = supported. i2c1 i2c2 i2c3 7-bit addressing mode x x x 10-bit addressing mode x x x standard mode (up to 100 kbit/s) x x x fast mode (up to 400 kbit/s) x x x fast mode plus with 20ma output drive i/os (up to 1 mbit/s) x x x independent clock x x x smbus x x x w akeup from st op x x x functional overview stm32f301x6/x8 24/130 docid025146 rev 1 3.18 universal synchronous/asynchronous receiver transmitter (usart) the stm32f301x6/x8 devices have three embedded universal synchronous receiver transmitters (usart1, usart2 and usart3). the usart interfaces are able to communicate at speeds of up to 9 mbits/s. all usarts support hardware management of the cts and rts signals, multiprocessor communication mode, single-wire half-duplex communication mode and synchronous mode. usart1 supports smartcard mode, irda sir endec, lin master capability and autobaudrate detection. all usart interfaces can be served by the dma controller. refer to t able 7 for the features available in all usarts interfaces. 3.19 serial peripheral interfaces (spi)/inter-integrated sound interfaces (i2s) two spi interfaces (spi2 and spi3) allow communication up to 18 mbits/s in slave and master modes in full-duplex and simplex modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. two standard i2s interfaces (multiplexed with spi2 and spi3) are available, that can be operated in master or slave mode. these interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i2s interfaces is/are configured in master t able 7. usart features usart modes/features (1) 1. x = supported. usart1 usart2 usart3 hardware flow control for modem x x x continuous communication using dma x x x multiprocessor communication x x x synchronous mode x x x smartcard mode x single-wire half-duplex communication x x x irda sir endec block x lin mode x dual clock domain and wakeup from stop mode x receiver timeout interrupt x modbus communication x auto baud rate detection x driver enable x x x docid025146 rev 1 25/130 stm32f301x6/x8 functional overview 48 mode, the master clock can be output to the external dac/codec at 256 times the sampling frequency. refer to t able 8 for the features available in spi2 and spi3. 3.20 t ouch sensing controller (tsc) the stm32f301x6/x8 devices provide a simple solution for adding capacitive sensing functionality to any application. these devices offer up to 18 capacitive sensing channels distributed over 6 analog i/o groups. capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). the capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. it consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. t o limit the cpu bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate. t able 8. stm32f301x6/x8 spi/i2s implementation spi features (1) 1. x = supported. spi2 spi3 hardware crc calculation x x rx/tx fifo x x nss pulse mode x x i2s mode x x ti mode x x functional overview stm32f301x6/x8 26/130 docid025146 rev 1 t able 9. capacitive sensing gpios available on stm32f301x6/x8 devices group capacitive sensing signal name pin name 1 tsc_g1_io1 p a0 tsc_g1_io2 p a1 tsc_g1_io3 p a2 tsc_g1_io4 p a3 2 tsc_g2_io1 p a4 tsc_g2_io2 p a5 tsc_g2_io3 p a6 tsc_g2_io4 p a7 3 tsc_g3_io1 pc5 tsc_g3_io2 pb0 tsc_g3_io3 pb1 tsc_g3_io4 pb2 4 tsc_g4_io1 p a9 tsc_g4_io2 p a10 tsc_g4_io3 p a13 tsc_g4_io4 p a14 5 tsc_g5_io1 pb3 tsc_g5_io2 pb4 tsc_g5_io3 pb6 tsc_g5_io4 pb7 6 tsc_g6_io1 pb1 1 tsc_g6_io2 pb12 tsc_g6_io3 pb13 tsc_g6_io4 pb14 docid025146 rev 1 27/130 stm32f301x6/x8 functional overview 48 3.21 infrared transmitter the stm32f301x6/x8 devices provide an infrared transmitter solution. the solution is based on internal connections between tim16 and tim17 as shown in the figure below. tim17 is used to provide the carrier frequency and tim16 provides the main signal to be sent. the infrared output signal is available on pb9 or pa13. to generate the infrared remote control signals, tim16 channel 1 and tim17 channel 1 must be properly configured to generate correct waveforms. all standard ir pulse modulation modes can be obtained by programming the two timers output compare channels. figure 3. infrared transmitter t able 10. no. of capacitive sensing channels available on stm32f301x6/x8 devices analog i/o group number of capacitive sensing channels STM32F301RX stm32f301cx stm32f301kx g1 3 3 3 g2 3 3 3 g3 3 2 1 g4 3 3 3 g5 3 3 3 g6 3 3 0 number of capacitive sensing channels 18 17 13 7 , 0 ( 5 i r u h q y h o r s 7 , 0 ( 5 i r u f d u u l h u 2 & 2 & 3 % 3 $ 0 6 9 functional overview stm32f301x6/x8 28/130 docid025146 rev 1 3.22 development support 3.22.1 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jt ag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jt ag tms and tck pins are shared respectively with swdio and swclk and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. docid025146 rev 1 29/130 stm32f301x6/x8 pinouts and pin description 48 4 pinouts and pin description figure 4. stm32f301x6/x8 ufqfn32 pinout figure 5. stm32f301x6/x8 lqfp48 pinout 8 ) 4 ) 1 0 6 9 9 ' ' b 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 1 5 6 7 9 ' ' $ 9 5 ( ) 9 6 6 $ 9 5 ( ) 3 $ 3 $ 9 6 6 b % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' b 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 9 6 6 b 3 $ 3 % 3 % 9 6 6 b % 2 2 7 3 % 3 % 3 % 9 ' ' b 9 6 6 b 3 $ 3 % 3 % 3 % 3 % 3 % 9 6 6 b 3 % 9 ' ' b 9 % $ 7 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 1 5 6 7 9 6 6 $ 9 5 ( ) 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' b 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 3 & 0 6 9 / 4 ) 3 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ pinouts and pin description stm32f301x6/x8 30/130 docid025146 rev 1 figure 6. stm32f301x6/x8 lqfp64 pinout 9 % $ 7 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 5 ( ) 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' b 3 ' 3 & 3 & 3 & 9 ' ' b 9 6 6 b 3 & 3 & 3 & 3 % 9 6 6 b 3 $ 9 ' ' b 3 & 3 & 3 % 3 % 3 ) 2 6 & b 2 8 7 3 ) 2 6 & b , 1 3 & 9 6 6 b 3 % 9 6 6 b 9 ' ' b , 1 & 0 d l 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 % 3 % 3 % 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ docid025146 rev 1 31/130 stm32f301x6/x8 pinouts and pin description 48 figure 7. stm32f301x6/x8 wlcsp49 ballout 0 6 9 $ % ( ' & ) * 3 & 9 ' ' 1 5 6 7 9 6 6 3 $ 9 ' ' $ 9 % $ 7 3 & 9 6 6 $ 9 5 ( ) 3 $ 3 $ % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 9 ' ' 3 $ 9 6 6 3 $ 3 % 3 $ 3 % 3 $ 3 % 3 $ 3 % 9 ' ' 9 6 6 3 % 3 $ 3 $ 3 % 3 % 3 % 3 % 3 & 3 $ 3 $ 3 $ 3 $ 3 % 1 r w f r q q h f w h g 3 ) 2 6 & b 2 8 7 3 ) 2 6 & b , 1 pinouts and pin description stm32f301x6/x8 32/130 docid025146 rev 1 t able 1 1. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, i2c fm+ option tt a 3.3 v tolerant i/o tt 3.3 v tolerant i/o tc standard 3.3v i/o b dedicated boot0 pin rst bi-directional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers stm32f301x6/x8 pinouts and pin description docid025146 rev 1 33/130 t able 12. stm32f301x6/x8 pin definitions pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 - b6 1 1 vba t s - backup power supply -d 5 2 2 pc13 (1) t amper1 wkup2 (pc13) i/o tc (1) tim1_ch1n wkup2, r tc_t amp1, r tc_ts, r tc_out -c 7 3 3 pc14 (1) osc32_in (pc14) i/o tc (1) osc32_in -c 6 4 4 pc15 (1) osc32_out (pc14) i/o tc (1) osc32_out 2 d7 5 5 pf0 osc_in (pf0) i/o ftf i2c2_sda, spi2_nss/i2s2_ws, tim1_ch3n osc_in 3 d6 6 6 pf1 osc_out (pf1) o ftf i2c2_scl, spi2_sck/i2s2_ck osc_out 4 e7 7 7 nrst i/o rst device reset input/internal reset output (active low) - - - 8 pc0 i/o tt a event out , tim1_ch1 adc1_in6 - - - 9 pc1 i/o tt a event out , tim1_ch2 adc1_in7 - - - 10 pc2 i/o tt a event out , tim1_ch3 adc1_in8 - - - 1 1 pc3 i/o tt a event out , tim1_ch4, tim1_bkin2 adc1_in9 6 b7 8 12 vssa/vref- s - analog ground/negative reference voltage 5 a6 9 13 vdda/vref+ s - analog power supply/positive reference voltage pinouts and pin description stm32f301x6/x8 34/130 docid025146 rev 1 7 f6 1 0 1 4 p a0 -t amper2-wkup1 i/o tt a tim2_ch1/tim2_etr, tsc_g1_io1, usar t2_cts, event out adc1_in1, r tc_t amp2, wkup1 8 g7 1 1 15 p a1 i/o tt a r tc_refin, tim2_ch2, tsc_g1_io2, usar t2_r ts, tim15_ch1n, event out adc1_in2 9 e5 12 16 p a2 i/o tt a tim2_ch3, tsc_g1_io3, usar t2_tx, comp2_out , tim15_ch1, event out adc1_in3, comp2_inm 10 e4 13 17 p a3 i/o tt a tim2_ch4, tsc_g1_io4, usar t2_rx, tim15_ch2, event out adc1_in4 - - - 18 vss s - - - - 19 vdd s - 1 1 g6 14 20 p a4 i/o tt a tsc_g2_io1, spi3_nss/i2s3_ws, usar t2_ck, event out adc1_in5, dac1_out1, comp2_inm, comp4_inm, comp6_inm 12 f5 15 21 p a5 i/o tt a tim2_ch1/tim2_etr, tsc_g2_io2, event out op amp2_vinm 13 f4 16 22 p a6 i/o tt a tim16_ch1, tsc_g2_io3, tim1_bkin, event out adc1_in10, op amp2_vout 14 f3 17 23 p a7 i/o tt a tim17_ch1, tsc_g2_io4, tim1_ch1n, event out adc1_in15, comp2_inp , op amp2_vinp t able 12. stm32f301x6/x8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 stm32f301x6/x8 pinouts and pin description docid025146 rev 1 35/130 - - - 24 pc4 i/o tt event out , tim1_etr, usar t1_tx - - - 25 pc5 i/o tt a event out , tim15_bkin, tsc_g3_io1, usar t1_rx op amp2_vinm 15 g5 18 26 pb0 i/o tt a tsc_g3_io2, tim1_ch2n, event out adc1_in1 1, comp4_inp , op amp2_vinp - g4 19 27 pb1 i/o tt a tsc_g3_io3, tim1_ch3n, comp4_out , event out adc1_in12 - g3 20 28 pb2 i/o tt a tsc_g3_io4, event out comp4_inm - e3 21 29 pb10 i/o tt tim2_ch3, tsc_sync, usar t3_tx, event out - g2 22 30 pb1 1 i/o tt a tim2_ch4, tsc_g6_io1, usar t3_rx, event out adc1_in14, comp6_inp 16 d3 23 31 vss s - digital ground 17 f2 24 32 vdd s - digital power supply - e2 25 33 pb12 i/o tt tsc_g6_io2, i2c2_smbal, spi2_nss/i2s2_ws, tim1_bkin, usar t3_ck, event out - g1 26 34 pb13 i/o tt a tsc_g6_io3, spi2_sck/i2s2_ck, tim1_ch1n, usar t3_cts, event out adc1_in13 t able 12. stm32f301x6/x8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 pinouts and pin description stm32f301x6/x8 36/130 docid025146 rev 1 - f1 2 7 3 5 pb14 i/o tt a tim15_ch1, tsc_g6_io4, spi2_miso/i2s2ext_sd, tim1_ch2n, usar t3_r ts, event out op amp2_vinp - e1 28 36 pb15 i/o tt a r tc_refin, tim15_ch2, tim15_ch1n, tim1_ch3n, spi2_mosi/i2s2_sd, event out comp6_inm - - - 37 pc6 i/o ft event out , i2s2_mck, comp6_out - - - 38 pc7 i/o ft event out , i2s3_mck - - - 39 pc8 i/o ft event out - - - 40 pc9 i/o ftf event out , i2c3_sda, i2sckin 18 d1 29 41 p a8 i/o ft mco, i2c3_scl, i2c2_smbal, i2s2_mck, tim1_ch1, usar t1_ck, event out 19 d2 30 42 p a9 i/o ftf i2c3_smbal, tsc_g4_io1, i2c2_scl, i2s3_mck, tim1_ch2, usar t1_tx, tim15_bkin, tim2_ch3, event out t able 12. stm32f301x6/x8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 stm32f301x6/x8 pinouts and pin description docid025146 rev 1 37/130 20 c2 31 43 p a10 i/o ftf tim17_bkin, tsc_g4_io2, i2c2_sda, spi2_miso/i2s2ext_sd, tim1_ch3, usar t1_rx, comp6_out , tim2_ch4, event out 21 c1 32 44 p a1 1 i/o ft spi2_mosi/i2s2_sd, tim1_ch1n, usar t1_cts, tim1_ch4, tim1_bkin2, event out 22 c3 33 45 p a12 i/o ft tim16_ch1, i2sckin, tim1_ch2n, usar t1_r ts, comp2_out , tim1_etr, event out 23 b3 34 46 p a13 i/o ft swdio, tim16_ch1n, tsc_g4_io3, ir-out , usar t3_cts, event out - b1 35 47 vss_3 s - digital ground - b2 36 48 vdd_3 s - digital power supply 24 a1 37 49 p a14 i/o ftf swclk-jtck, tsc_g4_io4, i2c1_sda, tim1_bkin, usar t2_tx, event out 25 a2 38 50 p a15 i/o ftf jtdi, tim2_ch1/tim2_etr, tsc_sync, i2c1_scl, spi3_nss/i2s3_ws, usar t2_rx, tim1_bkin, event out t able 12. stm32f301x6/x8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 pinouts and pin description stm32f301x6/x8 38/130 docid025146 rev 1 - - - 51 pc10 i/o ft event out , spi3_sck/i2s3_ck, usar t3_tx - - - 52 pc1 1 i/o ft event out , spi3_miso/i2s3ext_sd, usar t3_rx - - - 53 pc12 i/o ft event out , spi3_mosi/i2s3_sd, usar t3_ck - - - 54 pd2 i/o ft event out 26 a3 39 55 pb3 i/o ft jtdo-traceswo, tim2_ch2, tsc_g5_io1, spi3_sck/i2s3_ck, usar t2_tx, event out 27 a4 40 56 pb4 i/o ft jtrst , tim16_ch1, tsc_g5_io2, spi3_miso/i2s3ext_sd, usar t2_rx, tim17_bkin, event out 28 b4 41 57 pb5 i/o ft tim16_bkin, i2c1_smbal, spi3_mosi/i2s3_sd, usar t2_ck, i2c3_sda, tim17_ch1, event out 29 c4 42 58 pb6 i/o ftf tim16_ch1n, tsc_g5_io3, i2c1_scl, usar t1_tx, event out 30 d4 43 59 pb7 i/o ftf tim17_ch1n, tsc_g5_io4, i2c1_sda, usar t1_rx, event out t able 12. stm32f301x6/x8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 stm32f301x6/x8 pinouts and pin description docid025146 rev 1 39/130 31 a5 44 60 boot0 i b boot memory selection - b5 45 61 pb8 i/o ftf tim16_ch1, tsc_sync, i2c1_scl, usart3_rx, tim1_bkin, event out - c5 46 62 pb9 i/o ftf tim17_ch1, i2c1_sda, ir-out , usar t3_tx, comp2_out , event out 32 e6 47 63 vss_1 s - digital ground "1" f7 48 64 vdd_1 s - digital power supply 1. pc13, pc14 and pc15 are supplied through the power switch. since the switch sinks only a limited amount of current (3 ma), th e use of gpio pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf - these gpios must not be used as current sources (e.g. to drive an led). after the first backup domain power-up, pc13, pc14 and pc15 operate as gpios. their function then depends on the content of the backup registers which is not reset by the main reset. for details on how to manage these gpios, refer to the battery backup domain and bkp register description secti ons in the rm0366 reference manual. t able 12. stm32f301x6/x8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes alternate functions additional functions uqfn32 wlcsp49 lqfp48 lqfp64 pinouts and pin description stm32f301x6/x8 40/130 docid025146 rev 1 t able 13. alternate functions for port a port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af1 1 af12 af13 af14 af15 sys_af tim2/tim15/tim16 /tim17/event i2c3/tim1/tim2/tim15 i2c3/tim15/tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3/infrared spi2/i2s2/spi3/ i2s3/tim1/infrared usart1/usart2/usart3/ gpcomp6 i2c3/gpcomp2 /gpcomp4/gpcomp6 tim1/tim15 tim2/tim17 tim1 tim1 event pa 0 tim2_c h1/ tim2_e tr tsc_g 1_io1 usar t 2_cts event out pa 1 r tc_re fin tim2_c h2 tsc_g 1_io2 usar t 2_r ts tim15_ ch1n event out pa 2 tim2_c h3 tsc_g 1_io3 usar t 2_tx comp2 _out tim15_ ch1 event out pa 3 tim2_c h4 tsc_g 1_io4 usar t 2_rx tim15_ ch2 event out pa 4 tsc_g 2_io1 spi3_nss/ i2s3_ws usar t 2_ck event out pa 5 tim2_c h1/ tim2_e tr tsc_g 2_io2 event out pa 6 tim16_ ch1 tsc_g 2_io3 tim1_bkin event out pa 7 tim17_ ch1 tsc_g 2_io4 tim1_ch1 n event out p a8 mco i2c3_s cl i2c2_s mbal i2s2_mc k tim1_ch1 usar t 1_ck event out stm32f301x6/x8 pinouts and pin description docid025146 rev 1 41/130 pa9 i2c3_s mbal tsc_g 4_io1 i2c2_s cl i2s3_mc k tim1_ch2 usar t 1_tx tim15_ bkin tim2_c h3 event out p a10 tim17_ bkin tsc_g 4_io2 i2c2_s da spi2_mis o/i2s2ext _sd tim1_ch3 usar t 1_rx comp6 _out tim2_c h4 event out pa 11 spi2_mo si/i2s2_s d tim1_ch1 n usar t 1_cts tim1_c h4 tim1_b kin2 event out p a12 tim16_ ch1 i2sckin tim1_ch2 n usar t 1_r ts comp2 _out tim1_e tr event out p a13 swda t - jtms tim16_ ch1n tsc_g 4_io3 ir-out usar t 3_cts event out p a14 swclk- jtck tsc_g 4_io4 i2c1_s da tim1_bkin usar t 2_tx event out p a15 jtdi tim2_c h1/ tim2_e tr tsc_s ync i2c1_s cl spi3_nss/ i2s3_ws usar t 2_rx tim1_b kin event out t able 13. alternate functions for port a (continued) port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af1 1 af12 af13 af14 af15 sys_af tim2/tim15/tim16 /tim17/event i2c3/tim1/tim2/tim15 i2c3/tim15/tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3/infrared spi2/i2s2/spi3/ i2s3/tim1/infrared usart1/usart2/usart3/ gpcomp6 i2c3/gpcomp2 /gpcomp4/gpcomp6 tim1/tim15 tim2/tim17 tim1 tim1 event pinouts and pin description stm32f301x6/x8 42/130 docid025146 rev 1 t able 14. alternate functions for port b port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af1 1 af12 af13 af14 af15 sys_af tim2/tim15/tim16 /tim17/event i2c3/tim1/tim2/tim15 i2c3/tim15/tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3/infrared spi2/i2s2/spi3/ i2s3/tim1/infrared usart1/usart2/usart3/ gpcomp6 i2c3/gpcomp2 /gpcomp4/gpcomp6 tim1/tim15 tim2/tim17 tim1 tim1 event pb0 tsc_g 3_io2 tim1_c h2n event out pb1 tsc_g 3_io3 tim1_c h3n comp4 _out event out pb2 tsc_g 3_io4 event out pb3 jtdo- trace swo tim2_c h2 tsc_g 5_io1 spi3_s ck/i2s3 _ck usar t 2_tx event out pb4 jtrst tim16_ ch1 tsc_g 5_io2 spi3_mi so/i2s3 _sd usar t 2_rx tim17_ bkin event out pb5 tim16_ bkin i2c1_s mbal spi3_m osi/i2s 3ext_sd usar t 2_ck i2c3_s da tim17_ ch1 event out pb6 tim16_ ch1n tsc_g 5_io3 i2c1_s cl usar t 1_tx event out pb7 tim17_ ch1n tsc_g 5_io4 i2c1_s da usar t 1_rx event out pb8 tim16_ ch1 tsc_s ync i2c1_s cl usar t 3_rx tim1_b kin event out pb9 tim17_ ch1 i2c1_s da ir-out usar t 3_tx comp2 _out event out stm32f301x6/x8 pinouts and pin description docid025146 rev 1 43/130 pb10 tim2_c h3 tsc_s ync usar t 3_tx event out pb1 1 tim2_c h4 tsc_g 6_io1 usar t 3_rx event out pb12 tsc_g 6_io2 i2c2_s mbal spi2_n ss/i2s2 _ws tim1_b kin usar t 3_ck event out pb13 tsc_g 6_io3 spi2_s ck/ i2s2_c k tim1_c h1n usar t 3_cts event out pb14 tim15_ ch1 tsc_g 6_io4 spi2_mi so/i2s2 ext_sd tim1_c h2n usar t 3_r ts event out pb15 r tc_r efin tim15_ ch2 tim15_ ch1n tim1_c h3n spi2_m osi/ i2s2_s d event out t able 14. alternate functions for port b (continued) port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af1 1 af12 af13 af14 af15 sys_af tim2/tim15/tim16 /tim17/event i2c3/tim1/tim2/tim15 i2c3/tim15/tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3/infrared spi2/i2s2/spi3/ i2s3/tim1/infrared usart1/usart2/usart3/ gpcomp6 i2c3/gpcomp2 /gpcomp4/gpcomp6 tim1/tim15 tim2/tim17 tim1 tim1 event pinouts and pin description stm32f301x6/x8 44/130 docid025146 rev 1 t able 15. alternate functions for port c port & pin name af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim2/tim15/ tim16/tim17/ event i2c3/tim1/tim2 /tim15 i2c3/tim15/ tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3 infrared spi2/i2s2/spi3/ i2s3/tim1/ infrared usart1/ usart2/ usart3/ gpcomp6 pc0 event out tim1_ch1 pc1 event out tim1_ch2 pc2 event out tim1_ch3 pc3 event out tim1_ch4 tim1_bkin2 pc4 event out tim1_etr usar t1_tx pc5 event out tim15_bkin tsc_g3_io1 usar t1_rx pc6 event out i2s2_mck comp6_out pc7 event out i2s3_mck pc8 event out pc9 event out i2c3_sda i2sckin pc10 event out spi3_sck/ i2s3_ck usar t3_tx pc1 1 event out spi3_miso/i2s3e xt_sd usar t3_rx pc12 event out spi3_mosi/i2s3_ sd usar t3_ck pc13 tim1_ch1n pc14 pc15 stm32f301x6/x8 pinouts and pin description docid025146 rev 1 45/130 t able 16. alternate functions for port d port & pin name af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim2/tim15/ tim16/tim17/ event i2c3/tim1/tim2/ tim15 i2c3/tim15/tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3/ infrared spi2/i2s2/spi3/ i2s3/tim1/ infrared usart1/ usart2/ usart3/ gpcomp6 pd2 event out t able 17. alternate functions for port f port & pin name af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim2/tim15/ tim16/tim17/ event i2c3/tim1/tim2/ tim15 i2c3/tim15/tsc i2c1/i2c2/tim1/ tim16/tim17 spi2/i2s2/ spi3/i2s3/ infrared spi2/i2s2/spi3/ i2s3/tim1/ infrared usart1/usar t2/usart3/ gpcomp6 pf0 i2c2_sda spi2_nss/ i2s2_ws tim1_ch3n pf1 i2c2_scl spi2_sck/ i2s2_ck memory mapping stm32f301x6/x8 46/130 docid025146 rev 1 5 memory mapping figure 8. stm32f301x6/x8 memory mapping [ ) ) ) ) ) ) ) ) [ ( [ & [ $ [ [ [ [ [ & r u w h [ 0 z l w k ) 3 8 , q w h u q d o 3 h u l s k h u d o v 3 h u l s k h u d o v 6 5 $ 0 & 2 ' ( 2 s w l r q e \ w h v 6 \ v w h p p h p r u \ ) o d v k p h p r u \ ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q % 2 2 7 f r q i l j x u d w l r q $ + % $ + % $ 3 % $ 3 % [ [ [ [ ) ) [ [ & [ [ $ [ [ ) ) ) ) ) ) ) [ ) ) ) ) [ ) ) ) ' [ [ [ [ 5 h v h u y h g 0 6 y 9 $ + % [ ) ) 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g docid025146 rev 1 47/130 stm32f301x6/x8 memory mapping 48 t able 18. stm32f301x6/x8 peripheral register boundary addresses bus boundary address size (bytes) peripheral ahb3 0x5000 0000 - 0x5000 03ff 1 k adc1 0x4800 1800 - 0x4fff ffff ~132 m reserved ahb2 0x4800 1400 - 0x4800 17ff 1 k gpiof 0x4800 1000 - 0x4800 13ff 1 k reserved 0x4800 0c00 - 0x4800 0fff 1 k gpiod 0x4800 0800 - 0x4800 0bff 1 k gpioc 0x4800 0400 - 0x4800 07ff 1 k gpiob 0x4800 0000 - 0x4800 03ff 1 k gpioa 0x4002 4400 - 0x47ff ffff ~128 m reserved ahb1 0x4002 4000 - 0x4002 43ff 1 k tsc 0x4002 3400 - 0x4002 3fff 3 k reserved 0x4002 3000 - 0x4002 33ff 1 k crc 0x4002 2400 - 0x4002 2fff 3 k reserved 0x4002 2000 - 0x4002 23ff 1 k flash interface 0x4002 1400 - 0x4002 1fff 3 k reserved 0x4002 1000 - 0x4002 13ff 1 k rcc 0x4002 0400 - 0x4002 0fff 3 k reserved 0x4002 0000 - 0x4002 03ff 1 k dma1 0x4001 8000 - 0x4001 ffff 32 k reserved apb2 0x4001 4c00 - 0x4001 7fff 13 k reserved 0x4001 4800 - 0x4001 4bff 1 k tim17 0x4001 4400 - 0x4001 47ff 1 k tim16 0x4001 4000 - 0x4001 43ff 1 k tim15 0x4001 3c00 - 0x4001 3fff 1 k reserved 0x4001 3800 - 0x4001 3bff 1 k usart1 0x4001 3000 - 0x4001 37ff 2 k reserved 0x4001 2c00 - 0x4001 2fff 1 k tim1 0x4001 0800 - 0x4001 2bff 8 k reserved 0x4001 0400 - 0x4001 07ff 1 k exti 0x4001 0000 - 0x4001 03ff 1 k syscfg + comp + op amp 0x4000 9c00 - 0x4000 ffff 25 k reserved memory mapping stm32f301x6/x8 48/130 docid025146 rev 1 apb1 0x4000 7c00 - 0x4000 9bff 8 k reserved 0x4000 7800 - 0x4000 7bff 1 k i2c3 0x4000 7400 - 0x4000 77ff 1 k dac1 0x4000 7000 - 0x4000 73ff 1 k pwr 0x4000 5c00 - 0x4000 6fff 5 k reserved 0x4000 5800 - 0x4000 5bff 1 k i2c2 0x4000 5400 - 0x4000 57ff 1 k i2c1 0x4000 4c00 - 0x4000 53ff 2 k reserved 0x4000 4800 - 0x4000 4bff 1 k usar t3 0x4000 4400 - 0x4000 47ff 1 k usar t2 0x4000 4000 - 0x4000 43ff 1 k i2s3ext 0x4000 3c00 - 0x4000 3fff 1 k spi3/i2s3 0x4000 3800 - 0x4000 3bff 1 k spi2/i2s2 0x4000 3400 - 0x4000 37ff 1 k i2s2ext 0x4000 3000 - 0x4000 33ff 1 k iwdg 0x4000 2c00 - 0x4000 2fff 1 k wwdg 0x4000 2800 - 0x4000 2bff 1 k r tc 0x4000 1400 - 0x4000 27ff 5 k reserved 0x4000 1000 - 0x4000 13ff 1 k tim6 0x4000 0400 - 0x4000 0fff 3 k reserved 0x4000 0000 - 0x4000 03ff 1 k tim2 0x2000 4000 - 3fff ffff ~512 m reserved 0x2000 0000 - 0x2000 3fff 16 k sram 0x1fff f800 - 0x1fff ffff 2 k option bytes 0x1fff d800 - 0x1fff f7ff 8 k system memory 0x0801 0000 - 0x1fff d7ff ~384 m reserved 0x0800 0000 - 0x0800 ffff 64 k main flash memory 0x0001 0000 - 0x07ff ffff ~128 m reserved 0x0000 000 - 0x0000 ffff 64 k main flash memory, system memory or sram depending on boot configuration t able 18. stm32f301x6/x8 peripheral register boundary addresses (continued) bus boundary address size (bytes) peripheral docid025146 rev 1 49/130 stm32f301x6/x8 electrical characteristics 110 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ? ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3.3 v . they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ? ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 9 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 10 . figure 9. pin loading conditions figure 10. pin input voltage 0 6 9 & s ) 0 & 8 s l q 0 6 9 0 & 8 s l q 9 , 1 electrical characteristics stm32f301x6/x8 50/130 docid025146 rev 1 6.1.6 power supply scheme figure 1 1. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc..) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 3 r z h u v z l w f k 9 % $ 7 * 3 , 2 v 2 8 7 , 1 . h u q h o o r j l f & 3 8 ' l j l w d o 0 h p r u l h v % d f n x s f l u f x l w u \ / 6 ( 5 7 & % d f n x s u h j l v w h u v : d n h x s o r j l f q ) ? ? ) 9 5 h j x o d w r u 9 ' ' $ 9 6 6 $ $ ' & ' $ & / h y h o v k l i w h u , 2 / r j l f 9 ' ' q ) ? ) 9 ' ' $ 9 5 ( ) 9 5 ( ) 9 ' ' 9 6 6 ? ? ? ! n a l o g 2 # s 0 , , c o m p a r a t o r s / 0 ! - 0 0 6 9 docid025146 rev 1 51/130 stm32f301x6/x8 electrical characteristics 110 6.1.7 current consumption measurement figure 12. current consumption measurement scheme 0 6 9 9 % $ 7 9 ' ' 9 ' ' $ , ' ' , ' ' $ , ' ' b 9 % $ 7 electrical characteristics stm32f301x6/x8 52/130 docid025146 rev 1 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in t able 19: v oltage characteristics , t able 20: current characteristics , and t able 21: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. t able 19. v oltage characteristics (1) symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda, v ba t and v dd ) -0.3 4.0 v v dd ?v dda allowed voltage dif ference for v dd > v dda - 0.4 v in (2) input voltage on ft and ftf pins v ss ? 0.3 v dd + 4.0 input voltage on tt a and tt pins v ss ? 0.3 4.0 input voltage on any other pin v ss ?? 0.3 4.0 | ? v ddx | v ariations between dif ferent v dd power pins - 50 mv |v ssx ?? v ss | v ariations between all the dif ferent ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.12: electrical sensitivity characteristics v 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply , in the permitted range. the following relationship must be respected between v dda and v dd : v dda must power on before or at the same time as v dd in the power up sequence. v dda must be greater than or equal to v dd . 2. v in maximum must always be respected. refer to t able 20: current characteristics for the maximum allowed injected current values. docid025146 rev 1 53/130 stm32f301x6/x8 electrical characteristics 110 t able 20. current characteristics symbol ratings max. unit ? i vdd t otal current into sum of all vdd_x power lines (source) 130 ma ? i vss t otal current out of sum of all vss_x ground lines (sink) -130 i vdd maximum current into each v dd_x power line (source) (1) 100 i vss maximum current out of each v ss _x ground line (sink) (1) -100 i io(pin) output current sunk by any i/o and control pin 25 output current sourced by any i/o and control pin -25 ? i io(pin) t otal output current sunk by sum of all ios and control pins (2) 80 t otal output current sourced by sum of all ios and control pins (2) -80 i inj(pin) injected current on tt , ft , ftf and b pins (3) -5/+0 injected current on tc and rst pin (4) +/-5 injected current on tt a pins (5) +/-5 ? i inj(pin) t otal injected current (sum of all i/o and control pins) (6) +/-25 1. all main power (v dd , v dda ) and ground (v ss and v ssa ) pins must always be connected to the external power supply , in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins.the total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count lqfp packages. 3. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 4. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to t able 19: v oltage characteristics for the maximum allowed input voltage values. 5. a positive injection is induced by v in > v dda while a negative injection is induced by v in < v ss . i inj (pin) must never be exceeded. refer also to t able 19: v oltage characteristics for the maximum allowed input voltage values. negative injection disturbs the analog performance of the device. see note (2) below t able 64 . 6. when several inputs are submitted to a current injection, the maximum ? i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). t able 21. thermal characteristics symbol ratings v alue unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c electrical characteristics stm32f301x6/x8 54/130 docid025146 rev 1 6.3 operating conditions 6.3.1 general operating conditions t able 22. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency 0 72 mhz f pclk1 internal apb1 clock frequency 0 36 f pclk2 internal apb2 clock frequency 0 72 v dd standard operating voltage 2 3.6 v v dda analog operating voltage (op amp and dac not used) must have a potential equal to or higher than v dd 2 3.6 v analog operating voltage (op amp and dac used) 2.4 3.6 v ba t backup operating voltage 1.65 3.6 v v in i/o input voltage tc i/o ?0.3 v dd +0.3 v tt i/o (1) -0.3 3.6 tt a i/o ?0.3 v dda +0.3 ft and ftf i/o (1) 1. t o sustain a voltage higher than v dd +0.3 v , the internal pull-up/pull-down resistors must be disabled. ?0.3 5.5 boot0 0 5.5 p d power dissipation at t a = 85 c for suf fix 6 or t a = 105 c for suf fix 7 (2) 2. if t a is lower , higher p d values are allowed as long as t j does not exceed t jmax . see t able 77: package thermal characteristics . lqfp64 - 444 mw lqfp48 - 364 wlcsp49 - 408 ufqfn32 - 540 t a ambient temperature for 6 suf fix version maximum power dissipation ?40 85 c low power dissipation (3) 3. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . see t able 77: package thermal characteristics ?40 105 ambient temperature for 7 suf fix version maximum power dissipation ?40 105 c low power dissipation (3) ?40 125 t j junction temperature range 6 suf fix version ?40 105 c 7 suf fix version ?40 125 docid025146 rev 1 55/130 stm32f301x6/x8 electrical characteristics 110 6.3.2 operating conditions at power-up / power-down the parameters given in t able 23 are derived from tests performed under the ambient temperature condition summarized in t able 22 . 6.3.3 embedded reset and power control block characteristics the parameters given in t able 24 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in t able 22 . t able 23. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate 0 ? s/v v dd fall time rate 20 ? t vdda v dda rise time rate 0 ? v dda fall time rate 20 ? t able 24. embedded reset and power control block characteristics symbol parameter conditions min t yp max unit v por/pdr (1) 1. the pdr detector monitors v dd and also v dda (if kept enabled in the option bytes). the por detector monitors only v dd . power on/power down reset threshold falling edge 1.8 (2) 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (1) pdr hysteresis - 40 - mv t rsttempo (3) 3. based on characterization, not tested in production. por reset temporization 1.5 2.5 4.5 ms electrical characteristics stm32f301x6/x8 56/130 docid025146 rev 1 t able 25. programmable voltage detector characteristics symbol parameter conditions min (1) 1. data based on characterization results only , not tested in production. t yp max (1) unit v pvd0 pvd threshold 0 rising edge 2.1 2.18 2.26 v falling edge 2 2.08 2.16 v pvd1 pvd threshold 1 rising edge 2.19 2.28 2.37 falling edge 2.09 2.18 2.27 v pvd2 pvd threshold 2 rising edge 2.28 2.38 2.48 falling edge 2.18 2.28 2.38 v pvd3 pvd threshold 3 rising edge 2.38 2.48 2.58 falling edge 2.28 2.38 2.48 v pvd4 pvd threshold 4 rising edge 2.47 2.58 2.69 falling edge 2.37 2.48 2.59 v pvd5 pvd threshold 5 rising edge 2.57 2.68 2.79 falling edge 2.47 2.58 2.69 v pvd6 pvd threshold 6 rising edge 2.66 2.78 2.9 falling edge 2.56 2.68 2.8 v pvd7 pvd threshold 7 rising edge 2.76 2.88 3 falling edge 2.66 2.78 2.9 v pvdhyst (2) 2. guaranteed by design, not tested in production. pvd hysteresis - 100 - mv idd(pvd) pvd current consumption - 0.15 0.26 a docid025146 rev 1 57/130 stm32f301x6/x8 electrical characteristics 110 6.3.4 embedded reference voltage the parameters given in t able 26 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in t able 22 . 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 12: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. t able 26. embedded internal reference voltage symbol parameter conditions min t yp max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.2 1.25 v ?40 c < t a < +85 c 1.16 1.2 1.24 (1) 1. data based on characterization results, not tested in production. v t s_vrefint adc sampling time when reading the internal reference voltage 2.2 - - s v rerint internal reference voltage spread over the temperature range v dd = 3 v 10 mv - - 10 (2) 2. guaranteed by design, not tested in production. mv t coef f t emperature coef ficient - - 100 (2 ) ppm/ c t able 27. internal reference voltage calibration values calibration value name description memory address v refint_cal raw data acquired at temperature of 30 c v dda = 3.3 v 0x1fff f7ba - 0x1fff f7bb electrical characteristics stm32f301x6/x8 58/130 docid025146 rev 1 typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled except when explicitly mentioned ? the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz,1 wait state from 24 to 48 mhz and 2 wait states from 48 to 72 mhz) ? prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) ? when the peripherals are enabled f pclk2 = f hclk and f pclk1 = f hclk/2 ? when f hclk > 8 mhz, the pll is on and the pll input is equal to hsi/2 (4 mhz) or hse (8 mhz) in bypass mode. the parameters given in t able 28 to t able 34 are derived from tests performed under ambient temperature and supply voltage conditions summarized in t able 22 . t able 28. t ypical and maximum current consumption from vdd supply at vdd = 3.6v symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit ty p max @ t a (1) ty p max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c i dd supply current in run mode, executing from flash external clock (hse bypass) 72 mhz 45.7 48.6 50.0 52.0 25.5 27.5 28.1 28.8 ma 64 mhz 40.6 43.6 44.5 46.4 22.7 24.6 25.2 25.9 48 mhz 30.8 33.6 34.1 35.5 17.3 19.0 19.5 20.0 32 mhz 21.0 22.9 23.5 25.6 1 1.7 13.2 13.7 14.1 24 mhz 16.0 16.8 18.0 18.9 9.0 10.4 10.8 1 1.4 8 mhz 5.4 5.6 6.1 7.2 3.3 3.3 3.8 4.2 1 mhz 1.1 1.2 1.7 2.7 0.8 0.9 1.3 1.6 internal clock (hsi) 64 mhz 37.6 41.3 42.9 44.7 22.5 24.7 25.0 25.8 48 mhz 28.7 32.3 33.1 34.0 17.2 19.1 19.4 19.6 32 mhz 19.5 22.0 23.4 24.6 1 1.5 12.9 13.5 13.7 24 mhz 14.9 16.6 17.9 18.4 6.0 7.0 7.4 7.9 8 mhz 5.2 5.5 6.4 7.0 3.2 3.8 4.3 4.7 docid025146 rev 1 59/130 stm32f301x6/x8 electrical characteristics 110 i dd supply current in run mode, executing from ram external clock (hse bypass) 72 mhz 45.8 49.1 (2) 50.1 51.4 (2) 25.1 27.3 (2) 28.0 28.6 (2) ma 64 mhz 40.8 43.6 44.9 46.9 22.3 24.1 25.0 25.5 48 mhz 25.5 27.5 28.4 29.7 14.0 15.6 16.2 16.8 32 mhz 20.5 23.1 24.1 25.4 1 1.1 12.2 13.2 13.3 24 mhz 15.4 17.1 18.3 19.5 8.5 9.7 10.1 10.2 8 mhz 5.0 5.9 6.3 6.9 3.1 3.7 4.1 4.7 1 mhz 0.8 1.1 1.9 2.6 0.5 0.8 1.2 1.4 internal clock (hsi) 64 mhz 37.3 41.1 41.8 43.3 22.0 23.8 24.4 24.9 48 mhz 28.0 31.1 31.6 33.2 16.4 18.0 18.3 18.6 32 mhz 18.8 21.3 22.1 23.1 10.9 1 1.9 12.8 13.1 24 mhz 14.2 15.9 16.8 17.9 5.5 6.4 6.7 7.3 8 mhz 4.8 5.1 6.0 6.5 2.9 3.5 4.1 4.2 supply current in sleep mode, executing from flash or ram external clock (hse bypass) 72 mhz 30.0 32.8 (2) 33.1 34.1 (2) 5.9 6.8 (2) 6.9 7.4 (2) 64 mhz 26.7 29.2 29.6 30.5 5.3 5.9 6.2 6.7 48 mhz 16.7 18.5 19.0 19.7 3.6 4.5 4.5 5.3 32 mhz 13.3 14.9 15.3 15.4 2.9 3.7 3.8 4.3 24 mhz 10.2 1 1.4 12.0 12.3 2.2 2.7 2.9 3.2 8 mhz 3.6 4.4 4.8 5.3 0.9 1.2 1.5 2.1 1 mhz 0.5 0.8 1.1 1.3 0.1 0.4 0.8 0.8 i dd supply current in sleep mode, executing from flash or ram internal clock (hsi) 64 mhz 23.2 25.3 25.6 26.2 5.0 5.7 6.1 6.2 ma 48 mhz 17.5 19.2 19.4 19.9 3.9 4.7 4.8 5.3 32 mhz 1 1.7 12.9 13.2 13.3 2.6 3.4 3.6 4.2 24 mhz 8.9 10.2 10.6 10.8 1.4 2.1 2.4 2.7 8 mhz 3.4 4.0 4.6 5.1 0.7 1.1 1.4 1.9 1. data based on characterization results, not tested in production unless otherwise specified. 2. data based on characterization results and tested in production with code executing from ram. t able 28. t ypical and maximum current consumption from vdd supply at vdd = 3.6v (continued) symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit ty p max @ t a (1) ty p max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c electrical characteristics stm32f301x6/x8 60/130 docid025146 rev 1 t able 29. t ypical and maximum current consumption from the v dda supply symbol parameter conditions (1) f hclk v dda = 2.4 v v dda = 3.6 v unit ty p max @ t a (2) ty p max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dda supply current in run mode, code executing from flash or ram hse bypass 72 mhz 231 254 (3) 266 271 (3) 251 274 (3) 294 300 (3) a 64 mhz 203 226 239 243 222 245 261 266 48 mhz 153 174 182 186 165 185 198 203 32 mhz 105 124 131 133 1 14 132 141 143 24 mhz 82 98 104 105 89 106 1 1 1 1 13 8 mhz 3.1 4.1 4.1 5.1 3.6 4.7 5.2 5.5 1 mhz 3.1 4.1 4.1 5.1 3.6 4.7 5.2 5.5 hsi clock 64 mhz 270 294 307 312 296 322 338 343 48 mhz 219 242 253 257 240 263 276 281 32 mhz 171 192 201 203 188 209 219 222 24 mhz 148 169 175 177 163 182 190 193 8 mhz 69 84 87 87 79 92 94 96 1. current consumption from the v dda supply is independent of whether the peripherals are on or of f. furthermore when the pll is of f, i dda is independent from the frequency . 2. data based on characterization results, not tested in production. 3. data based on characterization results and tested in production. t able 30. t ypical and maximum v dd consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd =v dda ) max (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, all oscillators off 16.92 17.09 17.16 17.27 17.39 17.50 35.50 359.1 564.5 a regulator in low-power mode, all oscillators off 5.29 5.46 5.55 5.70 5.73 5.95 30.30 267.1 407.4 supply current in standby mode lsi on and iwdg on 0.80 0.93 1.1 1 1.19 1.31 1.41 - - - lsi off and iwdg off 0.63 0.76 0.84 0.95 1.02 1.10 5.00 6.30 12.60 1. data based on characterization results, not tested in production unless otherwise specified. docid025146 rev 1 61/130 stm32f301x6/x8 electrical characteristics 110 t able 31. t ypical and maximum v dda consumption in stop and standby modes symbol parameter conditions t yp @v dd (v dd = v dda ) max (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dda supply current in stop mode v dda monitoring on regulator in run/low- power mode, all oscillators off 1.70 1.83 1.95 2.08 2.22 2.37 3.40 5.30 5.5 a supply current in standby mode lsi on and iwdg on 2.08 2.25 2.41 2.59 2.79 3.01 - - - lsi off and iwdg off 1.59 1.72 1.83 1.96 2.10 2.25 2.80 2.90 3.60 supply current in stop mode v dda monitoring off regulator in run/low- power mode, all oscillators off 0.99 1.01 1.04 1.09 1.14 1.21 - - - supply current in standby mode lsi on and iwdg on 1.36 1.43 1.50 1.60 1.72 1.85 - - - lsi off and iwdg off 0.87 0.89 0.92 0.97 1.02 1.09 - - - 1. data based on characterization results, not tested in production. t able 32. t ypical and maximum current consumption from v ba t supply symbol para meter conditions (1) t yp.@v ba t max. @v ba t = 3.6v (2) t a (c) unit 1.65v 1.8v 2v 2.4v 2.7v 3v 3.3v 3.6v 25 85 105 i dd_vba t backup domain supply current lse & r tc on; ?xtal mode? lower driving capability; lsedr v[1: 0] = '00' 0.41 0.43 0.46 0.54 0.59 0.66 0.74 0.82 - - - a lse & r tc on; ?xtal mode? higher driving capability; lsedr v[1: 0] = '1 1' 0.65 0.68 0.73 0.80 0.87 0.95 1.03 1.14 - - - 1. crystal used: abracon abs07-120-32.768 khz-t with a cl of 6 pf for typical values. 2. data based on characterization results, not tested in production. electrical characteristics stm32f301x6/x8 62/130 docid025146 rev 1 figure 13. typical v bat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) typical current consumption the mcu is placed under the following conditions: ? v dd = v dda = 3.3 v ? all i/o pins available on each package are in analog input configuration ? the flash access time is adjusted to f hclk frequency (0 wait states from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states from 48 mhz to 72 mhz), and flash prefetch is on ? when the peripherals are enabled, f apb1 = f ahb/2 , f apb2 = f ahb ? pll is used for frequencies greater than 8 mhz ? ahb prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 mhz, 2 mhz, 1 mhz, 500 khz and 125 khz respectively. 0 6 0 6 [ [ [ [ [ 9 \ ? & ? & ? & ? & ? $ , 9 % $ 7 7 $ ? & 9 9 9 9 9 9 9 9 docid025146 rev 1 63/130 stm32f301x6/x8 electrical characteristics 110 t able 33. t ypical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk ty p unit peripherals enabled peripherals disabled i dd supply current in run mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash 72 mhz 44.8 24.9 ma 64 mhz 40.0 22.4 48 mhz 30.3 17.1 32 mhz 20.7 1 1.9 24 mhz 15.8 9.2 16 mhz 10.9 6.5 8 mhz 5.7 3.55 4 mhz 3.43 3.22 2 mhz 2.18 1.53 1 mhz 1.56 1.19 500 khz 1.25 0.96 125 khz 0.96 0.84 i dda (1) (2) supply current in run mode from v dda supply 72 mhz 237.1 a 64 mhz 208.3 48 mhz 154.3 32 mhz 105.0 24 mhz 81.3 16 mhz 57.8 8 mhz 1.15 4 mhz 1.15 2 mhz 1.15 1 mhz 1.15 500 khz 1.15 125 khz 1.15 1. v dda monitoring is off . 2. when peripherals are enabled, the power consumption of the analog part of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tables of characteristics in the subsequent sections. electrical characteristics stm32f301x6/x8 64/130 docid025146 rev 1 t able 34. t ypical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk ty p unit peripherals enabled peripherals disabled i dd supply current in sleep mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash or ram 72 mhz 28.7 6.1 ma 64 mhz 25.6 5.5 48 mhz 19.3 4.26 32 mhz 13.1 3.04 24 mhz 10.0 2.42 16 mhz 6.8 1.81 8 mhz 3.54 0.98 4 mhz 2.35 0.88 2 mhz 1.64 0.80 1 mhz 1.28 0.77 500 khz 1.1 1 0.75 125 khz 0.92 0.74 i dda (1) (2) supply current in sleep mode from v dda supply 72 mhz 237.1 a 64 mhz 208.3 48 mhz 154.3 32 mhz 105.0 24 mhz 81.3 16 mhz 57.8 8 mhz 1.15 4 mhz 1.15 2 mhz 1.15 1 mhz 1.15 500 khz 1.15 125 khz 1.15 1. v dda monitoring is off . 2. when peripherals are enabled, the power consumption of the analog part of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tables of characteristics in the subsequent sections. docid025146 rev 1 65/130 stm32f301x6/x8 electrical characteristics 110 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up generate current consumption when the pin is externally held low . the value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in t able 52: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applied. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input value. unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an intermediate voltage level or switch inadvertently , as a result of external electromagnetic noise. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by using pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see t able 36: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: i sw v dd f sw c ? ? = where i sw is the current sunk by a switching i/o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext +c s the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. electrical characteristics stm32f301x6/x8 66/130 docid025146 rev 1 t able 35. switching output i/o current consumption symbol parameter conditions (1) 1. cs = 5 pf (estimated value). i/o toggling frequency (f sw ) t yp unit i sw i/o current consumption v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.90 ma 4 mhz 0.93 8 mhz 1.16 18 mhz 1.60 36 mhz 2.51 48 mhz 2.97 v dd = 3.3 v c ext = 10 pf c = c int + c ext +c s 2 mhz 0.93 4 mhz 1.06 8 mhz 1.47 18 mhz 2.26 36 mhz 3.39 48 mhz 5.99 v dd = 3.3 v c ext = 22 pf c = c int + c ext +c s 2 mhz 1.03 4 mhz 1.30 8 mhz 1.79 18 mhz 3.01 36 mhz 5.99 v dd = 3.3 v c ext = 33 pf c = c int + c ext + c s 2 mhz 1.10 4 mhz 1.31 8 mhz 2.06 18 mhz 3.47 36 mhz 8.35 v dd = 3.3 v c ext = 47 pf c = c int + c ext + c s 2 mhz 1.20 4 mhz 1.54 8 mhz 2.46 18 mhz 4.51 docid025146 rev 1 67/130 stm32f301x6/x8 electrical characteristics 110 on-chip peripheral current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input configuration ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked of f ? with only one peripheral clocked on ? ambient operating temperature at 25c and v dd = v dda = 3.3 v. electrical characteristics stm32f301x6/x8 68/130 docid025146 rev 1 t able 36. peripheral current consumption peripheral t ypical consumption (1) 1. the power consumption of the analog part (i dda ) of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tables of characteristics in the subsequent sections. unit i dd busmatrix (2) 2. busmatrix is automatically active when at least one master is on (cpu or dma1). 1 1.3 a/mhz dma1 6.7 crc 2.0 gpioa 8.5 gpiob 8.3 gpioc 8.6 gpiod 1.5 gpiof 1.0 tsc 4.7 adc1 15.9 apb2-bridge (3) 3. the apbx bridge is automatically active when at least one peripheral is on on the same bus. 2.7 syscfg 3.2 tim1 27.6 usar t1 21.0 tim15 14.3 tim16 10.1 tim17 10.4 apb1-bridge (3) 5.8 tim2 40.7 tim6 7.4 wwdg 4.6 spi2 35.2 spi3 34.2 usar t2 13.9 usar t3 13.1 i2c1 9.4 i2c2 9.4 pwr 4.5 dac 8.3 i2c3 10.5 docid025146 rev 1 69/130 stm32f301x6/x8 electrical characteristics 110 6.3.6 wakeup time from low-power mode the wakeup times given in t able 37 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: ? for stop or sleep mode: the wakeup event is wfe. ? wkup1 (pa0) pin is used to wakeup from standby, stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in t able 22 . t able 37. low-power mode wakeup timings symbol parameter conditions t yp @v dd, v dd = v dda max unit 2.0 v 2.4 v 2.7 v 3 v 3.3 v 3.6 v t wust op w akeup from stop mode regulator in run mode 4.5 4.2 4.1 4.0 3.8 3.8 4.3 s regulator in low-power mode 8.2 7.0 6.4 6.0 5.7 5.5 8.7 t wust andby (1) w akeup from standby mode lsi and iwdg off 72.8 63.4 59.2 56.1 53.1 51.3 103 t wusleep w akeup from sleep mode 6- cpu clock cycles 1. data based on characterization results, not tested in production. electrical characteristics stm32f301x6/x8 70/130 docid025146 rev 1 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 14 . figure 14. high-speed external clock source ac timing diagram t able 38. high-speed external user clock characteristics symbol parameter conditions min t yp max unit f hse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. 1 8 32 mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss - 0.3v dd t w(hseh) t w(hsel) osc_in high or low time (1) 15 - - ns t r(hse) t f(hse) osc_in rise or fall time (1) -- 20 0 6 9 9 + 6 ( + w i + 6 ( 7 + 6 ( w w u + 6 ( 9 + 6 ( / w z + 6 ( + w z + 6 ( / docid025146 rev 1 71/130 stm32f301x6/x8 electrical characteristics 110 low-speed external user clock generated from an external source in bypass mode the lse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 15 figure 15. low-speed external clock source ac timing diagram t able 39. low-speed external user clock characteristics symbol parameter conditions min t yp max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss - 0.3v dd t w(lseh) t w(lsel) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) -- 50 0 6 9 9 / 6 ( + w i / 6 ( 7 / 6 ( w w u / 6 ( 9 / 6 ( / w z / 6 ( + w z / 6 ( / electrical characteristics stm32f301x6/x8 72/130 docid025146 rev 1 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph are based on design simulation results obtained with typical external components specified in t able 40 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). t able 40. hse oscillator characteristics symbol parameter conditions (1) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer . min (2) 2. guaranteed by design, not tested in production. t yp max (2) unit f osc_in oscillator frequency 4 8 32 mhz r f feedback resistor - 200 k ? i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time. - - 8.5 ma v dd =3.3 v , rm= 30 ? , cl=10 pf@8 mhz - 0.4 - v dd =3.3 v , rm= 45 ? , cl=10 pf@8 mhz - 0.5 - v dd =3.3 v , rm= 30 ? , cl=10 pf@32 mhz - 0.8 - v dd =3.3 v , rm= 30 ? , cl=10 pf@32 mhz -1 - v dd =3.3 v , rm= 30 ? , cl=10 pf@32 mhz - 1.5 - g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer . startup time v dd is stabilized - 2 - ms docid025146 rev 1 73/130 stm32f301x6/x8 electrical characteristics 110 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 16 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the combined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 16. t ypical application with an 8 mhz crystal 1. r ext value depends on the crystal characteristics. 0 6 9 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v % l d v f r q w u r o o h g j d l q 5 ( ; 7 & / & / 2 6 & b , 1 2 6 & b 2 8 7 5 ) i + 6 ( electrical characteristics stm32f301x6/x8 74/130 docid025146 rev 1 low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all the information given in this paragraph are based on design simulation results obtained with typical external components specified in t able 41 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. t able 41. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) t yp max (2) unit i dd lse current consumption lsedr v[1:0]=00 lower driving capability - 0.5 0.9 a lsedr v[1:0]=01 medium low driving capability -- 1 lsedr v[1:0]=10 medium high driving capability - - 1.3 lsedr v[1:0]=1 1 higher driving capability - - 1.6 g m oscillator transconductance lsedr v[1:0]=00 lower driving capability 5- - a/v lsedr v[1:0]=01 medium low driving capability 8- - lsedr v[1:0]=10 medium high driving capability 15 - - lsedr v[1:0]=1 1 higher driving capability 25 - - t su(lse) (3) startup time v dd is stabilized - 2 - s 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 2. guaranteed by design, not tested in production. 3. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer . docid025146 rev 1 75/130 stm32f301x6/x8 electrical characteristics 110 figure 17. typical application with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. 0 6 9 2 6 & b 2 8 7 2 6 & b , 1 i / 6 ( & / n + ] u h v r q d w r u & / 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v ' u l y h s u r j u d p p d e o h d p s o l i l h u electrical characteristics stm32f301x6/x8 76/130 docid025146 rev 1 6.3.8 internal clock source characteristics the parameters given in t able 42 are derived from tests performed under ambient temperature and supply voltage conditions summarized in t able 22 . high-speed internal (hsi) rc oscillator figure 18. hsi oscillator accuracy characterization results 1. the above curves are based on characterisation results, not tested in production. t able 42. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min t yp max unit f hsi frequency - 8 - mhz trim hsi user trimming step - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi) duty cycle 45 (2) -5 5 (2) % acc hsi accuracy of the hsi oscillator (factory calibrated) t a = ?40 to 105 c ?3.8 (3) 3. data based on characterization results, not tested in production. - 4.6 (3) % t a = ?10 to 85 c ?2.9 (3) - 2.9 (3) % t a = 0 to 70 c --- % t a = 25 c ?1 - 1 % t su(hsi) hsi oscillator startup time 1 (2) -2 (2) s i dd(hsi) hsi oscillator power consumption - 80 100 (2) a - 3 6 - ! 8 - ) . 4 ! ; ? # = ! # # ( 3 ) docid025146 rev 1 77/130 stm32f301x6/x8 electrical characteristics 110 low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in t able 44 are derived from tests performed under ambient temperature and supply voltage conditions summarized in t able 22 . t able 43. lsi oscillator characteristics (1) 1. v dda = 3.3 v , t a = ?40 to 105 c unless otherwise specified. symbol parameter min t yp max unit f lsi frequency 30 40 50 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time - - 85 s i dd(lsi) (2) lsi oscillator power consumption - 0.75 1.2 a t able 44. pll characteristics symbol parameter v alue unit min t yp max f pll_in pll input clock (1) 1. t ake care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 1 (2) -2 4 (2) mhz pll input clock duty cycle 40 (2) -6 0 (2) % f pll_out pll multiplier output clock 16 (2) - 72 mhz t lock pll lock time - - 200 (2) s jitter cycle-to-cycle jitter - - 300 (2) 2. guaranteed by design, not tested in production. ps electrical characteristics stm32f301x6/x8 78/130 docid025146 rev 1 6.3.10 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. t able 45. flash memory characteristics symbol parameter conditions min t yp max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a ??? ?40 to +105 c 20 - 40 s t erase page (2 kb) erase time t a ?? ?40 to +105 c 20 - 40 ms t me mass erase time t a ?? ?40 to +105 c 20 - 40 ms i dd supply current w rite mode - - 10 ma erase mode - - 12 ma t able 46. flash memory endurance and data retention symbol parameter conditions v alue unit min (1) 1. data based on characterization results, not tested in production. n end endurance t a = ?40 to +85 c (6 suf fix versions) t a = ?40 to +105 c (7 suf fix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 y ears 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 docid025146 rev 1 79/130 stm32f301x6/x8 electrical characteristics 110 6.3.11 emc characteristics susceptibility tests are performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in t able 47 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) t able 47. ems characteristics symbol parameter conditions level/ class v fesd v oltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v , lqfp64, t a = +25c, f hclk = 72 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v , lqfp64, t a = +25c, f hclk = 72 mhz conforms to iec 61000-4-4 4a electrical characteristics stm32f301x6/x8 80/130 docid025146 rev 1 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.12 electrical sensitivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. t able 48. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/72 mhz s emi peak level v dd ?? 3.6 v, t a ?? 25 c, lqfp64 package compliant with iec 61967-2 0.1 to 30 mhz 5 db v 30 to 130 mhz 6 130 mhz to 1ghz 28 sae emi level 4 - t able 49. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a ?? +25 c, conforming to jesd22-a1 14 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a ?? +25 c, conforming to ansi/esd stm5.3.1 ii 250 docid025146 rev 1 81/130 stm32f301x6/x8 electrical characteristics 110 static latch-up two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current injection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or other functional failure (for example reset occurrence or oscillator frequency deviation). the test results are given in t able 51 note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. t able 50. electrical sensitivities symbol parameter conditions class lu static latch-up class t a ?? +105 c conforming to jesd78a 2 level a t able 51. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 -0 na ma injected current on pc0 pin (tt a pin) -0 +5 injected current pc0, pc1, pc2, pc3, p a0, p a1, p a2, p a3, p a4, p a6, p a7, pc4, pb0, pb10, pb1 1, pb13 with induced leakage current on other pins from this group less than -100 a or more than +100 a -5 +5 injected current on any other tt , ft and ftf pins -5 na injected current on all other tc, tt a and reset pins -5 +5 electrical characteristics stm32f301x6/x8 82/130 docid025146 rev 1 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in t able 52 are derived from tests performed under the conditions summarized in t able 22 . all i/os are cmos and ttl compliant. t able 52. i/o static characteristics symbol parameter conditions min t yp max unit v il low level input voltage tt a and tt i/o - - 0.3 v dd + 0.07 (1) v ft and ftf i/o - - 0.475 v dd -0.2 (1) boot0 i/o - - 0.3 v dd ? 0.3 (1) all i/os except boot0 - - 0.3 v dd (2) v ih high level input voltage tt a and tt i/o 0.445 v dd +0.398 (1) -- ft and ftf i/o 0.5 v dd +0.2 (1) -- boot0 0.2 v dd +0.95 (1) -- all i/os except boot0 0.7 v dd (2) -- v hys schmitt trigger hysteresis tc and tt a i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) - i lkg input leakage current (3) tc, ft and ftf i/o tt a i/o in digital mode v ss ? ? v in ? ? v dd - - 0.1 a tt a i/o in digital mode v dd ? ? v in ? ? v dda -- 1 tt a i/o in analog mode v ss ? ? v in ? ? v dda - - 0.2 ft and ftf i/o (4) v dd ? ? v in ? ? 5 v -- 10 r pu w eak pull-up equivalent resistor (5) v in ?? v ss 25 40 55 k ? r pd w eak pull-down equivalent resistor (5) v in ?? v dd 25 40 55 k ? c io i/o pin capacitance - 5 - pf 1. data based on design simulation 2. t ested in production. 3. leakage could be higher than the maximum value. if negative current is injected on adjacent pins. refer to t able 51: i/o current injection susceptibility . 4. t o sustain a voltage higher than v dd +0.3 v , the internal pull-up/pull-down resistors must be disabled. 5. pull-up and pull-down resistors are designed with a true resistance in series with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimum (~10% order). docid025146 rev 1 83/130 stm32f301x6/x8 electrical characteristics 110 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 19 and figure 20 for standard i/os. figure 19. tc and tt a i/o input characteristics - cmos port figure 20. tc and tta i/o input characteristics - ttl port 0 6 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 9 , / p d [ 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g 7 h v w h g l q s u r g x f w l r q 7 h v w h g l q s u r g x f w l r q % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' 0 6 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 9 , / p d [ 9 ' ' 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v electrical characteristics stm32f301x6/x8 84/130 docid025146 rev 1 figure 21. five volt tolerant (ft and ftf) i/o input characteristics - cmos port figure 22. five volt tolerant (ft and ftf) i/o input characteristics - ttl port 0 6 9 9 ' ' 9 9 , / 9 , + 9 9 , / p d [ 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v 7 h v w h g l q s u r g x f w l r q & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' 7 h v w h g l q s u r g x f w l r q 0 6 9 9 ' ' 9 9 , / 9 , + 9 9 , / p l q 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v docid025146 rev 1 85/130 stm32f301x6/x8 electrical characteristics 110 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol/ v oh ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating ? i vdd (see t able 20 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating ? i vss (see t able 20 ). output voltage levels unless otherwise specified, the parameters given in t able 53 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in t able 22 . all i/os (ft, tta and tc unless otherwise specified) are cmos and ttl compliant. t able 53. output voltage characteristics symbol parameter conditions min max unit v ol (1) output low level voltage for an i/o pin cmos port (2) i io = +8 ma 2.7 v < v dd < 3.6 v - 0.4 v v oh (3) output high level voltage for an i/o pin v dd ?0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io = +8 ma 2.7 v < v dd < 3.6 v - 0.4 v oh (3) output high level voltage for an i/o pin 2.4 - v ol (1)(4) output low level voltage for an i/o pin i io = +20 ma 2.7 v < v dd < 3.6 v - 1.3 v oh (3)(4) output high level voltage for an i/o pin v dd ?1.3 - v ol (1)(4) output low level voltage for an i/o pin i io = +6 ma 2 v < v dd < 2.7 v - 0.4 v oh (3)(4) output high level voltage for an i/o pin v dd ?0.4 - v olfm+ (1)(4) output low level voltage for an ftf i/o pin in fm+ mode i io = +20 ma 2.7 v < v dd < 3.6 v - 0.4 1. the i io current sunk by the device must always respect the absolute maximum rating specified in t able 20 and the sum of i io (i/o ports and control pins) must not exceed ? i io(pin) . 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 3. the i io current sourced by the device must always respect the absolute maximum rating specified in t able 20 and the sum of i io (i/o ports and control pins) must not exceed ? i io(pin) . 4. data based on design simulation. electrical characteristics stm32f301x6/x8 86/130 docid025146 rev 1 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 23 and t able 54 , respectively. unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in t able 22 . t able 54. i/o ac characteristics (1) ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (2) c l = 50 pf , v dd = 2 v to 3.6 v- 2 (3) mhz t f(io)out output high to low level fall time c l = 50 pf , v dd = 2 v to 3.6 v -1 25 (3) ns t r(io)out output low to high level rise time -1 25 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf , v dd = 2 v to 3.6 v- 10 (3) mhz t f(io)out output high to low level fall time c l = 50 pf , v dd = 2 v to 3.6 v -2 5 (3) ns t r(io)out output low to high level rise time -2 5 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf , v dd = 2.7 v to 3.6 v- 50 (3) mhz c l = 50 pf , v dd = 2.7 v to 3.6 v- 30 (3) mhz c l = 50 pf , v dd = 2 v to 2.7 v- 20 (3) mhz t f(io)out output high to low level fall time c l = 30 pf , v dd = 2.7 v to 3.6 v- 5 (3) ns c l = 50 pf , v dd = 2.7 v to 3.6 v- 8 (3) c l = 50 pf , v dd = 2 v to 2.7 v- 12 (3) t r(io)out output low to high level rise time c l = 30 pf , v dd = 2.7 v to 3.6 v- 5 (3) c l = 50 pf , v dd = 2.7 v to 3.6 v- 8 (3) c l = 50 pf , v dd = 2 v to 2.7 v- 12 (3) fm+ configuration (4) f max(io)out maximum frequency (2) c l = 50 pf , v dd = 2 v to 3.6 v -2 (4) mhz t f(io)out output high to low level fall time -1 2 (4) ns t r(io)out output low to high level rise time -3 4 (4) 1. the i/o speed is configured using the ospeedrx[1:0] bits. refer to the rm0366 reference manual for a description of gpio port configuration register . 2. the maximum frequency is defined in figure 23 . 3. guaranteed by design, not tested in production. 4. the i/o speed configuration is bypassed in fm+ i/o mode. refer to the stm32f301x6/x8 reference manual rm0366 for a description of fm+ i/o mode configuration. docid025146 rev 1 87/130 stm32f301x6/x8 electrical characteristics 110 figure 23. i/o ac characteristics definition 1. see table 54: i/o ac characteristics . 6.3.15 nrst pin characteristics the nrst pin input driver uses cmos technology . it is connected to a permanent pull-up resistor, r pu (see t able 52 ). unless otherwise specified, the parameters given in t able 55 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in t able 22 . 0 6 9 w u , 2 r x w ( [ w h u q d o r x w s x w r q & / 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w u w i ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ & / 7 w i , 2 r x w v h h q r w h t able 55. nrst pin characteristics symbol parameter conditions min t yp max unit v il(nrst) (1) nrst input low level voltage - - 0.3v dd + 0.07 (1) v v ih(nrst) (1) nrst input high level voltage 0.445v dd + 0.398 (1) -- v hys(nrst) nrst schmitt trigger voltage hysteresis - 200 - mv r pu w eak pull-up equivalent resistor (2) v in ?? v ss 25 40 55 k ? v f(nrst) (1) nrst input filtered pulse - - 100 (1) ns v nf(nrst) (1) nrst input not filtered pulse 500 (1) -- ns 1. guaranteed by design, not tested in production. 2. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . electrical characteristics stm32f301x6/x8 88/130 docid025146 rev 1 figure 24. recommended nrst pin protection 1. the reset network protects the device against parasitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 55 . otherwise the reset will not be taken into account by the device. 6.3.16 timer characteristics the parameters given in t able 56 are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). 0 6 9 5 3 8 1 5 6 7 9 ' ' ) l o w h u , q w h u q d o 5 h v h w ? ) ( [ w h u q d o u h v h w f l u f x l w t able 56. timx (1)(2) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim15, tim16 and tim17 timers. 2. guaranteed by design, not tested in production. symbol parameter conditions min max unit t res(tim) t imer resolution time 1- t timxclk f timxclk = 72 mhz 13.9 - ns f timxclk = 144 mhz, x = 1, 15,16, 17 6.95 - ns f ext t imer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 72 mhz 0 36 mhz res tim t imer resolution timx (except tim2) - 16 bit tim2 - 32 t counter 16-bit counter clock period 1 65536 t timxclk f timxclk = 72 mhz (except tim1/15/16/17) 0.0139 910 s f timxclk = 144 mhz, x= 1/15/16/17 0.0069 455 s t max_count maximum possible count with 32-bit counter - 65536 65536 t timxclk f timxclk = 72 mhz - 59.65 s f timxclk = 144 mhz, x= 1/15/16/17 - 29.825 s docid025146 rev 1 89/130 stm32f301x6/x8 electrical characteristics 110 t able 57. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 khz clock but the microcontroller ? s internal rc frequency can vary from 30 to 60 khz. moreover , given an exact rc oscillator frequency , the exact timings still depend on the phasing of the apb interface clock versus the lsi clock so that there is always a full rc period of uncertainty . prescaler divider pr[2:0] bits min timeout (ms) rl[1 1:0]= 0x000 max timeout (ms) rl[1 1:0]= 0xfff /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 t able 58. wwdg min-max timeout value @72 mhz (pclk) (1) 1. guaranteed by design, not tested in production. prescaler wdgtb min timeout value max timeout value 1 0 0.05687 3.6409 2 1 0.1 137 7.2817 4 2 0.2275 14.564 8 3 0.4551 29.127 electrical characteristics stm32f301x6/x8 90/130 docid025146 rev 1 6.3.17 communications interfaces i 2 c interface characteristics the i2c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s ? fast-mode plus (fm+): with a bit rate up to 1 mbit/s. the i2c timings requirements are guaranteed by design when the i2c peripheral is properly configured (refer to reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not "true" open-drain. when configured as open-drain, the pmos connected between the i/o pin and vddiox is disabled, but is still present. only ftf i/o pins support fm+ low level output current maximum requirement. refer to section 6.3.14: i/o port characteristics for the i2c i/os characteristics. all i2c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics : t able 59. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns docid025146 rev 1 91/130 stm32f301x6/x8 electrical characteristics 110 spi/i 2 s characteristics unless otherwise specified, the parameters given in t able 60 for spi or in t able 61 for i 2 s are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in t able 22 . refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). t able 60. spi characteristics (1) 1. data based on characterization results, not tested in production. symbol parameter conditions min t yp max unit f sck 1/t c(sck) spi clock frequency master mode - - 18 mhz slave mode - - 18 t su(nss) nss setup time slave mode, spi presc = 2 4*tpcl k -- ns t h(nss) nss hold time slave mode, spi presc = 2 2*tpcl k -- t w(sckh) t w(sckl) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk- 2 tpclk tpclk+ 2 t su(mi) t su(si) data input setup time master mode 0 - - slave mode 1 - - t h(mi) data input hold time master mode 6.5 - - t h(si) slave mode 2.5 - - t a(so) data output access time slave mode 8 - 40 t dis(so) data output disable time slave mode 8 - 14 t v(so) t v(mo) data output valid time slave mode - 12 27 master mode - 1.5 4 t h(so) data output hold time slave mode 7.5 - - t h(mo) master mode 0 - - electrical characteristics stm32f301x6/x8 92/130 docid025146 rev 1 figure 25. spi timing diagram - slave mode and cpha = 0 figure 26. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at 0.5v dd and with external c l = 30 pf. d l f ^ < /v?? w , a d k ^ / / e w h d d / ^ k k h d w h d w , a d ^ k h d d ^ / e / d k h d > ^ / e > ^ k h d w k >a w k >a / d / e e ^ ^ ]v?? ? ^ h~ e ^ ^ ?~ ^ < ?z~ e ^ ^ ?~ ^ k ?~ ^ < ,?~ ^ < > ?~ ^ k ?z~ ^ k ??~ ^ <?(~ ^ < ?]?~ ^ k ??~ ^ / ?z~ ^ / d l ^ < /v?? w , a d k ^ / / e w h d d / ^ k k h d w h d w , a d ^ k h d d ^ / e / d k h d > ^ / e > ^ k h d w k > a w k > a / d / e ? ^ h~ e ^ ^ ? ~ ^ < ? z~ e ^ ^ ? ~ ^ k ? ~ ^ > , ? ~ ^ > > ? ~ ^ k ? z~ ^ k ? ?~ ^ > ? (~ ^ > ? ]?~ ^ k ? ?~ ^ / ? z~ ^ / e ^ ^ ]v?? docid025146 rev 1 93/130 stm32f301x6/x8 electrical characteristics 110 figure 27. spi timing diagram - master mode (1) 1. measurement points are done at 0.5v dd and with external c l = 30 pf. a i 6 3 # + / u t p u t # 0 ( ! - / 3 ) / 5 4 0 5 4 - ) 3 / ) . 0 5 4 # 0 ( ! - 3 " ) . - 3 " / 5 4 " ) 4 ) . , 3 " / 5 4 , 3 " ) . # 0 / , # 0 / , " ) 4 / 5 4 . 3 3 i n p u t t c 3 # + t w 3 # + ( t w 3 # + , t r 3 # + t f 3 # + t h - ) ( i g h 3 # + / u t p u t # 0 ( ! # 0 ( ! # 0 / , # 0 / , t s u - ) t v - / t h - / t able 61. i2s characteristics (1) symbol parameter conditions min max unit f mck i2s main clock output - 256 x 8k 256xfs (2) mhz f ck i2s clock frequency master data: 32 bits - 64xfs mhz slave data: 32 bits - 64xfs d ck i2s clock frequency duty cycle slave receiver 30 70 % electrical characteristics stm32f301x6/x8 94/130 docid025146 rev 1 note: refer to rm0366 reference manual i2s section for more details about the sampling frequency (fs), fmck, fck, dck values reflect only the digital peripheral behavior, source clock precision might slightly change the values dck depends mainly on odd bit value. digital contribution leads to a min of (i2sdiv/(2*i2sdiv+odd) and a max (i2sdiv+odd)/(2*i2sdiv+odd) and fs max supported for each mode/condition. t v(ws) ws valid time master mode - 20 ns t h(ws) ws hold time master mode 2 - t su(ws) ws setup time slave mode 0 - t h(ws) ws hold time slave mode 4 - t su(sd_mr) data input setup time master receiver 1 - t su(sd_sr) slave receiver 1 - t h(sd_mr) data input hold time master receiver 8 - t h(sd_sr) slave receiver 2.5 - t v(sd_st) data output valid time slave transmitter (after enable edge) - 50 t v(sd_mt) master transmitter (after enable edge) -2 2 t h(sd_st) data output hold time slave transmitter (after enable edge) 8 - t h(sd_mt) master transmitter (after enable edge) 1- 1. data based on characterization results, not tested in production. 2. 256xfs maximum is 36 mhz (apb1 maximum frequency) t able 61. i2s characteristics (1) (continued) symbol parameter conditions min max unit docid025146 rev 1 95/130 stm32f301x6/x8 electrical characteristics 110 figure 28. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at 0.5v dd and with external c l =30 pf. 2. lsb transmit/receive of the previously transmitted byte. no lsb transmit/receive is sent before the first byte. figure 29. i 2 s master timing diagram (philips protocol) (1) 1. measurement points are done at 0.5v dd and with external c l =30 pf. 2. lsb transmit/receive of the previously transmitted byte. no lsb transmit/receive is sent before the first byte. & . , q s x w & 3 2 / & 3 2 / w f & . : 6 l q s x w 6 ' w u d q v p l w 6 ' u h f h l y h w z & . + w z & . / w v x : 6 w y 6 ' b 6 7 w k 6 ' b 6 7 w k : 6 w v x 6 ' b 6 5 w k 6 ' b 6 5 0 6 % u h f h l y h % l w q u h f h l y h / 6 % u h f h l y h 0 6 % w u d q v p l w % l w q w u d q v p l w / 6 % w u d q v p l w d l e / 6 % u h f h l y h / 6 % w u d q v p l w # + o u t p u t # 0 / , # 0 / , t c # + 7 3 o u t p u t 3 $ r e c e i v e 3 $ t r a n s m i t t w # + ( t w # + , t s u 3 $ ? - 2 t v 3 $ ? - 4 t h 3 $ ? - 4 t h 7 3 t h 3 $ ? - 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b t f # + t r # + t v 7 3 , 3 " r e c e i v e , 3 " t r a n s m i t electrical characteristics stm32f301x6/x8 96/130 docid025146 rev 1 6.3.18 adc characteristics unless otherwise specified, the parameters given in t able 62 to t able 64 are guaranteed by design, with conditions summarized in t able 22 . t able 62. adc characteristics symbol parameter conditions min t yp max unit v dda analog supply voltage for adc 2 - 3.6 v i dda adc current consumption - - tbd tbd tbd f adc adc clock frequency 0.14 - 72 mhz f s (1) sampling rate resolution = 12 bits, fast channel 0.01 - 5.14 msps resolution = 10 bits, fast channel 0.012 - 6 resolution = 8 bits, fast channel 0.014 - 7.2 resolution = 6 bits, fast channel 0.0175 - 9 f trig (1) external trigger frequency f adc = 72 mhz resolution = 12 bits - - 5.14 mhz resolution = 12 bits - - 14 1/f adc v ain conversion voltage range 0 - v dda v r ain (1) external input impedance - - 100 k ? c adc (1) internal sample and hold capacitor -5 - pf t cal (1) calibration time f adc = 72 mhz 1.56 s 1 12 1/f adc t latr (1) t rigger conversion latency regular and injected channels without conversion abort ckmode = 00 1.5 2 2.5 1/f adc ckmode = 01 - - 2 1/f adc ckmode = 10 - - 2.25 1/f adc ckmode = 1 1 - - 2.125 1/f adc t latrinj (1) t rigger conversion latency injected channels aborting a regular conversion ckmode = 00 2.5 3 3.5 1/f adc ckmode = 01 - - 3 1/f adc ckmode = 10 - - 3.25 1/f adc ckmode = 1 1 - - 3.125 1/f adc t s (1) sampling time f adc = 72 mhz 0.021 - 8.35 s 1.5 - 601.5 1/f adc t adcvreg _stup (1) adc v oltage regulator start-up time -- 10 s t conv (1) t otal conversion time (including sampling time) f adc = 72 mhz resolution = 12 bits 0.19 - 8.52 s resolution = 12 bits 14 to 614 (t s for sampling + 12.5 for successive approximation) 1/f adc docid025146 rev 1 97/130 stm32f301x6/x8 electrical characteristics 110 1. data guaranteed by design. t able 63. maximum adc r ain (1) resolution sampling cycle @ 72 mhz sampling time [ns] @ 72 mhz r ain max (k ? ) fast channels (2) slow channels other channels (3) 12 bits 1.5 20.83 0.018 na na 2.5 34.72 0.150 na 0.022 4.5 62.50 0.470 0.220 0.180 7.5 104.17 0.820 0.560 0.470 19.5 270.83 2.70 1.80 1.50 61.5 854.17 8.20 6.80 4.70 181.5 2520.83 22.0 18.0 15.0 601.5 8354.17 82.0 68.0 47.0 10 bits 1.5 20.83 0.082 na na 2.5 34.72 0.270 0.082 0.100 4.5 62.50 0.560 0.390 0.330 7.5 104.17 1.20 0.82 0.68 19.5 270.83 3.30 2.70 2.20 61.5 854.17 10.0 8.2 6.8 181.5 2520.83 33.0 27.0 22.0 601.5 8354.17 100.0 82.0 68.0 8 bits 1.5 20.83 0.150 na 0.039 2.5 34.72 0.390 0.180 0.180 4.5 62.50 0.820 0.560 0.470 7.5 104.17 1.50 1.20 1.00 19.5 270.83 3.90 3.30 2.70 61.5 854.17 12.00 12.00 8.20 181.5 2520.83 39.00 33.00 27.00 601.5 8354.17 100.00 100.00 82.00 electrical characteristics stm32f301x6/x8 98/130 docid025146 rev 1 6 bits 1.5 20.83 0.270 0.100 0.150 2.5 34.72 0.560 0.390 0.330 4.5 62.50 1.200 0.820 0.820 7.5 104.17 2.20 1.80 1.50 19.5 270.83 5.60 4.70 3.90 61.5 854.17 18.0 15.0 12.0 181.5 2520.83 56.0 47.0 39.0 601.5 8354.17 100.00 100.0 100.0 1. data based on characterization results, not tested in production . 2. all fast channels, expect channel on p a6. 3. channel available on p a 6. t able 63. maximum adc r ain (1) (continued) resolution sampling cycle @ 72 mhz sampling time [ns] @ 72 mhz r ain max (k ? ) fast channels (2) slow channels other channels (3) docid025146 rev 1 99/130 stm32f301x6/x8 electrical characteristics 110 t able 64. adc accuracy - limited test conditions (1)(2) symbol parameter conditions min (3) ty p max (3) unit et t otal unadjusted error adc clock freq. ? 72 mhz sampling freq. ? 5 msps v dda = 3.3 v 25c single ended fast channel 5.1 ms - 4 4.5 lsb slow channel 4.8 ms - 5.5 6 dif ferential fast channel 5.1 ms - 3.5 4 slow channel 4.8 ms - 3.5 4 eo of fset error single ended fast channel 5.1 ms - 2 2 slow channel 4.8 ms - 1.5 2 dif ferential fast channel 5.1 ms - 1.5 2 slow channel 4.8 ms - 1.5 2 eg gain error single ended fast channel 5.1 ms - 3 4 slow channel 4.8 ms - 5 5.5 dif ferential fast channel 5.1 ms - 3 3 slow channel 4.8 ms - 3 3.5 ed dif ferential linearity error single ended fast channel 5.1 ms - 1 1 slow channel 4.8 ms - 1 1 dif ferential fast channel 5.1 ms - 1 1 slow channel 4.8 ms - 1 1 el integral linearity error single ended fast channel 5.1 ms - 1.5 2 slow channel 4.8 ms - 2 3 dif ferential fast channel 5.1 ms - 1.5 1.5 slow channel 4.8 ms - 1.5 2 enob (4) ef fective number of bits single ended fast channel 5.1 ms 10.8 10.8 - bit slow channel 4.8 ms 10.8 10.8 - dif ferential fast channel 5.1 ms 1 1.2 1 1.3 - slow channel 4.8 ms 1 1.2 1 1.3 - sinad (4) signal-to- noise and distortion ratio single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - dif ferential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - electrical characteristics stm32f301x6/x8 100/130 docid025146 rev 1 snr (4) signal-to- noise ratio adc clock freq. ?? ? 72 mhz sampling freq ?? ? 5 msps v dda = 3.3 v 25c single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - dif ferential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - thd (4) t otal harmonic distortion single ended fast channel 5.1 ms - -80 -80 slow channel 4.8 ms - -78 -77 dif ferential fast channel 5.1 ms - -83 -82 slow channel 4.8 ms - -81 -80 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and ? i inj(pin) in section 6.3.14 does not af fect the adc accuracy . 3. data based on characterization results, not tested in production. 4. v alue measured with a ?0.5db full scale 50khz sine wave input signal. t able 64. adc accuracy - limited test conditions (1)(2) (continued) symbol parameter conditions min (3) ty p max (3) unit docid025146 rev 1 101/130 stm32f301x6/x8 electrical characteristics 110 l t able 65. adc accuracy (1)(2)(3) symbol parameter conditions min (4) max (4) unit et t otal unadjusted error adc clock freq. ?? ? 72 mhz, sampling freq. ?? ? 5 msps 2.0 v ?? ? v dda ?? 3.6 v single ended fast channel 5.1 ms - 6.5 lsb slow channel 4.8 ms - 6.5 dif ferential fast channel 5.1 ms - 4 slow channel 4.8 ms - 4.5 eo of fset error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3 dif ferential fast channel 5.1 ms - 2.5 slow channel 4.8 ms - 2.5 eg gain error single ended fast channel 5.1 ms - 6 slow channel 4.8 ms - 6 dif ferential fast channel 5.1 ms - 3.5 slow channel 4.8 ms - 4 ed dif ferential linearity error single ended fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 dif ferential fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 el integral linearity error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3.5 dif ferential fast channel 5.1 ms - 2 slow channel 4.8 ms - 2.5 enob (5) ef fective number of bits single ended fast channel 5.1 ms 10.4 - bits slow channel 4.8 ms 10.4 - dif ferential fast channel 5.1 ms 10.8 - slow channel 4.8 ms 10.8 - sinad (5) signal-to- noise and distortion ratio single ended fast channel 5.1 ms 64 - db slow channel 4.8 ms 63 - dif ferential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - electrical characteristics stm32f301x6/x8 102/130 docid025146 rev 1 snr (5) signal-to- noise ratio adc clock freq. ?? ? 72 mhz, sampling freq ?? ? 5 msps, 2 v ?? ? v dda ?? 3.6 v single ended fast channel 5.1 ms 64 - db slow channel 4.8 ms 64 - dif ferential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - thd (5) t otal harmonic distortion single ended fast channel 5.1 ms - -75 slow channel 4.8 ms - -75 dif ferential fast channel 5.1 ms - -79 slow channel 4.8 ms - -78 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and ? i inj(pin) in section 6.3.14 does not af fect the adc accuracy . 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization results, not tested in production. 5. v alue measured with a ?0.5db full scale 50khz sine wave input signall. t able 65. adc accuracy (1)(2)(3) (continued) symbol parameter conditions min (4) max (4) unit t able 66. adc accuracy (1)(2) symbol parameter t est conditions t yp max (3) unit et t otal unadjusted error adc freq 72 mhz sampling freq 1msps 2.4 v v dda = v ref+ 3.6 v single-ended mode fast channel 2.5 5 lsb slow channel 3.5 5 eo of fset error fast channel 1 2.5 slow channel 1.5 2.5 eg gain error fast channel 2 3 slow channel 3 4 ed dif ferential linearity error fast channel 0.7 2 slow channel 0.7 2 el integral linearity error fast channel 1 3 slow channel 1.2 3 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current.. any positive injection current within the limits specified for iinj(pin) and iinj(pin) in section 6.3.14: i/o port characteristics does not af fect the adc accuracy . 3. data based on characterization results, not tested in production. docid025146 rev 1 103/130 stm32f301x6/x8 electrical characteristics 110 figure 30. adc accuracy characteristics figure 31. t ypical connection diagram using the adc 1. refer to t able 62 for the values of r ain . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 11 . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. % / % ' , 3 " ) $ % ! , % x a m p l e o f a n a c t u a l t r a n s f e r c u r v e 4 h e i d e a l t r a n s f e r c u r v e % n d p o i n t c o r r e l a t i o n l i n e % 4 4 o t a l 5 n a d j u s t e d % r r o r m a x i m u m d e v i a t i o n b e t w e e n t h e a c t u a l a n d t h e i d e a l t r a n s f e r c u r v e s % / / f f s e t % r r o r d e v i a t i o n b e t w e e n t h e f i r s t a c t u a l t r a n s i t i o n a n d t h e f i r s t i d e a l o n e % ' ' a i n % r r o r d e v i a t i o n b e t w e e n t h e l a s t i d e a l t r a n s i t i o n a n d t h e l a s t a c t u a l o n e % $ $ i f f e r e n t i a l , i n e a r i t y % r r o r m a x i m u m d e v i a t i o n b e t w e e n a c t u a l s t e p s a n d t h e i d e a l o n e % , ) n t e g r a l , i n e a r i t y % r r o r m a x i m u m d e v i a t i o n b e t w e e n a n y a c t u a l t r a n s i t i o n a n d t h e e n d p o i n t c o r r e l a t i o n l i n e % 4 % $ % , 6 $ $ ! 6 3 3 ! 0 6 9 6 $ $ ! , 3 " ) $ % ! , 0 6 9 9 ' ' $ , 1 [ , / ? ? $ 9 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 9 7 5 $ ' & & $ ' & c j u d p o w f s u f s 4 b n q m f b o e i p m e " % $ d p o w f s u f s electrical characteristics stm32f301x6/x8 104/130 docid025146 rev 1 6.3.19 dac electrical specifications t able 67. dac characteristics symbol parameter conditions min t yp max unit v dda analog supply voltage dac output buf fer on 2.4 - 3.6 v r load (1) resistive load dac output buf fer on 5 - - k ? r o (1) output impedance dac output buf fer on - - 15 k ? c load (1) capacitive load dac output buf fer on - - 50 pf v dac_out (1) v oltage on dac_out output corresponds to 12-bit input code (0x0e0) to (0xf1c) at v dda = 3.6 v and (0x155) and (0xeab) at v dda = 2.4 v dac output buf fer on. 0.2 - v dda ? 0.2 v dac output buf fer off - 0.5 v dda - 1lsb mv i dda (3) dac dc current consumption in quiescent mode (standby mode) (2) with no load, middle code (0x800) on the input. - - 380 a with no load, worst code (0xf1c) on the input. - - 480 a dnl (3) dif ferential non linearity dif ference between two consecutive code-1lsb) given for a 10-bit input code - - 0.5 lsb given for a 12-bit input code - - 2 lsb inl (3) integral non linearity (dif ference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095) given for a 10-bit input code - - 1 lsb given for a 12-bit input code - - 4 lsb of fset (3) of fset error (dif ference between measured value at code (0x800) and the ideal value = v dda /2) - - - 10 mv given for a 10-bit input code at v dda = 3.6 v - - 3 lsb given for a 12-bit input code at v dda = 3.6 v - - 12 lsb gain error (3) gain error given for a 12-bit input code - - 0.5 % t settling (3) settling time (full scale: for a 12-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 1lsb c load ? 50 pf , r load ? 5 k ? -3 4 s update rate (3) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) c load ? 50 pf , r load ? 5 k ? - - 1 ms/s docid025146 rev 1 105/130 stm32f301x6/x8 electrical characteristics 110 figure 32. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 6.3.20 comparator characteristics t w akeup (3) w akeup time from of f state (setting the enx bit in the dac control register) c load ? 50 pf , r load ? 5 k ? - 6.5 10 s psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement c load ? 50 pf , no r load ? 5 k ??? - ?67 ?40 db 1. guaranteed by design, not tested in production. 2. quiescent mode refers to the state of the dac a keeping steady value on the output, so no dynamic consumption is involved. 3. data based on characterization results, not tested in production. t able 67. dac characteristics (continued) symbol parameter conditions min t yp max unit 5 / 2 $ ' & / 2 $ ' % x i i h u h g 1 r q e x i i h u h g ' $ & ' $ & [ b 2 8 7 % x i i h u e l w g l j l w d o w r d q d o r j f r q y h u w h u d l t able 68. comparator characteristics (1) symbol parameter conditions min. t yp. max. unit v dda analog supply voltage - 2 - 3.6 v v in comparator input voltage range -0 - v dda v bg scaler input voltage - - v refinit - v sc scaler of fset voltage - - 5 10 mv t s_sc scaler startup time from power down - - - 0.1 ms t st ar t comparator startup time v dda ? 2.7 v- - 4 s v dda ? 2.7 v - - 10 electrical characteristics stm32f301x6/x8 106/130 docid025146 rev 1 t d propagation delay for 200 mv step with 100 mv overdrive v dda ? 2.7 v - 25 28 ns ? v dda ? 2.7 v - 28 30 propagation delay for full range step with 100 mv overdrive v dda ? 2.7 v - 32 35 ? v dda ? 2.7 v - 35 40 v offset comparator of fset error v dda ? 2.7 v - ? 5 ? 10 mv ? v dda ? 2.7 v - - ? 25 v offset t otal of fset variation full temperature range - - 3 mv i dd(comp) comp current consumption - - 400 600 a 1. guaranteed by design, not tested in production. t able 68. comparator characteristics (1) (continued) symbol parameter conditions min. t yp. max. unit docid025146 rev 1 107/130 stm32f301x6/x8 electrical characteristics 110 6.3.21 operational amplifier characteristics t able 69. operational amplifier characteristics (1) symbol parameter condition min t yp max unit v dda analog supply voltage - 2.4 - 3.6 v cmir common mode input range - 0 - v dda v vi offset input of fset voltage maximum calibration range 25c, no load on output. -- 4 mv all voltage/t emp. -- 6 after of fset calibration 25c, no load on output. - - 1.6 all voltage/t emp. -- 3 ? vi offset input of fset voltage drift - - 5 - v/c i load drive current - - - 500 a iddop amp consumption no load, quiescent mode - 690 1450 a cmrr common mode rejection ratio - - 90 - db psrr power supply rejection ratio dc 73 1 17 - db gbw bandwidth - - 8.2 - mhz sr slew rate - - 4.7 - v/ s r load resistive load - 4 - - k ? c load capacitive load - - - 50 pf voh sa t high saturation voltage r load = min, input at v dda . - - 100 mv r load = 20k, input at v dda . -- 20 vol sa t low saturation voltage rload = min, input at 0v - - 100 rload = 20k, input at 0v . -- 20 ? m phase margin - - 62 - t offtrim of fset trim time: during calibration, minimum time needed between two steps to have 1 mv accuracy -- - 2 ms t w akeup w ake up time from off state. c load ?? 50 pf, r load ? 4 k ??? follower configuration - 2.8 5 s t s_op am_vout adc sampling time when reading the op amp output 400 - - ns electrical characteristics stm32f301x6/x8 108/130 docid025146 rev 1 pga gain non inverting gain value - -2 - -4 - -8 - -1 6 - r network r2/r1 internal resistance values in pga mode (2) gain=2 - 5.4/5.4 - k ? gain=4 - 16.2/5.4 - gain=8 - 37.8/5.4 - gain=16 - 40.5/2.7 - pga gain error pga gain error - -1% - 1% i bias op amp input bias current - - - ? 0.2 (3) a pga bw pga bandwidth for dif ferent non inverting gain pga gain = 2, cload = 50pf , rload = 4 k ? -4 - mhz pga gain = 4, cload = 50pf , rload = 4 k ? -2 - pga gain = 8, cload = 50pf , rload = 4 k ? -1 - pga gain = 16, cload = 50pf , rload = 4 k ? - 0.5 - en v oltage noise density @ 1khz, output loaded with 4 k ? - 109 - @ 10khz, output loaded with 4 k ? -4 3 - 1. guaranteed by design, not tested in production. 2. r2 is the internal resistance between op amp output and op amp inverting input. r1 is the internal resistance between op amp inverting input and ground. the pga gain =1+r2/r1 3. mostly tt a i/o leakage, when used in analog mode. t able 69. operational amplifier characteristics (1) (continued) symbol parameter condition min t yp max unit nv hz ----------- docid025146 rev 1 109/130 stm32f301x6/x8 electrical characteristics 110 figure 33. opamp voltage noise versus frequency electrical characteristics stm32f301x6/x8 110/130 docid025146 rev 1 6.3.22 t emperature sensor characteristics 6.3.23 v ba t monitoring characteristics t able 70. ts characteristics symbol parameter min t yp max unit t l (1) 1. guaranteed by design, not tested in production. v sense linearity with temperature - ? 1 ? 2 c a vg_slope (1) a verage slope 4.0 4.3 4.6 mv/c v 25 v oltage at 25 c 1.34 1.43 1.52 v t st ar t (1) startup time 4 - 10 s t s_temp (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 2.2 - - s t able 71. t emperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at temperature of 1 10 c v dda = 3.3 v 0x1fff f7c2 - 0x1fff f7c3 t able 72. v ba t monitoring characteristics symbol parameter min t yp max unit r resistor bridge for v ba t -5 0- k ? q ratio on v ba t measurement - 2 - er (1) 1. guaranteed by design, not tested in production. error on q -1 - +1 % t s_vbat (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the v ba t 1mv accuracy 2.2 - - s docid025146 rev 1 111/130 stm32f301x6/x8 package characteristics 127 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www .st.com . ecopack ? is an st trademark. package characteristics stm32f301x6/x8 112/130 docid025146 rev 1 figure 34. wlcsp49 wafer level chip size package 1. primary datum z and seating plane are defined by the spherical crowns of the bump. 2. bump position designation per jesd 95-1, spp-010. % r w w r p y l h z % x p s v l g h 6 l g h y l h z ) u r q w y l h z 7 r s y l h z : d i h u e d f n v l g h $ e d o o o r f d w l r q h ) * h h h ( ' $ $ ' h w d l o $ $ e e e = ' h w d l o $ u r w d w h g 6 h d w l q j s o d q h 1 r w h 1 r w h % x p s [ h h h = 2 u l h q w d w l r q u h i h u h q f h $ [ ' ( $ $ e $ ; - b 0 ( b 9 $ docid025146 rev 1 113/130 stm32f301x6/x8 package characteristics 127 t able 73. wlcsp49 wafer level chip size package mechanical data (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. symbol millimeters inches min t yp max min t yp max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 0.175 0.0069 a2 0.380 0.0150 a3 (2) 2. back side coating 0.025 0.0010 b (3) 3. dimension is measured at the maximum bump diameter parallel to primary datum z. 0.220 0.250 0.280 0.0087 0.0098 0.01 10 d 3.382 3.417 3.452 0.1331 0.1345 0.1359 e 3.1 16 3.151 3.186 0.1227 0.1241 0.1254 e 0.400 0.0157 e1 2.400 0.0945 e2 2.400 0.0945 f 0.508 0.200 g 0.375 0.148 aaa 0.100 1.9291 bbb 0.100 0.0039 ccc 0.100 0.0039 ddd 0.050 0.0020 eee 0.050 0.0020 n number of pins 49 package characteristics stm32f301x6/x8 114/130 docid025146 rev 1 marking of engineering samples the following figure shows the engineering sample marking for the wlcsp49 package. only the information field containing the engineering sample marking is shown. figure 35. wlcsp49 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. 0 6 9 ( 6 ( q j l q h h u l q j v d p s o h p d u n l q j docid025146 rev 1 115/130 stm32f301x6/x8 package characteristics 127 figure 36. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline 1. drawing is not to scale. ! ! ! 3 % ! 4 ) . ' 0 , ! . % c c c # b # c ! , , + ' ! 5 ' % 0 , ! . % m m ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . $ $ $ e % % % 7 ? - % ? 6 package characteristics stm32f301x6/x8 116/130 docid025146 rev 1 figure 37. lqfp64 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. t able 74. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data symbol millimeters inches (1) 1. v alues in inches are converted from mm and rounded to 4 decimal digits. min t yp max min t yp max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 1 1.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d. 7.500 e 1 1.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.00 10.200 0.3858 0.3937 0.4016 e 0.500 0.0197 k 0 3.5 7 0 3.5 7 l 0.450 0.600 0.75 0.0177 0.0236 0.0295 l1 1.000 0.0394 ccc 0.080 0.0031 a i docid025146 rev 1 117/130 stm32f301x6/x8 package characteristics 127 marking of engineering samples the following figure shows the engineering sample marking for the lqfp64 package. only the information field containing the engineering sample marking is shown. figure 38. lqfp64 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. 0 6 9 ( 6 ( q j l q h h u l q j v d p s o h p d u n l q j package characteristics stm32f301x6/x8 118/130 docid025146 rev 1 figure 39. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package outline 1. drawing is not to scale. " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + docid025146 rev 1 119/130 stm32f301x6/x8 package characteristics 127 t able 75. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package mechanical data symbol millimeters inches (1) 1. v alues in inches are converted from mm and rounded to 4 decimal digits. min t yp max min t yp max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.500 0.2165 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.500 0.2165 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0 3.5 7 0 3.5 7 ccc 0.080 0.0031 package characteristics stm32f301x6/x8 120/130 docid025146 rev 1 figure 40. lqfp48 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. a i c docid025146 rev 1 121/130 stm32f301x6/x8 package characteristics 127 marking of engineering samples the following figure shows the engineering sample marking for the lqfp48 package. only the information field containing the engineering sample marking is shown. figure 41. lqfp48 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. 0 6 9 ( 6 ( q j l q h h u l q j v d p s o h p d u n l q j package characteristics stm32f301x6/x8 122/130 docid025146 rev 1 figure 42. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) 1. drawing is not to scale. t able 76. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data symbol millimeters inches (1) 1. v alues in inches are converted from mm and rounded to 4 decimal digits. t yp min max t yp min max a 0.550 0.500 0.600 0.0217 0.0197 0.0236 a1 0.020 0.000 0.050 0.0008 0.0000 0.0020 a3 0.200 0.0079 b 0.250 0.180 0.300 0.0098 0.0071 0.01 18 d 5.000 4.850 5.150 0.1969 0.1909 0.2028 d2 3.450 3.200 3.700 0.1358 0.1260 0.1457 e 5.000 4.850 5.150 0.1969 0.1909 0.2028 e2 3.450 3.200 3.700 0.1358 0.1260 0.1457 e 0.500 0.0197 l 0.400 0.300 0.500 0.0157 0.01 18 0.0197 ddd 0.080 0.0031 ! " ? - % ? 6 docid025146 rev 1 123/130 stm32f301x6/x8 package characteristics 127 figure 43. ufqfpn32 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. a0b8_fp_v2 5.30 3.80 0.60 3.45 0.50 3.45 3.80 0.75 3.80 0.30 5.30 package characteristics stm32f301x6/x8 124/130 docid025146 rev 1 marking of engineering samples the following figure shows the engineering sample marking for the ufqfpn32 package. only the information field containing the engineering sample marking is shown. figure 44. ufqfpn32 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. 0 6 9 ( 6 ( q j l q h h u l q j v d p s o h p d u n l q j docid025146 rev 1 125/130 stm32f301x6/x8 package characteristics 127 7.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in t able 22: general operating conditions . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ? ja ) where: ? t a max is the maximum ambient temperature in c, ?? ja is the package junction-to-ambient thermal resistance, in ? c/w , ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = ?? (v ol i ol ) + ? ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org t able 77. package thermal characteristics symbol parameter v alue unit ? ja thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 45 c/w thermal resistance junction-ambient lqfp48 - 7 7 mm 55 thermal resistance junction-ambient wcsp49 - 3.4 x 3.4 mm 49 thermal resistance junction-ambient ufqfn32 - 5 x 5 mm 37 package characteristics stm32f301x6/x8 126/130 docid025146 rev 1 7.2.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in chapter 8: part numbering . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. as applications do not commonly use the stm32f301x6/x8 at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. the following examples show how to calculate the temperature range needed for a given application. example 1: high-performance application assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v , maximum 3 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 2 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 3 8 ma 0.4 v + 2 20 ma 1.3 v = 61.6 mw this gives: p intmax = 175 mw and p iomax = 61.6 mw : p dmax = 175 + 61.6 = 236.6 mw thus: p dmax = 236.6 mw using the values obtained in t able 77 t jmax is calculated as follows: ? for lqfp64, 45c/w t jmax = 82 c + (45c/w 236.6 mw) = 82 c + 10.65 c = 92.65 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suf fix 6 (see chapter 8: part numbering ). docid025146 rev 1 127/130 stm32f301x6/x8 package characteristics 127 example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following application conditions: maximum ambient temperature t amax = 1 15 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v , maximum 9 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 9 8 ma 0.4 v = 28.8 mw this gives: p intmax = 70 mw and p iomax = 28.8 mw : p dmax = 70 + 28.8 = 98.8 mw thus: p dmax = 98.8 mw using the values obtained in t able 77 t jmax is calculated as follows: ? for lqfp100, 45c/w t jmax = 115 c + (45c/w 98.8 mw) = 115 c + 4.44 c = 119.44 c this is within the range of the suffix 7 version parts (?40 < t j < 125 c). in this case, parts must be ordered at least with the temperature range suf fix 7 (see chapter 8: part numbering ). part numbering stm32f301x6/x8 128/130 docid025146 rev 1 8 part numbering t able 78. ordering information scheme example: stm32 f 301 r 8 t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 301 = stm32f301xx, 2.0 to 3.6 v operating voltage pin count k = 32 pins c = 48 or 49 pins r = 64 pins flash memory size 6 = 32 kbytes of flash memory 8 = 64 kbytes of flash memory package t = lqfp y= wlcsp u= ufqfpn t emperature range 6 = industrial temperature range, ?40 to 85 c 7 = industrial temperature range, ?40 to 105 c options xxx = programmed parts tr = tape and reel docid025146 rev 1 129/130 stm32f301x6/x8 revision history 129 9 revision history t able 79. document revision history date revision changes 10-apr-2014 1 initial release. stm32f301x6/x8 130/130 docid025146 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. a ll st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? 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