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1 HD66113T (120-channel common driver packaged in a slim tape carrier package) ade-207-281(z) '99.9 rev. 0.0 description the HD66113T is a common driver for large dot matrix liquid crystal graphics displays. it features 120 channels which can be divided into two groups of 60 channels by selecting data input/output pins. the driver is powered by about 3v, making it suitable for the design of portable equipment which fully utilizes the low power dissipation of liquid crystal elements. the HD66113T, packaged in a slim tape carrier package (slim-tcp), makes it possible to reduce the size of the user area (wiring area). features duty cycle: about 1/100 to 1/480 120 lcd drive circuits high lcd driving voltage: 14v to 40v output division function (2 60-channel outputs) display off function operating voltage: 2.5v to 5.5v slim-tcp low output impedance: 0.7 k w (typ) ordering information type no. outer lead pitch ( m m) HD66113Ta0 190 HD66113Ta1 240 note: the details of tcp pattern are shown in ?he information of tcp.
HD66113T 2 pin arrangement 121 140 top view 1 2 x1 x2 x119 x120 119 120 note: this figure does not specify the tape carrier package dimensions. pin assignments vlcd2 v6r v5r v cc dio2 cl di ch shl dispoff m dio1 gnd v2l v5l v6l v1l vlcd1 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 v1r v2r
HD66113T 3 pin descriptions symbol pin no. pin name input/output classification vlcd1, 2 140, 121 vlcd power supply v cc 126 v cc power supply gnd 135 gnd power supply v1l, v1r 139, 122 v1 input power supply v2l, v2r 136, 125 v2 input power supply v5l, v5r 137, 124 v5 input power supply v6l, v6r 138, 123 v6 input power supply cl 128 clock input control signal m 133 m input control signal ch 130 ch input control signal shl 131 shift left input control signal dio1 134 data input/output control signal dio2 127 data input/output control signal di 129 data input control signal dispoff 132 display off input control signal x1?120 1?20 x1?120 output lcd drive output
HD66113T 4 pin functions power supply v cc , gnd: supply power to the internal logic circuits. vlcd, gnd: supply power to the lcd drive circuits (figure 1). v1l, v1r, v2l, v2r, v5l, v5r, v6l, v6r: supply different power levels to drive the lcd. v1 and v2 are selected levels, and v5 and v6 are non-selected levels. control signals cl: inputs data shift clock pulses for the shift register. at the falling edge of each cl pulse, the shift register shifts data input via the dio pins. m: changes the lcd drive outputs to ac. ch: selects the data shift mode. (ch = high: 2 60-output mode, ch = low: 120-output mode) shl: selects the data shift direction for the shift register and the common signal scan direction (figure 2). dio1, dio2: input or output data. dio1 is input and dio2 is output when shl is high. dio1 is output and dio2 is input when shl is low. di: input data. di is input to x61?120 when ch and shl are high, and to x60?1 when shl is low. dispoff : controls lcd output level. a low dispoff sets the lcd drive outputs x1?120 to the v2 level. a high dispoff is normally used. lcd drive outputs x1?120: each x outputs one of four voltage levels v1, v2, v5, or v6, depending on the combination of the m signal and the data level (figure 3).
HD66113T 5 gnd v cc vlcd1, 2 figure 1 power supply for lcd driver shift to right dio1 ? sr1 ? sr2 ? sr3 ?? ? sr120 ? dio2 high low data shift direction shl shift to left dio2 ? sr120 ? sr119 ?? ? sr1 ? dio1 note: sr1 to sr120 correspond to the outputs of x1 to x120, respectively. figure 2 selection of data shift direction and common signal scan direction by shl v2 v6 v1 v5 m data 10 11 00 x output level figure 3 selection of lcd drive output level
HD66113T 6 block diagram lcd drive circuit shift register x1?120 m dispoff cl v1r, v2r, v5r, v6r shl di ch v1l, v2l, v5l, v6l v cc gnd1, 2 vlcd1, 2 dio1 dio2 logic logic logic sr1 q d q d sr60 sr61 q d q d sr 120 level shifter ?????? ?????? shift register
HD66113T 7 block functions lcd drive circuit the 120-bit lcd drive circuit generates four voltage levels v1, v2, v5, and v6, which drive the lcd panel. one of these four levels is output to the corresponding x pin, depending on the combination of the m signal and the data in the shift register. level shifter the level shifter changes logic control signals (2.5 v?.5 v) into high-voltage signals for the lcd drive circuit. shift register the 120-bit shift register shifts the data input via the dio pin by one bit at a time. the one bit of shifted- out data is output from the dio pin to the next driver ic. both actions occur simultaneously at the falling edge of each shift clock (cl) pulse. the shl pin selects the data shift direction.
HD66113T 8 absolute maximum ratings item symbol rating unit notes power supply voltage for logic circuits v cc ?.3 to +7.0 v 1, 5 power supply voltage for lcd drive circuits vlcd ?.3 to +42 v 1, 5 input voltage 1 vt1 ?.3 to v cc + 0.3 v 1, 2 input voltage 2 vt2 ?.3 to vlcd + 0.3 v 1, 3 input voltage 3 vt3 ?.3 to +7.0 v 1, 4 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +110 c notes: 1. the reference point is gnd (0v). 2. applies to pins cl, m, shl, di, dispoff , and ch. 3. applies to pins v1 and v6. 4. applies to pins v2 and v5. 5. power should be applied to v cc ?nd first, and then vlcd?nd. it should be disconnected in the reverse order. 6. if the lsi is used beyond its absolute maximum ratings, it may be permanently damaged. it should always be used within its specified operating range in order to prevent malfunctions or loss of reliability.
HD66113T 9 electrical characteristics dc characteristics (v cc = 2.5v to 5.5v, gnd = 0v, and t a = ?0 c to +75 c, unless otherwise stated) item symbol pins min typ max unit test condition notes input high voltage vih 1 0.8 v cc ? cc v input low voltage vil 1 0 0.2 v cc v output high voltage voh 2 v cc ?0.4 v i oh = ?.4 ma output low voltage vol 2 0.4 v i ol = 0.4 ma vi?j on resistance r on 3 0.7 1.0 k w i on = 150 ma 1 input leakage current 1 i il1 15 5 m a vin = v cc to gnd input leakage current 2 i il2 4 ?5 25 m a vin = vlcd to gnd current consumption 1 i gnd 0.5 ma f cl = 36 khz f m = 75 khz 2 current consumption 2 i lcd 1.0 ma note: pins: 1. cl, m, shl, ch, di, dio1, dio2, dispoff 2. dio1, dio2 3. x1?120, v 4. v1, v2, v5, v6
HD66113T 10 notes: 1. indicates the resistance between one of the pins x1?120 and one of the voltage supply pins v1, v2, v5, or v6, when load current is applied to the x pin; defined under the following conditions: vlcd?nd = 40v v1, v6 = v cc ?{1/20 (vlcd?nd)} v5, v2 = gnd + {1/20 (vlcd?nd)} all voltages must be within d v, vlcd 3 v1 3 v6 3 vlcd ?7.0v, and 7.0v 3 v5 3 v2 3 gnd. note that d v depends on the power supply voltage vlcd?nd (figure 5). 2. input and output currents are excluded. when a cmos input is left floating, excess current flows from the power supply through the input circuit. to avoid this, vih and vil must be held at v cc and gnd, respectively. v1 v6 v5 v2 gnd d v d v vlcd figure 4 relation between driver output waveform and voltage levels 14 40 6.4 2.3 vlcd?nd (v) d v (v) voltage level range figure 5 relation between vlcd?nd and d v
HD66113T 11 ac characteristics (v cc = 2.5v to 5.5v, gnd = 0v, and t a = ?0 c to +75 c, unless otherwise stated) item symbol pins min max unit notes clock cycle time t cyc cl 400 ns clock high-level width t cwh cl 30 ns clock low-level width t cwl cl 370 ns clock rise time t r cl 30 ns 1 clock fall time t f cl 30 ns 1 data setup time t ds di, dio1, dio2, cl 100 ns data hold time t dh di, dio1, dio2, cl 30 ns data output delay time t dd dio1, dio2, cl 350 ns 2 m phase difference t m m, cl ?00 300 ns output delay time 1 t pd1 x (n), cl 1.2 m s3 output delay time 2 t pd2 x (n), m 1.2 m s3 ac characteristics (v cc = 5.0 v 10%, gnd = 0 v, and t a = ?0 c to +75 c, unless otherwise stated) item symbol pins min max unit notes clock cycle time t cyc cl 400 ns clock high-level width t cwh cl 30 ns clock low-level width t cwl cl 370 ns clock rise time t r cl 30 ns 1 clock fall time t f cl 30 ns 1 data setup time t ds di, dio1, dio2, cl 100 ns data hold time t dh di, dio1, dio2, cl 30 ns data output delay time t dd dio1, dio2, cl 150 ns 2 m phase difference t m m, cl ?00 300 ns output delay time 1 t pd1 x (n), cl 0.7 m s3 output delay time 2 t pd2 x (n), m 0.7 m s3 notes: 1. t r , t f < (t cyc ?t cwh ?t cwl )/2 and t r , t f 30 ns 2, 3 the load circuit shown in figure 6 is connected.
HD66113T 12 test point * 2: 30 pf * 3: 100 pf figure 6 load circuit cl t dd t cwl t cwh t cyc t ds t dh dio1, dio2/ di (input) dio1, dio2 (output) t f t r 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t m t pd1 t pd2 m x (n) 0.8 v cc 0.2 v cc figure 7 lcd controller interface timing
HD66113T 13 operation timing (1/240 duty cycle) 240 1 2 3 120 121 122 123 240 1 2 3 120 121 122 123 240 1 2 3 v6 v2 v2 v6 v6 v5 v1 v1 v5 v5 v1 v2 v6 v5 v6 v2 v2 v6 v5 v5 v6 v6 v6 v1 v1 v1 v5 v5 v5 v2 v2 v2 v6 v6 v6 v5 v5 v1 v5 m dio (input) cl x1 (com 1) x2 (com 2) x120 (com 120) dio (output) x1 (com 121) x2 (com 122) x120 (com 240) from lcd controller hd66113 no. 1 hd66113 no. 2 1 frame 1 frame
HD66113T 14 connection examples figures 8 and 9 show examples of how HD66113Ts can be configured to drive a 600-line lcd panel with a 1/300 duty cycle. figures 10 and 11 show examples of how HD66113Ts can be configured to drive a 240-line lcd panel with a 1/240 duty cycle. the HD66113T? 120 channels can be divided into two groups of 60 channels, and its data shift direction can be changed by selecting the data output mode pin (ch) and data shift pin (shl), respectively. ? ? x1 x120 dio1 dio2 ic1 (shl = high, ch = low) data (data of lines 1 to 300) ic2 (shl = high, ch = low) ic3 (shl = high, ch = high) ic4 (shl = high, ch = low) ic5 (shl = high, ch = low) ? ? x1 x120 dio1 dio2 ? ? x1 x120 dio1 dio2 ? ? x1 x120 dio1 dio2 ? ? x1 x120 dio1 dio2 di x60 x61 ? ? lcd panel line 1 line 120 line 121 line 240 line 241 line 301 line 300 line 360 line 361 line 480 line 481 line 600 ? ? segment driver data (data of lines 301 to 600) figure 8 dual-screen configuration of a 600-line lcd panel with a 1/300 duty cycle (1)
HD66113T 15 ? ? x1 x120 dio1 dio2 ic1 (shl = low, ch = low) data (data of lines 1 to 300) ic2 (shl = low, ch = low) ic3 (shl = low, ch = high) ic4 (shl = low, ch = low) ic5 (shl = low, ch = low) ? ? x1 x120 dio1 dio2 ? ? x1 x120 dio1 dio2 ? ? x1 x120 dio1 dio2 ? ? x1 x120 dio1 dio2 di x60 x61 ? ? lcd panel line 1 line 120 line 121 line 240 line 241 line 301 line 300 line 360 line 361 line 480 line 481 line 600 ? ? segment driver data (data of lines 301 to 600) figure 9 dual-screen configuration of a 600-line lcd panel with a 1/300 duty cycle (2)
HD66113T 16 ? ? x1 x120 dio1 dio2 ic1 (shl = high, ch = low) data (data of lines 1 to 240) ic2 (shl = high, ch = low) lcd panel line 1 ? ? x1 x120 dio1 dio2 line 120 line 121 line 240 ? ? segment driver figure 10 single-screen configuration of a 240-line lcd panel with a 1/240 duty cycle (1)
HD66113T 17 ? ? x1 x120 dio1 dio2 ic1 (shl = low, ch = low) ic2 (shl = low, ch = low) lcd panel line 1 ? ? x1 x120 dio1 dio2 line 120 line 121 line 240 ? ? segment driver data (data of lines 1 to 240) figure 11 single-screen configuration of a 240-line lcd panel with a 1/240 duty cycle (2)
HD66113T 18 notes on power-on/off of the lcd driver to prevent an lcd driver display error at power on/off, the sequence for power-on signal activation must be as follows (see figure 12): 2.7v v cc vlcd disp 0ms 0ms 0ms 0ms 2.7v input signals such as cl1, cl2, and data signal non-fixed period initializing period (1frame or longer) figure 12 sequence of power-on/off at power on (1) power on v cc . at this time, input 0 to the disp pin. (2) display-off function forces the lcd driver to output a v2 level (lowest level). (3) display-off function takes priority even if the input signal status becomes irregular immediately after v cc power-on. (4) input the specified signals to initialize registers of the lcd driver. its period must be 1 frame or longer. (5) set the disp level to 1 to cancel display-off function after steps (1) to (4). at this time, vlcd and each v pin input must be at the specified levels.
HD66113T 19 at power off basically, the power-off procedure is the reverse of the power-on procedure. (1) set the disp level to 0. (2) lower lcd driver power supply to 0v (3) lower v cc and each input signals to 0v at this time, each v pin input must be at 0v. display-off function stops when v cc falls to 0v, and therefore, the lcd driver may output a level other than v2 (lowest level). as a result, a display error may be caused at power-off or power-on.
HD66113T 20 lcd driver lsi power supply pin connection a feature of the lcd driver is the lcd drive power supply. as the number of pixel drives per lsi increases, so does the voltage and number of outputs. consequently, if multi-output cmos circuits are switched simultaneously, a wiring voltage drop may occurs due to transient currents, and the potential between the lcd drive circuit power supply (v lcd ) and lcd drive level power supplies (v1, v6, and v3) or gnd and the lcd level power supplies (v2, v5, and v4) may be inverted, resulting in latchup breakdown. to prevent this, it is recommended that, when designing the lcd drive power supply and board power supply wiring, the power supply wiring be designed as low-impedance and capacitors be inserted in the wiring between v lcd and v1, v3, v6, and between v2, v4, v5 and gnd. in set evaluation, it is recommended that a check be carried out to confirm that there is no inversion of the lcd drive power supply and level power supplies in the period between when the lcd drive power supply is turned on and turned off. example of capacitor insertion (when v lcd = v1 and gnd = v2) + + + + + + v lcd , v1 pins (com, seg) gnd, v2 pins (com, seg) v6 pin (com) v5 pin (com) v3 pin (seg) electrolytic capacitor ceramic capacitor v4 pin (seg) figure 13 example of capacitor insertion
HD66113T 21 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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