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datashee t product structure: silicon monolithic integrated circuit this product has no designed protec tion against radioactive rays 1/37 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev.001 www.rohm.com tsz22111 ? 14? 001 real-time clock (rtc) series i 2 c bus serial interface rtc with high-precision oscillation adjustment BU9873 outline the BU9873 is a cmos real-time clock, which has a built-in interrupt generation function. this product is connected to the cpu via i 2 c interface, and configured to perform serial transmission of time and calendar data to the cpu. a high-precision osc illation adjustment circuit is also integrated, which is capable of adjusting time counts with digital method, and correcting deviations in the oscillation frequency of the crystal oscillator. features connected to the cpu via i 2 c interface time (hour ? minute ? second, selectable 12-hour and 24-hour mode setting) calendar (year ?month ?day ? week) periodic interrupt function (output from intrb, ranging from 1 second to 1 month) alarm interrupt function (day-of-week ? hour ? minute in setting format, output from intrb) oscillation halt sensing function 32.768 khz clock output (output from 32kout with control pin) 30 second adjustment function automatic leap year recognition up to the year 2099 built-in oscillation stabilizing capacitors (c g , c d ) high-precision oscillation adjustment circuit important characteristics time keeping voltage 1.45v to 5.5v time keeping current 1 0.4a (typ) (v dd =3v, ta=+25c) time keeping current 2 1.0a (max) (v dd =3v, ta=-40c to +85c) power supply voltage 1.8v to 5.5v access frequency 1 100khz (max) (v dd =1.8v to 2.5v) access frequency 2 400khz (max) (v dd =2.5v to 5.5v) package w (typ) x d (typ) x h (max) v son008x2030 2.00mm x 3.00mm x 0.60mm tssop-b8 3.00mm x 6.40mm x 1.20mm sop8 5.00mm x 6.20mm x 1.71mm sop- j8 4.90mm x 6.00mm x 1.65mm msop8 2.90mm x 4.00mm x 0.90mm http://
datasheet datasheet 2/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 typical application circuit figure 1. typical application circuit (with primary battery) figure 2. typical application circuit (with secondary battery) http:// datasheet datasheet 3/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 pin configuration (top view) pin description pin no. symbol inpu t/output function 1 32kout output the 32kout pin is used to output 32.768 khz clock pulses, which is controlled by an internal register. this pin is enabled during power-on from 0v, and is cmos push-pull output. 2 scl input the scl pin is used to input clock pulses synchronizing the input/output data from sda pin. 3 sda input/output the sda pin is used to input and output data for writing and reading, which is synchronized with scl pin. this pin is n-channel open drain output. 4 vss - the vss pin is grounded. 5 intrb output the intrb pin is used to output periodic interrupt, or alarm interrupt (alarm_a, alarm_b) to the cpu. th is pin is disabled during power-on from 0v, and is also n-channel open drain output. 6 oscout - the oscin and oscout pins are used to connect the 32.768 khz crystal oscillator (beside the crystal, all other oscillation circuit components is already integrated in this ic). 7 oscin - 8 vdd - the vdd pin is connected to the power supply. figure 3. pin configuration 8 7 6 5 1 2 3 4 vdd oscin oscout intrb 32kout scl sda vss BU9873f :sop8 BU9873fj :sop-j8 BU9873fvt :tssop-b8 BU9873fvm :msop8 BU9873nux :vson008x2030 http:// datasheet datasheet 4/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 block diagram absolute maximum ratings item symbol rating unit remark supply voltage v dd 0.3 to 6.5 v power dissipation pd 0.45 (sop8) w when using above ta=25, decreased by 4.5mw/c. 0.45 (sop-j8) when using above ta=25, decreased by 4.5mw/c. 0.33 (tssop-b8) when using above ta=25, decreased by 3.3mw/c. 0.31 (msop8) when using above ta=25, decreased by 3.1mw/c. 0.30 (vson008x2030) when using above ta=25, decreased by 3.0mw/c. storage temperature ts td 55 to +125 c operating temperature topt 40 to +85 c terminal voltage D -0.3 to v dd +0.3 v the max value of terminal voltage is not over 6.5v. when the pulse width is 50ns or less, the min value of terminal voltage is not lower than -0.8v. caution: operating the ic over the absolute maximum ratings may damage the ic. in addition, it is impossible to predict all des tructive situations such as short-circuit modes, open circuit modes, etc. therefore, it is important to consider circuit protection measures, like adding a fuse, in case the ic is operated in a special mode exceeding the absolute maximum ratings recommended operating conditions item symbol rating unit supply voltage v dd 1.8 to 5.5 v timekeeping voltage (note 1) v clk 1.45 to 5.5 v input voltage v in 0 to v dd v (note1) for minimum time keeping voltage, c gout = c dout = 0 pf; quartz crystal unit: c l (load capacitor) = 6 pf to 12.5 pf, maximum value of r 1 (equivalent series resistance) = 80 k ? . figure 4. block diagram 1 2 3 4 5 6 7 8 filter filter sda control i/o control alarm_a alarm_b comp_a comp_b osc detect div intrb control osc sda scl 32kout vss vdd ocsin oscout intrb 32kout control time counter sec min hour week day month year http:// datasheet datasheet 5/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 dc characteristics item symbol pin name spec unit conditions min typ max ?h? input voltage v ih scl, sda 0.7v dd v dd +0.3 v ?l? input voltage v il scl, sda -0.3 0.3v dd v ?h? output current i oh 32kout -0.5 ma v oh =v dd -0.5v ?l? output current i ol1 intrb, 32kout 1 ma v ol1 =0.4v i ol2 sda 6 ma v ol2 =0.4v input leakage current i ilk scl -1 1 av in =5.5v or v ss , v dd =5.5v output off state leakage current i oz sda, intrb, 32kout -1 1 a v out =5.5v or v ss , v dd =5.5v standby current (time keeping current) i dd1 vdd 0.4 0.6 a v dd =3v, topt=25c, scl, sda=3v, c gout =c dout =0pf, output=open (note1) i dd2 vdd 1.0 a v dd =3v, topt=-40c to +85c, scl, sda=3v, c gout =c dout =0pf, output=open (note1) i dd3 vdd 1.35 a v dd =5.5v, topt=-40c to +85c, scl, sda=5.5v, c gout =c dout =0pf, output=open (note1) internal oscillation capacitance 1 c g oscin 10 pf internal oscillation capacitance 2 c d oscout 10 pf unless otherwise specified: vss=0v, v dd =3v, topt= ? 40c to +85c, oscillation frequency=32.768 khz (load capacitance c l =6pf, equivalent seri es resistance r 1 =20k ? ) (note 1) in this mode, 32kout is disabled and no clock is output from this pin. for time keeping current when outputting 32-khz pulse from 32kout pi n (this pin without loading), please refer to ?p.7 typical performance curves?. http:// datasheet datasheet 6/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 ac characteristics item symbol v dd 1.8v v dd 2.5v unit min typ max min typ max scl clock frequency f scl 0 100 0 400 khz scl clock ?l? time t low 4.7 1.3 s scl clock ?h? time t high 4.0 0.6 s start condition hold time t hd:sta 4.0 0.6 s stop condition setup time t su:sto 4.0 0.6 s start condition setup time t su:sta 4.7 0.6 s data setup time t su:dat 250 100 ns ?h? data hold time t hdh:dat 0 0 ns ?l? data hold time t hdl:dat 35 35 ns sda ?l? stable time after falling of scl t pl:dat 2.0 0.9 s sda off stable time after falling of scl t pz:dat 2.0 0.9 s rising time of scl and sda (input) t r 1000 300 ns falling time of scl and sda (input) t f 300 300 ns spike width that can be filtered t sp 50 50 ns unless additional specified: v ss =0v, topt= 40c to +85c (note1) not 100% tested condition input data level: v il =0.2v dd v ih =0.8v dd input data timing reference level: 0.3v dd /0.7v dd output data timing reference level: 0.3v dd /0.7v dd rise/fall time: Q 20ns figure 5. input and output timing figure 6. start and stop condition sda t su:sta t su:sto t hd:sta start bit stop bit scl sda (input) sda t hd:sta t hd:dat t su:dat t pl:dat t pz:dat t low t high t r t f scl (output) http:// datasheet datasheet 7/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 typical performance curves 0 0.2 0.4 0.6 0.8 0123456 supply voltage v dd [v] timekeeping current i dd [ua] figure 7. timekeeping current vs. supply voltage (with no 32-khz clock output, output pins open) (c gout =c dout =0pf, topt=25c) 0 1 2 3 4 01 2345 6 supply voltage v dd [v] timekeeping current i dd [ua] figure 9. timekeeping current vs. supply voltage (with 32-khz clock output, output pins open) (c gout =c dout =0pf, topt=25c) 0 0.2 0.4 0.6 0.8 1 1.2 -60 -30 0 30 60 90 120 operation te mperature topt [celsius] timekeeping current i dd [ua] figure 8. timekeeping current vs. operating temperature (with no 32-khz clock output, output pins open) (c gout =c dout =0pf, v dd =3v) 0 10 20 30 40 0 100 200 300 400 scl clock frequency [khz] c pu acc ess current i dd [ua] figure 10. cpu access current vs. scl clock frequency (with no 32-khz clock output, sda=?h?) (other pins open, c gout =c dout =0pf, topt=25c) v dd =1.5v v dd =3.0v v dd =5.8v http:// datasheet datasheet 8/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 -10 -5 0 5 10 0123456 supply voltage v dd [v] oscil lation frequ ency devi ation [ppm] figure 11. oscillation frequency deviation vs. supply voltage (v dd =3v, topt=25c as standard) -60 -40 -20 0 0 5 10 15 20 external capa citance [p f] oscil lation frequ ency devi ation [ppm] figure 13. oscillation frequency deviation vs. external c g and c d (v dd =3v, topt=25c as standard) -140 -120 -100 -80 -60 -40 -20 0 -60 -40 -20 0 20 40 60 80 100 ope ration temperature topt [celsius] oscil lation frequ ency devi ation [ppm] figure 12. oscillation frequen cy deviation vs. operating temperature (v dd =3v, topt=25c as standard) 0 100 200 300 400 500 0123456 supply voltage v dd [v] oscil lation start time [ms] figure 14. oscillation start time vs. supply voltage (topt=25c) f osc vs. c gout (c dout =0) f osc vs. c dout (c gout =0) http:// datasheet datasheet 9/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 0 10 20 30 40 00.10.20.30.40.5 v ol [v] i ol [m a] figure 15. i ol vs. v ol intrb pin (topt=25c) 0 10 20 30 40 00.10.20.30.40.5 v ol [v] i ol [m a] figure 16. i ol vs. v ol sda pin (topt=25c) v dd =1.6v v dd =3.0v v dd =5.5v v dd =1.6v v dd =3.0v v dd =5.5v http:// datasheet datasheet 10/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 function description ic function will be explained as the following sequence. 1. communication interface 2. address mapping of internal register 3. clock and calendar function 4. oscillation adjustment function with digital method 5. alarm interrupts function 6. periodic interrupt function 7. test bit 8. 30 second adjust function 9. oscillation halts sensing function 10. 32-khz clock output function http:// datasheet datasheet 11/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 1. communication interface this product can read/write data from i 2 c bus interface with 2-wires: sda (data) and scl (clock). since the output of sda pin is open-drain, data transferring between cpu with different supply voltage is possible by adopting a pull-up resistor on the circuit board. 1-1. i 2 c bus communication i 2 c bus data communication starts by a start condition input, and ends by a stop condition input. the data length is 8-bit, and acknowledges signal is always required after each byte. i 2 c bus carries out data transmission between plural devices connected by 2-wires: serial data (sda) and serial clock (scl). among these devices, there is ?master? that generates clock and control the start and end signal, and ?slave? that is controlled by unique device address. rtc is ?slave?. and the device that outputs data to bus during data transferring is called ?transmitter?, and the device that receives data is called ?receiver?. figure 17. i 2 c bus communication 1-2. start condition (start bit recognition) before executing any command, start c ondition (start bit) is necessary, where sda goes from ?h? down to ?l? when scl is ?h?. this ic always detects whether sda and scl are in start conditi on (start bit) or not, therefore, unless this condition is satisfied, no command will be executed. 1-3. stop condition (stop bit recognition) every command can be ended by stop condition (stop bit), where sda rising from ?l? to ?h? when scl is ?h?. 1-4. acknowledge (ack) signal ? this acknowledge (ack) signal is a software rule to judge whether data transfer has been executed successfully or not. for master and slave, the device (-com during inputting slave address of write command, read command, and this ic during outputting data of read command) at the transmitter side releases the bus after outputting 8-bit data. ? the device (this ic during inputting slave address of writ e command, read command, and -com during outputting data of read command) at the receiver side sets sda ?l? during the ninth clock cycle, and outputs acknowledge signal (ack) showing that it has received the 8-bit data. ? this ic outputs acknowledge signal (ack) ?l? after recognizing start condition and 8-bit slave address. ? every write action outputs acknowledge signal (ack) ?l? after receiving 8-bit data (word address and write data). ? every read action outputs 8-bit data (read data), and detects acknowledge signal (ack) ?l?. when acknowledge signal (ack) is detected, and stop condition is not sent from the master (-com) side, this ic will continue to output data. when acknowledge signal (ack) is not detected, this ic will stop data transfer, and end read ac tion after recognizing stop condition (stop bit). then, this ic will get in off-status. 89 89 89 s p condition condition ack stop ack data data address start r/w ack 1-7 sda scl 1-7 1-7 http:// datasheet datasheet 12/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 1-5. write command write command is illustrated as following: fi rstly, input start condition; then, enter the 7-bit slave address. slave address o f this ic is (0110010). thereafter, enter ?l? for the r/w DD bit, which indicates the direction of data transmission. in the next byte, input the internal address pointer (4-bit) and transmission format (4-bit) to the ic. for write operation, on ly one transmission format (0000) is available. the 3 rd byte transmits data that will be written to the address specified by the internal address pointer. internal address pointer settings will also be automatically incremented for 4byte and after. note that when the internal address pointer is fh, it will change to 0h during transmitting the next byte. example of write command (when writing to internal address eh to fh) figure 18. write command 1-6. read command this ic allows the following three methods of reading data from an internal register. 1-6-1. read from a specified internal address the first method uses data write command to specify the inte rnal address pointer and transfer format, and then repeat the start condition again. after the 7-bit slave address, enter ?h? for the r/ w bit, which indicates the direction of data transmission. in the next byte, data from the specified internal address will be output. if entering ?l? during the timing of a ck, the data from the next address will be output continuously. the read operation will not be ended until entering ?h? during the timing of ack and following a stop condition. the internal address pointer is reset to fh when a stop condition is met. therefore, this read method allows no insertion of stop condition before the end of read. example 1 of data read (when data is read from 2h to 3h) figure 19. read from a specified internal address 1 0 0 1 1 0 s t a r t s t o p slave addr ess 0 a c k sd a line 1 d7 data d0 a c k a c k r / w 1 1 0 0 0 0 0 d0 d7 data a c k internal address pointer transmission format 0 1 0 0 1 1 0 s t a r t s t o p slave address 0 a c k sda line 0 0 0 a c k a c k transmission format 0 1 0 0 0 0 1 0 1010 s t a r t d0 d7 dat a a c k d7 d0 a c k data internal address pointer slave address 1 0 r / w r / w http:// datasheet datasheet 13/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 1-6-2. fast read from a specified internal address (with changing transmission format) the second method uses data write command to specify the internal address pointer, but the transfer format is designated to be (0100). in the next byte, data from the specified internal address will be output immediately. if entering ?l? during the timing of ack, the data from the next address will be output continuously. the read operation will not be ended until entering ?h? during the timing of ack and following a stop condition. example 2 of data read (when data is read from internal addresses eh to 1h) figure 20. fast read from a specified internal address 1-6-3. read from address fh (without specifying the internal address) the third method starts with a start condition, and t hen enters the 7-bit slave address and ?h? for the r/ w bit, which indicates the direction of data transmission. in the next byte, data from address fh will be output immediately. if entering ?l? during the timing of ack, the data from the next address will be output continuously. the read operation will not be ended until entering ?h? during the timing of ack and following a stop condition since the internal address pointer is set to fh by a stop condition, this met hod is only effective when reading is started from the internal address fh. example 3 of data read (when data is read from internal addresses fh to 3h) figure 21. read from address fh 1 0 0 1 1 0 s t a r t slave address 0 a c k sda line d7 d7 data d0 d0 a c k a c k data s t o p d0 d7 data a c k d7 d7 d0 d0 a c k a c k data data 1 r / w 1 0 0 1 1 0 s t a r t slave address 0 a c k sda line 1 data 0 a c k a c k 1 1 0 0 1 0 s t o p d0 d7 dat a a c k d7 d0 a c k dat a int ernal address pointe r d7 d0 0 transmission form at r / w http:// datasheet datasheet 14/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 1-7. notes during rtc data transmission to avoid invalid read and write, two features should be noted when accessing the rtc. hold function of clock carry-up while read and write operation is executed (at the same time , rtc clock is still counting-up), this ic temporarily holds the clock carry-up from start condition to stop condition, to prevent invalid read and write. if clock carry-up happens during this period (read or write from start condition to stop condition), it will be adjusted within approx. 61 s after stop condition. automatic release function of access when 0.5 to 1.0 second elapses after start condition, any access to the rtc will be automatically terminated, to release the temporarily holding of clock carry-up, set fh to the address pointer, and access from the cpu is forced to be stopped (as long as stop condition is received, the same action will be made: automatic release function from the i 2 c bus interface). therefore, one access must be completed within 0.5 seconds. the automatic release function prevents delay in scl clock, even if scl is stopped because of system sudden failure during read operation. in addition, a second start condition (after the first start condition and ahead of the stop condition) is regarded as the ?repeated start condition?. therefore, when 0.5 to 1.0 seconds el apses after the first start condition, access to the rtc will also be released automatically. if access is tried after automatic release function is activated, no acknowledge signal will be output for writing while ffh will be output for reading. the following points should be noted during accessing the rtc. (1) no stop condition shall be generated until clock and calendar data read/write is started and completed bad example of time read (start condition) (read of seconds) (read of minutes) (stop condition) (start condition) (read of hours) (stop condition) assuming read is started at 05:59:59 p.m. and while reading seconds and minutes the time advanced to 06:00:00 p.m. during this time, second digit is hold so the read result is 05:59:59. then the ic confirms stop condition and carries second digit that is being hold and the time changes to 06:00: 00 p.m. thus, when the hour digit is read, it changes to be 6. the invalid results of 06:59:59 will be read. (2) one cycle of read/write operation shall be completed within 0.5 seconds. (3) do not send start condition within 61 s from stop condition, because the clock carry-up that is hold during i 2 c access will be adjusted within approx.61 s from stop condition. http:// datasheet datasheet 15/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 2. address mapping of internal register inte r nal address contents data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 second counter ? (note1) s 40 s 20 s 10 s 8 s 4 s 2 s 1 1 0 0 0 1 minute counter ? m 40 m 20 m 10 m 8 m 4 m 2 m 1 2 0 0 1 0 hour counter ? ? h 20 p/ab h 10 h 8 h 4 h 2 h 1 3 0 0 1 1 day-of-week counter ? ? ? ? ? w 4 w 2 w 1 4 0 1 0 0 day counter ? ? d 20 d 10 d 8 d 4 d 2 d 1 5 0 1 0 1 month counter ? ? ? mo 10 mo 8 mo 4 mo 2 mo 1 6 0 1 1 0 year counter y 80 y 40 y 20 y 10 y 8 y 4 y 2 y 1 7 0 1 1 1 time trimming register ? f 6 f 5 f 4 f 3 f 2 f 1 f 0 8 1 0 0 0 alarm_a (minute register) ? am 40 am 20 am 10 am 8 am 4 am 2 am 1 9 1 0 0 1 alarm_a (hour register) ? ? ah 20 ap/ab ah 10 ah 8 ah 4 ah 2 ah 1 a 1 0 1 0 alarm_a (day-of-week register) ? aw 6 aw 5 aw 4 aw 3 aw 2 aw 1 aw 0 b 1 0 1 1 alarm_b (minute register) ? bm 40 bm 20 bm 10 bm 8 bm 4 bm 2 bm 1 c 1 1 0 0 alarm_b (hour register) ? ? bh 20 bp/ab bh 10 bh 8 bh 4 bh 2 bh 1 d 1 1 0 1 alarm_b (day-of-week register) ? bw 6 bw 5 bw4 bw 3 bw 2 bw 1 bw 0 e 1 1 1 0 control register 1 aale bale ? ? test (note4) ct 2 ct 1 ct 0 f 1 1 1 1 control register 2 ? ? 12b/24 adj (note2) xstp (note3) clenb ctfg aafg bafg (note1) the ??? mark indicates data which can be read only and set to ?0? when it is read. (note2) for the adj/xstp bit of control register 2, adj will be set to ?1? if writing ?1?, while xstp will be set to ?0? if wr iting ?0? during normal oscillation. conversely, setting adj=0 and xstp=1 cause no event. the value of xstp bit is output when it is read. (note3) when xstp is set to ?1?, the internal register f6 to f0, ct2 to ct0, aale, bal e, clenb will be reset to ?0?. (note4) the test bit of control register 1 is for shipment test ing. please always set test = 0. if this bit is set to ?1? acci dentally, it will be reset to ?0? after stop condition is input. http:// datasheet datasheet 16/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 3. clock and calendar function the clock and calendar function is available in this ic, ranging from seconds to years (the last two digits of a year). every register is configured in bcd code, and assigned to the following address respectively. second counter (internal address 0h) minute counter (internal address 1h) hour counter (internal address 2h) day-of-week counter (internal address 3h) day counter (internal address 4h) month counter (internal address 5h) year counter (internal address 6h) 3-1. clock counter (second counter, minute counter a nd hour counter) time digit in bcd code is displayed as follows. second counter: be reset to ?00? and carried to minute digits when incremented from 59 to 00. minute counter: be reset to ?00? and carried to hour digits when incremented from 59 to 00. hour counter: be reset to ?00? and carried to day and day-of-the-week digits when incremented from 23 to 00 (in 24-hour mode). if non-existent time has been written, any carry from lower di gits may cause the time counters to malfunction. therefore, such incorrect writing should be replaced with the writing of existent time data. users can choose to display time in 12-hour mode or 24-hour mode by setting the 12b/24 bit (internal address fh). 12b/24-hour mode selection bit 12b/24 description 0 12- hour time display system (separate for morning and afternoon) 1 24- hour time display system time display table 24-hour mode 12-hour mode 24-hour mode 12-hour mode 00 01 02 03 04 05 06 07 08 09 10 11 12 (am12) 01 (am 1) 02 (am 2) 03 (am 3) 04 (am 4) 05 (am 5) 06 (am 6) 07 (am 7) 08 (am 8) 09 (am 9) 10 (am10) 11 (am11) 12 13 14 15 16 17 18 19 20 21 22 23 32 (pm12) 21 (pm 1) 22 (pm 2) 23 (pm 3) 24 (pm 4) 25 (pm 5) 26 (pm 6) 27 (pm 7) 28 (pm 8) 29 (pm 9) 30 (pm10) 31 (pm11) setting the 12-hour or 24-hour mode should precede writing time data. 3-2. day-of-week counter day-of-week digits are incremented by 1 corresponding to the 7 days of week, e.g. (w4, w2, w1) = (0, 0, 0) (0, 0, 1) ? (1, 1, 0) (0, 0, 0) the relation between the days of week and day-of-week digits is user definable. (e.g. sunday=0, 0, 0) (w4, w2, w1) should not be set to (1, 1, 1). 3-3. calendar counter (day counter , month counter and year counter) the automatic calendar function provides the calendar digit displayed in bcd code. day digits: range from 1 to 31 (for january, march, may, july, august, october, and december) range from 1 to 30 (for april, june, september, and november) range from 1 to 29 (for february in leap years) range from 1 to 28 (for february in ordinary years) carried to month digits when reset to 1 month digits: range from 1 to 12 and carried to year digits when reset to 1. year digits: range from 00 to 99 and 00, 04, 08? 92 and 96 are counted as leap years. if non-existent time has been written, any carry from lower di gits may cause the time counters to malfunction. therefore, such incorrect writing should be replaced with the writing of existent time data. http:// datasheet datasheet 17/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 3-4. automatic judgment of leap year automatic judgment function of leap year is inclu ded in this ic. leap year is defined as follows. the year that can be divided by 4 is leap year. the year that can be divided by 100 is ordinary year. the year that can be divided by 400 is leap year. for example, year 2000 is a leap year while year 2100 is ordinary year. because the year register of this ic only supports the last tw o digits, a year will be automatically recognized as a leap year if it is a multiple of 4. therefore, year 2100 or 2000 will be determined as leap year because the last two digits are ?00?. this result in automatic judgment of leap years only can be up to the year 2099 in this ic. 4. oscillation adjustment function with digital method this ic has built-in oscillation capacitance c g and c d , the oscillation circuit can be configured easily by connecting an external crystal oscillator. however, due to some variations such as parasitic capacitance, it is hardly for rtc to oscillate a t 32,768 hz exactly. therefore, if you want to achieve high-precision clock, it is necessary to use the error correction method. by using this feature, you can achieve high-precision clock with only 1.5ppm mismatch at a specified temperature. because the crystal oscillator has temperature dependency, the clock mismatch will increase when the temperature changes. the clock adjustment step is about 3ppm and the total range is 189ppm. as following, some application is possible: (1) if the temperature sensor is integrated in system, by setting the clock adjustment function in accordance with the variation of temperature, it is possible to realize high-precision clock that does not depend on the temperature. (2) by storing seasonal temperature information to the system, and using the clock adjustment function with this temperature information, the realization of high- precision clock is available throughout the year. 4-1. function description in the ic, counting up to seconds is made once per 32,768 of clock pulse generated by the oscillator. if oscillation frequency is not 32,768 hz which does not match with the number of clock counts, the time error will happen. this function is designated to compensate the clock mismatch. the adjustment function adds 2 clock pulses every 20 seconds: 2/(32,76820)=3.051ppm, which delays the clock by approx. 3ppm. likewise, decrementing 2 clock pulses advances the clock by 3ppm. thus the clock may be adjusted to the precision of 1.5ppm. and the total range is 189.2ppm (124 steps ) according to the internal 7-bit trim register. the time trimming circuit adjusts one second count based on this register when second digit is 00, 20 or 40 seconds. note that the time trimming function only adjust clock timing and oscillation frequency and 32-khz clock output is not adjusted. setting data to internal register (internal address 7h) activates the time trimming circuit. and bit f6 decides either increasing or decreasing the clock pulse. the clock counts will be increased as ((f5, f4, f3, f2, f1, f0) 1) 2 when f6 is set to ?0?. the clock counts will be decreased as ((/f 6 , /f 5 , /f 4 , /f 3 , /f 2 , /f 1 , /f 0 ) 1) 2 when f6 is set to ?1?. counts will not change when (f6, f5, f4, f3, f2, f1, f0) are set to ( , 0, 0, 0, 0, 0, ) for example, when 32.768 khz crystal is used: when (f6, f5, f4, f3, f2, f1, f0) are set to (0, 0, 0, 0, 1, 1, 1), counts will change as: 32,768 (7 1) 2=32,780 (clock will be delayed) when second digit is 00, 20 or 40. when (f6, f5, f4, f3, f2, f1, f0) are set to (0, 0, 0, 0, 0, 0, 1), counts will remain 32,768 without changing when second digit is 00, 20 or 40. when (f6, f5, f4, f3, f2, f1, f0) are set to (1, 1, 1, 1, 1, 1, 0), counts will change as: 32,768 ( 2) 2=32,764 (clock will be advanced) when second digit is 00, 20 or 40. http:// datasheet datasheet 18/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 4-2. configuration method of time adjustment time adjustment amount can be calculated following the rules below. case 1: when oscillation frequency (note1) >target frequency (note2) (clock gains) (oscillation frequency ? target frequency + 0.1) adjustment amount (note3) = -------------------------------------------------------------- oscillation frequency 3.051 10 ? 6 (oscillation frequency ? target frequency) 10 + 1 (note1) oscillation frequency : clock frequency out put from the 32kout pin at room temperature. (note2) target frequency : a frequency to be adjusted to. since temperature characteristics of a 32.768 khz crystal oscillator generally generates the highest frequency at a room temper ature, we recommend to set the target frequency to approx. 32768.00h z to 32768.10hz (+3.05ppm to 32768hz). note that this value may differ based on the environment or place where the device will be used. (note3) adjustment amount: a value to be set finally to f6 to f0 bits. this value is expressed in 7bit binary digits with sig n bit. example of calculations when oscillation frequency=32768.85 khz; target frequency=32768.05 khz oscillation adjustment value = (327 68.85 - 32768.05 + 0.1) / (32768.85 3.051 10 -6 ) (32768.85 - 32768.05) 10 + 1 = 9.001 9 in this instance, write the settings (dev, f6, f5, f4, f3, f2, f1, f0) = (0, 0, 0, 0, 1, 0, 0, 1) in the oscillation adjustment register. thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a distance from 01h. case 2: when oscillation frequency=target frequency (no clock gain or loss) (f6, f5, f4, f3, f2, f1, f0) = (*, 0, 0, 0, 0, 0, *). in this case, the correction is not performed. case 3: when oscillation frequency datasheet datasheet 20/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 5-2. alarm interrupt output alarm interrupt output is from intrb pin and the outputting is ?l?. in addition, by monitoring the value of aafg, bafg bits (internal address fh), the state of alarm can be checked. alarm_a (alarm_b) flag bit aafg, bafg description 0 unmatched alarm register with clock counter default 1 matched alarm register with clock counter the flag bit turns to ?1? and intrb is ?l? when matched time is sensed for each alarm. the aafg, bafg bit may be set only to ?0?. setting this bit to?0? sets the intrb to off status (?h?). when this bit is set to?1 ? nothing happens. when the aale, bale bit is set to?0?, alarm operation is disabled and ?0?is read from the aafg, bafg bit. output timing between aafg, bafg bit and intrb a afg bafg bit intrb pin matched alarm time setting of the aafg bafg matched alarm time matched alarm time setting of the aafg bafg figure 22. output timing between aafg (bafg) bit and intrb if time matching happened, aafg (bafg) bit will be kept high until it is set to ?0?. figure 23. output timing between aale (bale) bit, aafg (bafg) bit and intrb intrb intrb alarm-calendar coincidence period (1 min.) aale1 bale) aale0 bale aale0 bale aale1 bale aafg0 bafg a aale1 bale day-of-the- week, time matched day-of-the- week, time matched day-of-the- week, time matched day-of-the- week, time matched http:// datasheet datasheet 21/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 5-3. intrb output control alarm interrupt and periodic interrupt are both outputted from intrb pin, so there are totally three types of signal from this pin. if more than one signal is triggered at the same time, the output becomes a nor waveform of these signals. example: when alarm_a and alarm_b are output from the intrb pin figure 24. intrb output control by checking the flag bit, which interrupt outputted from intrb pin can be distinguished. flag bit enable bit alarm_a aafg (d1 at fh) aale (d7 at eh) alarm_b bafg (d0 at fh) bale (d6 at eh) periodic interrupt ctfg (d2 at fh) disabled at ct2=ct1=ct0=0 (d2 to d0 at eh) intrb bafg aafg http:// datasheet datasheet 22/37 BU9873 tsz02201-0919agz00010-1-2 ? 2013 rohm co., ltd. all rights reserved. 13.sep.2013 rev. 001 www.rohm.com tsz22111 ? 15? 001 6. periodic interrupt function the BU9873 can output periodic interrupt pulses in addition to alarm function from the intrb pin. output wave form for periodic interrupt may be selected from regular pulse waveform (2hz and 1hz) and waveforms (every second, every minute, every hour and every month) that are appropriate for cpu level interrupt. the condition of periodic interrupt signals can be monitored with using a polling function. 6-1. usage of periodic interrupt function periodic interrupt function selection with setting value to register (internal address eh) ct2 ct1 ct0 description wave from mode cycle and falling timing 0 0 0 off (default) default 0 0 1 fixed at ?l? 0 1 0 pulse mode 2hz (duty50%) 0 1 1 pulse mode 1hz (duty50%) 1 0 0 level mode every second (synchronized with second count-up) 1 0 1 level mode every minute (at 00 second of every minute) 1 1 0 level mode every hour (at 00 :00 of every hour) 1 1 1 level mode every month (1st day, 00:00:00 a.m. of every month) (1) pulse mode outputs 2hz, 1hz clock pulses (duty 50%). since counting up of second counter is delayed by approximately 92 s from the falling edge of clock pu lse, time reading immediately afte r the falling edge of clock pulse may appear to lag behind the time counts of the real-time clocks by approximately 1 second. figure 25. output timing of pulse mode (2) level mode one second, one minute or one month may be selected for an interrupt cycle. counting up of seconds is matched with falling edge of interrupt output. intrb pin will be kept ?l? until ctfg bit is set to ?0?. figure 26. output timing of level mode (3) when the time trimming circuit is used, periodic interrupt cycle changes every 20 seconds. pulse mode: ?l? duration of output of output pulses may change in the maximum rang of 3.784ms. for example, duty will be 500.3784 at 1hz. level mode: frequency in one second may change in the maximum range of 3.784ms. & |