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? freescale semiconductor, inc., 2005, 2007. all rights reserved. freescale semiconductor technical data this document is primarily concerned with the mpc7448, which is targeted at networking and computing systems applications. this document desc ribes pertinent electrical and physical characteristics of the mpc7448. for information regarding specific mpc7448 part numbers covered by this document and part numbers cove red by other documents, refer to section 11, ?part numbering and marking.? for functional characteristics of the processor, refer to the mpc7450 risc microprocessor family reference manual . to locate any published updates for this document, refer to the website listed on the back cover of this document. 1overview the mpc7448 is the sixth implementation of fourth- generation (g4) microprocessors from freescale. the mpc7448, built on power architecture? technology, implements the powerpc? instruction set architecture version 1.0 and is targeted at networking and computing systems applications. the mpc7448 consists of a processor core and a 1-mbyte l2. figure 1 shows a block diagram of the mpc7448. the core is a high-performance superscalar design supporting a double-precision floating-point unit and a simd multimedia unit. the memory storage subsystem supports the mpx bus protocol and a subset of the 60x bus protocol to main memory and other system resources. document number: mpc7448ec rev. 4, 3/2007 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. comparison with the mpc7447a, mpc7447, mpc7445, and mpc7441 . . . . . . . . . . . . . . . . . . . . . . 7 4. general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5. electrical and thermal characteristics . . . . . . . . . . . . 9 6. pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7. pinout listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8. package description . . . . . . . . . . . . . . . . . . . . . . . . . 29 9. system design information . . . . . . . . . . . . . . . . . . . 35 10. document revision history . . . . . . . . . . . . . . . . . . . 55 11. part numbering and marking . . . . . . . . . . . . . . . . . . 57 mpc7448 risc microprocessor hardware specifications
mpc7448 risc microprocessor hardware specifications, rev. 4 2 freescale semiconductor overview figure 1. mpc7448 block diagram + integer reservation station unit 2 + integer reservation station unit 2 additional features ? time base counter/decrementer ? clock multiplier ? jtag/cop interface ? thermal/power management ? performance monitor ? out-of-order issue of altivec instr. + + x fpscr fpscr pa + x instruction unit instruction queue (12-word) 96-bit (3 instructions) reservation integer 128-bit (4 instructions) 32-bit floating- point unit 64-bit reservation load/store unit (ea calculation) finished 32-bit (16-entry) tags 32-kbyte d cache 36-bit 64-bit integer stations (2) reservation station reservation stations (2) fpr file 16 rename buffers stations (2-entry) gpr file 16 rename buffers reservation station vr file 16 rename buffers 64-bit 128-bit 128-bit completed instruction mmu srs (shadow) 128-entry ibat array itlb tags 32-kbyte i cache stores stores load miss vector to u c h queue (3) vr issue fpr issue branch processing unit ctr lr btic (128-entry) bht (2048-entry) fetcher gpr issue (6-entry/3-issue) (4-entry/2-issue) (2-entry/1-issue) dispatch unit data mmu srs (original) 128-entry dbat array dtlb vector touch engine 32-bit ea l1 castout status l2 store queue (l2sq) vector fpu reservation station reservation station reservation station vector integer unit 1 vector integer unit 2 vector permute unit line ta g s block 0 (32-byte) status block 1 (32-byte) memory subsystem snoop push/ interventions l1 castouts bus accumulator l1 push (4) unit 2 unit 1 l1 load queue (llq) l1 load miss (5) cacheable store miss (2) instruction fetch (2) l1 service l1 store queue (lsq) system bus interface l2 prefetch (3) address bus data bus queues castout bus store queue push load queue (11) queue (5) / queue (6) 1 the castout queue and push queue share resources such for a combined total of 6 entries. the castout queue itself is limited to 5 entries, ensuring 1 entry will be available for a push. 1-mbyte unified l2 cache controller notes: completion queue completion unit completes up to three per clock instructions
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 3 features 2features this section summarizes features of the mpc7448 implementation. major features of the mpc7448 are as follows: ? high-performance, superscalar microprocessor ? up to four instructions can be fetched from the instruction cache at a time. ? up to three instructions plus a branch instruction can be dispatched to the issue queues at a time. ? up to 12 instructions can be in the instruction queue (iq). ? up to 16 instructions can be at some stage of execution simultaneously. ? single-cycle execution for most instructions ? one instruction per clock cycle throughput for most instructions ? seven-stage pipeline control ? eleven independent execution uni ts and three register files ? branch processing unit (bpu) features static and dynamic branch prediction ? 128-entry (32-set, four-way set-associative) branch target instruction cache (btic), a cache of branch instructions that have been encount ered in branch/loop code sequences. if a target instruction is in the btic, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. typically, a fetch that hits the btic provides the first four instructions in the target stream. ? 2048-entry branch history table (bht) with 2 bits per entry for four levels of prediction?not taken, strongly not ta ken, taken, and strongly taken ? up to three outstanding speculative branches ? branch instructions that do not update the count register (ctr) or link register (lr) are often removed from the instruction stream. ? eight-entry link register stack to predict the target address of branch conditional to link register ( bclr ) instructions ? four integer units (ius) that share 32 gprs for integer operands ? three identical ius (iu1a, iu1b, and iu1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions. ? iu2 executes miscellaneous instructions, including the cr logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions. ? five-stage fpu and 32-entry fpr file ? fully ieee std. 754?-1985?compliant fpu for both single- and double-precision operations ? supports non-ieee mode for time-critical operations ? hardware support for denormalized numbers ? thirty-two 64-bit fprs for single- or double-precision operands
mpc7448 risc microprocessor hardware specifications, rev. 4 4 freescale semiconductor features ? four vector units and 32-entry vector register file (vrs) ? vector permute unit (vpu) ? vector integer unit 1 (viu1) handles short-latency altivec? integer instructions, such as vector add instructions (for example, vaddsbs , vaddshs , and vaddsws ). ? vector integer unit 2 (viu2) handles longer-la tency altivec integer instructions, such as vector multiply add instructions (for example, vmhaddshs , vmhraddshs , and vmladduhm ). ? vector floating-point unit (vfpu) ? three-stage load/store unit (lsu) ? supports integer, floating-point, and vector instruction load/store traffic ? four-entry vector touch queue (vtq) supports all four architected altivec data stream operations ? three-cycle gpr and altivec load latency (byte, half word, word, vector) with one-cycle throughput ? four-cycle fpr load latency (si ngle, double) with one-cycle throughput ? no additional delay for misaligned access within double-word boundary ? a dedicated adder calculates effective addresses (eas). ? supports store gathering ? performs alignment, normalization, and precision conversion for floating-point data ? executes cache control and tlb instructions ? performs alignment, zero padding, and sign extension for integer data ? supports hits under misses (multiple outstanding misses) ? supports both big- and little-endian modes, including misaligned little-endian accesses ? three issue queues, fiq, viq, and giq, can accept as many as one, two, and three instructions, respectively, in a cycle. instruction dispatch requires the following: ? instructions can only be dispatched from the three lowest iq entries?iq0, iq1, and iq2. ? a maximum of three instructions can be di spatched to the issue queues per clock cycle. ? space must be available in the cq for an instruction to dispatch (this includes instructions that are assigned a space in the cq but not in an issue queue). ? rename buffers ? 16 gpr rename buffers ? 16 fpr rename buffers ? 16 vr rename buffers ? dispatch unit ? decode/dispatch stage fully decodes each instruction ? completion unit ? retires an instruction from the 16-entry completion queue (cq) when all instructions ahead of it have been completed, the instruction has finished executing, and no exceptions are pending ? guarantees sequential programming model (precise exception model)
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 5 features ? monitors all dispatched instructions and retires them in order ? tracks unresolved branches and flushes instructions after a mispredicted branch ? retires as many as three instructions per clock cycle ? separate on-chip l1 instruction and data caches (harvard architecture) ? 32-kbyte, eight-way set-associative instruction and data caches ? pseudo least-recently-used (plru) replacement algorithm ? 32-byte (eight-word) l1 cache block ? physically indexed/physical tags ? cache write-back or write-through operation progr ammable on a per-page or per-block basis ? instruction cache can provide four instructions per clock cycle; data cache can provide four words per clock cycle ? caches can be disabled in software. ? caches can be locked in software. ? mesi data cache coherency maintained in hardware ? separate copy of data cache tags for efficient snooping ? parity support on cache ? no snooping of instruction cache except for icbi instruction ? data cache supports altivec lru and transient instructions ? critical double- and/or quad-word forwarding is performed as needed. critical quad-word forwarding is used for altivec loads and instruction fetches. other accesses use critical double-word forwarding. ? level 2 (l2) cache interface ? on-chip, 1-mbyte, eight-way set-associative unified instruction and data cache ? cache write-back or write-through operation progr ammable on a per-page or per-block basis ? parity support on cache tags ? ecc or parity support on data ? error injection allows testing of error recovery software ? separate memory management units (mmus) for instructions and data ? 52-bit virtual address, 32- or 36-bit physical address ? address translation for 4-kbyte pages, va riable-sized blocks, and 256-mbyte segments ? memory programmable as write-back/write-thr ough, caching-inhibited/caching-allowed, and memory coherency enforced/memory coherenc y not enforced on a page or block basis ? separate ibats and dbats (eight each) also defined as sprs ? separate instruction and data translation lookaside buffers (tlbs) ? both tlbs are 128-entry, two-way set-associative and use an lru replacement algorithm. ? tlbs are hardware- or software-reloadable (tha t is, a page table search is performed in hardware or by system software on a tlb miss).
mpc7448 risc microprocessor hardware specifications, rev. 4 6 freescale semiconductor features ? efficient data flow ? although the vr/lsu interface is 128 bits, the l1/l2 bus interface allows up to 256 bits. ? the l1 data cache is fully pipelined to provide 128 bits/cycle to or from the vrs. ? the l2 cache is fully pipelined to provide 32 by tes per clock every other cycle to the l1 caches. ? as many as 16 out-of-order transactions can be present on the mpx bus. ? store merging for multiple store misses to the same line. only coherency action taken (address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed). ? three-entry finished store queue and five-ent ry completed store queue between the lsu and the l1 data cache ? separate additional queues for efficient bu ffering of outbound data (such as castouts and write-through stores) from the l1 data cache and l2 cache ? multiprocessing support features include the following: ? hardware-enforced, mesi cache coherency protocols for data cache ? load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations ? power and thermal management ? dynamic frequency switching (dfs) feature allows processor core frequency to be halved or quartered through software to reduce power consumption. ? the following three power-saving modes are available to the system: ? nap?instruction fetching is halted. only the clocks for the time base, decrementer, and jtag logic remain running. the part goes into the doze state to snoop memory operations on the bus and then back to nap using a qreq /qack processor-system handshake protocol. ? sleep?power consumption is further reduced by disabling bus snooping, leaving only the pll in a locked and running state. all internal functional units are disabled. ? deep sleep?when the part is in the sleep state, the system can disable the pll. the system can then disable the sysclk source for greater system power savings. power-on reset procedures for restarting and relocking the pll must be followed upon exiting the deep sleep state. ? instruction cache throttling provides control of instruction fetching to limit device temperature. ? a new temperature diode that can determine the temperature of the microprocessor ? performance monitor can be used to help debug system designs and improve software efficiency. ? in-system testability and debugging features through jtag boundary-scan capability ? testability ? lssd scan design ? ieee std. 1149.1? jtag interface
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 7 comparison with the mpc7447a, mpc7447, mpc7445, and mpc7441 ? reliability and serviceability ? parity checking on system bus ? parity checking on the l1 caches and l2 data tags ? ecc or parity checking on l2 data 3 comparison with the mpc7447a, mpc7447, mpc7445, and mpc7441 table 1 compares the key features of the mpc7448 with the key features of the earlier mpc7447a, mpc7447, mpc7445, and mpc7441. all are based on the mpc7450 risc microprocessor and are architecturally very similar. the mpc7448 is identical to the mpc7447a, but the mpc7448 supports 1 mbyte of l2 cache with ecc and the use of dynamic frequency switching (dfs) with more bus-to-core ratios. table 1. microarchitecture comparison microarchitectural specs mpc7448 mpc7447a mpc7447 mpc7445 mpc7441 basic pipeline functions logic inversions per cycle 18 pipeline stages up to execute 5 total pipeline stages (minimum) 7 pipeline maximum instruction throughput 3 + branch pipeline resources instruction buffer size 12 completion buffer size 16 renames (integer, float, vector) 16, 16, 16 maximum execution throughput sfx 3 vector 2 (any 2 of 4 units) scalar floating-point 1 out-of-order window size in execution queues sfx integer units 1 entry 3 queues vector units in order, 4 queues scalar floating-point unit in order branch processing resources prediction structures btic, bht, link stack btic size, associativity 128-entry, 4-way bht size 2k-entry link stack depth 8 unresolved branches supported 3 branch taken penalty (btic hit) 1 minimum misprediction penalty 6
mpc7448 risc microprocessor hardware specifications, rev. 4 8 freescale semiconductor comparison with the mpc7447a, mpc7447, mpc7445, and mpc7441 execution unit timings (latency-throughput) aligned load (integer, float, vector) 3-1, 4-1, 3-1 misaligned load (integer, float, vector) 4-2, 5-2, 4-2 l1 miss, l2 hit latency with ecc (data/instruction) 12/16 ? l1 miss, l2 hit latency without ecc (data/instruction) 11/15 9/13 sfx (add, sub, shift, rot, cmp, logicals) 1-1 integer multiply (32 8, 32 16, 32 32) 4-1, 4-1, 5-2 scalar float 5-1 vsfx (vector simple) 1-1 vcfx (vector complex) 4-1 vfpu (vector float) 4-1 vper (vector permute) 2-1 mmus tlbs (instruction and data) 128-entry, 2-way tablewalk mechanism hardware + software instruction bats/data bats 8/8 8/8 8/8 8/8 4/4 l1 i cache/d cache features size 32k/32k associativity 8-way locking granularity way parity on i cache word parity on d cache byte number of d cache misses (load/store) 5/2 5/1 data stream touch engines 4 streams on-chip cache features cache level l2 size/associativity 1-mbyte/ 8-way 512-kbyte/8-way 256-kbyte/8-way access width 256 bits number of 32-byte sectors/line 2 2 parity tag byte byte parity data byte byte data ecc 64-bit ? thermal control dynamic frequency switching divide-by-two mode yes yes no no no dynamic frequency switching divide-by-four mode yes no no no no thermal diode yes yes no no no table 1. microarchitecture comparison (continued) microarchitectural specs mpc7448 mpc7447a mpc7447 mpc7445 mpc7441
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 9 general parameters 4 general parameters the following list summarizes the general parameters of the mpc7448: technology 90 nm cmos soi, nine-layer metal die size 8.0 mm 7.3 mm transistor count 90 million logic design mixed static and dynamic packages surface mount 360 ceramic ball grid array (hcte) surface mount 360 ceramic land grid array (hcte) surface mount 360 ceramic ball grid array with lead-free spheres (hcte) core power supply 1.30 v (1700 mhz device) 1.25 v (1600 mhz device) 1.20 v (1420 mhz device) 1.15 v (1000 mhz device) i/o power supply 1.5 v, 1.8 v, or 2.5 v 5 electrical and thermal characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the mpc7448. 5.1 dc electrical characteristics the tables in this section describe the mpc7448 dc electrical characteristics. table 2 provides the absolute maximum ratings. see section 9.2, ?power suppl y design and sequencing,? for power sequencing requirements. table 2. absolute maximum ratings 1 characteristic symbol maximum value unit notes core supply voltage v dd ?0.3 to 1.4 v 2 pll supply voltage av dd ?0.3 to 1.4 v 2 processor bus supply voltage i/o voltage mode = 1.5 v ov dd ?0.3 to 1.8 v 3 i/o voltage mode = 1.8 v ?0.3 to 2.2 3 i/o voltage mode = 2.5 v ?0.3 to 3.0 3 input voltage processor bus v in ?0.3 to ov dd + 0.3 v 4 jtag signals v in ?0.3 to ov dd + 0.3 v storage temperature range t stg ? 55 to 150 ?c c notes : 1. functional and tested operating conditions are given in ta b l e 4 . absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. see section 9.2, ?power supply design and sequencing ? for power sequencing requirements. 3. bus must be configured in the corresponding i/o voltage mode; see tab le 3 . 4. caution : v in must not exceed ov dd by more than 0.3 v at any time including during power-on reset except as allowed by the overshoot specifications. v in may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 2 .
mpc7448 risc microprocessor hardware specifications, rev. 4 10 freescale semiconductor electrical and thermal characteristics figure 2 shows the undershoot and overshoot voltage on the mpc7448. figure 2. overshoot/undershoot voltage the mpc7448 provides several i/o voltages to support both compatibility with existing systems and migration to future systems. the mpc7448 core voltage must always be provided at the nominal voltage (see table 4 ). the input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal hreset . the output voltage will swing from gnd to the maximum voltage applied to the ov dd power pins. table 3 provides the input threshold voltage settings. because these settings may change in future products , it is recommended that bvsel[0:1] be configured using resistor options, jumpers, or some other flex ible means, with the capability to reconfigure the termination of this signal in the future, if necessary. table 3. input threshold voltage setting bvsel0 bvsel1 i/o voltage mode 1 notes 0 0 1.8 v 2, 3 0 1 2.5 v 2, 4 1 0 1.5 v 2 1 1 2.5 v 4 notes: 1. caution: the i/o voltage mode selected must agree with the ov dd voltages supplied. see ta b l e 4 . 2. if used, pull-down resistors should be less than 250 . 3. the pin configuration used to select 1.8v mode on the mpc7448 is not compatible with the pin configuration used to select 1.8v mode on the mpc7447a and earlier devices. 4. the pin configuration used to select 2.5v mode on the mpc7448 is fully compatible with the pin configuration used to select 2.5v mode on the mpc7447a and earlier devices. v ih gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% ov dd + 20% v il ov dd ov dd + 5% of t sysclk
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 11 electrical and thermal characteristics table 4 provides the recommended operating conditions fo r the mpc7448 part numbers described by this document; see section 11.1, ?part numbers fully addressed by this document,? for more information. see section 9.2, ?power supply design and sequencing ? for power sequencing requirements. table 4. recommended operating conditions 1 characteristic symbol recommended value unit notes 1000 mhz 1420 mhz 1600 mhz 1700 mhz min max min max min max min max core supply voltage v dd 1.15 v 50 mv 1.2 v 50 mv 1.25 v 50 mv 1.3 v +20/ ?50mv v 3, 4, 5 pll supply voltage av dd 1.15 v 50 mv 1.2 v 50 mv 1.25 v 50 mv 1.3 v +20/ ?50mv v 2, 3, 4 processor bus supply voltage i/o voltage mode = 1.5 v ov dd 1.5 v 5% 1.5 v 5% 1.5 v 5% 1.5 v 5% v 4 i/o voltage mode = 1.8 v 1.8 v 5% 1.8 v 5% 1.8 v 5% 1.8 v 5% 4 i/o voltage mode = 2.5 v 2.5 v 5% 2.5 v 5% 2.5 v 5% 2.5 v 5% 4 input voltage processor bus v in gnd ov dd gnd ov dd gnd ov dd gnd ov dd v jtag signals v in gnd ov dd gnd ov dd gnd ov dd gnd ov dd die-junction temperature t j 0 105 0 105 0 105 0 105 ?c c6 notes: 1. these are the recommended and tested operating conditions. 2. this voltage is the input to the filter discussed in section 9.2.2, ?pll power supply filtering,? and not necessarily the voltage at the av dd pin, which may be reduced from v dd by the filter. 3. some early devices supported voltage and frequency derating whereby vdd (and avdd) could be reduced to reduce power consumption. this feature has been superseded and is no longer supported. see section 5.3, ?voltage and frequency derating,? for more information. 4. caution : power sequencing requirements must be met; see section 9.2, ?power supply design and sequencing?. 5. caution : see section 9.2.3, ?transient specifications? for information regarding transients on this power supply. 6. for information on extended temperature devices, see section 11.2, ?part numbers not fully addressed by this document.?
mpc7448 risc microprocessor hardware specifications, rev. 4 12 freescale semiconductor electrical and thermal characteristics table 5 provides the package thermal characteristics for the mpc7448. for more information regarding thermal management, see section 9.7, ?power and thermal management information.? table 6 provides the dc electrical characteristics for the mpc7448. table 5. package thermal characteristics 1 characteristic symbol value unit notes junction-to-ambient thermal resistance, natural convection, single-layer (1s) board r ja 26 ?c/w c/w 2, 3 junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board r jma 19 ?c/w c/w 2, 4 junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board r jma 22 ?c/w c/w 2, 4 junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board r jma 16 ?c/w c/w 2, 4 junction-to-board thermal resistance r jb 11 ?c/w c/w 5 junction-to-case thermal resistance r jc < 0.1 ?c/w c/w 6 notes : 1. refer to section 9.7, ?power and thermal management information,? for details about thermal management. 2. junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 3. per jedec jesd51-2 with the single-layer board horizontal 4. per jedec jesd51-6 with the board horizontal 5. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 6. this is the thermal resistance between die and case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the calculated case temperature. the actual value of r jc for the part is less than 0.1c/w. table 6. dc electrical specifications at recommended operating conditions. see table 4 . characteristic nominal bus voltage 1 symbol min max unit notes input high voltage (all inputs) 1.5 v ih ov dd 0.65 ov dd + 0.3 v 2 1.8 ov dd 0.65 ov dd + 0.3 2.5 1.7 ov dd + 0.3 input low voltage (all inputs) 1.5 v il ?0.3 ov dd 0.35 v 2 1.8 ?0.3 ov dd 0.35 2.5 ?0.3 0.7 input leakage current, all signals except bvsel0, lssd_mode , tck , tdi, tms, trst : v in = ov dd v in = gnd ?i in ? 50 ? 50 a 2, 3 input leakage current, bvsel0, lssd_mode , tck , tdi, tms, trst : v in = ov dd v in = gnd ?i in ? 50 ? 2000 a 2, 6
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 13 electrical and thermal characteristics table 7 provides the power consumption for the mpc7448 part numbers described by this document; see section 11.1, ?part numbers fully addressed by this document,? for information regarding which part numbers are described by this document. freescale al so offers mpc7448 part numbers that meet lower power consumption specifications by adhering to lo wer core voltage and core frequency specifications. for more information on these devices, including re ferences to the mpc7448 hardware specification addenda that describe these devices, see section 11.2, ?part numbers not fully addressed by this document .? the power consumptions provided in table 7 represent the power consumption of each speed grade when operated at the rated maximum core frequency (see table 8 ). freescale sorts devices by power as well as by core frequency, and power limits for each speed gr ade are independent of each other. each device is tested at its maximum core frequency only. (note that deep sleep mode power consumption is independent of clock frequency.) operating a device at a frequency lower than its rated maximum is fully supported provided the clock frequencies ar e within the specifications given in table 8 , and a device operated below its rated maximum w ill have lower power consumption. however, inferences should not be made about a device?s power consumption based on the power specifications of another (lower) speed grade. for example, a 1700 mhz device operated at 1420 mhz may not exhibit the same power consumption as a 1420 mhz device operated at 1420 mhz. for all mpc7448 devices, the following guidelines on th e use of these parameters for system design are suggested. the full-power mode?typical value represen ts the sustained power consumption of the device high-impedance (off-state) leakage current: v in = ov dd v in = gnd ?i tsi ? 50 ? 50 a 2, 3, 4 output high voltage @ i oh = ?5 ma 1.5 v oh ov dd ? 0.45 ? v 1.8 ov dd ? 0.45 ? 2.5 1.8 ? output low voltage @ i ol = 5 ma 1.5 v ol ?0.45v 1.8 ? 0.45 2.5 ? 0.6 capacitance, v in = 0 v, f = 1 mhz all inputs c in ?8.0pf5 notes : 1. nominal voltages; see ta b l e 4 for recommended operating conditions. 2. all i/o signals are referenced to ov dd . 3. excludes test signals and ieee std. 1149.1 boundary scan (jtag) signals 4. the leakage is measured for nominal ov dd and v dd , or both ov dd and v dd must vary in the same direction (for example, both ov dd and v dd vary by either +5% or ?5%). 5. capacitance is periodically sampled rather than 100% tested. 6. these pins have internal pull-up resistors. table 6. dc electrical specifications (continued) at recommended operating conditions. see table 4 . characteristic nominal bus voltage 1 symbol min max unit notes
mpc7448 risc microprocessor hardware specifications, rev. 4 14 freescale semiconductor electrical and thermal characteristics when running a typical benchmark at temperatures in a typical system. the full-power mode?thermal value is intended to represent the sustained power c onsumption of the device when running a typical code sequence at high temperature and is recommended to be used as the basis for designing a thermal solution; see section 9.7, ?power and thermal management information ? for more information on thermal solutions. the full-power mode?maximum value is recommended to be used for power supply design because this represents the maximum peak power draw of the device that a power supply must be capable of sourcing without voltage droop. for informa tion on power consumption when dynamic frequency switching is enabled, see section 9.7.5, ?dynamic fre quency switching (dfs).? table 7. power consumption for mpc7448 at maximum rated frequency die junction temperature (t j ) maximum processor core frequency (speed grade, mhz) unit notes 1000 mhz 1420 mhz 1600 mhz 1700 mhz full-power mode typical 65 ?c c 15.0 19.0 20.0 21.0 w 1, 2 thermal 105 ?c c 18.6 23.3 24.4 25.6 w 1, 5 maximum 105 ?c c 21.6 27.1 28.4 29.8 w 1, 3 nap mode typical 105 ?c c 11.1 11.8 13.0 13.0 w 1, 6 sleep mode typical 105 ?c c 10.8 11.4 12.5 12.5 w 1, 6 deep sleep mode (pll disabled) typical 105 ?c c 10.4 11.0 12.0 12.0 w 1, 6 notes: 1. these values specify the power consumption for the core power supply (v dd ) at nominal voltage and apply to all valid processor bus frequencies and configurations. the values do not include i/o supply power (ov dd ) or pll supply power (av dd ). ov dd power is system dependent but is typically < 5% of v dd power. worst case power consumption for av dd < 13 mw. freescale also offers mpc7448 part numbers that meet lower power consumption specifications; for more information on these devices, see section 11.2, ?part numbers not fully addressed by this document .? 2. typical power consumption is an average value measured with the processor operating at its rated maximum processor core frequency (except for deep sleep mode), at nominal recommended v dd (see ta b l e 4 ) and 65 c while running the dhrystone 2.1 benchmark and achieving 2.3 dhrystone mips/mhz. this parameter is not 100% tested but periodically sampled.b 3. maximum power consumption is the average measured with the processor operating at its rated maximum processor core frequency, at nominal v dd and maximum operating junction temperature (see ta b l e 4 ) while running an entirely cache-resident, contrived sequence of instructions to keep all the execution units maximally busy. 4. doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode. as a result, power consumption for this mode is not tested. 5. thermal power consumption is an average value measured at the nominal recommended v dd (see ta ble 4 ) and 105 c while running the dhrystone 2.1 benchmark and achieving 2.3 dhrystone mips/mhz. this parameter is not 100% tested but periodically sampled. 6. typical power consumption for these modes is measured at the nominal recommended v dd (see ta b l e 4 ) and 105 c in the mode described. this parameter is not 100% tested but is periodically sampled.
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 15 electrical and thermal characteristics 5.2 ac electrical characteristics this section provides the ac electrical characteristic s for the mpc7448. after fabrication, functional parts are sorted by maximum processor core frequency as shown in section 5.2.1, ?clock ac specifications,? and tested for conformance to the ac specifications for that frequency. the processor core frequency, determined by the bus (sysclk) frequency and the settings of the pll_cfg[0:5] signals, can be dynamically modified using dynamic frequency switching (dfs). parts are sold by maximum processor core frequency; see section 11, ?part numbering and marking,? for information on ordering parts. dfs is described in section 9.7.5, ?dynamic fre quency switching (dfs).? 5.2.1 clock ac specifications table 8 provides the clock ac timing specifications as defined in figure 3 and represents the tested operating frequencies of the devices. th e maximum system bus frequency, f sysclk , given in table 8 , is considered a practical maximum in a typical single-processor system. this does not exclude multi-processor systems, but these typically require considerably more design effort to achieve the maximum rated bus frequency. the actual maximum sysclk frequency for a ny application of the mpc7448 will be a function of the ac timings of the microprocessor(s), the ac timings for the system controller, bus loading, circuit board topology, trace le ngths, and so forth, and may be less than the value given in table 8 .
mpc7448 risc microprocessor hardware specifications, rev. 4 16 freescale semiconductor electrical and thermal characteristics notes : 1. caution : the sysclk frequency and pll_cfg[0:5] settings must be chosen such that the resulting sysclk (bus) frequency, processor core frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0:5] signal description in section 9.1.1, ?pll configuration,? for valid pll_cfg[0:5] settings. 2. actual maximum system bus frequency is system-dependent. see section 5.2.1, ?clock ac specifications.? 3. rise and fall times for the sysclk input measured from 0.4 to 1.4 v 4. timing is guaranteed by design and characterization. 5. guaranteed by design 6. the sysclk driver?s closed loop jitter bandwidth should be less than 1.5 mhz at ?3 db. 7. relock timing is guaranteed by design and characterization. pll-relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. 8. this reflects the maximum and minimum core frequencies when the dynamic frequency switching feature (dfs) is disabled. f core_dfs provides the maximum and minimum core frequencies when operating in a dfs mode. 9.this specification supports the dynamic frequency switching (dfs) feature and is applicable only when one of the dfs modes (divide-by-2 or divide-by-4) is enabled. when dfs is disabled, the core frequency must conform to the maximum and minimum frequencies stated for f core . 10.use of the dfs feature does not affect vco frequency. table 8. clock ac timing specifications at recommended operating conditions. see table 4 . characteristic symbol maximum processor core frequency (speed grade) unit notes 1000 mhz 1420 mhz 1600 mhz 1700 mhz min max min max min max min max processor core frequency dfs mode disabled f core 600 1000 600 1420 600 1600 600 1700 mhz 1, 8 dfs mode enabled f core _ df 300 500 300 710 300 800 300 850 9 vco frequency f vco 600 1000 600 1420 600 800 600 1700 mhz 1, 10 sysclk frequency f sysclk 33 200 33 200 33 200 33 200 mhz 1, 2, 8 sysclk cycle time t sysclk 5.0 30 5.0 30 5.0 30 5.0 30 ns 2 sysclk rise and fall time t kr , t kf ?0.5?0.5?0.5?0.5ns 3 sysclk duty cycle measured at ov dd /2 t khkl / t sysclk 40 60 40 60 40 60 40 60 % 4 sysclk cycle-to-cycle jitter ? 150 ? 150 ? 150 ? 150 ps 5, 6 internal pll relock time ? 100 ? 100 ? 100 ? 100 s7
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 17 electrical and thermal characteristics figure 3 provides the sysclk input timing diagram. figure 3. sysclk input timing diagram 5.2.2 processor bus ac specifications table 9 provides the processor bus ac timing specifications for the mpc7448 as defined in figure 4 and figure 5 . table 9. processor bus ac timing specifications 1 at recommended operating conditions. see table 4 . parameter symbol 2 all speed grades unit notes min max input setup times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , artry , bg , ckstp_in , dbg , dti[0:3], gbl , tt[0:4], qack , ta , tben, tea , ts , ext_qual, pmon_in , shd [0:1] bmode [0:1], bvsel[0:1] t avkh t dvkh t ivkh t mvkh 1.5 1.5 1.5 1.5 ? ? ? ? ns ? ? ? 8 input hold times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , artry , bg , ckstp_in , dbg , dti[0:3], gbl , tt[0:4], qack , ta , tben, tea , ts , ext_qual, pmon_in , shd [0:1] bmode [0:1], bvsel[0:1] t axkh t dxkh t ixkh t mxkh 0 0 0 0 ? ? ? ? ns ? ? ? ? 8 output valid times: a[0:35], ap[0:4] d[0:63], dp[0:7] br , ci , drdy , gbl , hit , pmon_out , qreq , tbst , tsiz[0:2], tt[0:4], wt ts artry , shd [0:1] t khav t khdv t khov t khtsv t kharv ? ? ? ? ? 1.8 1.8 1.8 1.8 1.8 ns output hold times: a[0:35], ap[0:4] d[0:63], dp[0:7] br , ci , drdy , gbl , hit , pmon_out , qreq , tbst , tsiz[0:2], tt[0:4], wt ts artry , shd [0:1] t khax t khdx t khox t khtsx t kharx 0.5 0.5 0.5 0.5 0.5 ? ? ? ? ? ns sysclk to output enable t khoe 0.5 ? ns 5 sysclk v m v m v m cv ih cv il v m = midpoint voltage (ov dd /2) t sysclk t kr t kf t khkl
mpc7448 risc microprocessor hardware specifications, rev. 4 18 freescale semiconductor electrical and thermal characteristics sysclk to output high impedance (all except ts , artry , shd0 , shd1 ) t khoz ?1.8ns5 sysclk to ts high impedance after precharge t khtspz ?1t sysclk 3, 4, 5 maximum delay to artry /shd0 /shd1 precharge t kharp ?1t sysclk 3, 5, 6, 7 sysclk to artry /shd0 /shd1 high impedance after precharge t kharpz ?2t sysclk 3, 5, 6, 7 notes: 1. all input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the i nput sysclk. all output specifications are measured from the midpoint of the rising edge of sysclk to the midpoint of the signal in question. all output timings assume a purely resistive 50- load (see figure 4 ). input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbology used for timing specifications herein follows the pattern of t (signal)(state)(reference)(state) for inputs and t (reference)(state)(signal)(state) for outputs. for example, t ivkh symbolizes the time input signals (i) reach the valid state (v) relative to the sysclk reference (k) going to the high (h) state or input setup time. and t khov symbolizes the time from sysclk(k) going high (h) until outputs (o) are valid (v) or output valid time. input hold time can be read as the time that the input signal (i) went invalid (x) with respect to the rising clock edge (kh) (note the position of the reference and its state for inputs) and output hold time can be read as the time from the rising edge (kh) until the output went invalid (ox). 3. t sysclk is the period of the external clock (sysclk) in ns. the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in ns) of the parameter in question. 4. according to the bus protocol, ts is driven only by the currently active bus master. it is asserted low and precharged high before returning to high impedance, as shown in figure 6 . the nominal precharge width for ts is t sysclk , that is, one clock period. since no master can assert ts on the following clock edge, there is no concern regarding contention with the precharge. output valid and output hold timing is tested for the signal asserted. output valid time is tested for precharge.the high-impedance behavior is guaranteed by design. 5. guaranteed by design and not tested 6. according to the bus protocol, artry can be driven by multiple bus masters through the clock period immediately following aack . bus contention is not an issue because any master asserting artry will be driving it low. any master asserting it low in the first clock following aack will then go to high impe dance for a fraction of a cycle, then negated for up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. the nominal precharge width for artry is 1.0 t sysclk ; that is, it should be high impedance as shown in figure 6 before the first opportunity for another master to assert artry . output valid and output hold timing is tested for the signal asserted.the high-impedance behavior is guaranteed by design. 7. according to the mpx bus protocol, shd0 and shd1 can be driven by multiple bus masters beginning two cycles after ts . timing is the same as artry , that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. the nominal precharge width for shd0 and shd1 is 1.0 t sysclk . the edges of the precharge vary depending on the programmed ratio of core to bus (pll configurations). 8. bmode [0:1] and bvsel[0:1] are mode select inputs. bmode [0:1] are sampled before and after hreset negation. bvsel[0:1] are sampled before hreset negation. these parameters represent the input setup and hold times for each sample. these values are guaranteed by design and not tested. bmode [0:1] must remain stable after the second sample; bvsel[0:1] must remain stable after the first (and only) sample. see figure 5 for sample timing. table 9. processor bus ac timing specifications 1 (continued) at recommended operating conditions. see table 4 . parameter symbol 2 all speed grades unit notes min max
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 19 electrical and thermal characteristics figure 4 provides the ac test load for the mpc7448. figure 4. ac test load figure 5 provides the bmode [0:1] input timing diagram for the mpc 7448. these mode select inputs are sampled once before and once after hreset negation. figure 5. bmode [0:1] input sample timing diagram output z 0 = 50 ov dd /2 r l = 50 hreset bmode[0:1] v m = midpoint voltage (ov dd /2) sysclk 1st sample 2nd sample v m v m
mpc7448 risc microprocessor hardware specifications, rev. 4 20 freescale semiconductor electrical and thermal characteristics figure 6 provides the input/output timing diagram for the mpc7448. figure 6. input/output timing diagram sysclk all inputs v m v m = midpoint voltage (ov dd /2) all outputs t khox v m t khdv (except ts , artry , shd0 , shd1 ) all outputs ts artry , (except ts , artry , shd0 , shd1 ) v m t khoe t khoz t khtspz t kharpz t kharp shd1 shd0 , t khov t khav t khdx t khax t ixkh t axkh t khtsx t khtsv t khtsv t kharv t kharx t ivkh t avkh t mvkh t mxkh
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 21 electrical and thermal characteristics 5.2.3 ieee std. 1149.1 ac timing specifications table 10 provides the ieee std. 1149.1 (jtag) ac timing specifications as defined in figure 8 through figure 11 . table 10. jtag ac timing specifications (independent of sysclk) 1 at recommended operating conditions. see table 4 . parameter symbol min max unit notes tck frequency of operation f tclk 033.3mhz tck cycle time t tclk 30 ? ns tck clock pulse width measured at 1.4 v t jhjl 15 ? ns tck rise and fall times t jr and t jf ?2ns trst assert time t trst 25 ? ns 2 input setup times: boundary-scan data tms, tdi t dvjh t ivjh 4 0 ? ? ns 3 input hold times: boundary-scan data tms, tdi t dxjh t ixjh 20 25 ? ? ns 3 valid times: boundary-scan data tdo t jldv t jlov 4 4 20 25 ns 4 output hold times: boundary-scan data tdo t jldx t jlox 30 30 ? ? ns 4 tck to output high impedance: boundary-scan data tdo t jldz t jloz 3 3 19 9 ns 4, 5 notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of tclk to the midpoint of the signal in questi on. the output timings are measured at the pins. all output timings assume a purely resistive 50- load (see figure 7 ). time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. trst is an asynchronous level sensitive signal. the time is for test purposes only. 3. non-jtag signal input timing with respect to tck. 4. non-jtag signal output timing with respect to tck. 5. guaranteed by design and characterization.
mpc7448 risc microprocessor hardware specifications, rev. 4 22 freescale semiconductor electrical and thermal characteristics figure 7 provides the ac test load for tdo and the boundary-scan outputs of the mpc7448. figure 7. alternate ac test load for the jtag interface figure 8 provides the jtag clock input timing diagram. figure 8. jtag clock input timing diagram figure 9 provides the trst timing diagram. figure 9. trst timing diagram figure 10 provides the boundary-scan timing diagram. figure 10. boundary-scan timing diagram output z 0 = 50 ov dd /2 r l = 50 v m v m v m v m = midpoint voltage (ov dd /2) t tclk t jr t jf t jhjl tclk trst t trst v m = midpoint voltage (ov dd /2) v m v m v m tck boundary boundary boundary data outputs data inputs data outputs v m = midpoint voltage (ov dd /2) t dxjh t dvjh t jldv t jldz input data valid output data valid output data valid t jldx v m
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 23 electrical and thermal characteristics figure 11 provides the test access port timing diagram. figure 11. test access port timing diagram 5.3 voltage and frequency derating voltage and frequency de rating is no longer supported for part numbers described by this document beginning with datecode 0613. (see section 11, ?part numbering and marking ,? for information on date code markings.) it is supported by some mpc7448 part numbers which ta rget low-power applications; see section 11.2, ?part numbers not fully addressed by this document ? and the referenced mpc7448 hardware specification addenda for more information on these low-power devices. for those devices which previously supported this feature, information has been archived in the chip errata for the mpc7448 (document order no. mpc7448ce). v m tck tdi, tms tdo output data valid v m = midpoint voltage (ov dd /2) t ixjh t ivjh t jlov t jloz input data valid tdo output data valid t jlox v m
mpc7448 risc microprocessor hardware specifications, rev. 4 24 freescale semiconductor pin assignments 6 pin assignments figure 12 (in part a) shows the pinout of the mpc7448, 360 high coefficient of thermal expansion ceramic ball grid array (hcte) package as viewed from the top surface. part b shows the side profile of the hcte package to indicate the direction of the top surface view. figure 12. pinout of the mpc7448, 360 hcte package as viewed from the top surface a b c d e f g h j k l m n p r t 12 3 4 5 678 910111213141516 not to scale 17 18 19 u v w part a view part b die substrate assembly encapsulant
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 25 pinout listings 7 pinout listings table 11 provides the pinout listing for the mpc7448, 360 hcte package. the pinouts of the mpc7448 and mpc7447a are compatible, but the requirements re garding the use of the additional power and ground pins have changed. the mpc7448 requires these pins be connected to the appropriate power or ground plane to achieve high core frequencies; see section 9.3, ?connection recommendations,? for additional information. as a result, these pins should be connected in all new designs. additionally, the mpc7448 may be populated on a board designed for a mpc7447 (or mpc7445 or mpc7441), provided the core voltage can be made to match the requirements in table 4 and all pins defined as ?no connect? for the mpc7447 are unterminated, as required by the mpc7457 risc microprocessor hardware specifications . the mpc7448 uses pins previously marked ?no connect? for the temperature diode pins and for additional power and ground connections. the additional power and ground pins are required to achieve high core frequenc ies and core frequency will be limited if they are not connected; see section 9.3, ?connection recommendations,? for additional information. because these ?no connect? pins in the mpc7447 360 pin package are not driven in functional mode, an mpc7447 can be populated in an mpc7448 board. note caution must be exercised when performing boundary scan test operations on a board designed for an mpc7448, but populated with an mpc7447 or earlier device. this is because in the mpc7447 it is possible to drive the latches associated with the former ?no connect? pins in the mpc7447, potentially causing contention on those pins. to prevent this, ensure that these pins are not connected on the board or, if they are connected, ensure that the states of internal mpc7447 latches do not cause these pins to be driven during board testing. for the mpc7448, pins that were defined as the test[0:4] factory test signal group on the mpc7447a and earlier devices have been assigned new functions. for most of these, the termination recommendations for the test[0:4] pins of the mpc7447a are compatible with the mpc7448 and will allow correct operation with no performance loss. the exception is bvsel1 (test3 on the mpc7447a and earlier devices), which may require a different termination depending which i/o voltage mode is desired; see table 3 for more information. note this pinout is not compatible with the mpc750, mpc7400, or mpc7410 360 bga package.
mpc7448 risc microprocessor hardware specifications, rev. 4 26 freescale semiconductor pinout listings table 11. pinout listing for the mpc7448, 360 hcte package signal name pin number active i/o notes a[0:35] e11, h1, c11, g3, f10, l2, d11, d1, c10, g2, d12, l3, g4, t2, f4, v1, j4, r2, k5, w2, j2, k4, n4, j3, m5, p5, n3, t1, v2, u1, n5, w1, b12, c4, g10, b11 high i/o 2 aack r1 low input ap[0:4] c1, e3, h6, f5, g7 high i/o 2 artry n2 low i/o 3 av dd a8 ? input bg m1 low input bmode0 g9 low input 4 bmode1 f8 low input 5 br d2 low output bvsel0 b7 high input 1, 6 bvsel1 e10 high input 1, 20 ci j1 low output ckstp_in a3 low input ckstp_out b1 low output clk_out h2 high output d[0:63] r15, w15, t14, v16, w16, t15, u15, p14, v13, w13, t13, p13, u14, w14, r12, t12, w12, v12, n11, n10, r11, u11, w11, t11, r10, n9, p10, u10, r9, w10, u9, v9, w5, u6, t5, u5, w7, r6, p7, v6, p17, r19, v18, r18, v19, t19, u19, w19, u18, w17, w18, t16, t18, t17, w3, v17, u4, u8, u7, r7, p6, r8, w8, t8 high i/o dbg m2 low input dfs2 a12 low input 20, 21 dfs4 b6 low input 12, 20, 21 dp[0:7] t3, w4, t4, w9, m6, v3, n8, w6 high i/o drdy r3 low output 7 dti[0:3] g1, k1, p1, n1 high input 8 ext_qual a11 high input 9 gbl e2 low i/o gnd b5, c3, d6, d13, e17, f3, g17, h4, h7, h9, h11, h13, j6, j8, j10, j12, k7, k3, k9, k11, k13, l6, l8, l10, l12, m4, m7, m9, m11, m13, n7, p3, p9, p12, r5, r14, r17, t7, t10, u3, u13, u17, v5, v8, v11, v15 ?? gnd a17, a19, b13, b16, b18, e12, e19, f13, f16, f18, g19, h18, j14, l14, m15, m17, m19, n14, n16, p15, p19 ?? 15 gnd_sense g12, n13 ? ? 19 hit b2 low output 7 hreset d8 low input int d4 low input l1_tstclk g8 high input 9 l2_tstclk b3 high input 10
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 27 pinout listings lv r a m b10 ? ? 12, 20, 22 nc (no connect) a6, a14, a15, b14, b15, c14, c15, c16, c17, c18, c19, d14, d15, d16, d17, d18, d19, e14, e15, f14, f15, g14, g15, h15, h16, j15, j16, j17, j18, j19, k15, k16, k17, k18, k19, l15, l16, l17, l18, l19 ?? 11 lssd_mode e8 low input 6, 12 mcp c9 low input ov dd b4, c2, c12, d5, f2, h3, j5, k2, l5, m3, n6, p2, p8, p11, r4, r13, r16, t6, t9, u2, u12, u16, v4, v7, v10, v14 ?? ovdd_sense e18, g18 ? ? 16 pll_cfg[0:4] b8, c8, c7, d7, a7 high input pll_cfg[5] d10 high input 9, 20 pmon_in d9 low input 13 pmon_out a9 low output qack g5 low input qreq p4 low output shd [0:1] e4, h5 low i/o 3 smi f9 low input sreset a2 low input sysclk a10 ? input ta k6 low input tben e1 high input tbst f11 low output tck c6 high input tdi b9 high input 6 tdo a4 high output tea l1 low input temp_anode n18 ? ? 17 temp_cathode n19 ? ? 17 tms f1 high input 6 trst a5 low input 6, 14 ts l4 low i/o 3 tsiz[0:2] g6, f7, e7 high output tt[0:4] e5, e6, f6, e9, c5 high i/o wt d3 low output v dd h8, h10, h12, j7, j9, j11, j13, k8, k10, k12, k14, l7, l9, l11, l13, m8, m10, m12 ?? v dd a13, a16, a18, b17, b19, c13, e13, e16, f12, f17, f19, g11, g16, h14, h17, h19, m14, m16, m18, n15, n17, p16, p18 ?? 15 table 11. pinout listing for the mpc7448, 360 hcte package (continued) signal name pin number active i/o notes
mpc7448 risc microprocessor hardware specifications, rev. 4 28 freescale semiconductor pinout listings vdd_sense g13, n12 ? ? 18 notes: 1. ov dd supplies power to the processor bus, jtag, and all control signals, and is configurable. (v dd supplies power to the processor core, and av dd supplies power to the pll after filtering from v dd ). to program the i/o voltage, see ta b l e 3 . if used, the pull-down resistor should be less than 250 . because these settings may change in future products, it is recommended bvsel[0:1] be configured using resistor options, jumpers, or some other flexible means, with the capability to reconfigure the termination of this signal in the future if necessary. for actual recommended value of v in or supply voltages see ta b l e 4 . 2. unused address pins must be pulled down to gnd and corresponding address parity pins pulled up to ov dd . 3. these pins require weak pull-up resistors (for example, 4.7 k ) to maintain the control signals in the negated state after they have been actively negated and released by the mpc7448 and other bus masters. 4. this signal selects between mpx bus mode (asserted) and 60x bus mode (negated) and will be sampled at hreset going high. 5. this signal must be negated during reset, by pull-up resistor to ov dd or negation by ?hreset (inverse of hreset ), to ensure proper operation. 6. internal pull up on die. 7. not used in 60x bus mode. 8. these signals must be pulled down to gnd if unused, or if the mpc7448 is in 60x bus mode. 9. these input signals are for factory use only and must be pulled down to gnd for normal machine operation. 10.this test signal is recommended to be tied to hreset ; however, other configurations will not adversely affect performance. 11.these signals are for factory use only and must be left unconnected for normal machine operation. some pins that were ncs on the mpc7447, mpc7445, and mpc7441 have now been defined for other purposes. 12.these input signals are for factory use only and must be pulled up to ov dd for normal machine operation. 13.this pin can externally cause a performance monitor event. counting of the event is enabled through software. 14.this signal must be asserted during reset, by pull down to gnd or assertion by hreset , to ensure proper operation. 15.these pins were ncs on the mpc7447, mpc7445, and mpc7441. see section 9.3, ?connection recommendations,? for more information. 16.these pins were ov dd pins on the mpc7447, mpc7445, and mpc7441. these pins are internally connected to ov dd and are intended to allow an external device (such as a power supply) to detect the i/o voltage level present inside the device package. if unused, it is recommended they be connected to test points to facilitate system debug; otherwise, they may be connected directly to ov dd or left unconnected. 17.these pins provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature of the processor. these pins may be left unterminated if unused. 18.these pins are internally connected to v dd and are intended to allow an external device (such as a power supply) to detect the processor core voltage level present inside the device package. if unused, it is recommended they be connected to test points to facilitate system debug; otherwise, they may be connected directly to v dd or left unconnected. 19.these pins are internally connected to gnd and are intended to allow an external device to detect the processor ground voltage level present inside the device package. if unused, it is recommended they be connected to test points to facilitate system debug; otherwise, they may be connected directly to gnd or left unconnected. 20.these pins were in the test[0:4] factory test pin group on the mpc7447a, mpc7447, mpc7445, and mpc7441. they have been assigned new functions on the mpc7448. 21.these pins can be used to enable the supported dynamic frequency switching (dfs) modes via hardware. if both are pulled down, dfs mode is disabled completely and cannot be enabled via software. if unused, they should be pulled up to ov dd to allow software control of dfs. see the mpc7450 risc microprocessor family reference manual for more information. 22.this pin is provided to allow operation of the l2 cache at low core voltages and is for factory use only. see the mpc7450 risc microprocessor family reference manual for more information. table 11. pinout listing for the mpc7448, 360 hcte package (continued) signal name pin number active i/o notes
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 29 package description 8 package description the following sections provide the package parame ters and mechanical dimensions for the hcte package. 8.1 package parameters for the mpc7448, 360 hcte bga the package parameters are as provided in the following list. the package type is 25 25 mm, 360-lead high coefficient of thermal expansion ceramic ball grid array (hcte). package outline 25 25 mm interconnects 360 (19 19 ball array ? 1) pitch 1.27 mm (50 mil) minimum module height 2.32 mm maximum module height 2.80 mm ball diameter 0.89 mm (35 mil) coefficient of thermal expansion12.3 ppm/c
mpc7448 risc microprocessor hardware specifications, rev. 4 30 freescale semiconductor package description 8.2 mechanical dimensions for the mpc7448, 360 hcte bga figure 13 provides the mechanical dimensions and bottom surface nomenclature for the mpc7448, 360 hcte bga package. figure 13. mechanical dimensions and bottom surface nomenclature for the mpc7448, 360 hcte bga package notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 2. dimensions in millimeters. 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array. 0.2 c a 360x d 2x a1 corner e e 0.2 2x c b 12345678910111213141516 a b c d e f g h j k l m n p r t b 0.3 a 0.15 b a 0.15 a 171819 u w v millimeters dim min max a 2.32 2.80 a1 0.80 1.00 a2 0.70 0.90 a3 ? 0.6 b 0.82 0.93 d 25.00 bsc d1 ? 11.3 d2 8.0 ? d3 ? 6.5 d4 7.2 7.4 e 1.27 bsc e 25.00 bsc e1 ? 11.3 e2 8.0 ? e3 ? 6.5 e4 7.9 8.1 capacitor region 1 d3 e2 e1 a a1 a2 a3 e4 d4 e3 d1 d2 0.35 a
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 31 package description 8.3 package parameters for the mpc7448, 360 hcte lga the package parameters are as provided in the following list. the package type is 25 25 mm, 360 pin high coefficient of thermal expansi on ceramic land grid array (hcte). package outline 25 25 mm interconnects 360 (19 19 ball array ? 1) pitch 1.27 mm (50 mil) minimum module height 1.52 mm maximum module height 1.80 mm pad diameter 0.89 mm (35 mil) coefficient of thermal expansion12.3 ppm/c
mpc7448 risc microprocessor hardware specifications, rev. 4 32 freescale semiconductor package description 8.4 mechanical dimensions for the mpc7448, 360 hcte lga figure 13 provides the mechanical dimensions and bottom surface nomenclature for the mpc7448, 360 hcte lga package. figure 14. mechanical dimensions and bottom surface nomenclature for the mpc7448, 360 hcte lga package notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 2. dimensions in millimeters 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a pad missing from the array. 0.2 c a 360x d 2x a1 corner e e 0.2 2x c b 12345678910111213141516 a b c d e f g h j k l m n p r t b 0.3 a 0.15 b a 0.15 a 171819 u w v millimeters dim min max a 1.52 1.80 a1 0.70 0.90 a2 ? 0.6 b 0.82 0.93 d 25.00 bsc d1 ? 11.3 d2 8.0 ? d3 ? 6.5 d4 7.2 7.4 e 1.27 bsc e 25.00 bsc e1 ? 11.3 e2 8.0 ? e3 ? 6.5 e4 7.9 8.1 capacitor region 1 d3 e2 e1 a a1 a2 e4 d4 e3 d1 d2 0.35 a
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 33 package description 8.5 package parameters for the mpc7448, 360 hcte rohs-compliant bga the package parameters are as provided in the following list. the package type is 25 25 mm, 360-lead high coefficient of thermal expansion ceramic ball grid array (hcte) with rohs-compliant lead-free spheres. package outline 25 25 mm interconnects 360 (19 19 ball array ? 1) pitch 1.27 mm (50 mil) minimum module height 1.92 mm maximum module height 2.40 mm ball diameter 0.75 mm (30 mil) coefficient of thermal expansion12.3 ppm/c
mpc7448 risc microprocessor hardware specifications, rev. 4 34 freescale semiconductor package description 8.6 mechanical dimensions for the mpc7448, 360 hcte rohs-compliant bga figure 13 provides the mechanical dimensions and bottom surface nomenclature for the mpc7448, 360 hcte bga package with rohs-compliant lead-free spheres. figure 15. mechanical dimensions and bottom surface nomenclature for the mpc7448, 360 hcte rohs-compliant bga package notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 2. dimensions in millimeters. 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array. 4. dimension a1 represents the collapsed sphere diameter. 0.2 c a 360x d 2x a1 corner e e 0.2 2x c b 12345678910111213141516 a b c d e f g h j k l m n p r t b 0.3 a 0.15 b a 0.15 a 171819 u w v millimeters dim min max a 1.92 2.40 a1 4 0.40 0.60 a2 0.70 0.90 a3 ? 0.6 b 0.60 0.90 d 25.00 bsc d1 ? 11.3 d2 8.0 ? d3 ? 6.5 d4 7.2 7.4 e 1.27 bsc e 25.00 bsc e1 ? 11.3 e2 8.0 ? e3 ? 6.5 e4 7.9 8.1 capacitor region 1 d3 e2 e1 a a1 a2 a3 e4 d4 e3 d1 d2 0.35 a
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 35 system design information 9 system design information this section provides system and thermal desi gn requirements and recommendations for successful application of the mpc7448. 9.1 clocks the following sections provide more detailed information regarding the clocking of the mpc7448. 9.1.1 pll configuration the mpc7448 pll is configured by the pll_cfg[0:5] signals. for a given sysclk (bus) frequency, the pll configuration signals set the internal cpu and vco frequency of operation. the pll configuration for the mpc7448 is shown in table 12 . in this example, shaded cells represent settings that, for a given sysclk frequency, result in core and/or vco frequencies that do not comply with table 8 . when enabled, dynamic frequency switching (dfs) also affects the core frequency by halving or quartering the bus-to-core multiplier; see section 9.7.5, ?dynamic fre quency switching (dfs),? for more information. note that when dfs is enabled the resulting core frequency must meet the adjusted minimum core frequency requirements (f core_dfs ) described in table 8 . note that the pll_cfg[5] is currently used for factory test only and should be tied low, and that the mpc7448 pll configuration settings are compatible with the mpc7447a pll configuration settings when pll_cfg[5] = 0. table 12. mpc7448 microprocessor pll configuration example pll_cfg[0:5] example core and vco frequency in mhz bus-to-core multiplier 5 core-to-vco multiplier 5 bus (sysclk) frequency 33.3 mhz 50 mhz 66.6 mhz 75 mhz 83 mhz 100 mhz 133 mhz 167 mhz 200 mhz 010000 2x 6 1x 100000 3x 6 1x 600 101000 4x 6 1x 667 800 101100 5x 1x 667 835 1000 100100 5.5x 1x 733 919 1100 110100 6x 1x 600 800 1002 1200 010100 6.5x 1x 650 866 1086 1300 001000 7x 1x 700 931 1169 1400 000100 7.5x 1x 623 750 1000 1253 1500 110000 8x 1x 600 664 800 1064 1336 1600 011000 8.5x 1x 638 706 850 1131 1417 1700 011110 9x 1x 600 675 747 900 1197 1500 011100 9.5x 1x 633 712 789 950 1264 1583 101010 10x 1x 667 750 830 1000 1333 1667 100010 10.5x 1x 700 938 872 1050 1397
mpc7448 risc microprocessor hardware specifications, rev. 4 36 freescale semiconductor system design information 100110 11x 1x 733 825 913 1100 1467 000000 11.5x 1x 766 863 955 1150 1533 101110 12x 1x 600 800 900 996 1200 1600 111110 12.5x 1x 625 833 938 1038 1250 1667 010110 13x 1x 650 865 975 1079 1300 111000 13.5x 1x 675 900 1013 1121 1350 110010 14x 1x 700 933 1050 1162 1400 000110 15x 1x 750 1000 1125 1245 1500 110110 16x 1x 800 1066 1200 1328 1600 000010 17x 1x 850 1132 1275 1417 1700 001010 18x 1x 600 900 1200 1350 1500 001110 20x 1x 667 1000 1332 1500 1666 010010 21x 1x 700 1050 1399 1575 011010 24x 1x 800 1200 1600 111010 28x 1x 933 1400 001100 pll bypass pll off, sysclk clocks core circuitry directly 111100 pll off pll off, no core clocking occurs notes: 1. pll_cfg[0:5] settings not listed are reserved. 2. the sample bus-to-core frequencies shown are for reference only. some pll configurations may select bus, core, or vco frequencies which are not useful, not supported, or not tested for by the mpc7448; see section 5.2.1, ?clock ac specifications ,? for valid sysclk, core, and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly and the pll is disabled. however, the bus interface unit requires a 2x clock to function. therefore, an additional signal, ext_qual, must be driven at half the frequency of sysclk and offset in phase to meet the required input setup t ivkh and hold time t ixkh (see ta b l e 9 ). the result will be that the processor bus frequency will be one-half sysclk, while the internal processor is clocked at sysclk frequency. this mode is intended for factory use and emulator tool use only. note : the ac timing specifications given in this document do not apply in pll-bypass mode. 4. in pll-off mode, no clocking occurs inside the mpc7448 regardless of the sysclk input. 5. applicable when dfs modes are disabled. these multipliers change when operating in a dfs mode. see section 9.7.5, ?dynamic frequency switching (dfs) ? for more information. 6. bus-to-core multipliers less than 5x require that assertion of aack be delayed by one or two bus cycles to allow the processor to generate a response to a snooped transaction. see the mpc7450 risc microprocessor reference manual for more information. table 12. mpc7448 microprocessor pll configuration example (continued) pll_cfg[0:5] example core and vco frequency in mhz bus-to-core multiplier 5 core-to-vco multiplier 5 bus (sysclk) frequency 33.3 mhz 50 mhz 66.6 mhz 75 mhz 83 mhz 100 mhz 133 mhz 167 mhz 200 mhz
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 37 system design information 9.1.2 system bus clock (sysclk) and spread spectrum sources spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (emi) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industr y and government requirements. thes e clock sources intentionally add long-term jitter in order to diffuse the emi spec tral content. the jitter specification given in table 8 considers short-term (cycle-to-cycle) jitter only and the clock generator?s cycle-to-cycle output jitter should meet the mpc7448 input cycle-to-cycle jitter requirement. frequency modulation and spread are separate concerns, and the mpc7448 is compatible with spread spectrum sources if the recommendations listed in table 13 are observed. it is imperative to note that the processor?s minimum and maximum sysclk, core, and vco frequencies must not be exceeded regardless of the type of clock source. therefore, systems in which the processor is operated at its maximum rated core or bus freque ncy should avoid violating the stated limits by using down-spreading only. 9.2 power supply design and sequencing the following sections provide detailed informa tion regarding power supply design for the mpc7448. 9.2.1 power supply sequencing the mpc7448 requires its power rails and clock to be applied in a specific sequence to ensure proper device operation and to prevent device damage. th e power sequencing requirements are as follows: ?av dd must be delayed with respect to v dd by the rc time constant of the pll filter circuit described in section 9.2.2, ?pll power supply filtering?. this time constant is nominally 100 s. ?ov dd may ramp anytime before or after v dd and av dd . additionally, the following requirements exist regarding the application of sysclk: ? the voltage at the sysclk input must not exceed v dd until v dd has ramped to 0.9 v. ? the voltage at the sysclk input must not exceed ov dd by more 20% during transients (see overshoot/undershoot specifications in figure 2 ) or 0.3 v dc (see table 2 ) at any time. table 13. spread spectrum clock source recommendations at recommended operating conditions. see ta b l e 4 . parameter min max unit notes frequency modulation ? 50 khz 1 frequency spread ? 1.0 % 1, 2 notes: 1. guaranteed by design 2. sysclk frequencies resulting from frequency spreading, and the resulting core and vco frequencies, must meet the minimum and maximum specifications given in table 8 .
mpc7448 risc microprocessor hardware specifications, rev. 4 38 freescale semiconductor system design information these requirements are shown graphically in figure 16 . figure 16. mpc7448 power up sequencing requirements certain stipulations also apply to the manner in which the power rails of the mpc7448 power down, as follows: ?ov dd may ramp down any time before or after v dd . ? the voltage at the sysclk input must not exceed v dd once v dd has ramped down below 0.9 v. ? the voltage at the sysclk input must not exceed ov dd by more 20% during transients (see overshoot/undershoot specifications in figure 2 ) or 0.3 v dc (see table 2 ) at any time. av dd v dd ov dd sysclk 0.9 v no restrictions between ov dd and v dd 0.9 v limit imposed by v dd if ov dd ramps up first limit imposed by ov dd if v dd ramps up first 100 s (nominal) delay from v dd to av dd
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 39 system design information figure 17. mpc7448 power down sequencing requirements there is no requirement regarding av dd during power down, but it is recommended that av dd track v dd within the rc time constant of the pll filter circuit described in section 9.2.2, ?pll power supply filtering? (nominally 100 s). 9.2.2 pll power supply filtering the av dd power signal is provided on the mpc7448 to provi de power to the clock generation pll. to ensure stability of the internal clock, the power supplied to the av dd input signal should be filtered of any noise in the 500-khz to 10-mhz resonant frequency range of the pll. the circuit shown in figure 18 using surface mount capacitors with minimum effectiv e series inductance (esl) is strongly recommended. in addition to filtering noise from the av dd input, it also provides the required delay between v dd and av dd as described in section 9.2.1, ?power supply sequencing.? the circuit should be placed as close as possible to the av dd pin to minimize noise coupled from nearby circuits. it is often possible to route directly from the capacitors to the av dd pin, which is on the periphery of the device footprint. figure 18. pll power supply filter circuit v dd ov dd no restrictions between v dd and ov dd sysclk 0.9 v av dd no restrictions between v dd and av dd note also restrictions between sysclk and ov dd 0.9 v limit imposed by v dd if v dd ramps down first limit imposed by ov dd if ov dd ramps down first v dd av dd 10 2.2 f 2.2 f gnd low esl surface mount capacitors
mpc7448 risc microprocessor hardware specifications, rev. 4 40 freescale semiconductor system design information 9.2.3 transient specifications the ensure the long-term reliability of the device, the mpc7448 requires that transients on the core power rail (v dd ) be constrained. the recommended operati ng voltage specifications provided in table 4 are dc specifications. that is, the device may be operated continuously with v dd within the specified range without adversely affecting the device?s reliability . excursions above the stated recommended operation range, including overshoot during power-up, can impact the long-term reliability of the device. excursions are described by their amplitude and duration. duration is defined as the time period during which the v dd power plane, as measured at the vdd_sense pins, will be within a specific voltage range, expressed as percentage of the total time the device will be powered up over the device lifetime. in practice, the period over which transients are measured can be any arbitrary period of time that accurately represents the expected range of processor and system activity. the voltage ranges and dura tions for normal operation and transients are described in table 14 . note that, to simplify transient measurements, the duration of the excursion into the high transient region is also included in the low transient duration, so that only the time the voltage is above each threshold must be considered. figure 19 shows an example of measuring voltage transients. figure 19. voltage transient example table 14. vdd power supply transient specifications at recommended operating temperatures. see ta b l e 4 . voltage region voltage range (v) permitted duration 1 notes min max normal v dd minimum v dd maximum 100% 2 low transient v dd maximum 1.35 v 10% 2, 3 high transient 1.35 v 1.40 v 0.2% 4 notes: 1. permitted duration is defined as the percentage of the total time the device is powered on that the v dd power supply voltage may exist within the specified voltage range. 2. see table 4 for nominal v dd specifications. 3. to simplify measurement, excursions into the high transient region are included in this duration. 4. excursions above the absolute maximum rating of 1.4 v are not permitted; see ta b l e 2 . v dd (nominal) 1.40 v a + b < t ? 10% 1.35 v v dd (maximum) a c b t c < t ? 0.2% v dd (minimum) normal low transient high transient
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 41 system design information 9.2.4 decoupling recommendations due to the mpc7448 dynamic power management feat ure, large address and data buses, and high operating frequencies, the mpc7448 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the mpc7448 system, and the mpc7448 itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer use sufficient decoupling capacitors, typically one capacitor for every v dd pin, and a similar amount for the ov dd pins, placed as close as possible to the power pins of the mpc7448. it is also recommended that these decoupling capacitors receive their power from separate v dd , ov dd , and gnd power planes in the pcb, using short traces to minimize inductance. these capacitors should have a value of 0.01 or 0.1 f. only ceramic surface mount technology (smt) capacitors should be used to minimize lead inductan ce. orientations where connections are made along the length of the part, such as 0204, are preferable but not mandatory. consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993) and contrary to previous recommendations for decoupling freescale microprocessors, multiple small capacitors of equal value are recommended over using multiple values of capacitance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd and ov dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low equivalent series resist ance (esr) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors are 100?330 f (avx tps tantalum or sanyo oscon). 9.3 connection recommendations to ensure reliable operation, it is highly recommende d to connect unused inputs to an appropriate signal level. unless otherwise noted, unused active low inputs should be tied to ov dd and unused active high inputs should be connected to gnd. all nc (no connect) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , and gnd pins in the mpc7448. for backward compatibility with the mpc7447, mpc7445, and mp7441, or for migrating a system originally designed for one of these devices to th e mpc7448, the new power and ground signals (formerly nc, see table 11 ) may be left unconnected if the core freque ncy is 1 ghz or less. operation above 1 ghz requires that these additional power and ground signals be connected, and it is strongly recommended that all new designs include the additional connections. see also section 7, ?pinout listings,? for additional information. the mpc7448 provides vdd_sense, ovdd_sense, and gnd_sense pins. these pins connect directly to the power/ground planes in the device pack age and are intended to allow an external device to measure the voltage present on the v dd , ov dd and gnd planes in the device package. the most common use for these signals is as a feedback signal to a power supply regulator to allow it to compensate for board losses and supply the correct voltage at the device. (n ote that all voltage parameters are specified at the pins of the device.) if not used for this purpose, it is recommended that these signa ls be connected to test points that can be used in the event that an accurate measurement of the voltage at the device is needed during system debug. otherwise, these signals shou ld be connected to the appropriate power/ground planes on the circuit board or left unconnected.
mpc7448 risc microprocessor hardware specifications, rev. 4 42 freescale semiconductor system design information 9.4 output buffer dc impedance the mpc7448 processor bus drivers are characterized over process, voltage, and temperature. to measure z 0 , an external resistor is connected from the chip pad to ov dd or gnd. the value of each resistor is varied until the pad voltage is ov dd /2. figure 20 shows the driver impedance measurement. figure 20. driver impedance measurement the output impedance is the average of two components?the resistances of the pull-up and pull-down devices. when data is held low, sw2 is closed (sw1 is open), and r n is trimmed until the voltage at the pad equals ov dd /2. r n then becomes the resistance of the pull-down devices. when data is held high, sw1 is closed (sw2 is open), and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. table 15 summarizes the signal impedance results. the impedance increases with junction temperature and is relatively unaffected by bus voltage. 9.5 pull-up/pull-down resistor requirements the mpc7448 requires high-resistive (weak: 4.7-k ) pull-up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the mpc7448 or other bus masters. these pins are: ts , artry , shdo , and shd1 . some pins designated as being factory test pins must be pulled up to ov dd or down to gnd to ensure proper device operation. the pins that must be pulled up to ov dd are lssd_mode and test[0:3]; the pins that must be pulled down to gnd are l1_tstclk and test[4]. the ckstp_in signal should table 15. impedance characteristics at recommended operating conditions. see table 4 impedance processor bus unit z 0 typical 33?42 maximum 31?51 ov dd ognd r p r n pad data sw1 sw2
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 43 system design information likewise be pulled up through a pull-up resistor (weak or stronger: 4.7?1 k ) to prevent erroneous assertions of this signal. in addition, the mpc7448 has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7?1 k ) if it is used by the system. this pin is ckstp_out . bvsel0 and bvsel1 should not be allowed to float, and should be configured either via pull-up or pull-down resistors or actively driven by external logic. if pull-down resistors are used to configure bvsel0 or bvsel1, the resistors should be less than 250 (see table 11 ). because pll_cfg[0:5] must remain stable during normal operation, strong pull-up and pull-down resistors (1 k or less) are recommended to configure these signals in order to protect against erroneous switching due to ground bounce, power supply noise, or noise coupling. during inactive periods on the bus, the address and transf er attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. because the mpc7448 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the mpc7448 or by other receivers in the system. these signals can be pulled up through weak (10-k ) pull-up resistors by the system, address bus driven mode enabled (see the mpc7450 risc microprocessor family users? manual for more information on this mode), or they may be otherwise driven by the system during inactive peri ods of the bus to avoid this additional power draw. preliminary studies have shown th e additional power draw by the mpc7448 input receivers to be negligible and, in any event, none of these measures are necessary for proper device operation. the snooped address and transfer attribute inputs are: a[0:35], ap[0:4], tt[0:4], ci , wt , and gbl . if address or data parity is not used by the system, and respective parity checking is disabled through hid1, the input receivers for those pins are disabled and do not require pull-up resistors, therefore they may be left unconnected by the system. if extended addressing is not used (hid0[xaen] = 0), a[0:3] are unused and must be pulled low to gnd through weak pull-down re sistors; additionally, if address parity checking is enabled (hid1[eba] = 1) and extended addressing is not used, ap[0] must be pulled up to ov dd through a weak pull-up resistor. if the mpc7448 is in 60x bus mode, dti[0:3] must be pulled low to gnd through weak pull-down resistors. the data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. other data bus receivers in the system, however, may require pull-ups or require that those signals be otherwise driven by the system during inactive periods. the data bus signals are d[0:63] and dp[0:7]. 9.6 jtag configuration signals boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 standard specification, but is typically provided on all processors that implement the powerpc architecture. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power-on reset performance will be obtained if the trst signal is asserted during power-on reset. because the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these processors allows a remote computer system (typically a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order
mpc7448 risc microprocessor hardware specifications, rev. 4 44 freescale semiconductor system design information to fully control the processor. if the target system ha s independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 21 allows the cop port to independently assert hreset or trst , while ensuring that the target can drive hreset as well. if the jtag interface and cop header will not be used, trst should be tied to hreset through a 0- isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during power-on. although freescale recommends that the cop header be designed into the system as shown in figure 21 , if this is not possible, the isolation resistor will allow future access to trst in the case where a jtag interface may need to be wired onto the system in debug situations. the cop header shown in figure 21 adds many benefits?breakpoints, wa tchpoints, register and memory examination/modification, and othe r standard debugger features are possible through this interface?and can be as inexpensive as an unpopulated footpr int for a header to be added when needed. the cop interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. there is no standardized way to number the cop header shown in figure 21 ; consequently, many different pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top- to-bottom, while still others number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal placement recommended in figure 21 is common to all known emulators. the qack signal shown in figure 21 is usually connected to the bridge chip or other system control logic in a system and is an input to the mpc7448 informi ng it that it can go into the quiescent state. under normal operation this occurs during a low-power mode selection. in order for cop to work, the mpc7448 must see this signal asserted (pulled down). while shown on the cop header, not all emulator products drive this signal. if the product does not, a pull-down resistor can be populated to assert this signal. additionally, some emulator products implement open-drain type outputs and can only drive qack asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is negated when it is not being driven by the tool. note that the pull-up and pull-down resistors on the qack signal are mutually exclusive and it is never necessary to popul ate both in a system. to preserve correct power-down operation, qack should be merged through logic so that it also can be driven by the bridge or system logic.
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 45 system design information figure 21. jtag interface connection hreset hreset 6 from target board sources hreset 13 sreset sreset sreset nc nc 11 vdd_sense 6 5 1 15 2 k 10 k 10 k 10 k ov dd ov dd ov dd ov dd chkstp_in chkstp_in 8 tms tdo tdi tck tms tdo tdi tck 9 1 3 4 trst 7 16 2 10 12 (if any) cop header 14 2 key qack ov dd ov dd 10 k ov dd 10 k ov dd 10 k 10 k qack qack chkstp_out chkstp_out 3 13 9 5 1 6 10 2 15 11 7 16 12 8 4 key no pin cop connector physical pin out 10 k 4 ov dd 1 2 k 3 0 5 notes: 1. run/stop , normally found on pin 5 of the cop header, is not implemented on the mpc7448. connect pin 5 of the cop header to ov dd with a 10-k pull-up resistor. 2. key location; pin 14 is not physically present on the cop header. 3. component not populated. populate only if debug tool does not drive qack . 4. populate only if debug tool uses an open-drain type output and does not actively negate qack . 5. if the jtag interface is implemented, connect hreset from the target source to trst from the cop header though an and gate to trst of the part. if the jtag interface is not implemented, connect hreset from the target source to trst of the part through a 0- isolation resistor. 6. the cop port and target board should be able to independently assert hreset and trst to the processor in order to fully control the processor as shown above. trst 6 10 k ov dd
mpc7448 risc microprocessor hardware specifications, rev. 4 46 freescale semiconductor system design information 9.7 power and thermal management information this section provides thermal mana gement information for the high co efficient of thermal expansion (hcte) package for air-cooled applications. proper th ermal control design is pr imarily dependent on the system-level design?the heat sink, airflow, and thermal interface materi al. the mpc7448 implements several features designed to assist with thermal management, including dfs and the temperature diode. dfs reduces the power consumption of the device by reducing the core frequency; see section 9.7.5.1, ?power consumption with dfs enabled,? for specific information regarding power reduction and dfs. the temperature diode allows an external device to monitor the die temperature in order to detect excessive temperature conditions and alert the system; see section 9.7.4, ?temperature diode,? for more information. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods?spring clip to holes in the printed-circu it board or package, and mounting clip and screw assembly (see figure 22 ); however, due to the potential large mass of the heat sink, attachment through the printed-circuit board is suggested. in any implement ation of a heat sink solution, the force on the die should not exceed ten pounds (45 newtons). figure 22. bga package exploded cross-sectional view with several heat sink options note a clip on heat sink is not recommended for lga because there may not be adequate clearance between the devi ce and the circuit board. a through-hole solution is recommended, as shown in figure 23 . thermal heat sink hcte bga package heat sink clip printed-circuit board interface material
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 47 system design information figure 23. lga package exploded cross-sectional view with several heat sink options there are several commercially-available heat si nks for the mpc7448 provided by the following vendors: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com alpha novatech 408-567-8082 473 sapena ct. #12 santa clara, ca 95054 internet: www.alphanovatech.com calgreg thermal solutions 888-732-6100 60 alhambra road, suite 1 warwick, ri 02886 internet: www.calgregthermalsolutions.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com tyco electronics 800-522-6752 chip coolers? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.tycoelectronics.com wakefield engineering 603-635-2800 33 bridge st. pelham, nh 03076 internet: www.wakefield.com ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air veloc ity, spatial volume, mass, attachme nt method, assembly, and cost. thermal heat sink hcte lga package heat sink clip printed-circuit board interface material
mpc7448 risc microprocessor hardware specifications, rev. 4 48 freescale semiconductor system design information 9.7.1 internal package conduction resistance for the exposed-die packaging technology described in table 5 , the intrinsic conduction thermal resistance paths are as follows: ? the die junction-to-case thermal resistance (the case is actually the top of the exposed silicon die) ? the die junction-to-board thermal resistance figure 24 depicts the primary heat transfer path for a pa ckage with an attached heat sink mounted to a printed-circuit board. figure 24. c4 package with heat sink mounted to a printed-circuit board heat generated on the active side of the chip is conducted through the silicon, through the heat sink attach material (or thermal interface material), and, finally, to the heat sink, where it is removed by forced-air convection. because the silicon thermal resistance is quite small, the temperature drop in the silicon may be neglected for a first-order analysis. thus, the thermal interf ace material and the heat sink conduction/convective thermal resistances are the dominant terms. 9.7.2 thermal interface materials a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 25 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, fluoroether oil), a bare joint, a nd a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 22 ). therefore, synthetic grease offers the best thermal performance due to the low interface pressure and is recommended due to the high power di ssipation of the mpc7448. of course, the selection external resistance external resistance internal resistance radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package (note the internal versus external package resistance.)
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 49 system design information of any thermal interface material depends on many factors?thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, and so on. figure 25. thermal performance of select thermal interface material the board designer can choose between several types of thermal interfaces. heat sink adhesive materials should be selected based on high conductivity and mechan ical strength to meet equipment shock/vibration requirements. there are several commercially available thermal interfaces and adhesive materials provided by the following vendors: the bergquist company 800-347-4572 18930 west 78 th st. chanhassen, mn 55317 internet: www.bergquistcompany.com chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01801 internet: www.chomerics.com dow-corning corporation 800-248-2481 corporate center p.o. box 994. midland, mi 48686-0994 internet: www.dowcorning.com 0 0.5 1 1.5 2 0 1020304050607080 silicone sheet (0.006 in.) bare joint fluoroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
mpc7448 risc microprocessor hardware specifications, rev. 4 50 freescale semiconductor system design information shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com laird technologies - thermal 888-246-905 (formerly thermagon inc.) 4707 detroit ave. cleveland, oh 44102 internet: www.lairdtech.com the following section provides a heat sink selection ex ample using one of the commercially available heat sinks. 9.7.3 heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t i + t r + (r jc + r int + r sa ) p d where: t j is the die-junction temperature t i is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet r jc is the junction-to-case thermal resistance r int is the adhesive or interface material thermal resistance r sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation, the die-junction temperatures (t j ) should be maintained less than the value specified in table 4 . the temperature of air cooling the component gr eatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t i ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the thermal interface material (r int ) is typically about 1.1 c/w. for example, assuming a t i of 30 c, a t r of 5 c, an hcte package r jc = 0.1, and a power consumption (p d ) of 25.6 w, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.1 c/w + 1.1 c/w + sa ) 25.6 for this example, a r sa value of 1.53 c/w or less is required to maintain the die junction temperature below the maximum value of table 4 . though the die junction-to-ambient and the heat si nk-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise cauti on when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. the final die-junction operating temperature is not only a function of th e component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the final operating die-j unction temperature?airflow, board population (local heat flux of adjacent components), h eat sink efficiency, heat sink attach , heat sink placement, next-level interconnect technology, system air temperature rise, altitude, and so on.
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 51 system design information due to the complexity and variety of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transf er mechanisms (radiation, convection, and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board as well as system-level designs. for system thermal modeling, the mpc7448 thermal model is shown in figure 26 . four volumes represent this device. two of the volumes, solder ball-air and substrate, are modeled using the package outline size of the package. the other two, die and bump-underfill, have the same size as the die. the silicon die should be modeled 8.0 7.3 0.86 mm 3 with the heat source applied as a uniform source at the bottom of the volume. the bump and underfill layer is modeled as 8.0 7.3 0.07 mm 3 collapsed in the z-direction with a thermal conductivity of 5.0 w/(m ? k) in the z-direction. the substrate volume is 25 25 1.14 mm 3 and has 9.9 w/(m ? k) isotropic conductivity in the xy-plane and 2.95 w/(m ? k) in the direction of the z-axis. the solder ball and air layer are modeled with the same horizontal dimensions as the substrate and is 0.8 mm thick. for the lga package the solder and air layer is 0.1 mm thick, but the material properties are the same. it can also be modeled as a collapsed volume using orthotropic material properties: 0.034 w/(m ? k) in the xy-plane direction and 11.2 w/(m ? k) in the direction of the z-axis. figure 26. recommended thermal model of mpc7448 bump and underfill die substrate solder and air die substrate side view of model (not to scale) top view of model (not to scale) x y z conductivity value unit die (8.0 7.3 0.86 mm 3 ) silicon temperature- dependent w/(m ? k) bump and underfill (8.0 7.3 0.07 mm 3 ) k z 5.0 w/(m ? k) substrate (25 25 1.14 mm 3 ) k x 9.9 w/(m ? k) k y 9.9 k z 2.95 solder ball and air (25 25 0.8 mm 3 ) k x 0.034 w/(m ? k) k y 0.034 k z 11.2
mpc7448 risc microprocessor hardware specifications, rev. 4 52 freescale semiconductor system design information 9.7.4 temperature diode the mpc7448 has a temperature diode on the microproces sor that can be used in conjunction with other system temperature monitoring devices (such as analog devices, adt7461?). these devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment. for proper operation, the monitoring device used should auto-calibrate the device by canceling out the v be variation of each mpc7448?s internal diode. the following are the specifications of the mpc7448 on-board temperature diode: v f > 0.40 v v f < 0.90 v operating range 2?300 a diode leakage < 10 na @ 125 c ideality factor over 5?150 a at 60 c: n = 1.0275 0.9% ideality factor is defined as the de viation from the ideal diode equation: another useful equation is: where: i fw = forward current i s = saturation current v d = voltage at diode v f = voltage forward biased v h = diode voltage while i h is flowing v l = diode voltage while i l is flowing i h = larger diode bias current i l = smaller diode bias current q = charge of electron (1.6 x 10 ?19 c) n = ideality factor (normally 1.0) k = boltzman?s constant (1.38 x 10 ?23 joules/k) t = temperature (kelvins) the ratio of i h to i l is usually selected to be 10:1. the previous equation simplifies to the following: i fw = i s e ? 1 qv f ___ nkt v h ? v l = n ln ? 1 kt __ q i h __ i l v h ? v l = 1.986 10 ?4 nt
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 53 system design information solving for t, the equation becomes: 9.7.5 dynamic frequency switching (dfs) the dfs feature in the mpc7448 adds the ability to divide the processor-to-system bus ratio by two or four during normal functional operati on. divide-by-two mode is enabled by setting the hid1[dfs2] bit in software or by asserting the dfs2 pin via hardware. the mpc7448 can be returned for full speed by clearing hid1[dfs2] or negating dfs2 . similarly, divide-by-four mode is enabled by setting hid1[dfs4] in software or by asserting the dfs4 pin. in all cases, the frequency change occurs in 1 clock cycle and no idle waiting period is required to switch between modes. note that asserting either dfs2 or dfs4 overrides software control of dfs, and that asserting both dfs2 and dfs4 disables dfs completely, including software control. additiona l information regarding dfs can be found in the mpc7450 risc microprocessor family reference manual. note that minimum core frequency requirements must be observed when enabling dfs, and the resulting core frequency must meet the requirements for f core_dfs given in table 8 . 9.7.5.1 power consumption with dfs enabled power consumption with dfs enabled can be approximated using the following formula: where: p dfs = power consumption with dfs enabled f dfs = core frequency with dfs enabled f = core frequency prior to enabling dfs p = power consumption prior to enabling dfs (see table 7 ) p ds = deep sleep mode power consumption (see table 7 ) the above is an approximation only. power consumption with dfs enab led is not tested or guaranteed. 9.7.5.2 bus-to-core multiplier constraints with dfs dfs is not available for all bus-to-core multipliers as configured by pll_cfg[0:5] during hard reset. the complete listing is shown in table 16 . shaded cells represent dfs modes that are not available for a particular pll_cfg[0:5] setting. should software or hardware attempt to transition to a multiplier that is not supported, the device will remain at its current multiplier. for example, if a transition from dfs-disabled to an unsupported divide-by-2 or divide -by-4 setting is attempted, the bus-to-core multiplier will remain at the setting configured by the pll_cfg[0:5] pins. in the case of an attempted transition from a supported divide-by-2 mode to an unsupported divide- by-4 mode, the device will remain in divide-by-2 mode. in all cases, the hid1[pc0-5] bits will correctly reflect the current bus-to-core frequency multiplier. nt = v h ? v l __________ 1.986 10 ?4 p dfs = (p? p ds ) + p ds f dfs ___ f
mpc7448 risc microprocessor hardware specifications, rev. 4 54 freescale semiconductor system design information table 16. valid divide ratio configurations dfs mode disabled dfs divide-by-2 mode enabled (hid1[dfs2] = 1 or dfs2 =0) dfs divide-by-4 mode enabled (hid1[dfs4] = 1 or dfs4 =0) bus-to-core multiplier configured by pll_cfg[0:5] (see table 12 ) hid1[pc0-5] 3 bus-to-core multiplier hid1[pc0-5] 3 bus-to-core multiplier hid1[pc0-5] 3 2x 4 010000 n/a (unchanged) 1 unchanged 1 n/a (unchanged) 1 unchanged 1 3x 4 100000 n/a (unchanged) 1 unchanged 1 n/a (unchanged) 1 unchanged 1 4x 4 101000 2x 4 010000 n/a (unchanged) 1 unchanged 1 5x 101100 2.5x 4 010101 n/a (unchanged) 1 unchanged 1 5.5x 100100 2.75x 4 110101 2 n/a (unchanged) 1 unchanged 1 6x 110100 3x 4 100000 n/a (unchanged) 1 unchanged 1 6.5x 010100 3.25x 4 100000 2 n/a (unchanged) 1 unchanged 1 7x 001000 3.5x 4 110101 n/a (unchanged) 1 unchanged 1 7.5x 000100 3.75x 4 110101 2 n/a (unchanged) 1 unchanged 1 8x 110000 4x 4 101000 4 2x 4 010000 8.5x 011000 4.25x 4 101000 2 n/a (unchanged) 1 unchanged 1 9x 011110 4.5x 4 011101 2.25x 4 010000 2 9.5x 011100 4.75x 4 011101 2 n/a (unchanged) 1 unchanged 1 10x 101010 5x 101100 2.5x 4 010101 10.5x 100010 5.25x 101100 2 n/a (unchanged) 1 unchanged 1 11x 100110 5.5x 100100 2.75x 4 010101 2 11.5x 000000 5.75x 100100 2 n/a (unchanged) 1 unchanged 1 12x 101110 6x 110100 3x 4 100000 12.5x 111110 6.25x 110100 2 n/a (unchanged) 1 unchanged 1 13x 010110 6.5x 010100 3.25x 4 100000 2 13.5x 111000 6.75 010100 2 n/a (unchanged) 1 unchanged 1 14x 110010 7x 001000 3.5x 4 110101 15x 000110 7.5x 000100 3.75x 4 110101 2 16x 110110 8x 110000 4x 4 101000 17x 000010 8.5x 011000 4.25x 4 101000 2 18x 001010 9x 011110 4.5x 4 011101 20x 001110 10x 101010 5x 101100 21x 010010 10.5x 100010 5.25x 101100 2
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 55 document revision history 9.7.5.3 minimum core frequency requirements with dfs in many systems, enabling dfs can result in very low processor core frequencies. however, care must be taken to ensure that the resulting processor core frequency is within the limits specified in table 8 . proper operation of the device is not guaranteed at co re frequencies below the specified minimum f core . 10 document revision history table 17 provides a revision history for this hardware specification. 24x 011010 12x 101110 6x 110100 28x 111010 14x 110010 7x 001000 notes: 1. dfs mode is not supported for this combination of dfs mode and pll_cfg[0:5] setting. as a result, the processor will ignore these settings and remain at the previous multiplier, as reflected by the hid1[pc0-pc5] bits. 2. though supported by the mpc7448 clock circuitry, multipliers of n .25x and n .75x cannot be expressed as valid pll configuration codes. as a result, the values displayed in hid1[pc0-pc5] are rounded down to the nearest valid pll configuration code. however, the actual bus-to-core multiplier is as stated in this table. 3. note that in the hid1 register of the mpc7448, the pc0, pc1, pc2, pc3, pc4, and pc5 bits are bits 15, 16, 17, 18, 19, and 14 (respectively). see the mpc7450 risc microprocessor reference manual for more information. 4. special considerations regarding snooped transactions must be observed for bus-to-core multipliers less than 5x. see the mpc7450 risc microprocessor reference manual for more information. table 17. document revision history revision date substantive change(s) 4 3/2007 tab le 1 9 : added 800 mhz processor frequency. 3 10/2006 section 9.7, ?power and thermal management information ?: updated contact information. tab le 1 8 , ta b l e 2 0 , and ta b l e 1 9 : added revision d pvr. tab le 1 9 : added 600 processor frequency, additional product codes, date codes for 1400 processor frequency, and footnotes 1 and 2. tab le 2 0 : added ppc product code and footnote 1. tab le 1 9 and ta b l e 2 0 : added revision d information for 1267 processor frequency. table 16. valid divide ratio configurations (continued) dfs mode disabled dfs divide-by-2 mode enabled (hid1[dfs2] = 1 or dfs2 =0) dfs divide-by-4 mode enabled (hid1[dfs4] = 1 or dfs4 =0) bus-to-core multiplier configured by pll_cfg[0:5] (see table 12 ) hid1[pc0-5] 3 bus-to-core multiplier hid1[pc0-5] 3 bus-to-core multiplier hid1[pc0-5] 3
mpc7448 risc microprocessor hardware specifications, rev. 4 56 freescale semiconductor document revision history 2 table 6: added separate input leakage specification for bvsel0, lssd_mode , tck , tdi, tms, trst signals to correctly indicate leakage current for signals with internal pull-up resistors. section 5.1: added paragraph preceding table 7 and edited notes in table 7 to clarify core frequencies at which power consumption is measured. section 5.3: removed voltage derating specifications; this feature has been made redundant by new device offerings and is no longer supported. changed names of ?typical?nominal? and ?typical?thermal? power consumption parameters to ?typical? and ?thermal?, respectively. (name change only?no specifications were changed.) table 11: revised notes 16, 18, and 19 to reflect current recommendations for connection of sense pins. section 9.3: added paragraph explaining connection recommendations for sense pins. (see also table 11 entry above.) table 19: updated table to reflect changes in specifications for mc7448xxnnnnnc devices. table 9: changed all instances of tt[0:3] to tt[0:4] removed mention of these input signals from output valid times and output hold times: ? aack, ckstp_in, dt[0:3] figure 17: modified diagram slightly to correctly show constraint on sysclk ramping is related to v dd voltage, not av dd voltage. (diagram clarification only; no change in power sequencing requirements.) added table 20 to reflect introduction of extended temperature devices and associated hardware specification addendum. 1 added 1600 mhz, 1420 mhz, and 1000 mhz devices section 4: corrected die size table 2: revised note 4 to consider overshoot/undershoot and combined with note 5. table 4: revised operating voltage for 1700 mhz device from 50 mv to +20 mv / ?50 mv. table 7: updated and expanded table to include typical ? nominal power consumption. table 11: added voltage derating information for 1700 mhz devices; this feature is not supported at this time for other speed grades. added transient specifications for vdd power supply in section 9.2.3, added table 15 and figure 19 and renumbered subsequent tables and figures. moved decoupling recommendations from section 9.4 to section 9.2.4 and renumbered subsequent sections. section 9.2.1: revised power sequencing requirements. section 9.7.4: added thermal diode ideality factor information (previously tbd). table 17: expanded table to show hid1 register values when dfs modes are enabled. section 11.2: updated to include additional n-spec device speed grades tables 18 and 19: corrected pvr values and added ?mc? product code prefix 0 initial public release. table 17. document revision history (continued) revision date substantive change(s)
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 57 part numbering and marking 11 part numbering and marking ordering information for the part numbers fully cove red by this specification document is provided in section 11.1, ?part numbers fully addressed by this document.? note that the individual part numbers correspond to a maximum processor core frequency. fo r available frequencies, contact a local freescale sales office. in addition to the processor frequency, th e part numbering scheme also includes an application modifier that may specify special application cond itions. an optional specification modifier may also apply for parts to indicate a specific change in speci fications, such as support for an extended temperature range. finally, each part number contains a revision level code that refers to the die mask revision number. section 11.2, ?part numbers not fully addressed by this document,? lists the part numbers that do not fully conform to the specifications of this document. these special part numbers require an additional document called a hardware specification addendum. 11.1 part numbers fully addressed by this document table 18 provides the freescale part numbering nomenclature for the mpc7448 part numbers fully addressed by this document. for information regarding other mpc7448 part numbers, see section 11.2, ?part numbers not fully addressed by this document.? table 18. part numbering nomenclature xx 7448 xx nnnn l x product code part identifier package processor frequency application modifier revision level mc ppc 1 7448 hx = hcte bga vs = rohs lga vu = rohs bga 1700 l: 1.3 v +20/?50 mv 0 to 105 c c: 2.1; pvr = 0x8004_0201 d: 2.2; pvr = 0x8004_0202 1600 l: 1.25 v 50 mv 0 to 105 c 1420 l: 1.2 v 50 mv 0 to 105 c 1000 l: 1.15 v 50 mv 0 to 105 c notes: 1. the p prefix in a freescale part number designates a ?pilot production prototype? as defined by freescale sop 3-13. these parts have only preliminary reliability and characterization data. before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur as pilot production prototypes are shipped.
mpc7448 risc microprocessor hardware specifications, rev. 4 58 freescale semiconductor part numbering and marking 11.2 part numbers not fully addressed by this document parts with application modifiers or revision levels not fully addressed in this specification document are described in separate hardware sp ecification addenda which supplement and supersede this document. as such parts are released, these specifications will be listed in this section. table 19. part numbers addressed by mc7448 xxnnnn n x series hardware specification addendum (document order no. mpc7448ecs01ad) xx 7448 xx nnnn n x product code part identifier package processor frequency application modifier revision level mc 7448 hx = hcte bga vs = rohs lga vu = rohs bga 1400 n: 1.15 v 50 mv 0 to 105 c (date code 0613 and later) 2 c: 2.1; pvr = 0x8004_0201 d: 2.2; pvr = 0x8004_0202 mc ppc 1 1400 n: 1.1 v 50 mv 0 to 105 c (date code 0612 and prior) 2 mc ppc 1 1267 revision c only n: 1.1 v 50 mv 0 to 105 c mc ppc 1 1267 revision d only n: 1.05 v 50 mv 0 to 105 c mc ppc 1 1250 n: 1.1 v 50 mv 0 to 105 c mc ppc 1 1000 867 800 667 600 n: 1.0 v 50 mv 0 to 105 c notes: 1. the p prefix in a freescale part number designates a ?pilot production prototype? as defined by freescale sop 3-13. these parts have only preliminary reliability and characterization data. before pilot production prototypes can be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur as pilot production prototypes are shipped. 2. core voltage for 1400 mhz devices currently in production (date code of 0613 and later) is 1.15 v 50 mv; all such devices have the mc product code. the 1400 mhz devices with date code of 0612 and prior specified core voltage of 1.1 v 50 mv; this includes all 1400 mhz devices with the ppc product code. see section 11.3, ?part marking,? for information on part marking.
mpc7448 risc microprocessor hardware specifications, rev. 4 freescale semiconductor 59 part numbering and marking 11.3 part marking parts are marked as the example shown in figure 27 . figure 27. part marking for bga and lga device table 20. part numbers addressed by mc7448t xxnnnn n x series hardware specification addendum (document order no. mpc7448ecs02ad) xx 7448 t xx nnnn n x product code part identifier specificatio n modifier package processor frequency application modifier revision level mc ppc 1 7448 t = extended temperature device hx = hcte bga 1400 n: 1.15 v 50 mv ? 40 to 105 c c: 2.1; pvr = 0x8004_0201 d: 2.2; pvr = 0x8004_0202 1267 revision c only n: 1.1 v 50 mv ? 40 to 105 c 1267 revision d only n: 1.05 v 50 mv ? 40 to 105 c 1000 n: 1.0 v 50 mv ? 40 to 105 c notes: 1. the p prefix in a freescale part number designates a ?pilot production prototype? as defined by freescale sop 3-13. these parts have only preliminary reliability and characterization data. before pilot production prototypes can be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur as pilot production prototypes are shipped. notes : ywwlaz is the assembly traceability code. awlyyww is the test code, where yyww is the date code (yy = year, ww = work week ) mmmmmm is the m00 (mask) number. xx7448 xxnnnnnx awlyyww mmmmmm ywwlaz 7448 bga/lga
document number: mpc7448ec rev. 4 3/2007 freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. the described product is a powerpc microprocessor. the powerpc name is a trademark of ibm corp. and is used under license. ieee stds. 1149.1? and 754? are trademarks of the institute of electrical and electronics engineers, inc., (ieee). this product is not endosed or approved by the ieee. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2005, 2007. information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com email: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 1-800-521-6274 480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064, japan 0120 191014 +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate, tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com
kmc7448vu1400nd information general information package information environmental and compliance information manufacturing and qualification information ordering information product/process chan g e notice ( pcn ) general information parameter value part number kmc7448vu1400nd description apl8,rv2.2.1,1.15v,105c material type tested packaged device life cycle description (code) product newly intro d/ramp-up(1) status active packa g e information parameter value package description fccbga 360 25sq*2.2p1.27 jedec pkg description cbga-b360 pin/lead/ball count 360 package material ceramic mounting style surface mount tape & reel no environmental and com p liance information parameter value pb-free no rohs compliant halogen free yes product content report product content report 2nd level interconnect e1 moisture sensitivity level (msl) 1 floor life unlimited package peak temperature (c) 260 manufacturin g and qualification information parameter value micron size (m) .09 pa g e 1 of 2 05-se p -2007 mhtml:file://y:\avnet\09052007\ fscl\mht\kmc7448vu1400nd.mht
application/qualification tier commercial, industrial orderin g information parameter value last order date last ship date minimum package quantity (mpq) 1 mpq container tray preferred order quantity (poq) 2 poq container box leadtime (weeks) export control classification number (us) 3a991 harmonized tariff (us) disclaimer 8542.31.0000 budgetary price qty 1000+ ($us) - order product/process chan g e notice ( pcn ) number type title issue date effectivity date 12712 product change notice mc7448 second source c4 bump processing 20 jun 2007 18 sep 2007 pa g e 2 of 2 05-se p -2007 mhtml:file://y:\avnet\09052007\ fscl\mht\kmc7448vu1400nd.mht
kmc7448vu1267nd information general information package information environmental and compliance information manufacturing and qualification information ordering information product/process chan g e notice ( pcn ) general information parameter value part number kmc7448vu1267nd description apl8,rv2.2.1,1.1v,105c material type tested packaged device life cycle description (code) product newly intro d/ramp-up(1) status active packa g e information parameter value package description fccbga 360 25sq*2.2p1.27 jedec pkg description cbga-b360 pin/lead/ball count 360 package material ceramic mounting style surface mount tape & reel no environmental and com p liance information parameter value pb-free no rohs compliant halogen free yes product content report product content report 2nd level interconnect e1 moisture sensitivity level (msl) 1 floor life unlimited package peak temperature (c) 260 manufacturin g and qualification information parameter value micron size (m) .09 pa g e 1 of 2 05-se p -2007 mhtml:file://y:\avnet\09052007\ fscl\mht\kmc7448vu1267nd.mht
application/qualification tier commercial, industrial orderin g information parameter value last order date last ship date minimum package quantity (mpq) 1 mpq container tray preferred order quantity (poq) 2 poq container box leadtime (weeks) export control classification number (us) 3a991 harmonized tariff (us) disclaimer 8542.31.0000 budgetary price qty 1000+ ($us) - order product/process chan g e notice ( pcn ) number type title issue date effectivity date 12712 product change notice mc7448 second source c4 bump processing 20 jun 2007 18 sep 2007 pa g e 2 of 2 05-se p -2007 mhtml:file://y:\avnet\09052007\ fscl\mht\kmc7448vu1267nd.mht
kmc7448vs1267nd information general information package information environmental and compliance information manufacturing and qualification information ordering information product/process chan g e notice ( pcn ) general information parameter value part number kmc7448vs1267nd description apl8,rv2.2.1,1.1v,105c material type tested packaged device life cycle description (code) product newly intro d/ramp-up(1) status active packa g e information parameter value package description fcclga 360 25sq*1.9p1.27 jedec pkg description cbga-n360 pin/lead/ball count 360 package material ceramic mounting style surface mount tape & reel no environmental and com p liance information parameter value pb-free no rohs compliant halogen free yes product content report product content report 2nd level interconnect e4 moisture sensitivity level (msl) 1 floor life unlimited package peak temperature (c) 260 manufacturin g and qualification information parameter value micron size (m) .09 pa g e 1 of 2 05-se p -2007 mhtml:file://y:\avnet\09052007\ fscl\mht\kmc7448vs1267nd.mht
application/qualification tier commercial, industrial orderin g information parameter value last order date last ship date minimum package quantity (mpq) 1 mpq container tray preferred order quantity (poq) 2 poq container box leadtime (weeks) export control classification number (us) 3a991 harmonized tariff (us) disclaimer 8542.31.0000 budgetary price qty 1000+ ($us) - order product/process chan g e notice ( pcn ) number type title issue date effectivity date 12712 product change notice mc7448 second source c4 bump processing 20 jun 2007 18 sep 2007 pa g e 2 of 2 05-se p -2007 mhtml:file://y:\avnet\09052007\ fscl\mht\kmc7448vs1267nd.mht

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