cystech electronics corp. spec. no. : c446n6 issued date : 2009.06.15 revised date : 2013.09.06 page no. : 1/7 MTDNK2N6 cystek product specification dual n-channel enhanc ement mode mosfet bv dss 60v i d 0.51a r dson(max) 1.6 MTDNK2N6 description the MTDNK2N6 is a dual n-channel enhancement-mode mosfet, providing the designer with the best combination of fast switching, ruggedized device de sign, low on-resistance and cost effectiveness. the sot-26 package is universally preferred for a ll commercial-industrial surface mount applications. features equivalent circuit ? simple drive requirement MTDNK2N6 ? low on-resistance ? small package outline * with gate protection diode ? pb-free package the following characteristics apply to both tr1 and tr2 absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v ds 60 v gate-source voltage v gs 20 v continuous drain current @t a =25 c (note 1) i d 0.51 a pulsed drain current (note 2, 3) i dm 1.5 a pd 0.96 w total power dissipation @ t a =25 c linear derating factor 0.016 w / c operating junction temperature and storage temperature range tj, tstg -55~+150 c thermal resistance, junction-to-ambient (note 1) rth,ja 130 c/w note : 1.surface mounted on 0.125 in2 copper pad of fr -4 board. 180 /w when mounted on minimum copper pad. 2.pulse width lim ited by maximum junc tion temperature. 3.pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c446n6 issued date : 2009.06.15 revised date : 2013.09.06 page no. : 2/7 MTDNK2N6 cystek product specification e lectrical characteristics (ta=25 c, unless otherwise noted) symbol min. typ. max. unit test conditions bv dss 60 - - v v gs =0v, i d =250 a v gs(th) 1 1.6 2.5 v v ds =v gs , i d =250 a i gss - - 5 a v gs =20v, v ds =0v i dss - - 1 a v ds =60v, v gs =0v i dss - - 10 a v ds =48v, v gs =0v, tj=125 - 1.4 2 i d =100ma, v gs =5v *r ds(on) - 1.1 1.6 i d =500ma, v gs =10v *g fs 200 - - ms v ds =10v, i d =200ma ciss - 62.7 - coss - 17.6 - crss - 9 - pf v ds =25v, v gs =0, f=1mhz t d(on) - 8 20 t r - 7 20 t d(off) - 13 20 t f - 6 20 ns v ds =25v, i d =0.25a, v gs =10v, r g =25 ? qg - 1.1 - qgs - 0.2 - qgd - 0.4 - nc v ds =25v, i d =0.51a, v gs =10v, *pulse test : pulse width 300 s, duty cycle 2% source drain diode symbol min. typ. max. unit test conditions *i s - - 0.51 *i sm - - 1.5 a *v sd - 0.87 1.2 v i s =510ma,v gs =0v *pulse test : pulse width 300 s, duty cycle 2% ordering information device package shipping MTDNK2N6-0-t1-g sot-26 (pb-free lead plating an d halogen-free package) 3000 pcs / tape & reel
cystech electronics corp. spec. no. : c446n6 issued date : 2009.06.15 revised date : 2013.09.06 page no. : 3/7 MTDNK2N6 cystek product specification characteristic curves typical output characteristics 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0123 4 typical output characteristics 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 01234 drain-source voltage---vds(v) drain current --- id(a) drain-source voltage ---vds(v) drain current --- id(a) vgs=3v 6v ta=125c ta=25c 10v 3.5v 4.0v 4.5v vgs=3v 10v 6v 3.5v 4.5v 4.0v typical transfer characteristics 0 100 200 300 400 500 600 700 800 900 1000 0123456 gate-source voltage---vgs(v) drain current ---id(ma) vds=5v breakdown voltage variation with temperature 0.95 0.97 0.99 1.01 1.03 1.05 0255075100125150 junction temperature---tj(c) normalized drain-source breakdown voltage static drain-source on-state resistance vs drain current 1 2 3 0.001 0.01 0.1 1 drain current-id(a) static drain-source on-state resistance- rds(on)() vgs=3.5v vgs=5v ta=25c static drain-source on-state resistance vs drain current 1 2 3 0.001 0.01 0.1 1 drain current-id(a) static drain-source on-state resistance- rds(on)() vgs=3.5v vgs=5v ta=125c
cystech electronics corp. spec. no. : c446n6 issued date : 2009.06.15 revised date : 2013.09.06 page no. : 4/7 MTDNK2N6 cystek product specification characteristic curves(cont.) static drain-source on-state resistance vs gate-source voltage 0 1 2 3 4 5 024681 0 static drain-source on-state resistance vs gate-source voltage 0 1 2 3 4 5 024681 gate-source voltage-vgs(v) static drain-source on-state resistance-rds(on)() 0 id=300ma id=50ma ta=125c gate-source voltage-vgs(v) static drain-source on-state resistance-rds(on)() ta=25c id=300ma id=50ma reverse drain current vs source-drain voltage 0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 reverse drain current -idr(a) source-drain voltage-vsd(v) ta=125c ta=25c capacitance vs drain-to-source voltage 1 10 100 0 5 10 15 20 25 30 drain-source voltage -vds(v) capacitance---(pf) c oss ciss crss
cystech electronics corp. spec. no. : c446n6 issued date : 2009.06.15 revised date : 2013.09.06 page no. : 5/7 MTDNK2N6 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c446n6 issued date : 2009.06.15 revised date : 2013.09.06 page no. : 6/7 MTDNK2N6 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c446n6 issued date : 2009.06.15 revised date : 2013.09.06 page no. : 7/7 MTDNK2N6 cystek product specification sot-26 dimension inches millimeters inches millimeters dim min. max. min. max. j 12 3 4 5 6 a b c d d1 d2 e f g k i l h 6-lead sot-26 plastic surface mounted package cystek package code: n6 style: pin 1. gate 1 (g1) pin 2. source 2 (s2) pin 3. gate 2 (g2) pin 4. drain 2 (d2) pin 5. source 1 (s1) pin 6. drain 1 ( d1 ) device code date code marking: dim min. max. min. max. a 0.1063 0.1220 2.70 3.10 f 0.0472 ref 1.20 ref b 0.1024 0.1181 2.60 3.00 g 0 0.0039 0 0.10 c 0.0551 0.0709 1.40 1.80 h - 0.0079 - 0.20 d 0.0748 ref 1.90 ref i 0.0047 ref 0.12 ref d1 0.0374 ref 0.95 ref j 0.0146 ref 0.37 ref d2 0.0374 ref 0.95 ref k 0.0236 ref 0.60 ref e 0.0118 0.0217 0.30 0.55 l 0 10 0 10 notes : 1.controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material : ? mold compound : epoxy resin family, flammability solid burning class:ul94v-0 important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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