View MT48H4M16LFB4-75ITH_7902754.PDF datasheet online --- IC-ON-LINE

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products and specifications discussed herein ar e subject to change by micron without notice. 64mb: 4 meg x 16 mobile sdram features pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_1.fm - rev. c 10/07 en 1 ?2006 micron technology, inc. all rights reserved. mobile sdram mt48h4m16lf ? 1 meg x 16 x 4 banks features ? 1.70?1.95v ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operatio n; column address can be changed every clock cycle ? internal banks for hiding row access/precharge ? programmable burst lengths: 1, 2, 4, 8, or continuous page 1 ? auto precharge, includes concurrent auto precharge ? self refresh mode ? 64ms, 4,096-cycle refresh ? lvttl-compatible inputs and outputs ? partial-array self refresh (pasr) power-saving mode ? on-die temperature-compensated self refresh (tcsr) ? deep power-down (dpd) mode ? programmable output drive strength ? operating temperature ranges ? commercial (0c to +70c) ? industrial (?40c to +85c) notes: 1. for continuous page burst, contact factory for availability. options marking ?v dd /v dd q ? 1.8v/1.8v h ? configurations ? 4 meg x 16 (1 meg x 16 x 4 banks) 4m16 ?plastic ?green? package ? 54-ball vfbga, 8mm x 8mm b4 ? timing (cycle time) ? 7.5ns @ cl = 3 (133 mhz) -75 ? 8ns @ cl = 3 (125 mhz) -8 ? operating temperature ? commercial (0 c to +70 c) none ? industrial (?40 c to +85 c) it ? die revision designator :h figure 1: 54-ball vfbga ball assignment (top view) table 1: address table 4 meg x 16 configuration 1 meg x 16 x 4 banks refresh count 4k row addressing 4k (a0?a11) bank addressing 4 (ba0, ba1) column addressing 256 (a0?a7) table 2: key timing parameters cl = cas (read) latency speed grade clock rate (mhz) access time cl = 2 cl = 3 cl = 2 cl = 3 -75 104 133 8ns 6ns -8 83 125 8ns 6ns a b c d e f g h j 1 2 3 4 5 6 7 8 top view (ball down) v ss dq14 dq12 dq10 dq8 udqm nc a8 v ss dq15 dq13 dq11 dq9 nc clk a11 a7 a5 v ss q v dd q v ss q v dd q v ss cke a9 a6 a4 v dd q v ss q v dd q v ss q v dd cas# ba0 a0 a3 dq0 dq2 dq4 dq6 ldqm ras# ba1 a1 a2 v dd dq1 dq3 dq5 dq7 we# cs# a10 v dd 9
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24ltoc.fm - rev. c 10/07 en 2 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram table of contents table of contents options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 burst length (bl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 cas latency (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 write burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 temperature?compensated self refresh (tcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 partial-array self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 driver strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 command inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 deep power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 bank/row activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 deep power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 clock suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 burst read/single write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 read with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 write with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24llof.fm - rev. c 10/07 en 3 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram list of figures list of figures figure 1: 54-ball vfbga ball assignment (t op view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: part numbering diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 3: functional block diagram ? 4 meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 4: mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 7: activating a specific row in a sp ecific bank register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 8: meeting trcd (min) when 2 < trcd (min)/tck < 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 9: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 10: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 11: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 12: read-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 13: read-to-write with extra clock cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 14: read-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 15: terminating a read bu rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 16: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 17: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 18: write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 19: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 20: write-to-read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 21: write-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 22: terminating a write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 23: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 24: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 25: clock suspend during write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 26: clock suspend during read burs t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 27: read with auto precha rge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 28: read with auto precha rge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 29: write with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 30: write with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 31: typical self refresh current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 32: initialize and load mode regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 33: power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 34: clock suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 35: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 36: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 37: read ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 38: read ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 39: single read ? without auto prec harge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 40: single read ? with auto precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 41: alternating bank read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 42: read ? dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 43: write ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 44: write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 45: single write ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 46: single write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 47: alternating bank writ e accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 48: write ? dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 49: 54-ball vfbga (8mm x 8mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24llot.fm - rev. c 10/07 en 4 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram list of tables list of tables table 1: address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 4: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 5: truth table 1 ? commands and dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 6: truth table 2 ? cke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 7: truth table 3 ? current state bank n , command to bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 8: truth table 4 ? current state bank n , command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 9: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 10: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 11: ac electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 12: electrical characteristics and re commended ac operating conditions . . . . . . . . . . . . . . . . . . . . . . .40 table 13: ac functional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 14: i dd specifications and conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 15: i dd 7 - self refresh current options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 16: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 5 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram general description figure 2: part numbering diagram general description the micron ? 64mb sdram is a high-speed cmos , dynamic random access memory containing 67,108,864 bits. it is internally configured as a quad-bank dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the x16?s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. read and write accesses to the sdram are bu rst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0?a11 select the row). the address bits registered coincident with the read or write command are used to select the star ting column location for the burst access. the sdram provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca- tions with a burst terminate option. an au to precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the 64mb sdram uses an internal pipelined architecture to achieve high-speed opera- tion. this architecture is compatible with the 2 n rule of prefetch architectures, but it also enables the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank wh ile accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access operation. the 64mb sdram is designed to operate in 1.8v, low-power memory systems. an auto refresh mode is provided, along with a power-saving, deep power-down mode. all inputs and outputs are lvttl-compatible. ? configuration mt48 v dd / v dd q package speed v dd /v dd q 1.8v/1.8v h configuration 4 meg x16 4m16lf package b4 speed grade 7.5ns 8ns -75 -8 example part number: mt48h4m16lfb4-8 it :h 54-ball vfbga (8mm x 8mm) ?green? temp :h design revision revision operating temp. commercial industrial none it
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 6 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram general description self refresh mode offers temperature compensation through an on-die temperature sensor and partial-array self refresh (pasr) . pasr enables users to achieve additional power savings from normal usage. the temper ature sensor is enabled by default and the pasr settings can be programmed through the extended mode register. sdram offers substantial advances in dr am operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to inte rleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. figure 3: functional block diagram ? 4 meg x 16 12 ras# cas# row- address mux clk cs# we# cke control logic column- address counter/ latch mode register 8 command decode a0-a11, ba0, ba1 ldqm, udqm 12 address register 14 256 (x16) 4096 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (4,096 x 256 x 16) bank0 row- address latch & decoder 4096 sense amplifiers bank control logic dq0- dq15 16 16 data input register data output register 16 12 bank1 bank2 bank3 12 8 2 2 2 2 refresh counter ba1 ba0 bank 000 011 102 113
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 7 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram general description table 3: ball descriptions 54-ball vfbga symbol type description f2 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and contro ls the output registers. f3 cke input clock enable: cke activates (high) a nd deactivates (low ) the clk signal. deactivating the clock provides prec harge power-down and self refresh operation (all banks idle), active power-down (row active in any bank), deep power-down (all banks idle), or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until afte r exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. g9 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands ar e masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. f7, f8, f9 cas#, ras#, we# input command inputs: cas#, ras#, and we# (along with cs#) define the command being entered. e8, f1 ldqm, udqm input input/output mask: dqm is sampled high and is an input mask signal for write accesses and an output enable si gnal for read accesses. input data is masked during a write cycle. the outp ut buffers are placed in a high-z state (two-clock latency) during a read cycle. ldqm corresponds to dq0? dq7, udqm corresponds to dq8?dq15 . ldqm and udqm are considered same state when referenced as dqm. dqm loading is designed to match that of dq balls. g7, g8 ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write, or precharge command is being applied. these pins also select between the mode register and the extended mode register. h7, h8, j8, j7, j3, j2, h3, h2, h1, g3, h9, g2 a0?a11 input address inputs: a0?a11 are sample d during the active command (row- address a0?a11) and read/write command (column-address a0?a7; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether all banks are to be precharged (a10 high) or bank select ed by ba0, ba1. the address inputs also provide the op-code during a load mode register command. a8, b9, b8, c9, c8, d9, d8, e9, e1, d2, d1, c2, c1, b2, b1, a2 dq0?dq15 i/o data input/output: data bus. e2, g1 nc ? nc = no connect (internally unconnected): these may be left unconnected, but it is recommended that they be connected to v ss . dnu = do not use; must be left unconnected. a7, b3, c7, d3 v dd q supply dq power: provides isolated power to dq for improved noise immunity. a3, b7, c3, d7 v ss q supply dq ground: provides isolated ground to dq for improved noise immunity. a9, e7, j9 v dd supply core power supply. a1, e3, j1 v ss supply ground.
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 8 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram functional description functional description the 64mb sdram (1 meg x 16 x 4 banks) is a quad-bank dram that operates at 1.8v and includes a synchronous interface (all signals ar e registered on the positive edge of the clock signal, clk). each of the x16?s 16,777, 216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. read and write accesses to the sdram are bu rst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the ba nk and row to be accessed (ba0 and ba1 select the bank; a0?a11 select the row). the address bits (a0?a7) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. initialization sdram must be powered up and initialized in a predefined manner. operational proce- dures other than those specified may result in undefined operation. power should be applied to v dd and v dd q simultaneously. after the power is applied to v dd and v dd q and the clock is stable (stable clock is de fined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a command in hibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. after the 100s delay has been satisfied wi th at least one command inhibit or nop command having been applied, a precharge command should be applied. all banks must then be precharged, thereby placin g the device in the all-banks-idle state. when in the idle state, two auto refresh cy cles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. mode register definition two mode registers exist in mobile sdram: the mode register and the extended mode register. the mode register is illustrated in figure 4 on page 9, and the extended mode register is illustrated in figure 6 on page 12. the mode register defines the specific mode of operation of the sdram, including burst length, burst type, cas latency, operating mode, and write burst mode. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0?m2 specify the burs t length, m3 specifies the type of burst (sequential or interleaved), m4?m6 specify th e cas latency, m7 and m8 specify the oper- ating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use and should be set to zero. m12 and m13 are set to zero to select the mode register.
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 9 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram mode register definition the mode register must be loaded when all banks are idle, and the controller must wait t mrd before initiating the subsequent operatio n. violating either of these requirements will result in unspecified operation. figure 4: mode register definition burst length (bl) read and write accesses to the sdram are bu rst oriented, with th e burst length (bl) being programmable, as shown in figure 4 on page 9. the bl determines the maximum number of column locations that can be ac cessed for a given read or write command. bls of 1, 2, 4, or 8 locations are available fo r both the sequential and the interleaved burst types. reserved states must not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the bl is effec- tively selected. all accesses for that burst ta ke place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected m3 = 0 1 2 4 8 reserved reserved m3 = 1 1 2 4 8 reserved reserved reserved 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 0 0 0 1 mode register (mx) address bus m8 0 ? m7 0 ? m6?m0 defined ? operating mode normal operation all other states reserved mode register definintion base mode register extended mode register m13 m12 m9 0 1 write burst mode programmed burst length single location access 9 7 6 5 4 3 8 2 1 burst length 0 0 m12 a11 m11 a10 m10 a9 m9 a8 m8 a7 m7 a6 m6 a5 m5 a4 m4 a3 m3 a2 m2 a1 m1 a0 m0 10 11 12 ba1 ba0 m13 13 0 bt cas latency op mode wb reserved reserved reserved reserved
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 10 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram mode register definition by a1?a7 when bl = 2; by a2?a7 when bl = 4; and by a3?a7 when bl = 8. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. burst type accesses within a given burst may be programmed to be sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the bl, the burst type, and the starting column address, as shown in table 4. cas latency (cl) the cas latency (cl) is the delay, in clock cycles, between the registration of a read command and the availability of the first piec e of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dq will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the re levant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dq will start driving after t1 and the data will be valid by t2, as shown in figure 5 on page 11. table 5 on page 14 indicates the operating frequencies at which each cl setting can be used. reserved states should not be used becaus e unknown operation or incompatibility with future versions may result. table 4: burst definition burst length order of accesses within a burst starting column address type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 11 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram mode register definition figure 5: cas latency operating mode the normal operating mode is selected by se tting m7 and m8 to zero; the other combi- nations of values for m7 and m8 are reserved for future use. the programmed burst length applies to both read and write bursts. reserved states must not be used; unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programme d via m0?m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are sing le-location accesses. extended mode register the extended mode register controls the func tions beyond those controlled by the mode register. these additional functions are special features of the mobile device. they include temperature-compensated self refresh (tcsr) control, partial-array self refresh (pasr), and output drive strength. the extended mode register is programmed via the mode register set command with ba = 1 and ba = 0 and retains the stor ed information until it is programmed again or the device loses power. the extended mode register must be loaded wh en all banks are idle and no bursts are in progress, and the controller must wait t mrd before initiating any subsequent operation. violating any of these requirements will result in unspecified operation. clk dq t2 t1 t3 t0 cl = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t3 t0 cl = 2 lz d out t oh t command nop read t ac nop
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 12 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram mode register definition figure 6: extended mode register notes: 1. the on-die temperature sensor is used in place of tcsr. setting these bits has no effect. 2. 1/2- and 1/4-bank settings w ill default to one-bank pasr. temperature?compensated self refresh (tcsr) on this version of the mobile sdr sdram, a temperature sensor is implemented for automatic control of the self refresh oscillat or on the device. therefore, it is recom- mended not to program or use the tcsr cont rol bits in the extended mode register. programming of the tcsr bits has no effect on the device. the self refresh oscillator will continue refresh at the factory-programmed optimal rate for the device temperature. partial-array self refresh for further power savings during self refresh, the pasr feature enables the controller to select the amount of memory th at will be refreshed during self refresh. the following refresh options are available: ? all banks (banks 0, 1, 2, and 3) ? two banks (banks 0 and 1; ba1 = 0) ? one bank (bank 0; ba1 = ba0 = 0) write and read commands occur to any bank selected during standard operation, but only the selected banks in pasr will be refr eshed during self refresh. data in unused banks, or portions of banks, is lost when pasr is used. maximum case temp. e4 e3 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 9 7 6 5 4 3 8 2 1 0 a10 a11 10 11 12 pasr tcsr 13 all must be set to ?0? ba0 e9 e7 e6 e5 e4 e3 e8 e2 e1 e0 e10 e11 e12 ba1 e13 85c 1 1 70c 0 0 45c 15c 0 1 1 0 ds e5 e6 driver strength 0 0 0 0 1 1 1 1 full strength quarter strength reserved half strength 1 e2 0 0 0 0 1 1 1 1 e1 0 0 1 1 0 0 1 1 e0 0 1 0 1 0 1 0 1 self refresh coverage four banks two banks one bank reserved reserved 1/2 bank 2 1/4 bank 2 reserved 0 0 1 1 mode register definition base mode register reserved extended mode register reserved e13 0 1 0 1 e12 10
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 13 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram mode register definition driver strength bits e5 and e6 of the extended mode register can be used to select the driver strength of the dq outputs. this value should be set according to the application?s requirements. full-drive strength is suitable to drive high er load systems. half-drive strength is intended for multi-drop systems with various loads. quarter-drive strength is intended for lighter loads or point-to-point systems.
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 14 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram commands commands table 5 provides a quick reference of availabl e commands. this is followed by a written description of each command. three addition al truth tables appear following ?opera- tions? on page 18; these tables provid e current state/next state information. notes: 1. cke is high for all commands shown except self refresh and deep power-down. 2. a0?a11 define op-code wr itten to mode register. 3. a0?a11 provide row address, and ba0, ba 1 determine which bank is made active. 4. a0?a7 provide column address; a10 high enables the au to precharge feature (nonpersis- tent), while a10 low disables the auto precharge feature; ba0, ba1 determine which bank is being read from or written to. 5. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0, ba1 are ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. activates or deactivates the dq during writes (zero-clock delay) and reads (two-clock delay). ldqm controls dq0?7, udqm controls dq8?15. 9. this command is burst terminate when cke is high and deep power-down when cke is low. 10. the purpose of the burst ter minate command is to stop a data burst; thus, the command could coincide with data on the bus. however, the dq column reads a ?don?t care? state to illustrate that the burst terminate command can occur when there is no data present. table 5: truth table 1 ? commands and dqm operation note 1; notes appear below table name (function) cs# ras# cas# we# dqm addr dq notes command inhibit (nop) hx x x x x x no operation (nop) lh hh x x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column, and start read burst) l h l h l/h bank/col x 4 write (select bank and colu mn, and start write burst) l h l l l/h bank/col valid 4 burst terminate or deep power-down (enter deep power-down mode) lh h l x x x9, 10 precharge (deactivate row in bank or banks) l l h l x bank, a10 x 5 auto refresh or self refresh (enter self refresh mode) ll lhx x x6, 7 load mode register/load extended mode register ll l l xop-codex 2 write enable/output enable x x x x l x active 8 write inhibit/output high-z xx x x h x high-z8
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 15 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram commands command inhibit the command inhibit function prevents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively dese- lected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram which is selected (cs# is low). this prevents unwant ed commands from being registered during idle or wait states. operations al ready in progress are not affected. load mode register the mode register is loaded via inputs a0?a11, ba0, ba1. see the ?mode register? heading in the register definition sect ion. the load mode register and load extended mode register commands can only be issued when all banks are idle, and a subsequent executable co mmand cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a7 selects the starting column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read da ta appears on the dq subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corresponding dq will be high-z two clocks later; if the dqm signal was registered low, the dq will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a7 selects the starting column location. the va lue on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dq is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be exec uted to that byte/column location.
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 16 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram commands precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? after a bank has been precharged, it is in the idle state and must be acti- vated prior to any read or write commands being issued to that bank. burst terminate the burst terminate command is used to truncate fixed-length bursts. the most recently registered read or write command prior to the burst terminate command will be truncated, as shown in ?operations? on page 18. auto precharge auto precharge is a feature that performs the same individual-bank precharge func- tion described above, without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon co mpletion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each indi- vidual read or write command. auto precharge ensures that the precharge is in itiated at the earliest valid stage within a burst. the user must not issue another comma nd to the same bank until the precharge time ( t rp) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as desc ribed for each burst type in ?operations? on page 18. auto refresh auto refresh is used during normal operation of the sdram and is analogous to cas#-before-ras# (cbr) refresh in conven tional dram. this command is nonpersis- tent, so it must be issued each time a refresh is required. all active banks must be precharged prior to issuing an auto refresh command. the auto refresh command should not be issued until the minimum t rp has been met after the precharge command, as shown in ?operations? on page 18. the addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 64mb sdram requires 4,096 auto refresh cycles every 64ms ( t ref). providing a distributed auto refresh command every 15.625s will me et the refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rfc), once every 64ms. self refresh the self refresh command can be used to reta in data in the sdram, even if the rest of the system is powered down, as long as power is not completely removed from the sdram. when in the self refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 17 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram commands except cke is disabled (low). when the self refresh command is registered, all the inputs to the sdram become ?don?t care? with the exception of cke, which must remain low. during self refresh, the device is refreshed as identified in the extended mode register pasr settings. after self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is defi ned as a signal cycling within timing constraints specified for the clock pin) prior to cke going back high. when cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr because time is required for the completion of an y internal refresh in progress. upon exiting the self refresh mode, auto refresh commands should be issued at once and then every 15.625s or less, because self refresh and auto refresh use the row refresh counter. deep power-down deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power to the memory array. da ta is not retained after the device enters deep power-down mode. this mode is entered by having all banks idle then cs# and we# held low with ras# and cas# held high at the rising edge of th e clock, while cke is low. this mode is exited by asserting cke high.
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 18 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations operations bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated (see figure 7). after opening a row (issuing an active co mmand), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rounded to 3. this is reflected in figure 8 on page 19, which covers any case where 2 < t rcd (min)/ t ck 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active comma nds to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active co mmands to different banks is defined by t rrd. figure 7: activating a specific row in a specific bank register cs# we# cas# ras# cke clk address row address don?t care high ba0, ba1 bank address
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 19 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations figure 8: meeting t rcd (min) when 2 < t rcd (min)/ t ck < 3 reads read bursts are initiated with a read command, as shown in figure 8. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. note: for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out elem ent from the starting column address will be available following the cl after the read command. each subsequent data-out element will be valid by the next positive clock edge. figure 5 on page 11 shows general timing for each possible cl setting. upon completion of a burst, assuming no ot her commands have been initiated, the dq will go high-z. data from any read burst may be truncate d with a subsequent read command, and data from a fixed-length read burst may be immediately followed by data from a read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burs t that is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 10 on page 20 fo r cl = 2 and cl = 3; data element n + 3 is either the last of a burst of four or the last desire d of a longer burst. the mobile sdram uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in figure 11 on page 21, or each subsequent read may be performed to a different bank. data from any read burst may be truncate d with a subsequent write command, and data from a fixed-length read burst may be immediately followed by data from a write command (subject to bus turnaround limitations). the write burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o cont ention can be avoided. in a given system design, there may be a possibility that the device driving the input data will go low-z before the sdram dq go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. clk t 2 t1 t 3 t 0 t command nop active read or write t4 nop rcd don?t care
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 20 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations figure 9: read command figure 10: consecutive read bursts note: each read command may be issued to any bank. dqm is low. cs# we# cas# ras# cke clk column address a10 ba0, ba1 don?t care high enable auto precharge disable auto precharge bank address address don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cl = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cl = 3 transitioning data
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 21 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations figure 11: random read accesses note: each read command may be issued to any bank. dqm is low. the dqm input is used to avoid i/o contention, as shown in figure 12 on page 22 and figure 13 on page 22. the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two cl ocks for output buffers) to suppress data- out from the read. after the write command is registered, the dq will go high-z (or remain high-z), regardless of the state of the dqm signal, provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. for example, if dqm was low during t4 in figure 14 on page 23, then the writes at t5 and t7 would be valid, while the write at t6 would be invalid. the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 13 on page 22 shows the case where the clock frequency allows for bus contention to be avoided without adding a nop cycle, and figure 14 on page 23 shows the case where the additional nop is needed. a fi xed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated). the precharge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cl minus one. this is shown in figure 14 for each possible cl; data element n + 3 is either the last of a burst of four or the last desired of a longer burs t. following the precharge command, a subse- quent command to the same ba nk cannot be issued until t rp is met. note: part of the row precharge time is hidden du ring the access of the last data element(s). clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n don?t care d out n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m cl = 2 cl = 3 transitioning data
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 22 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as desc ribed above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvan- tage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length bursts. figure 12: read-to-write note: a cl of three is used for illustration. th e read command may be i ssued to any bank, and the write command may be issued to any bank. if a burst of one is used, then dqm is not required. figure 13: read-to-write with extra clock cycle note: a cl of three is used for illustration. th e read command may be i ssued to any bank, and the write command may be issued to any bank. don?t care read nop nop write nop clk t2 t1 t4 t3 t0 dqm dq d out n command d in b address bank, col n bank, col b ds t hz t t ck transitioning data don?t care read nop nop nop nop dqm clk dq d out n t2 t1 t4 t3 t0 command address bank, col n write d in b bank, col b t5 ds t hz t transitioning data
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 23 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations figure 14: read-to-precharge note: dqm is low. figure 15: terminating a read burst note: dqm is low. don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 x = 1 cycle cl = 2 cl = 3 x = 2 cycles bank a , col n bank a , row bank ( a or all) bank a , col n bank a , row bank ( a or all) transitioning data clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop t7 don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop x = 1 cycle cl = 2 cl = 3 x = 2 cycles transitioning data
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 24 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations fixed-length read bursts may be truncated with a burst terminate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cl minus one. this is sh own in figure 15 on page 23 for each possible cl; data element n + 3 is the last desired data element of a longer burst. writes write bursts are initiated with a write command, as shown in figure 16. the starting column and bank addresses are provided with the write command and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at th e completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dq will remain high-z and any additional input data will be ignored (see figure 18 on page 25). figure 16: write command data for any write burst may be truncate d with a subsequent write command, and data for a fixed-length write burst may be immediately followed by data for a write command. the new write command can be issued on any clock following the previous write command, and the data provided coin cident with the new command applies to the new command. an example is shown in figure 19 on page 26. data n + 1 is either the last of a burst of two or the last desired of a longer burst. the mobile sdram uses a pipe- lined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous cs # we# c a s # ra s # c ke c lk c olumn a dd ress hi g h ena b le auto pre c har g e disa b le auto pre c har g e bank a dd ress a dd ress a10 ba0, ba1 vali d a dd ress don ? t c are
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 25 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations write command. full-speed random write acce sses within a page can be performed to the same bank, as shown in figure 19 on page 26, or each subsequent write may be performed to a different bank. figure 17: write burst note: bl = 2. dqm is low. figure 18: write-to-write note: dqm is low. each write comma nd may be issued to any bank. data for any write burst may be truncate d with a subsequent read command, and data for a fixed-length write burst may be immediately followed by a read command. after the read command is registered, the data inputs will be ignored and writes will not be executed. an example is shown in figure 20 on page 26. data n + 1 is either the last of a burst of two or the last desired of a longer burst. data for a fixed-length write burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not acti- vated). the precharge command should be issued t wr after the clock edge at which the last desired input data element is regi stered. the auto precharge mode requires a t wr of at least one clock plus time, regardless of frequency. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in figure 21 on page 27. data n + 1 is clk dq d in n t2 t1 t3 t0 command address nop nop don?t care write d in n + 1 nop bank, col n transitioning data clk dq t 2 t1 t 0 command address nop write write bank, col n bank, col b d in n d in n + 1 d in b don?t care transitioning data
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 26 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations either the last of a burst of two or the la st desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as desc ribed above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvan- tage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length bursts. fixed-length write bursts can be truncated with the burst terminate command. when truncating a write burst, the input data applied coincident with the burst terminate command will be ignored. the la st data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 22 on page 27, where data n is the last desired data element of a longer burst. figure 19: random write cycles note: each write command may be i ssued to any bank. dqm is low. figure 20: write-to-read note: the write command may be issued to an y bank, and the read command may be issued to any bank. dqm is low. cl = 2 for illustration. don?t care clk dq d in n t 2 t1 t 3 t 0 command address write bank, col n d in a d in x d in m write write write bank, col a bank, col x bank, col m transitioning data don?t care clk dq t2 t1 t3 t0 command address nop write bank, col n d in n d in n + 1 d out b read nop nop bank, col b nop d out b + 1 t4 t5 transitioning data
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 27 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations figure 21: write-to-precharge note: dqm could remain low in this example if the write burst is a fixed length of two. figure 22: terminating a write burst note: dqm is low. don?t care dqm clk dq t 2 t1 t4 t 3 t 0 command address bank a , col n t5 nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row dqm dq command address bank a , col n nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row t 6 nop nop t wr @ t clk 15ns t wr = t clk < 15ns transitioning data don?t care clk dq t 2 t1 t 0 command address bank, col n write burst terminate next command d in n (address) (data) transitioning data
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 28 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations precharge the precharge command (see figure 23 on page 28) is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) wi ll be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged , inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 ar e treated as ?don?t care.? after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. figure 23: precharge command power-down power-down occurs if cke is registered low coincident with a nop or command inhibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and outp ut buffers, excluding cke, for maximum power savings while in standby. the device must not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. the power-down state is exited by regist ering an nop or command inhibit and cke high at the desired clock edge (meeting t cks). see figure 24 on page 29. cs# we# cas# ras# cke clk a10 high all banks bank selected address bank address valid address don?t care ba0, ba1
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 29 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations figure 24: power-down deep power-down deep power-down mode is a maximum power savings feature achieved by shutting off the power to the entire memory array of the device. data on the memory array will not be retained after deep power-down mode is executed. deep power-down mode is entered by having all banks idle then cs# and we# held low with ras# and cas# high at the rising edge of the clock, while cke is low. cke must be held low during deep power-down. to exit deep power-down mode, cke must be asserted high. upon exit of deep power- down mode, a full mobile sdram initialization sequence is required. clock suspend the clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deactivated, ?freezing? the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (see examples in figure 25 on page 30 and figure 26 on page 30.) clock suspend mode is exited by registering cke high; the internal clock and related operation will resume on the subsequent positive clock edge. t ra s t r c d t r c all b anks i d le input b uffers g ate d off exit power- d own mo d e ( ) ( ) ( ) ( ) ( ) ( ) t c k s > t c k s c omman d nop a c tive enter power- d own mo d e nop c lk c ke ( ) ( ) ( ) ( )
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 30 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations figure 25: clock suspend during write burst note: for this example, bl = 4 or greater, and dm is low. figure 26: clock suspend during read burst note: for this example, cl = 2, bl = 4 or greater, and dqm is low. don?t care d in command address write bank, col n d in n nop nop clk t2 t1 t4 t3 t5 t0 cke nop d in n + 1 d in n + 2 transitioning data internal clock don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 cke internal clock nop transitioning data
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 31 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations burst read/single write the burst read/single write mode is entere d by programming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write commands result in the access of a single column location (burst of one), regardless of the programmed burst length. read commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (m9 = 0). concurrent auto precharge micron sdram devices support concurrent au to precharge, which enables an access command (read or write) to another bank while an access command with auto precharge enabled is executing. four cases where concurrent auto precharge occurs are defined below. read with auto precharge 1. interrupted by a read (with or without auto precharge): a read to bank m will inter- rupt a read on bank n , two or three clocks later, depending on cl. the precharge to bank n will begin when the read to bank m is registered (see figure 27). 2. interrupted by a write (with or without auto precharge): when a write to bank m registers, a read on bank n will be interrupted. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (see figure 28 on page 32). figure 27: read with auto precharge interrupted by a read note: dqm is low. don?t care clk dq d out a t 2 t1 t4 t 3 t 6 t5 t 0 command read - ap bank n nop nop nop nop d out a + 1 d out d d out d + 1 nop t7 bank n cl = 3 (bank m ) bank m address idle nop bank n, col a bank m , col d read - ap bank m internal states t page active read with bl = 4 interrupt burst, precharge page active read with bl = 4 precharge rp - bank n t rp - bank m cl = 3 (bank n ) transitioning data
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 32 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations figure 28: read with auto pr echarge interrupted by a write note: dqm is high at t2 to prevent d out a + 1 from contending with d in d at t4. write with auto precharge 3. interrupted by a read (with or without auto precharge): when a read to bank m reg- isters, it will interrupt a write on bank n , with the data-out appearing 2 or 3 clocks later, depending on cl. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (see figure 29 on page 33). 4. interrupted by a write (with or without auto precharge): when a write to bank m registers, it will interrupt a write on bank n . the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m (see figure 30 on page 33). clk dq t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d + 1 d in d d in d + 2 d in d + 3 nop t7 bank n bank m address idle nop dqm 1 bank n, col a bank m, col d write - ap bank m internal states t page active read with bl = 4 interrupt burst, precharge page active write with bl = 4 w rite-bank rp - bank n t wr - bank m cl = 3 (bank n ) read - ap bank n don?t care transitioning data d out a
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 33 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations figure 29: write with auto precharge interrupted by a read note: dqm is low. figure 30: write with auto precharge interrupted by a write note: dqm is low. don?t care clk dq t 2 t1 t4 t 3 t 6 t5 t 0 command write - ap bank n nop nop nop nop d in a + 1 d in a nop nop t7 bank n bank m address bank n , col a bank m , col d read - ap bank m internal states page active write with bl = 4 interrupt burst, write-back precharge page active read with bl = 4 t rp - bank m d out d d out d + 1 cl = 3 (bank m) t rp - bank n t wr - bank n transitioning data don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d + 1 d in d d in a + 1 d in a + 2 d in a d in d + 2 d in d + 3 nop t7 bank n bank m address nop bank n , col a bank m , col d write - ap bank m internal states page active write with bl = 4 interrupt burst, write-back precharge page active write with bl = 4 w rite-bank t wr - bank n t rp - bank n t wr - bank m transitioning data
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 34 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations notes: 1. cke n is the logic state of cke at clock edge n ; cke n - 1 was the state of cke at the previous clock edge. 2. current state is the state of the sd ram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of com- mand n . 4. all states and sequences not sh own are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in the all banks idle state when t xsr is met. command inhibit or nop co mmands should be issued on any clock edges occurring during the t xsr period. a minimum of two nop commands must be provided during t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n + 1. 8. deep power-down is a power-saving feature of this mobile sdram device. this command is burst terminate when cke is high and deep power-down when cke is low. table 6: truth table 2 ? cke notes: 1?4; notes appear below table cke n - 1 cke n current state command n action n notes l l power-down x maintain power-down self refresh x maintain self refresh clock suspend x maintain clock suspend deep power-down x maintain deep power-down 8 l h power-down command inhibit or nop exit power-down 5 deep power-down x exit deep power-down 8 self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 h l all banks idle command inhibit or nop power-down entry all banks idle burst terminate deep power-down entry 8 all banks idle auto refresh self refresh entry reading or writing valid clock suspend entry h h see table 7 on page 35
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 35 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations notes: 1. this table applies when cke n - 1 was high and cke n is high (see table 6 on page 34) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where note d; for example, the current state is for a spe- cific bank and the commands shown are those allo wed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: the following states must not be interrupted by a command is sued to the same bank. com- mand inhibit or nop commands, or allowabl e commands to the other bank, should be issued on any clock edge occurring during th ese states. allowable commands to the other bank are determined by its current state and table 7, and according to table 8. table 7: truth table 3 ? current state bank n , command to bank n notes: 1?5; notes appear be low table and on next page current state cs# ras# cas# we# command (action) notes any hxxx command inhibit (nop/conti nue previous operation) l hhh no operation (nop/continue previous operation) idle l l h h active (select an d activate row) lllh auto refresh 6 llll load mode register 6 llhl precharge 10 row activelhlh read (select column and start read burst) 9 lhl l write (select column and start write burst) 9 llhl precharge (deactivate row in bank or banks) 7 read (auto precharge disabled) lhlh read (select column and start new read burst) 9 lhl l write (select column and start write burst) 9 llhl precharge (truncate re ad burst, start precharge) 7 lhhl burst terminate 8 write (auto precharge disabled) lhlh read (select column and start read burst) 9 lhl l write (select column a nd start new write burst) 9 llhl precharge (truncate write burst, start precharge) 7 lhhl burst terminate 8 idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/ accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, wi th auto precharge disabled, and has not yet terminated or been terminated. precharging: starts with registration of a precharge comma nd and ends when t rp is met. after t rp is met, the bank will be in the idle state. row activating: starts with registration of an active comma nd and ends when t rcd is met. after t rcd is met, the bank will be in the row active state. read with auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write with auto precharge enabled: starts with registration of a wr ite command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state.
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 36 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations 4. the following states must not be inte rrupted by any executable command; command inhibit or nop commands must be applied on each positive cl ock edge during these states. 5. all states and sequences not sh own are illegal or reserved. 6. not bank specific; requires that all banks are idle. 7. may or may not be bank specific; if all banks are to be precharged, all must be in a valid state for precharging. 8. not bank specific; burst terminate affects th e most recent write or read burst, regard- less of bank. 9. reads or writes listed in the command (action) column include reads or writes with auto precharge enabled and reads or wr ites with auto precharge disabled. 10. does not affect the state of the ba nk and acts as a nop to that bank. refreshing: starts with registration of an auto refresh comma nd and ends when t rfc is met. after t rfc is met, the sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. after t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. after t rp is met, all banks will be in the idle state.
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 37 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations notes: 1. this table applies when cke n-1 was high and cke n is high (see table 6 on page 34) and after t xsr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given comma nd is allowable). exceptions are covered in the notes below. 3. current state definitions: 4. auto refresh, self refresh, and load mo de register commands may only be issued when all banks are idle. table 8: truth table 4 ? current state bank n , command to bank m notes: 1?6; notes appear be low table and on next page current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/conti nue previous operation) lhhh no operation (nop/continue previous operation) idle x x x x any command otherwise allowed to bank m row activating, active, or precharging ll hh active (select and activate row) lh l h read (select column and start read burst) 7 lh l l write (select column and start write burst) 7 ll hl precharge read (auto precharge disabled) ll hh active (select and activate row) lh l h read (select column and start new read burst) 7, 10 lh l l write (select column and start write burst) 7, 11 ll hl precharge 9 write (auto precharge disabled) ll hh active (select and activate row) lh l h read (select column and start read burst) 7, 12 lh l l write (select column and start new write burst) 7, 13 ll hl precharge 9 read (with auto precharge) ll hh active (select and activate row) lh l h read (select column and start new read burst) 7, 8, 14 lh l l write (select column and start write burst) 7, 8, 15 ll hl precharge 9 write (with auto precharge) ll hh active (select and activate row) lh l h read (select column and start read burst) 7, 8, 16 lh l l write (select column and start new write burst) 7, 8, 17 ll hl precharge 9 idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regist er accesses are in progress. read: a read burst has been initiated wi th auto precharge disabled and has not yet terminated or been terminated. write: a write burst has been initiated with auto precharg e disabled and has not yet terminated or been terminated. read with auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write with auto precharge enabled: starts with registration of a writ e command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state.
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 38 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram operations 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not sh own are illegal or reserved. 7. reads or writes to bank m listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been interrupted by bank m ?s burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrup ted by a read (with or without auto pre- charge), the read to bank m will interrupt the read on bank n , cl later (see figure 10 on page 20). 11. for a read without auto precharge interrup ted by a write (with or without auto pre- charge), the write to bank m will interrupt the read on bank n when registered (see figure 12 on page 22 and figure 13 on page 22). dq m should be used one clock prior to the write command to prev ent bus contention. 12. for a write without auto precharge interru pted by a read (with or without auto pre- charge), the read to bank m will interrupt the write on bank n when registered (see figure 20 on page 26), with the data-out appearin g cl later. the last valid write to bank n will be data-in registered one cl ock prior to the read to bank m . 13. for a write without auto precharge interrupt ed by a write (with or without auto pre- charge), the write to bank m will interrupt the write on bank n when registered (see figure 18 on page 25). the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 14. for a read with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n , cl later (see figure 27 on page 31). the precharge to bank n will begin when the read to bank m is registered. 15. for a read with auto precharge interrupted by a write (with or with out auto precharge), the write to bank m will interrupt the read on bank n when registered (see figure 28 on page 32). dqm should be used two clocks prior to the write command to prevent bus con- tention. the precharge to bank n will begin when the write to bank m is registered. 16. for a write with auto precha rge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cl later (see figure 29 on page 33). the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write bank n will be data-in registered one clock prior to the read to bank m . 17. for a write with auto precha rge interrupted by a write (wit h or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when th e write to bank m is reg- istered (see figure 30 on page 33). the last valid write to bank n will be data registered one clock to the write to bank m .
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 39 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram electrical specifications electrical specifications stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. table 9: absolute maximum ratings parameter symbol min max units voltage on v dd /v dd q supply relative to v ss /v ss q v dd /v dd q ?0.35 +2.8 v voltage on any ball relative to v ss v in ?0.35 +2.8 v storage temperature (plastic) t stg ?55 +150 c table 10: dc electrical characteristics and operating conditions notes: 1, 5, 6; notes ap pear on page 43 and 44; v dd /v dd q = 1.7?1.95v parameter/condition symbol min max units notes supply voltage v dd 1.7 1.95 v i/o supply voltage v dd q 1.7 1.95 v input high voltage: logic 1; all inputs v ih 0.8 v dd qv dd q + 0.3 v 22 input low voltage: logic 0; all inputs v il ?0.3 +0.3 v 22 output high voltage: all inputs: i out = -100a v oh 0.9 v dd q? v input low voltage: all inputs: i out = 100a v ol ?0.2v input leakage current: any input 0v v in v dd (all other pins not under test = 0v) i i ?1.0 +1.0 a output leakage current: dq disabled; 0v v out v dd q i oz ?1.5 +1.5 a operating temperature commercial industrial t a 0 ?40 +70 +85 c table 11: ac electrical characteristics and operating conditions v dd /v dd q = 1.7?1.95v parameter/condition symbol min max units input high voltage: logic 1; all inputs v ih 1.4 ? v input low voltage: logic 0; all inputs v il ?0.4v
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 40 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram electrical specifications table 12: electrical characteristics and recommended ac operating conditions notes: 5, 6, 8, 9, and 11; notes appear on page 43 and 44 ac characteristics -75 -8 units notes parameter symbol min max min max access time from clk (positive edge) cl = 3 t ac (3) ? 6 ? 6 ns cl = 2 t ac (2) ? 8 ? 8 ns address hold time t ah 1 ? 1 ? ns address setup time tas 2.5 ? 2.5 ? ns clk high-level width t ch 3 ? 3 ? ns clk low-level width t cl 3 ? 3 ? ns clock cycle time cl = 3 t ck (3) 7.5 100 8 100 ns 23 cl = 2 t ck (2) 9.6 100 12 100 ns 23 cke hold time t ckh 1 ? 1 ? ns cke setup time t cks 2.5 ? 2.5 ? ns cs#, ras#, cas#, we#, dqm hold time t cmh 1 ? 1 ? ns cs#, ras#, cas#, we#, dqm setup time t cms 2.5 ? 2.5 ? ns data-in hold time t dh 1 ? 1 ? ns data-in setup time t ds 2.5 ? 2.5 ? ns data-out high-z time cl = 3 t hz (3) ? 6 ? 6 ns 10 cl = 2 t hz (2) ? 8 ? 8 ns 10 data-out low-z time t lz 1 ? 1 ? ns data-out hold time (load) t oh 2.5 ? 2.5 ? ns data-out hold time (no load) t oh n 1.8 ? 1.8 ? ns 26 active-to-precharge command t ras 45 120,000 48 120,000 ns active-to-active command period t rc 67.5 ? 72 ? ns active-to-read or write delay t rcd 19.2 ? 24 ? ns refresh period (4,096 rows) t ref ? 64 ? 64 ms auto refresh period t rfc 75 ? 80 ? ns precharge command period t rp 19.2 ? 24 ? ns active bank a to active bank b command t rrd 15 ? 16 ? ns transition time t t 0.5 1.2 0.5 1.2 ns 7 write recovery time t wr 15 ? 15 ? ns 24 exit self refresh-to-active command t xsr 75 ? 80 ? ns 20
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 41 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram electrical specifications table 13: ac functional characteristics notes: 5, 6, 8, 9, and 11; notes appear on page 43 and 44 parameter symbol -75 -8 units notes read/write command to read/write command t ccd 1 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 1 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 1 t ck 14 dqm to input data delay t dqd 0 0 t ck 17 dqm to data mask during writes t dqm 0 0 t ck 17 dqm to data high-z during reads t dqz 2 2 t ck 17 write command to input data delay t dwd 0 0 t ck 17 data-in to active command t dal 5 5 t ck 15, 21 data-in to precharge command t dpl 2 2 t ck 16, 21 last data-in to burst stop command t bdl 1 1 t ck 17 last data-in to ne w read/write command t cdl 1 1 t ck 17 last data-in to precharge command t rdl 2 2 t ck 16, 21 load mode register command to active or refresh command t mrd 2 2 t ck 24 data-out to high-z from precharge command cl = 3 t roh(3) 3 3 t ck 17 cl = 2 t roh(2) 2 2 t ck 17 table 14: i dd specifications and conditions (x16) notes: 1, 5, 6, 11, and 13; no tes appear on page 43 and 44; v dd = 1.7v?1.95v, v dd q = 1.7v?1.95v parameter/condition symbol max units notes -75 -8 operating current: active mode; burst = 1; read or write; t rc = t rc (min) i dd 16055ma3, 18, 19 standby current: power-down mode; all ba nks idle; cke = low i dd 2p 150 150 a 25 standby current: nonpower-down mode; all banks idle; cke = high i dd 2n 10 10 ma 3, 12, 19, 25 standby current: active mode; cke = low; cs# = high; all banks active; no accesses in progress i dd 3p 5 5 ma 3, 18, 19 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd 3n 15 15 ma 3, 18, 19 operating current: burst mode; continuous burst; re ad or write; all banks active, half dq toggling every cycle i dd 45050ma3, 18, 19 auto refresh current: cke = high; cs# = high t rfc = t rfc (min) i dd 57560ma3, 12, 18, 19 t rfc = 15.625s i dd 62 2ma3, 12, 18, 19, 26 deep power-down i zz 10 10 a 25, 27
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 42 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram electrical specifications figure 31: typical self refresh current vs. temperature table 15: i dd 7 - self refresh current options notes: 4, 13, 25, an d 28; notes appear on page 43 and 44; v dd /v dd q = 1.7?1.95v temperature-compensated self refresh parameter/condition max temperature -75/-8 units self refresh current: cke < 0.2v ? 4 banks open 85oc 180 a 45oc 120 a self refresh current: cke < 0.2v ? 2 banks open 85oc 130 a 45oc 80 a self refresh current: cke < 0.2v ? 1 bank open 85oc 100 a 45oc 80 a self refresh current: cke < 0.2v ? 1/2 bank open 85oc 100 a 45oc 80 a self refresh current: cke < 0.2v ? 1/4 bank open 85oc 100 a 45oc 80 a table 16: capacitance note: 2; notes appear on page 43 parameter symbol min max units input capacitance: clk c i 1 1.5 4.0 pf input capacitance: all other input-only pins c i2 1.5 4.0 pf input/output capacitance: dq c io 3.0 6.0 pf current (a) 0 10 20 30 40 50 60 70 80 90 100 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 temperature (c) 4-banks 2-banks 1-bank, 1/2 bank, 1/4 bank
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 43 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram notes notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd /v dd q = 1.7?1.95v; t a = 25c; pin under test biased at 1.4v. f = 1 mhz. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0c t a +70c for commercial parts; ?40c t a +85c for industrial parts) is ensured. 6. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be pow- ered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh require- ment is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specification, the cl ock and cke must tran- sition between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured for 1.8v at 0.9v with equivalent load: 10. t hz defines the time at which the output achi eves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il and v ih , with timing referenced to v ih /2 = crossover point. if the input transition time is longer than t t (max), then the timing is refer- enced at v il (max) and v ih (min) and no longer at the v ih /2 crossover point. 12. other input signals are allowed to transiti on no more than once every two clocks and are otherwise at valid v ih or v il levels. 13. i dd specifications are tested after th e device is properly initialized. 14. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 18. the i dd current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. address transitions average on e transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 7.5ns for -75 and t ck = 8.0ns for -8. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one-third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns. q 20pf
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 44 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram notes 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for th e clock pin) during access or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. 24. for auto precharge mode, at least one clock cycle is required during t wr. during auto precharge mode, the precharge timing budget ( t rp) begins at 7.5ns for -75, and 7ns for -8, after the first clock delay after the last write is executed. 25. measurement is taken 500ms after entering this operating mode to allow for tester measurement settling time. 26. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 27. deep power-down current is a nominal value at 25c. the parameter is not tested. 28. values for i dd 7 85c are guaranteed for the entire temperature range. all other i dd 7 values are estimated.
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 45 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams timing diagrams figure 32: initialize and load mode register notes: 1. pre = precharge command, ar = auto refresh command, and lmr = load mode reg- ister command. 2. only nops or command inhibits may be issued during t rfc time. 3. at least one nop or command inhibit is required during t mrd time. c ke ba0, ba1 loa d exten d e d mo d e re g ister loa d mo d e re g ister t c k s power-up: v dd an d c lk sta b le t = 100s t c kh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqm ( ) ( ) ( ) ( ) dq hi g h-z a0?a9, a11 vali d a10 vali d c lk t c k c omman d 1 ar nop lmr ar lmr valid t c m s t c mh t a s t ah ba0 = l, ba1 = l ( ) ( ) ( ) ( ) c o d e c o d e t a s t ah c o d e c o d e ( ) ( ) ( ) ( ) pre all banks t a s t ah ( ) ( ) ( ) ( ) t0 t1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp t mrd 3 t mrd 3 t rf c 2 t rf c 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) vali d ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ba0 = l, ba1 = l ba0 = l, ba1 = h ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) pre c har g e all b anks ( ) ( ) ( ) ( ) tn + 1 to + 1 tp + 1 t q + 1 tr + 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 46 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 33: power-down mode notes: 1. violating refresh requirements during power-down may result in a loss of data. t ch t cl t ck two clock cycles cke clk dq all banks idle, enter power-down mode precharge all active banks input buffers gated off while in power-down mode exit power-down mode ( ) ( ) ( ) ( ) don?t care t cks t cks command t cmh t cms precharge nop nop active nop ( ) ( ) ( ) ( ) all banks idle ba0, ba1 bank banks\s) ( ) ( ) ( ) ( ) high-z t ah t as t ckh t cks dqm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a0?a9, a11 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 tn + 2
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 47 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 34: clock suspend mode notes: 1. for this example, the bl = 2, the cl = 3, and auto precharge is disabled. 2. a8, a9, and a11 = ?don?t care.? t c h t c l t c k t a c t lz dqm c lk a0?a9, a11 dq ba0, ba1 a10 t oh d out m t ah t a s t ah t a s t ah t a s bank t dh d out e t a c t hz d out m + 1 c omman d t c mh t c m s nop nop nop nop nop read write un d efine d c ke t c k s t c kh bank c olumn m t d s d out e + 1 nop t c kh t c k s t c mh t c m s 2 c olumn e 2 t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 don ? t c are
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 48 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 35: auto refresh mode note: t rfc must not be interrupted by any execut able command; command inhibit or nop com- mands must be applied on any positive edge during t rfc. t c h t c l t c k c ke c lk dq t rf c 1 ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) c omman d t c mh t c m s nop nop ( ) ( ) ( ) ( ) bank a c tive auto refre s h ( ) ( ) ( ) ( ) nop nop pre c har g e pre c har g e all a c tive b anks auto refre s h t rf c 1 hi g h-z ba0, ba1 bank( s ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ah t a s t c kh t c k s ( ) ( ) nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqm a0?a9, a11 row ( ) ( ) ( ) ( ) all b anks s in g le b ank a10 row ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 don ? t c are
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 49 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 36: self refresh mode note: t xsr requires a minimum of two clocks regardless of frequency or timing. t c h t c l t c k t rp c ke c lk dq enter self refresh mo d e pre c har g e all a c tive b anks t x s r c lk sta b le prior to exitin g self refresh mo d e exit self refresh mo d e (restart refresh time b ase) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) c omman d t c mh t c m s auto 1 refre s h pre c har g e nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ba0, ba1 bank(s) hi g h-z t c k s ah a s auto 1 refre s h > t ra s ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t c kh t c k s dqm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t t a0?a9, a11 ( ) ( ) ( ) ( ) all banks s in g le bank a10 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 to + 2 ( ) ( ) ( ) ( ) don ? t c are
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 50 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 37: read ? without auto precharge notes: 1. for this example, the bl = 4, the cl = 2, and the read burst is followed by a ?manual? pre- charge. 2. a8, a9, and a11 = ?don?t care.? all b anks t c h t c l t c k t a c t lz t rp t ra s t r c d c a s laten c y t r c t oh d out m t c mh t c m s t ah t a s t ah t a s t ah t a s row row bank bank(s) bank row row bank t hz t oh d out m +3 t a c t oh t a c t oh t a c d out m +2 d out m +1 t c mh t c m s pre c har g e nop nop nop a c tive nop read nop a c tive disa b le auto pre c har g e s in g le b anks c olumn m 2 t c kh t c k s t0 t1 t2 t3 t4 t5 t 6 t7 t8 dqm c ke c lk a0?a9, a11 dq ba0, ba1 a10 c omman d don ? t c are un d efine d
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 51 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 38: read ? with auto precharge notes: 1. for this example, the bl = 4, and the cl = 2. 2. a8, a9, and a11 = ?don?t care.? ena b le auto pre c har g e t c h t c l t c k t a c t lz t rp t ra s t r c d c a s laten c y t r c dqm c ke c lk a0?a9, a11 dq ba0, ba1 a10 t oh d out m t c mh t c m s t ah t a s t ah t a s t ah t a s row row bank bank row row bank t hz t oh d out m + 3 t a c t oh t a c t oh t a c d out m + 2 d out m + 1 c omman d t c mh t c m s nop nop nop a c tive nop read nop a c tive nop t c kh t c k s c olumn m 2 t0 t1 t2 t4 t3 t5 t 6 t7 t8 un d efine d don ? t c are
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 52 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 39: single read ? without auto precharge notes: 1. for this example, the bl = 4, the cl = 2, and the read burst is followed by a ?manual? pre- charge. 2. a8, a9, and a11 = ?don?t care.? 3. precharge command not allowed, or t ras would be violated. all b anks t c h t c l t c k t a c t lz t rp t ra s t r c d c a s laten c y t r c t oh d out m t c mh t c m s t ah t a s t ah t a s t ah t a s row row bank bank( s ) bank row row bank t hz t c mh t c m s nop nop nop pre c har g e a c tive nop read a c tive nop disa b le auto pre c har g e s in g le b anks c olumn m 2 t c kh t c k s t0 t1 t2 t3 t4 t5 t 6 t7 t8 dqm c ke c lk a0?a9, a11 dq ba0, ba1 a10 c omman d 3 3 un d efine d don ? t c are
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 53 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 40: single read ? with auto precharge notes: 1. for this example, the bl = 4 and the cl = 2. 2. a8, a9, and a11 = ?don?t care.? 3. precharge command not allowed, or t ras would be violated. ena b le auto pre c har g e t c h t c l t c k t rp t ra s t r c d c a s laten c y t r c dqm c ke c lk a0?a9, a11 dq ba0, ba1 a10 t c mh t c m s t ah t a s t ah t a s t ah t a s row row bank bank row row bank t hz t oh d out m t a c c omman d t c mh t c m s nop 3 read a c tive nop nop 3 a c tive nop t c kh t c k s c olumn m 2 t0 t1 t2 t4 t3 t5 t 6 t7 t8 nop nop un d efine d don ? t c are
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 54 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 41: alternating bank read accesses notes: 1. for this example, th e bl = 4, and the cl = 2. 2. a8, a9, and a11 = ?don?t care.? ena b le auto pre c har g e t c h t c l t c k t a c t lz dqm c lk a0?a9, a11 dq ba0, ba1 a10 t oh d out m t c mh t c m s t ah t a s t ah t a s t ah t a s row row row row t oh d out m + 3 t a c t oh t a c t oh t a c d out m + 2 d out m + 1 c omman d t c mh t c m s nop nop a c tive nop read nop a c tive t oh d out b t a c t a c read ena b le auto pre c har g e row a c tive row bank 0 bank 0 bank 3 bank 3 bank 0 c ke t c kh t c k s c olumn m 2 c olumn b 2 t0 t1 t2 t4 t3 t5 t 6 t7 t8 t rp - bank 0 t ra s - bank 0 t r c d - bank 0 t r c d - bank 0 c a s laten c y - bank 0 t r c d - bank 3 c a s laten c y - bank 3 t t r c - bank 0 rrd un d efine d don ? t c are
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 55 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 42: read ? dqm operation notes: 1. for this example, the cl = 2. 2. a8, a9, and a11 = ?don?t care.? t c h t c l t c k t r c d c a s laten c y dqm c ke c lk a0?a9, a11 dq ba0, ba1 a10 t c m s row bank row bank t a c lz d out m t oh d out m + 3 d out m + 2 t t hz lz t t c mh c omman d nop nop nop a c tive nop read nop nop nop t hz t a c t oh t a c t oh t ah t a s t c m s t c mh t ah t a s t ah t a s t c kh t c k s ena b le auto pre c har g e disa b le auto pre c har g e c olumn m 2 t0 t1 t2 t4 t3 t5 t 6 t7 t8 un d efine d don ? t c are
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 56 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 43: write ? without auto precharge notes: 1. for this example, the bl = 4, and the wr ite burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command, regardless of fre- quency. 3. a8, a9, and a11 = ?don?t care.? disa b le auto pre c har g e all b anks t c h t c l t c k t rp t ra s t r c d t r c dqm c ke c lk a0?a9, a11 dq ba0, ba1 a10 t c mh t c m s t ah t a s row row bank bank bank row row bank t wr d in m t dh t d s d in m + 1 d in m + 2 d in m + 3 c omman d t c mh t c m s nop nop nop a c tive nop write nop pre c har g e a c tive t ah t a s t ah t a s t dh t d s t dh t d s t dh t d s s in g le b ank t c kh t c k s c olumn m 3 2 t0 t1 t2 t4 t3 t5 t 6 t7 t8 t9 nop don ? t c are
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 57 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 44: write ? with auto precharge notes: 1. for this example, the bl = 4. 2. a8, a9, and a11 = ?don?t care.? ena b le auto pre c har g e t c h t c l t c k t rp t ra s t r c d t r c dqm c ke c lk a0?a9, a11 dq ba0, ba1 a10 t c mh t c m s t ah t a s row row bank bank row row bank t wr d in m t dh t d s d in m + 1 d in m + 2 d in m + 3 c omman d t c mh t c m s nop nop nop a c tive nop write nop a c tive t ah t a s t ah t a s t dh t d s t dh t d s t dh t d s t c kh t c k s nop nop c olumn m 2 t0 t1 t2 t4 t3 t5 t 6 t7 t8 t9 don ? t c are
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 58 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 45: single write ? without auto precharge notes: 1. for this example, the bl = 1, and the wr ite burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command , regardless of frequency. 3. a8, a9, and a11 = ?don?t care.? 4. precharge comman d not allowed or t ras would be violated. disable auto precharge all banks t ch t cl t ck t rp t ras t rcd t rc dqm cke clk a0?a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row bank bank bank row row bank t wr d in m t dh t ds command t cmh t cms nop 4 nop 4 precharge active nop write active nop nop t ah t as t ah t as single bank t ckh t cks column m 3 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 don?t care
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 59 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 46: single write ? with auto precharge notes: 1. for this example, the bl = 1. 2. 15ns is required between and the precharge command , regardless of frequency. 3. a8, a9, and a11 = ?don?t care.? 4. write command not allowed or t ras would be violated. enable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqm cke clk a0?a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr d in m command t cmh t cms nop 4 nop 4 nop active nop 4 write nop active t ah t as t ah t as t dh t ds t ckh t cks nop nop column m 3 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 don?t care 2
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 60 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 47: alternating bank write accesses notes: 1. for this example, the bl = 4. 2. a8, a9, and a11 = ?don?t care.? don?t care t ch t cl t ck clk dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop active nop write nop nop active t dh t ds t dh t ds t dh t ds active write d in b t dh t ds d in b + 1 d in b + 3 t dh t ds t dh t ds enable auto precharge dqm a0?a9, a11 ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row row row row row bank 0 bank 0 bank 1 bank 0 bank 1 cke t ckh t cks d in b + 2 t dh t ds column b 2 column m 2 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t t rcd - bank 0 t wr - bank 0 wr - bank 1 t rcd - bank 1 t t rc - bank 0 rrd t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 enable auto precharge
pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 61 ?2006 micron technology, inc. all rights reserved. 64mb: 4 meg x 16 mobile sdram timing diagrams figure 48: write ? dqm operation notes: 1. for this example, the bl = 4. 2. a8, a9, and a11 = ?don?t care.? don?t care t ch t cl t ck t rcd dqm cke clk a0?a9, a11 dq ba0, ba1 a10 t cms t ah t as row bank row bank enable auto precharge d in m + 3 t dh t ds d in m d in m + 2 t cmh command nop nop nop active nop write nop nop t cms t cmh t dh t ds t dh t ds t ah t as t ah t as disable auto precharge t ckh t cks column m 2 t 0 t1 t 2 t 3 t4 t5 t 6 t7
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 64mb: 4 meg x 16 mobile sdram package dimensions pdf: 09005aef8237ed98/source: 09005aef8237ed68 micron technology, inc., reserves the right to change products or specifications without notice. 64mb_x16_mobile sdram_y24l_2.fm - rev. c 10/07 en 62 ?2006 micron technology, inc. all rights reserved. package dimensions figure 49: 54-ball vfbga (8mm x 8mm) notes: 1. all dimensions are in millimeters. ball a1 id 0.65 0.05 seating plane 0.10 c c 1.00 max ball a9 0.80 typ 0.80 typ 3.20 0.05 6.40 8.00 0.10 4.00 0.05 solder ball diameter refers to post-reflow condition. the pre-reflow diameter is 0.42. 54x ?0.45 0.05 solder ball material: 96.5% sn, 3% ag, 0.5% cu solder mask defined ball pads: ?0.40 mold compound: epoxy novolac substrate material: plastic laminate 6.40 3.20 0.05 4.00 0.05 8.00 0.10 c l c l ball a1 id ball a1

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