cystech electronics corp. spec. no. : c465y3 issued date : 2012.04.13 revised date : 2012.05.19 page no. : 1/ 8 MTP3J15Y3 cystek product specification 50v p-channel enhancement mode mosfet MTP3J15Y3 bv dss -50v i d -130ma 8 (max) r dson @-10v 10 (max) r dson @-5v 12 (max) r dson @-4v r dson @-2.5v 32 (max) features ? low gate charge ? excellent thermal and electrical capabilities ? pb-free lead plating and halogen-free package equivalent circuit outline sot-723 MTP3J15Y3 d g gate s source d drain g s absolute maximum ratings (tj=25 c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds -50 v gate-source voltage v gs 20 v continuous drain current @ t a =25 c, v gs =-10v i d -130 ma pulsed drain current (note 1) i dm -520 ma maximum power dissipation @ t a =25 (note 2) p d 150 mw thermal resistance, junction-to-ambient (note 2) r th,ja 833 c/w operating junction and storage temp erature range tj, tstg -55~+150 c note : 1. pulse width 10 s, duty cycle 2%. 2. surface mounted on 1 in2 copper pad of fr-4 board, t 5s.
cystech electronics corp. spec. no. : c465y3 issued date : 2012.04.13 revised date : 2012.05.19 page no. : 2/ 8 MTP3J15Y3 cystek product specification electrical characteristics (tj=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss -50 - - v v gs =0v, i d =-250 a v gs(th) -1 -1.4 -2 v v ds =v gs , i d =-1ma g fs 20 - - ms v ds =-3v, i d =-10ma i gss - - 10 a v gs = 20v, v ds =0 - - -1 v ds =-50v, v gs =0 i dss - - -25 v ds =-50v, v gs =0, tj=125 c - 5 8 v gs =-10v, i d =-100ma - 6 10 v gs =-5v, i d =-100ma - - 12 v gs =-4v, i d =-10ma *r ds(on) - - 32 v gs =-2.5v, i d =-1ma dynamic ciss - 25 - coss - 7 - crss - 2 - pf v ds =-5v, v gs =0, f=1mhz *t d(on) - 2.5 - *t r - 2 - *t d(off) - 7.3 - *t f - 3 - ns v ds =-15v, i d =-100ma, v gs =-5v, r g =3.3 *qg - 1.2 - nc v ds =-40v, i d =-500ma, v gs =-5v source-drain diode *i s - - -130 *i sm - - -520 ma *v sd - -0.85 -1.2 v v gs =0v, i s =-130ma *pulse test : pulse width 300 s, duty cycle 2% ordering information device package shipping marking MTP3J15Y3 sot-723 (pb-free lead plating & halogen-free package) 8000 pcs / tape & reel pd
cystech electronics corp. spec. no. : c465y3 issued date : 2012.04.13 revised date : 2012.05.19 page no. : 3/ 8 MTP3J15Y3 cystek product specification typical characteristics typical output characteristics 0 100 200 300 400 500 600 012345678910 -v ds , drain-source voltage(v) -i d , drain current (ma) -v gs =2.5v -v gs =3v -v gs =2v -v gs =3.5v -v gs =4v -v gs =4.5v -v gs =5v brekdown voltage vs ambient temperature 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) -bv dss , normalized drain-source breakdown voltage i d =-250 a, v gs =0v static drain-source on-state resistance vs drain current 4 5 6 7 8 9 10 11 12 0.001 0.01 0.1 1 -i d , drain current(a) r ds(on) , static drain-source on-state resistance() -v gs =10v -v gs =5v -v gs =3v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 0 0.1 0.2 0.3 0.4 0.5 -i dr , reverse drain current (a) -v sd , source-drain voltage(v) tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 2 4 6 8 10 12 14 16 18 20 02468 -v gs , gate-source voltage(v) r ds( on) , static drain-source on- state resistance() 10 drain-source on-state resistance vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -60 -20 20 60 100 140 180 tj, junction temperature(c) r ds( on) , normalized static drain- source on-state resistance v gs =-5v, i d =-100ma v gs =-10v, i d =-100ma i d =-100ma i d =-30ma
cystech electronics corp. spec. no. : c465y3 issued date : 2012.04.13 revised date : 2012.05.19 page no. : 4/ 8 MTP3J15Y3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 1 10 100 0.1 1 10 100 -v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 1.6 -60 -40 -20 0 20 40 60 80 100 120 140 160 tj, junction temperature(c) -v gs( th) , normalized threshold voltage i d =-250 a single pulse power rating, junction to ambient (note on page 1) 0 2 4 6 8 10 0.001 0.01 0.1 1 10 100 pulse width(s) power (w) t j( max) =150c t a =25c r ja =833c/w gate charge characteristics 0 2 4 6 8 10 0 0.6 1.2 1.8 2.4 3 3.6 qg, total gate charge(nc) -v gs , gate-source voltage(v) v ds =-40v i d =-500ma maximum drain current vs junctiontemperature 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 25 50 75 100 125 150 175 tj, junction temperature(c) -i d , maximum drain current(a) t a =25c, v gs =-10v, r ja =833c/w maximum safe operating area 0.001 0.01 0.1 1 0.01 0.1 1 10 100 -v ds , drain-source voltage(v) -i d , drain current (a) dc 100 s 1ms 10ms 100m t a =25c, tj=150c, v gs =-10v, r ja =883c/w single pulse 1s
cystech electronics corp. spec. no. : c465y3 issued date : 2012.04.13 revised date : 2012.05.19 page no. : 5/ 8 MTP3J15Y3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 100 200 300 400 500 600 0123456 -v gs , gate-source voltage(v) -i d , drain current (ma) -v ds =10v power derating curve 0 0.05 0.1 0.15 0.2 0 20 40 60 80 100 120 140 160 t a , ambient temperature() p d , power dissipation(w) surface mounted on fr-4 board of 1 in 2 copper pad transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) normalized transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *z jc (t) 4.r ja =833 c/w
cystech electronics corp. spec. no. : c465y3 issued date : 2012.04.13 revised date : 2012.05.19 page no. : 6/ 8 MTP3J15Y3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c465y3 issued date : 2012.04.13 revised date : 2012.05.19 page no. : 7/ 8 MTP3J15Y3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds 183 c 60-150 seconds time maintained above: ? temperature (t l ) 217 c ? time (t l ) 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak 10-30 seconds 20-40 seconds temperature(tp) ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c465y3 issued date : 2012.04.13 revised date : 2012.05.19 page no. : 8/ 8 MTP3J15Y3 cystek product specification sot-723 dimension *typical millimeters marking: pd style: pin 1.gate 2.source 3.drain 3-lead sot-723 plastic surface mounted package cystek package code: y3 inches millimeters inches dim min. max. min. max. dim min. max. min. max. a 0.000 0.500 0.000 0.020 d 1. 150 1.250 0.045 0.049 a1 0.000 0.050 0.000 0.002 e 1.150 1.250 0.045 0.049 b 0.170 0.270 0.007 0.011 e1 0.750 0.850 0.030 0.033 b1 0.270 0.370 0.011 0.015 e 0.800* 0.031* c 0.000 0.150 0.000 0.006 7 ref 7 ref notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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