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approximate scale 1:1 description the A8480 is a 1.2 mhz optimized boost converter with internal soft-start and compensation to support wled, flash/torch, and display bias applications. the input voltage range of 2.7 to 9 v supports either 1 or 2 li-ion battery applications. the high voltage integrated double-diffused mosfet (dmos) allows output voltages as high as 23 v with a switch current limit of 1.5 a, this increases the maximum quantity of leds that can be used in series. to maximize battery life in the application, the output can be completely disconnected from the battery voltage to virtually eliminate leakage current in the system. for system protection, the A8480 has internal overtemperature and overvoltage protection. the A8480 is available in both 1.6 mm 1.6 mm, 0.5 mm nominal height csp, and 3 mm 3 mm, 0.75 mm nominal height mlp/dfn packages. applications include: ? wled flash/torch ? wled backlight ? oled bias supplies ? lcd bias supplies ? general purpose boost converter 8480-ds features and benefits ? output disconnect during shutdown ? 1 a shutdown current ? 2.7 to 9 v input ? operate with 1 or 2 li+ battery input supply ? output voltage up to 23 v ? 1.2 mhz switching frequency ? 1.5 a switch current limit ? internal overvoltage and overtemperature protection, and soft start boost regulator for display bias or led driver typical applications A8480 package: 9-pin csp (suffix cg) 10-pin mlp/dfn (suffix ej) with exposed thermal pad A8480 sw cap out1 gnd on1 vin ej only fbadj dim cin 1 f 6.3 v l1 22 h d1 v out mbra130lt3 30 48 k 12.1 k cout 2.2 f 16 v v supply 2.8 to 5 v radj a1[7] [pgnd] fb[fb1] a3[10] a2[9] b3[8] c3[6] c2[5] c1[4] b1[3] b2[2] [1] square brackets indicate pin names or numbers used only with the ej package; where no brackets are shown with a pin name, name applies to both cg and ej packages figure 1. using the A8480 to drive a flash (100 ma) or torch (20 ma)
boost regulator for display bias or led driver A8480 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number package packing a A8480ecglt-t b 9-bump chip scale package tape and reel A8480eejtr-t 10-pin mlp/dfn package 1500 pieces per reel a contact allegro for additional packing options. b contact allegro factory for availability. ab so lute max i mum rat ings package thermal characteristics input or output voltage sw, cap, out1, fbadj pins ................................. ?0.3 to 26 v vin pin, v in ............................................................. ?0.3 to 9.5 v all other pins, v x ....................... ?0.3 to v in + 0.3 v (7 v max.) operating ambient temperature, t a ................................ ?40c to 85c maximum junction temperature, t j (max) ...................................... 150c storage temperature, t stg ............................................. ?55c to 150c vin sw clock on/off logic soft start pad ramp drive s1 c1 c2 r temp uvlo v cap c4 s oscillator fault protection fb [ej only: fb1] dim on1 r q 0.6 v error amplifier v ref1 fbadj cap out1 s2 s3 gnd pgnd ej only ej only cg only functional block diagram packages are lead (pb) free. ej package has 100% matte tin leadframe plating. ej package: r ja = 45 c/w, on a 4-layer board. additional information is available on the allegro web site.
boost regulator for display bias or led driver A8480 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagrams a3 b3 c3 a2 b2 c2 a1 b1 c1 terminal list table number name description cg ej ? 1 pgnd power ground connection; use to avoid interference with signal ground. a1 ? gnd power and signal ground connection; connect directly to the ground plane. ? 7 gnd signal ground reference; connect directly to the ground plane. a2 9 cap this is the connection to the output capacitor for the boost regulator output. a3 10 sw this is the connection between the internal boost switch and the external inductor. because rapid changes of current occur at this pin, the board traces connected to this pin should be minimized and the inductor and diode should be connected as close to this pin as possible. b1 3 vin this is the power input supply connection to the circuit. a bypass capacitor tying this pin to gnd must be connected close to this pin. b2 ? fb this is the feedback pin for controlling voltage on the out1 pin. the nominal reference voltage on this pin is 600 mv. in order to minimize noise, connect the feedback resistor network close to this pin. ? 2 fb1 b3 8 out1 this is the voltage-controlled output pin for the oled drive. an internal switch disconnects the oled during shutdown. c1 4 fbadj open collector output driven by dim. this can be used to provide dimming by connecting an additional feedback circuit or it can be used to drive external output. c2 5 dim logic input. driving dim puts the fbadj open collector output low. c3 6 on1 this is the enable pin for out1. ? pad ? exposed thermal pad. connect to gnd plane for enhanced thermal performance. 1 2 3 4 5 10 9 8 7 6 pad cg package (top view) ej package (top view)
boost regulator for display bias or led driver A8480 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics at t a = 25c, vin = on1 = dim = 3.0 v (unless noted otherwise) characteristics symbol test conditions min. typ. max. units input voltage range v in 2.7 ? 9 v quiescent input current i in(q) dim=on1=0 ? ? 1 a undervoltage lockout threshold v uvlo v in rising 2.25 2.45 2.60 v feedback reference voltage v fb 584 610 636 mv feedback voltage line regulation 2.7 v v in 9 v ? 0.1 ? %/v feedback input current i fb ? 45 100 na switch current limit i swlim ? 1.5 ? a switch frequency f sw 1 1.2 1.4 mhz switch maximum duty cycle* dc 85 90 ? % switch s1 on resistance r ds1(on) i sw = 0.5 a ? 225 ? m switch leakage current i sw(lkg) v sw = 5 v ? ? 1 a fbadj mosfet on resistance r dsf(on) v dim > v ih ?10? fbadj mosfet leakage current i fbadj(lkg) v dim < v il , v fbadj = 0.6 v ? 1 ? a on1, dim input threshold low v il ? ? 0.4 v on1, dim input threshold high v ih 1.5 ? ? v on1, dim input bias current i ib ?65? a output overvoltage rising limit v ovpr ? 24.5 25.5 v thermal shutdown threshold t shdn ? 160 ? c thermal shutdown hysteresis t shdnhys ?10?c soft-start period t ss v out = 10 v ? 2 ? ms *guaranteed by design.
boost regulator for display bias or led driver A8480 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com performance characteristics tests performed using application circuit shown in figure 4 l1 = 4.7 h, c in = c out = 1 f, t a = 25c (unless otherwise noted) 50.00 55.00 60.00 65.00 70.00 75.00 80.00 85.00 90.00 0 20406080 load current (ma) efficiency (%) 5.0 4.2 3.3 efficiency versus load current v out = 12 v v in (v) 2.5 50.00 55.00 60.00 65.00 70.00 75.00 80.00 85.00 90.00 0 20406080 load current (ma) efficiency (%) v out = 15 v 5.0 4.2 3.3 v in (v) 2.5 efficiency versus load current v out = 18 v 50.00 55.00 60.00 65.00 70.00 75.00 80.00 85.00 90.00 0 20406080 load current (ma) efficiency (%) 5.0 4.2 3.3 v in (v) 2.5 4.2 3.3 2.5 -3.00 0 20 40 60 80 100 120 140 160 -2.50 -2.00 -1.50 -1.00 -0.50 0 0.50 1.00 i out (ma) load regulation (%) load regulation v out = 12 v v in (v) 5.0 4.2 3.6 3.0 -3.00 -2.50 -2.00 -1.50 -1.00 -0.50 0 0.50 1.00 i out (ma) load regulation (%) load regulation v out = 15 v v in (v) 5.0 4.2 3.6 3.0 0 20 40 60 80 100 120 140 160 -3.00 -2.50 -2.00 -1.50 -1.00 -0.50 0 0.50 1.00 i out (ma) load regulation (%) v in (v) 5.0 4.2 3.6 3.0 load regulation v out = 18 v 0 20406080100120140160
boost regulator for display bias or led driver A8480 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com symbol parameter units/division c1 i l 500 ma c2 v out1 10.0 v c3 v sw 10.0 v c4 v on1 2.00 v t time 5 ms conditions parameter value v in 3.3 v v out 18 v i out 80 ma startup -3.00 -2.50 -2.00 -1.50 -1.00 -0.50 0 0.50 1.00 2.5 3.3 4.2 5 7 9 v in (v) line regulation (%) line regulation v out = 12 v dimming level (ma) 0 20 40 60 80 -3.00 -2.50 -2.00 -1.50 -1.00 -0.50 0 0.50 1.00 2.5 3.3 4.2 5 7 9 v in (v) line regulation (%) line regulation v out = 15 v dimming level (ma) 0 20 40 60 80 line regulation v out = 18 v -3.50 -3.00 -2.50 -2.00 -1.50 -1.00 -0.50 0 0.50 2.5 3.3 4.2 5 7 9 v in (v) dimming level (ma) line regulation (%) 0 20 40 60 80 t v out1 v on1 c3 c1 c2 i l v sw c4 symbol parameter units/division c1 i l 500 ma c2 v out1 10.0 v c3 v sw 10.0 v c4 v on1 2.00 v t time 5 ms conditions parameter value v in 3.3 v v out 18 v i out 80 ma shutdown t v out1 v on1 c3 c1 c2 i l v sw c4
boost regulator for display bias or led driver A8480 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the A8480 is a boost converter with output disconnect. the boost stage boosts input battery voltage to a sufficient level to drive an oled or a set of series-connected wleds. this stage uses 1.2 mhz constant frequency, current mode control. typical appli- cation circuits are shown in figure 1, and the typical applications section. when out1 is enabled and v in is greater than v in (min), the boost stage is ramped-up with soft start, with switch, s2, com- pletely turned on. the constant voltage drive for oled is provided through the out1 pin. the internal switch between the cap and out1 pins disconnects the oled when out1 is disabled. for driving oleds, output voltage is sensed by the fb1 pin through a voltage divider network. output voltage (v) is set as: v out1 = 0.61 r 2 r 1 + r 2 (1) when dim is high and rfbadj is used (r2 is configured in parallel with rfbadj in the circuit; see figure 4a), the output voltage is set as follows: v out1 = 0.61 r 1 + r 2 r fbadj r 2 + r fbadj ? ? r 2 r fbadj r 2 + r fbadj (2) the A8480 provides protection against output overvoltage on the cap pin, overload, and overtemperature. also, it has an input undervoltage lockout to avoid malfunction and battery drain. at light loads, instantaneous inductor current drops to zero. this is known as discontinuous mode operation and will result in some low frequency ripple. in discontinuous mode, the voltage at the sw pin will ring, due to the resonant lc circuit formed by the inductor and the switch and diode capacitance. this ringing is low frequency and is not harmful. it can be damped with a resis- tor across the inductor, but this will reduce efficiency and is not recommended. dual oled application the A8480 can be easily used as a dual oled driver. in this application, the main oled can be connected to out1 and the sub oled can be connected between the output of the boost stage, at v out , and the fbadj pin, as in the application shown in figure 5. the sub oled is controlled by the dim pin. pulling the dim pin high turns on the internal switch s3, which pulls the fbadj pin low, allowing the sub oled to turn on. figure 5 shows that the sub oled is grounded as well. functional description
boost regulator for display bias or led driver A8480 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com component selection the component values shown in the application circuits will be sufficient for most applications (typical application circuits are shown in figure 1, and the typical applications section). to reduce the output ripple, the output inductor may be increased in value, but in most cases this will result in excessive board area and cost. inductor selection the inductor is the most important component in the power supply design because it affects the steady-state performance, transient response, and loop stability. the inductance value, dc resistance, and the saturation current should be considered when choosing the inductor. the dc current of the inductor can be calculated by: v out i out v in i l_dc = (3) and the inductance value can be calculated by: 1 f v i min v out l min 1 C = ? i v i min ? ? ? ? ? ? ? ? (4) where ? i = (20% to 40%) i l_dc is the peak-to-peak ripple cur- rent. smaller inductance values force the converter into discontinuous mode, which will reduce the maximum output current. larger inductance values reduce the gain and phase margin, which will result in instability of the loop. the inductor should have low winding resistance, typically < 0.2 and low 1.2 mhz core loss for better efficiency . the inductor should have a saturation current higher than 1.5 a, in order to provide 20 v at the out1 pin, and 100 ma at 2.7 v in . for high temperature operation, a suitable derating factor should be considered. several inductor manufacturers, including: coilcraft, murata, panasonic, sumida, taiyo yuden, and tdk, have and are developing suitable small-size inductors. diode selection the diode should have a low forward voltage to reduce conduc- tion losses and a low capacitance to reduce switching losses. schottky diodes can provide both of these features, if carefully selected. the forward voltage drop is a natural advantage for schottky diodes and decreases as the current rating increases. however, as the current rating increases, the diode capacitance also increases, so the optimum selection is usually the lowest cur- rent rating above the circuit maximum. the diode rms current rating should be: i out (1C d ) 1/2 i diode(rms) = (5) diode piv should be higher than the output voltage on the cap pin. capacitor selection the input capacitor selection is based on the input voltage ripple. it can be calculated as: f sw 8 ? i v in(ripple) c in (min) = (6) where v in(ripple) is the input ripple. the output capacitor selection is based on the output ripple requirement. it can be calculated by: 1 f v out C v in v out i out v ripple(pp) c out = (7) where v ripple is the peak-to-peak output ripple. in addition, the esr-related output ripple can be calculated by: v ripple(esr) i out esr . = (8) if a ceramic capacitor is selected, the esr-related ripple can be neglected, due to the low esr. if a tantalum electrolytic capacitor is selected, this portion of ripple voltage has to be considered. during load transient response, a larger output capacitance always helps to supply or absorb additional current, which results in lower overshoot and undershoot voltage. because the capacitor values are low, ceramic capacitors are the best choice for this application. to reduce performance variation over temperature, low drift types such as x7r and x5r should be used. recommended specifications are shown in the table below. suitable capacitors are available from tdk, taiyo yuden, murata, kemet, and avx. the output capacitor is placed on the cap pin only. an additional capacitor can be added on the out1 pin, but it is not needed for proper operation and it cannot replace the capacitor on the cap pin. applications information
boost regulator for display bias or led driver A8480 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 2a. dual outputs (v out and ?v out ) A8480 sw cap out1 on1 [gnd] fb[fb1] vin fbadj dim cin l1 d1 v out1 v out2 +5 v r1 cout 820 k r2 61.9 k d2 d3 d4 bat54s bat54s v sw 512 k r4 3.3 k r3 ?7.5 v 8.75 v 50 ma 2.2 f 16 v 7.5 v cs4 1 f 25 v 1 f 25 v cs1 1 f 25 v cs2 cs3 2.2 f 16 v cs5 10 h ej only a3[10] a2[9] b3[8] a1[1] c3[6] c2[5] c1[4] [7] b1[3] gnd[pgnd] b2[2] square brackets indicate pin names or numbers used only with the ej package; where no brackets are shown with a pin name, name applies to both cg and ej packages typical application circuits figure 2b. triple outputs (v out , ?v out , and 2v out ) A8480 sw cap out1 on1 vin fbadj cin l1 d1 +5 v r1 cout 820 k r2 61.9 k d2 d3 d4 bat54s bat54s v sw 512 k r4 3.3 k r3 v out3 ?7.5 v v out1 8.75 v 50 ma 2.2 f 16 v 7.5 v cs4 1 f 25 v 1 f 25 v cs1 1 f 25 v cs2 cs3 2.2 f 16 v cs5 1 f 25 v cs6 d5 d6 bat54s 15 k r6 1 k r5 v out2 +15 v 2.2 f 16 v 16 v cs7 2.2 f 16 v cs8 10 h [gnd] fb[fb1] dim ej only a3[10] a2[9] a1[1] c3[6] c1[4] [7] b1[3] c2[5] gnd[pgnd] b2[2] square brackets indicate pin names or numbers used only with the ej package; where no brackets are shown with a pin name, name applies to both cg and ej packages
boost regulator for display bias or led driver A8480 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 3. using the A8480 to drive 10 white leds (wled) A8480 vin sw cap out1 gnd on1 fb[fb1] fbadj dim cin d10 d9 l1a 10 h l1a, l1b 744878100; wurth electronics d0 bat400d-7 dz in4747adict l1b 10 h d0 dz v out r2 30 cout li+ battery 2.7 to 5.5 v d2 d1 a3[10] a2[9] b3[8] a1[7] c3[6] c2[5] c1[4] [1] b1[3] [pgnd] b2[2] ej only square brackets indicate pin names or numbers used only with the ej package; where no brackets are shown with a pin name, name applies to both cg and ej packages (%) 67 68 69 70 71 72 73 74 2.5 3.0 3.5 4.5 4.0 5.0 5.5 v in (v) efficiency versus input voltage figure 4a. typical application circuit for A8480 driving an oled with dimming. A8480 sw cap out1 on1 gnd fb[fb1] vin fbadj dim cin l1 d1 v out r1 r2 radj cout li+ battery oled ej only square brackets indicate pin names or numbers used only with the ej package; where no brackets are shown with a pin name, name applies to both cg and ej packages a3[10] a2[9] b3[8] a1[7] c3[6] c2[5] c1[4] [1] b1[3] [pgnd] b2[2] figure 4b. timing diagram for circuit shown in figure 4a. on1 dim v out
boost regulator for display bias or led driver A8480 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com A8480 sw cap out1 on1 gnd[pgnd] fb[fb1] vin fbadj dim cin l1 d1 v out v batt v in r3 r4 cout 18 v +5 v + 8 to 16 v r1 r2 oled [gnd] a3[10] a2[9] b3[8] a1[1] c3[6] c2[5] c1[4] b1[3] b2[2] ej only [7] square brackets indicate pin names or numbers used only with the ej package; where no brackets are shown with a pin name, name applies to both cg and ej packages A8480 sw cap out1 gnd on1 fb[fb1] vin fbadj dim cin l1 d1 v out cout 3 v 3.4 v 250 ma r2 2.5 ej only a3[10] a2[9] b3[8] a1[7] c3[6] c2[5] c1[4] [1] b1[3] [pgnd] b2[2] square brackets indicate pin names or numbers used only with the ej package; where no brackets are shown with a pin name, name applies to both cg and ej packages figure 6. oled supply for gps/auto infotainment, with external output disconnect fet figure 7. A8480 driving high current flash/torch leds figure 5. main and sub oled bias with both grounded A8480 sw cap out1 gnd on1 fb[fb1] vin fbadj dim cin l1 d1 v out r1 r2 cout oled main r3 r4 li+ battery oled sub ej only a3[10] a2[9] b3[8] a1[7] c3[6] c2[5] c1[4] [1] b1[3] [pgnd] b2[2] square brackets indicate pin names or numbers used only with the ej package; where no brackets are shown with a pin name, name applies to both cg and ej packages (%) 87 88 89 90 91 92 94 93 95 96 8 10121416 v batt (v) efficiency versus input voltage 300 ma 250 ma 200 ma 00 ma
boost regulator for display bias or led driver A8480 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package cg, 9-pin csp ? 0.255 x ? .25 1.605 1.625 0.50 1.00 0.50 0.50 0.50 0.302 1.00 1.00 1.00 0.50 0.312 a b c c b a 321 a b c 321 1 2 3 a die orientation mark all dimensions nominal, not for tooling use dimensions in millimeters dimensions exclusive of burrs exact configuration at supplier discretion within limits shown a terminal #1 mark area b b c c reference pad layout; all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances pcb layout reference view seating plane c c 0.05 9x
boost regulator for display bias or led driver A8480 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ej, 10-pin mlp/dfn 2.38 10 10 2 1 2 1 a a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) all dimensions nominal, not for tooling use (reference jedec mo-229weed) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c reference land pattern layout (reference ipc7351 son50p300x300x80-11weed3m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) b pcb layout reference view 1.65 2.38 0.30 1 10 0.50 0.85 3.10 c 1.65 3.00 3.00 0.75 0.25 0.50 0.40 c 0.08 11x d d coplanarity includes exposed thermal pad and terminals copyright ?2007, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

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