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1 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b 8m-bit [1024k x 8 / 512k x 16] single voltage 5v only flash memory features general features ? single power supply operation - 4.5 to 5.5 volt for read, erase, and program operations ? 1,048,576 x 8 / 524,288 x 16 switchable ? boot sector architecture - t = top boot sector - b = bottom boot sector ? sector structure - 16k-byte x 1, 8k-byte x 2, 32k-byte x 1, and 64k-byte x 15 ? sector protection - hardware method to disable any combination of sectors from program or erase operations - temporary sector unprotected allows code changes in previously locked sectors ? latch-up protected to 100ma from -1v to vcc + 1v ? compatible with jedec standard - pinout and software compatible to single power supply flash performance ? high performance - access time: 70ns - byte/word program time: 9us/11us (typical) - erase time: 0.7s/sector, 8s/chip (typical) ? low power consumption - low active read current: 40ma (maximum) at 5mhz - low standby current: 1ua (typical) ? minimum 100,000 erase/program cycle ? 20 years data retention software features ? erase suspend/ erase resume - suspends sector erase operation to read data from or program data to another sector which is not being erased ? status reply - data# polling & toggle bits provide detection of program and erase operation completion hardware features ? ready/busy# (ry/by#) output - provides a hardware method of detecting program and erase operation completion ? hardware reset (reset#) input - provides a hardware method to reset the internal state machine to read mode package ? 44-pin sop ? 48-pin tsop ? 48-ball tfbga (6x8mm) ? all pb-free devices are rohs compliant ? all non rohs compliant devices are not recommeded for new design in
2 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b pin configurations 44 sop(500mil) 48 tsop(type i) (12mm x 20mm) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce# gnd oe# q0 q8 q1 q9 q2 q10 q3 q11 reset# we# a8 a9 a10 a11 a12 a13 a14 a15 a16 byte# gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc mx29f800ct/cb a15 a14 a13 a12 a11 a10 a9 a8 nc nc we# reset# nc nc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 byte# gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc q11 q3 q10 q2 q9 q1 q8 q0 oe# gnd ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mx29f800c t/b
3 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b logic symbol pin description symbol pin name a0~a18 address input q0~q14 data input/output q15/a-1 q15(word mode)/lsb addr(byte mode) ce# chip enable input we# write enable input byte# word/byte selection input reset# hardware reset pin/sector protect unlock oe# output enable input ry/by# ready/busy output vcc power supply pin (+5v) gnd ground pin 16 or 8 q0-q15 (a-1) ry/by# a0-a18 ce# oe# we# reset# byte# 19 a13 6 5 4 3 2 1 a b c d e f g h a9 a7 a3 we# ry/ by# a12 a8 nc a17 a4 a14 a10 nc a18 a6 a2 a15 a11 re- set# nc nc a5 a1 a16 q7 q5 q2 q0 a0 byte# q15/ a-1 q14 q12 q10 q8 q13 vcc q11 q9 gnd q6 q4 q3 q1 gnd ce# oe# 48-ball tfbga (6x8mm)
4 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b block diagram control input logic program/erase high voltage write state machine (wsm) state register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15/a-1 a0-am am: msb address ce# oe# we# reset# byte#
5 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b table 1. sector structure note: address range is a18~a-1 in byte mode and a18~a0 in word mode. mx29f800ct top boot sector address table mx29f800cb bottom boot sector address table sector sector size address range sector address byte mode word mode byte mode (x8) word mode(x16) a18 a17 a16 a15 a14 a13 a12 sa0 64kbytes 32kwords 00000h-0ffffh 00000h-07fffh 0 0 0 0 x x x sa1 64kbytes 32kwords 10000h-1ffffh 08000h-0ffffh 0 0 0 1 x x x sa2 64kbytes 32kwords 20000h-2ffffh 10000h-17fffh 0 0 1 0 x x x sa3 64kbytes 32kwords 30000h-3ffffh 18000h-1ffffh 0 0 1 1 x x x sa4 64kbytes 32kwords 40000h-4ffffh 20000h-27fffh 0 1 0 0 x x x sa5 64kbytes 32kwords 50000h-5ffffh 28000h-2ffffh 0 1 0 1 x x x sa6 64kbytes 32kwords 60000h-6ffffh 30000h-37fffh 0 1 1 0 x x x sa7 64kbytes 32kwords 70000h-7ffffh 38000h-3ffffh 0 1 1 1 x x x sa8 64kbytes 32kwords 80000h-8ffffh 40000h-47fffh 1 0 0 0 x x x sa9 64kbytes 32kwords 90000h-9ffffh 48000h-4ffffh 1 0 0 1 x x x sa10 64kbytes 32kwords a0000h-affffh 50000h-57fffh 1 0 1 0 x x x sa11 64kbytes 32kwords b0000h-bffffh 58000h-5ffffh 1 0 1 1 x x x sa12 64kbytes 32kwords c0000h-cffffh 60000h-67fffh 1 1 0 0 x x x sa13 64kbytes 32kwords d0000h-dffffh 68000h-6ffffh 1 1 0 1 x x x sa14 64kbytes 32kwords e0000h-effffh 70000h-77fffh 1 1 1 0 x x x sa15 32kbytes 16kwords f0000h-f7fffh 78000h-7bfffh 1 1 1 1 0 x x sa16 8kbytes 4kwords f8000h-f9fffh 7c000h-7cfffh 1 1 1 1 1 0 0 sa17 8kbytes 4kwords fa000h-fbfffh 7d000h-7dfffh 1 1 1 1 1 0 1 sa18 16kbytes 8kwords fc000h-fffffh 7e000h-7ffffh 1 1 1 1 1 1 x sector sector size address range sector address byte mode word mode byte mode (x8) word mode(x16) a18 a17 a16 a15 a14 a13 a12 sa0 16kbytes 8kwords 00000h-03fffh 00000h-01fffh 0 0 0 0 0 0 x sa1 8kbytes 4kwords 04000h-05fffh 02000h-02fffh 0 0 0 0 0 1 0 sa2 8kbytes 4kwords 06000h-07fffh 03000h-03fffh 0 0 0 0 0 1 1 sa3 32kbytes 16kwords 08000h-0ffffh 04000h-07fffh 0 0 0 0 1 x x sa4 64kbytes 32kwords 10000h-1ffffh 08000h-0ffffh 0 0 0 1 x x x sa5 64kbytes 32kwords 20000h-2ffffh 10000h-17fffh 0 0 1 0 x x x sa6 64kbytes 32kwords 30000h-3ffffh 18000h-1ffffh 0 0 1 1 x x x sa7 64kbytes 32kwords 40000h-4ffffh 20000h-27fffh 0 1 0 0 x x x sa8 64kbytes 32kwords 50000h-5ffffh 28000h-2ffffh 0 1 0 1 x x x sa9 64kbytes 32kwords 60000h-6ffffh 30000h-37fffh 0 1 1 0 x x x sa10 64kbytes 32kwords 70000h-7ffffh 38000h-3ffffh 0 1 1 1 x x x sa11 64kbytes 32kwords 80000h-8ffffh 40000h-47fffh 1 0 0 0 x x x sa12 64kbytes 32kwords 90000h-9ffffh 48000h-4ffffh 1 0 0 1 x x x sa13 64kbytes 32kwords a0000h-affffh 50000h-57fffh 1 0 1 0 x x x sa14 64kbytes 32kwords b0000h-bffffh 58000h-5ffffh 1 0 1 1 x x x sa15 64kbytes 32kwords c0000h-cffffh 60000h-67fffh 1 1 0 0 x x x sa16 64kbytes 32kwords d0000h-dffffh 68000h-6ffffh 1 1 0 1 x x x sa17 64kbytes 32kwords e0000h-effffh 70000h-77fffh 1 1 1 0 x x x sa18 64kbytes 32kwords f0000h-fffffh 78000h-7ffffh 1 1 1 1 x x x
6 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b table 2. bus operation notes: 1. vhv is the very high voltage, 11.5v to 12.5v. 2. x means input high (vih) or input low (vil). 3. sa means sector address: a12~a18. 4. code=00h/xx00h means unprotected. code=01h/xx01h means protected. mode pins ce# oe# we# reset# a0 a1 a6 a9 q0 ~ q15 read silicon id manufacture code l l h h l l x vhv c2h (byte mode) 00c2h (word mode) read silicon id device code l l h h h l x vhv d6/58 (byte mode) 22d6/2258(word mode) read l l h h a0 a1 a6 a9 d out standby h x x h x x x x high z output disable l h h h x x x x high z write l h l h a0 a1 a6 a9 d in sector protect l h l vhv l h l x d in chip unprotect l h l vhv l h h x d in verify sector protect/unprotect l l h h l h l vhv code(4) reset x x x l x x x x high z
7 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b requirements for reading array data read array action is to read the data stored in the array out. while the memory device is in powered up or has been reset, it will automatically enter the status of read array. if the microprocessor wants to read the data stored in array, it has to drive ce# (device enable control pin) and oe# (output control pin) as vil, and input the address of the data to be read into address pin at the same time. after a period of read cycle (tce or taa), the data being read out will be displayed on output pin for microprocessor to access. if ce# or oe# is vih, the output will be in tri-state, and there will be no data displayed on output pin at all. after the memory device completes embedded operation (automatic erase or program), it will automatically re- turn to the status of read array, and the device can read the data in any address in the array. in the process of erasing, if the device receives the erase suspend command, erase operation will be stopped after a period of time no more than treadyand the device will return to the status of read array. at this time, the device can read the data stored in any address except the sector being erased in the array. in the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. similarly, if program command is issued after erase suspend, after program operation is completed, system can still read ar- ray data in any address except the sectors to be erased. the device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. in program or erase operation, the programming or erasing failure causes q5 to go high. 2. the device is in auto select mode. in the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. write commands/command sequences to write a command to the device, system must drive we# and ce# to vil, and oe# to vih. in a command cycle, all address are latched at the later falling edge of ce# and we#, and all data are latched at the earlier rising edge of ce# and we#. figure 1 illustrates the ac timing waveform of a write command, and table 3 defnes all the valid command sets of the device. system is not allowed to write invalid commands not defned in this datasheet. writing an invalid command will bring the device to an undefned state. reset# operation driving reset# pin low for a period more than trp will reset the device back to read mode. if the device is in program or erase operation, the reset operation will take at most a period of tready for the device to return to read array mode. before the device returns to read array mode, the ry/by# pin remains low (busy status). when reset# pin is held at gnd 0.3v, the device consumes standby current(isb).however, device draws larg- er current if reset# pin is held at vil but not within gnd 0.3v. it is recommended that the system to tie its reset signal to reset# pin of fash memory, so that the fash memo- ry will be reset during system reset and allows system to read boot code from fash memory.
8 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b sector protect operation when a sector is protected, program or erase operation will be disabled on these sectors. mx29f800c t/b pro- vides one method for sector protection. once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by asserting reset# pin at vhv. refer to temporary sector unprotect operation for further details. this method is by applying vhv on reset# pin. refer to figure 12 for timing diagram and figure 13 for the al- gorithm for this method. chip unprotect operation mx29f800c t/b provides one method for chip unprotect. the chip unprotect operation unprotects all sectors within the device. it is recommended to protect all sectors before activating chip unprotect mode. all sector are unprotected when shipped from the factory. this method is by applying vhv on reset# pin. refer to figure 12 for timing diagram and figure 13 for algo - rithm of the operation. temporary sector unprotect operation system can apply reset# pin at vhv to place the device in temporary unprotect mode. in this mode, previously protected sectors can be programmed or erased just as it is unprotected. the devices returns to normal opera - tion once vhv is removed from reset# pin and previously protected sectors are again protected. automatic select operation when the device is in read array mode or erase-suspended read array mode, user can issue read silicon id command to enter read silicon id mode. after entering read silicon id mode, user can query several silicon ids continuously and does not need to issue read silicon id mode again. when a0 is low, device will output ma- cronix manufacture id c2. when a0 is high, device will output device id. in read silicon id mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. another way to enter read silicon id is to apply high voltage on a9 pin with ce#, oe# and a1 at vil. while the high voltage of a9 pin is discharged, device will automatically leave read silicon id mode and go back to read array mode or erase-suspended read array mode. when a0 is low, device will output macronix manufacture id c2. when a0 is high, device will output device id.
9 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b verify sector protect status operation mx29f800c t/b provides hardware sector protection against program and erase operation for protected sec- tors. the sector protect status can be read through sector protect verify command. this method requires v hv on a9 pin, vih on we# and a1 pins, vil on ce#, oe#, a6 and a0 pins, and sector address on a12 to a17 pins. if the read out data is 01h, the designated sector is protected. oppositely, if the read out data is 00h, the designated sector is still not being protected. data protection to avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. besides, only after successful completion of the specifed command sets will the device begin its erase or program operation. other features to protect the data from accidental alternation are described as followed. write pulse "glitch" protection ce#, we#, oe# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. logical inhibit a valid write cycle requires both ce# and we# at vil with oe# at vih. write cycle is ignored when either ce# at vih, we# a vih, or oe# at vil. power-up sequence upon power up, mx29f800c t/b is placed in read array mode. furthermore, program or erase operation will be- gin only after successful completion of specifed command sequences. power-up write inhibit when we#, ce# is held at vil and oe# is held at vih during power up, the device ignores the frst command on the rising edge of we#. power supply decoupling a 0.1uf capacitor should be connected between the vcc and gnd to reduce the noise effect.
10 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b table 3. mx29f800c t/b command definitions notes: 1. device id: 22d6h/d6h for top boot sector device. 2258h/58h for bottom boot sector device. 2. for sector protect verify result, xx00h/00h means sector is not protected, xx01h/01h means sector has been protected. 3. sector protect command is valid during vhv at reset# pin, vih at a1 pin and vil at a0, a6 pins. the last bus cyc is for protect verify. 4. it is not allowed to adopt any other code which is not in the above command defnition table. command read mode reset mode automatic select manufacturer id device id sector protect verify word byte word byte word byte 1st bus cycle addr addr xxx 555 aaa 555 aaa 555 aaa data data f0 aa aa aa aa aa aa 2nd bus cycle addr 2aa 555 2aa 555 2aa 555 data 55 55 55 55 55 55 3rd bus cycle addr 555 aaa 555 aaa 555 aaa data 90 90 90 90 90 90 4th bus cycle addr x00 x00 x01 x02 (sector)x02 (sector)x04 data 00c2 c2 id id xx00/xx01 00/01 5th bus cycle addr data 6th bus cycle addr data command program chip erase sector erase erase suspend erase resume sector protect word byte word byte word byte word byte 1st bus cycle addr 555 aaa 555 aaa 555 aaa sector sector xxx xxx data aa aa aa aa aa aa b0 30 60 60 2nd bus cycle addr 2aa 555 2aa 555 2aa 555 sector sector data 55 55 55 55 55 55 60 60 3rd bus cycle addr 555 aaa 555 aaa 555 aaa sector sector data a0 a0 80 80 80 80 40 40 4th bus cycle addr addr addr 555 aaa 555 aaa sector sector data data data aa aa aa aa 00/01 00/01 5th bus cycle addr 2aa 555 2aa 555 data 55 55 55 55 6th bus cycle addr 555 aaa sector sector data 10 10 30 30
11 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b reset in the following situations, executing reset command will reset device back to read array mode: ? among erase command sequence (before the full command set is completed) ? sector erase time-out period ? erase fail (while q5 is high) ? among program command sequence (before the full command set is completed, erase-suspended program included) ? program fail (while q5 is high, and erase-suspended program fail is included) ? read silicon id mode ? sector protect verify while device is at the status of program fail or erase fail (q5 is high), user must issue reset command to reset device back to read array mode. while the device is in read silicon id mode or sector protect verify mode, user must issue reset command to reset device back to read array mode. when the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ig- nore reset command. automatic select command sequence automatic select mode is used to access the manufacturer id, device id and to verify whether or not a sector is protected. the automatic select mode has four command cycles. the frst two are unlock cycles, and followed by a specifc command. the fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. the reset command is necessary to exit the automatic se- lect mode and back to read array. the following table shows the identifcation code with corresponding address. address data (hex) representation manufacturer id word x00 00c2 byte x00 c2 device id word x01 22d6/2258 top/bottom boot sector byte x02 d6/58 top/bottom boot sector sector protect verify word (sector address) x 02 00/01 unprotected/protected byte (sector address) x 04 00/01 unprotected/protected there is an alternative method to that shown in table 2, which is intended for eprom programmers and requires vhv on address bit a9.
12 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b automatic programming the mx29f800c t/b can provide the user program function by the form of byte-mode or word-mode. as long as the users enter the right cycle defned in the table.3 (including 2 unlock cycles and a0h), any data user inputs will automatically be programmed into the array. once the program function is executed, the internal write state controller will automatically execute the algo - rithms and timings necessary for program and verifcation, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verifcation. meanwhile, the internal control will prohibit the programming to cells that pass verifcation while the other cells fail in verifcation in order to avoid over-programming. programming will only change the bit status from "1" to "0". that is to say, it is impossible to convert the bit status from "0" to "1" by programming. meanwhile, the internal write verifcation only detects the errors of the "1" that is not successfully programmed to "0". any command written to the device during programming will be ignored except hardware reset, which will termi- nate the program operation after a period of time no more than tready. when the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. with the internal write state controller, the device requires the user to write the program command and data only. the typical chip program time at room temperature of the mx29f800c t/b is 3 seconds. (word-mode) when the embedded program operation is on going, user can confrm if the embedded operation is fnished or not by the following methods: *1: the status "in progress" means both program mode and erase-suspended program mode. *2: ry/by# is an open drain output pin and should be weakly connected to vdd through a pull-up resistor. *3: when an attempt is made to program a protected sector, q7 will output its complement data or q6 continues to toggle for about 1us and the device returns to read array state without programing the data in the protected sector. status q7 q6 q5 ry/by#*2 in progress*1 q7# toggling 0 0 finished q7 stop toggling 0 1 exceed time limit q7# toggling 1 0
13 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b sector erase sector erase is to erase all the data in a sector with "1" and "0" as all "1". it requires six command cycles to is- sue. the frst two cycles are "unlock cycles", the third one is a confguration cycle, the fourth and ffth are also "unlock cycles" and the sixth cycle is the sector erase command. after the sector erase command sequence is issued, there is a time-out period of 40us counted internally. during the time-out period, additional sector ad- dress and sector erase command can be written multiply. once user enters another sector erase command, the time-out period of 40us is recounted. if user enters any command other than sector erase or erase suspend dur- ing time-out period, the erase command would be aborted and the device is reset to read array condition. the number of sectors could be from one sector to all sectors. after time-out period passing by, additional erase com- mand is not accepted and erase embedded operation begins. during sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. when the embedded erase operation is on going, user can confrm if the embedded operation is fnished or not by the following methods: status q7 q6 q5 q3 q2 ry/by#*2 time-out period 0 toggling 0 0 toggling 0 in progress 0 toggling 0 1 toggling 0 finished 1 stop toggling 0 1 1 1 exceed time limit 0 toggling 1 1 toggling 0 chip erase chip erase is to erase all the data with "1" and "0" as all "1". it needs 6 cycles to write the action in, and the frst two cycles are "unlock" cycles, the third one is a confguration cycle, the fourth and ffth are also "unlock" cycles, and the sixth cycle is the chip erase operation. during chip erasing, all the commands will not be accepted except hardware rests or the working voltage is too low that chip erase will be interrupted. after chip erase, the chip will return to the state of read array. when the embedded chip erase operation is on going, user can confrm if the embedded operation is fnished or not by the following methods: *1: the status q3 is the time-out period indicator. when q3=0, the device is in time-out period and is acceptible to another sector address to be erased. when q3=1, the device is in erase operation and only erase suspend is valid. *2: ry/by# is open drain output pin and should be weakly connected to vdd through a pull-up resistor. *3: when an attempt is made to erase a protected sector, q7 will output its complement data or q6 continues to toggle for 100us and the device returned to read array status without erasing the data in the protected sector. status q7 q6 q5 q2 ry/by# in progress 0 toggling 0 toggling 0 finished 1 stop toggling 0 1 1 exceed time limit 0 toggling 1 toggling 0
14 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b when the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon id, sector protect verify, program, and erase resume. sector erase resume sector erase resume command is valid only when the device is in erase suspend state. after erase resume, user can issue another erase suspend command, but there should be a 400us interval between erase resume and the next erase suspend. if user issue infnite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase. sector erase suspend during sector erasure, sector erase suspend is the only valid command. if user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase-suspended read array mode. if user issue erase suspend command during the sector erase is be- ing operated, device will suspend the ongoing erase operation, and after the tready1(<=20us) suspend fnishes and the device will enter erase-suspended read array mode. user can judge if the device has fnished erase sus- pend through q6, q7, and ry/by#. after device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of taa; while reading the sector in erase-suspend mode, device will output its status. user can use q6 and q2 to judge the sector is erasing or the erase is suspended. status q7 q6 q5 q3 q2 ry/by# erase suspend read in erase suspended sector 1 no toggle 0 n/a toggle 1 erase suspend read in non-erase suspended sector data data data data data 1 erase suspend program in non-erase suspended sector q7# toggle 0 n/a n/a 0
15 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b absolute maximum stress ratings operating temperature and voltage commercial (c) grade surrounding temperature (t a ) 0c to +70c industrial (i) grade surrounding temperature (t a ) -40c to +85c vcc supply voltages vcc range +4.5 v to 5.5 v surrounding temperature with bias -65c to +125c storage temperature -65c to +150c voltage range vcc -0.5v to +7.0v reset#, a9 -0.5v to +12.5v the other pins. -0.5v to vcc+0.7v output short circuit current (less than one second) 200 ma
16 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b dc characteristics symbol description min typ max remark iilk input leak 1.0ua iolk output leak 10ua iilk9 a9 leak 35ua a9: 12.5v icr1 read current (10mhz) 50ma ce#=vil, oe#=vih icr2 read current (5mhz) 40ma ce#=vil, oe#=vih isb1 standby current (ttl) 1ma vcc=vcc max, ce#=vih other pin disable isb2 standby current (cmos) 1ua 50ua vcc=vccmax, ce#=vcc +0.3v, other pin disable icw write current 50ma ce#=vil, oe#=vih, we#=vil vil input low voltage -0.3v 0.8v vih input high voltage 0.7xvcc vcc+0.3v vhv very high voltage for hardware protect/ unprotect/auto select/ temporary unprotect 11.5v 12v 12.5v vol output low voltage 0.45v iol=2.1ma, vcc=vcc min voh1 ouput high voltage (ttl) 2.4v ioh1=-2ma voh2 ouput high voltage (cmos) vcc-0.4v ioh2=-100ua
17 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b switching test circuits test condition output load : 1 ttl gate output load capacitance,cl : 30pf for 70ns rise/fall times : 10ns input pulse levels: 0.45v/0.7xvcc reference levels for measuring timing :0.8v, 2.0v switching test waveforms r1=6.2k ohm r2=2.7k ohm tested device diodes=in3064 or equivalent cl r1 vcc 0.1uf r2 vcc 2.0v 2.0v 0.8v 0.8v test points 0.7xvcc 0.45v output input
18 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b ac characteristics symbol description speed option -70 unit min. typ. max. taa valid data output after address 70 ns tce valid data output after ce# low 70 ns toe valid data output after oe# low 30 ns tdf data output foating after oe# high 20 ns toh output hold time from the earliest rising edge of address, ce#, oe# 0 ns twc write period time 70 ns tcwc command write period time 70 ns tas address setup time 0 ns tah address hold time 45 ns tds data setup time 30 ns tdh data hold time 0 ns tcs ce# setup time 0 ns tch ce# hold time 0 ns toes output enable setup time 0 ns tcep ce# pulse width 35 ns tceph ce# pulse width high 20 ns tbusy program/erase active time by ry/by# 90 ns tavt program operation byte 9 300 us word 11 360 us taetc chip erase operation 8 32 sec taetb sector erase operation 0.7 15 sec tbal sector address hold time 40 us
19 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 1. command write operation addresses ce# oe# we# din tds ta h data tdh tcs tch tcwc toes ta s vih vil vih vil vih vil vih vil vih vil va va: valid address
20 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b read/reset operation figure 2. read timing waveforms addresses ce# oe# ta a we# vih vil vih vil vih vil vih vil voh vol high z high z data valid to e tdf tce trc outputs to h add valid
21 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 3. reset# timing waveform ac characteristics trh trb1 trp2 trp1 tready2 tready1 ry/by# ce#, oe# reset# reset timing not during automatic algorithms reset timing during automatic algorithms ry/by# ce#, oe# trb2 we# reset# item description setup speed unit trp1 reset# pulse width (during automatic algorithms) min 10 us trp2 reset# pulse width (not during automatic algorithms) min 500 ns trh reset# high time before read min 0 ns trb1 ry/by# recovery time (to ce#, oe# go low) min 0 ns trb2 ry/by# recovery time (to we# go low) min 50 ns tready1 reset# pin low (during automatic algorithms) to read or write max 20 us tready2 reset# pin low (not during automatic algorithms) to read or write max 500 ns
22 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b erase/program operation figure 4. automatic chip erase timing waveform twc address oe# ce# 55h 2aah sa 10h in progress complete va va ta s ta h sa: 555h for chip erase tch tds tdh taetc read status last 2 erase command cycle tbusy trb tcs we# data ry/by#
23 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 5. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no data=ffh ? write data 10h address 555h write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto chip erase completed
24 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 6. automatic sector erase timing waveform twc address oe# ce# 55h 2aah sector address 1 sector address 0 30h in progress complete va va 30h sector address n ta s ta h tbal tch tds tdh taetb read status last 2 erase command cycle tbusy trb tcs we# data ry/by# 30h
25 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 7. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto sector erase completed no last sector to erase yes yes no data=ffh
26 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 8. erase suspend/resume flowchart start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume
27 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 9. automatic program timing waveforms address oe# ce# a0h 555h pa pd status dout va va ta s ta h tch tds tdh tavt last 2 read status cycle last 2 program command cycle tbusy trb tcs we# data ry/by#
28 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 10. ce# controlled write timing waveform address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tcep tds tdh tavt or taetb tbusy tceph we# data ry/by#
29 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 11. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes read again data: program data? yes auto program completed data# polling algorithm or toggle bit algorithm next address last word to be programed no no
30 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b sector protect/chip unprotect figure 12. sector protect/chip unprotect waveform (reset# control) 150us: sector protect 15ms: chip unprotect 1us vhv vih data sa, a6 a1, a0 ce# we# oe# va va va status va: valid address 40h 60h 60h verification reset#
31 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 13-1. in-system sector protect with reset#=vhv start retry count=0 reset#=vhv wait 1us write sector address with [a6,a1,a0]:[0,1,0] data: 60h write sector address with [a6,a1,a0]:[0,1,0] data: 40h read at sector address with [a6,a1,a0]:[0,1,0] wait 150us reset plscnt=1 temporary unprotect mode reset#=vih write reset cmd sector protect done device fail temporary unprotect mode retry count +1 first cmd=60h? data=01h? retry count=25? yes yes yes yes no no no no protect another sector?
32 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 13-2. chip unprotect algorithms with reset#=vhv write [a6,a1,a0]:[1,1,0] data: 60h write [a6,a1,a0]:[1,1,0] data: 40h read [a6,a1,a0]:[1,1,0] wait 15ms temporary unprotect write reset cmd chip unprotect done retry count +1 device fail all sectors protected? data=00h? retry count=1000? yes yes no no yes protect all sectors start retry count=0 reset#=vhv wait 1us temporary unprotect first cmd=60h? yes no no
33 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 14. temporary sector unprotect waveforms table 5. temporary sector unprotect reset# ce# we# ry/by# trpvhh 12v vhv 0 or 5v 0 or 5v tvhhwl trpvhh program or erase command sequence parameter alt description condition speed unit trpvhh tvidr reset# rise time to vhv and vhv fall time to reset# min 500 ns tvhhwl trsp reset# vhv to we# low min 4 us
34 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 15. temporary sector unprotect flowchart notes: 1. temporary unprotect all protected sectors vhv=11.5 ~ 12.5v. 2. the protected conditions of the protected sectors are the same to temporary sector unprotect mode. start apply reset# pin vhv volt enter program or erase mode (1) remove vhv volt from reset# (2) reset# = vih completed temporary sector unprotected mode mode operation completed
35 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 16. silicon id read timing waveform ta a tce ta a to e to h to h tdf data out c2h 23h (top boot) abh (bottom boot) vhv vih vil a9 add ce# a1 oe# we# a0 data out data q0-q7 vih vil vih vil vih vil vih vil vih vil vih vil vih vil
36 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b write operation status figure 17. data# polling timing waveforms (during automatic algorithms) tdf tce tch to e toeh to h ce# oe# we# q7 q0-q6 ry/by# tbusy status data status data complement complement true valid data ta a trc address va va high z high z valid data true
37 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 18. data# polling algorithm read q7~q0 at valid address (note 1) read q7~q0 at valid address start q7 = data# ? q5 = 1 ? q7 = data# ? (note 2) fail pass no no no ye s ye s ye s notes: 1. for programming, valid address means program address. for erasing, valid address means erase sectors address. 2. q7 should be rechecked even q5="1" because q7 may change simultaneously with q5.
38 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 19. toggle bit timing waveforms (during automatic algorithms) tdf tce tch to e ta a to h address ce# oe# we# q6/q2 ry/by# tbusy valid status (first read) valid status (second read) (stops toggling) valid data va va va notes: 1. va : valid address 2. ce# must be toggled when toggle bit toggling. va valid data
39 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b figure 20. toggle bit algorithm notes: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 changes to "1". read q7-q0 twice q5 = 1? read q7~q0 twice program/erase fail write reset cmd program/erase complete q6 toggle ? q6 toggle ? no (note1) (note1, 2) yes no no yes yes start
40 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power- up. if the timing in the fgure is ignored, the device may not operate correctly. figure a. ac timing at device power-up vcc address ce# we# oe# data tvr taa tr or tf tr or tf tce tf vcc(min) gnd vih vil vih vil vih vil vih vil vih vil voh high z vol wp#/acc valid ouput valid address tvcs tr toe tf tr symbol parameter min. max. unit tvr vcc rise time 20 500000 us/v tr input signal rise time 20 us/v tf input signal fall time 20 us/v
41 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b latch-up characteristics erase and programming performance tsop pin capacitance parameter limits units min. typ. max. byte programming time 9 300 us word programming time 11 360 us sector erase time 0.7 8 sec chip erase time 8 32 sec chip programming time byte mode 10 27 sec word mode 7.5 17 sec erase/program cycles 100,000 cycles note: 1. typical condition means 25 c, 5v. 2. maximum condition means 85 c, 4.5v, 100k cycles. min. max. input voltage voltage difference with gnd on a9, reset# pins -1.0v 12.5v input voltage voltage difference with gnd on all normal pins inputs -1.0v vcc + 1.0v input current pulse -100ma +100ma includes all pins except vcc. test conditions: vcc = 5v, one pin per testing parameter symbol parameter description test set typ max unit cin2 control pin capacitance vin=0 12 pf cout output capacitance vout=0 12 pf cin input capacitance vin=0 8 pf
42 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b ordering information part no. access time (ns) temperature range package remark mx29f800ctmi-70g 70 -40 o c~85 o c 44 pin sop pb-free MX29F800CBMI-70G 70 -40 o c~85 o c 44 pin sop pb-free mx29f800ctti-70g 70 -40 o c~85 o c 48 pin tsop (normal type) pb-free mx29f800cbti-70g 70 -40 o c~85 o c 48 pin tsop (normal type) pb-free mx29f800ctxei-70g 70 -40 o c~85 o c 48 ball tfbga (6x8mm) pb-free mx29f800cbxei-70g 70 -40 o c~85 o c 48 ball tfbga (6x8mm) pb-free
43 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b part name description mx 29 f 70 c t t i g option: g: lead-free package speed: 70:70ns temperature range: i: industrial (-40c to 85c) package: m:sop t: tsop xe: tfbga (6x8x1.3mm, pitch 0.8mm, 0.4mm ball) boot block type: t: top boot b: bottom boot revision: c density & mode: 800: 8m, x8/x16 boot sector type: f: 5v device: 29: flash 800
44 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b package information
45 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b
46 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b
47 p/n:pm1493 rev. 1.0, nov. 17, 2009 mx29f800c t/b revision history revision no. description page date 1.0 1. removed "preliminary" p1 nov/17/2009 2. removed 90ns grade at order information p1,18,42,43 3.modifed tbal spec from 50us to 40us p13,17 4. modifed typical chip programming time p41
mx29f800c t/b 48 m acronix i nternational c o., l td. macronix offces : taiwan headquarters, fab2 macronix, international co., ltd. 16, li-hsin road, science park, hsinchu, taiwan, r.o.c. tel: +886-3-5786688 fax: +886-3-5632888 taipei offce macronix, international co., ltd. 19f, 4, min-chuan e. road, sec. 3, taipei, taiwan, r.o.c. tel: +886-2-2509-3300 fax: +886-2-2509-2200 macronix offces : china macronix (hong kong) co., limited. 702-703, 7/f, building 9, hong kong science park, 5 science park west avenue, sha tin, n.t. tel: +86-852-2607-4289 fax: +86-852-2607-4229 macronix (hong kong) co., limited, suzhou offce no.5, xinghai rd, suzhou industrial park, suzhou china 215021 tel: +86-512-62580888 ext: 3300 fax: +86-512-62586799 macronix (hong kong) co., limited, shenzhen offce room 1401 & 1404, block a, tianan hi-tech plaza tower, che gong miao, futiandistrict, shenzhen prc 518040 tel: +86-755-83433579 fax: +86-755-83438078 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifcations without notice. macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military ap- plication. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications. copyright ? macronix international co., ltd. 2009. all rights reserved. macronix, mxic, mxic logo, mx logo, are trademarks or registered trademarks of macronix international co., ltd.. the names and brands of other companies are for identifcation purposes only and may be claimed as the property of the respective companies. macronix offces : japan macronix asia limited. nkf bldg. 5f, 1-2 higashida-cho, kawasaki-ku kawasaki-shi, kanagawa pref. 210-0005, japan tel: +81-44-246-9100 fax: +81-44-246-9105 macronix offces : korea macronix asia limited. #906, 9f, kangnam bldg., 1321-4, seocho-dong, seocho-ku, 135-070, seoul, korea tel: +82-02-588-6887 fax: +82-02-588-6828 macronix offces : singapore macronix pte. ltd . 1 marine parade central, #11-03 parkway centre, singapore 449408 tel: +65-6346-5505 fax: +65-6348-8096 macronix offces : europe macronix europe n.v. koningin astridlaan 59, bus 1 1780 wemmel belgium tel: +32-2-456-8020 fax: +32-2-456-8021 macronix offces : usa macronix america, inc. 680 north mccarthy blvd. milpitas, ca 95035, u.s.a. tel: +1-408-262-8887 fax: +1-408-262-8810

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