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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 2 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . n o t e b o o k p w m c o n t r o l l e r w i t h d i f f e r e n t i a l v o l t a g e f e e d b a c k f e a t u r e s adjustable output voltage from +0.5v to +3.3v - 0.5v reference voltage - + 0.6% accuracy operates from an input battery voltage range of +1.8v to +28v remote feedback sense for excellent output voltage refin function for over-clocking purpose from 0.5v~2.5v range power-on-reset monitoring on vcc pin excellent line and load transient responses pfm mode for increased light load efficiency 350khz constant pwm switching frequency integrated mosfet drivers integrated bootstrap forward p-ch mosfet adjustable integrated soft-start and soft-stop power good monitoring 70% under-voltage protection 125% over-voltage protection adjustable current-limit protection -using sense low-side mosfet?|s rds(on) over-temperature protection tdfn-10 3x3 package lead free and green device available (rohs compliant) g e n e r a l d e s c r i p t i o n a p p l i c a t i o n s notebook table pc hand-held portable aio pc the APW8821 is a single-phase, constant on-time, syn- chronous pwm controller, which drives n-channel mosfets. the APW8821 steps down high voltage to generate low-voltage chipset or ram supplies in note- book computers. the APW8821 provides excellent transient response and accurate dc voltage output in either pfm or pwm mode. in pulse frequency mode (pfm), the APW8821 provides very high efficiency over light to heavy loads with loading- modulated switching frequencies. in pwm mode, the con- verter works nearly at constant frequency for low-noise requirements. APW8821 is built in remote sense func- tion for applications that require remote sense. t h e a p w 8 8 2 1 i s e q u i p p e d w i t h a c c u r a t e p o s i t i v e c u r - r e n t l i m i t , o u t p u t u n d e r - v o l t a g e , a n d o u t p u t o v e r - v o l t - a g e p r o t e c t i o n s , p e r f e c t f o r n b a p p l i c a t i o n s . t h e p o w e r - o n - r e s e t f u n c t i o n m o n i t o r s t h e v o l t a g e o n v c c t o p r e v e n t w r o n g o p e r a t i o n d u r i n g p o w e r - o n . t h e a p w 8 8 2 1 h a s a 1 m s d i g i t a l s o f t s t a r t a n d b u i l t - i n a n i n t e g r a t e d o u t p u t d i s c h a r g e d e v i c e f o r s o f t s t o p . a n i n t e r n a l i n t e g r a t e d s o f t - s t a r t r a m p s u p t h e o u t p u t v o l t - a g e w i t h p r o g r a m m a b l e s l e w r a t e t o r e d u c e t h e s t a r t - u p c u r r e n t . a s o f t - s t o p f u n c t i o n a c t i v e l y d i s c h a r g e s t h e o u t p u t c a p a c i t o r s . the APW8821 is available in 10pin tdfn 3x3 package respectively. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . p i n c o n f i g u r a t i o n apw 8821 handling code temperature range . package code apw 8821 qb : assembly meterial package code temperature range . i : - 40 to 85 o c handling code assembly meterial g : halogen and lead free device : qb tdfn 3 x 3 - 10 tr : tape & reel l : lead free device apw 8821 xxxxx xxxxx - date code s i m p l i f i e d a p p l i c a t i o n c i r c u i t v out l q 1 q 2 refin apw 8821 v in rtn vout pok v cc = 5 v phase ugate lgate / ocset r pok = gnd and thermal pad ( connected to gnd plane for better heat dissipation ) 10 boot tdfn 3 x 3 - 10 top view vout 3 pok 1 refin 2 fb 5 9 ugate 7 vcc 8 phase rtn 4 6 lgate / ocset free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 3 a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v cc vcc supply voltage (vcc to gnd) - 0.3 ~ 7 v v boot - gnd boot supply voltage (boot to gnd ) - 0.3 ~ 35 v v boot boot supply voltage (boot to phase) - 0.3 ~ 7 v all other pins (fb, vout, pok, and refin to gnd) - 0.3 ~ v cc +0.3 v ugate voltage (ugate to phase) < 20 ns pulse width > 2 0ns pulse width - 5 ~ v boot +0.3 - 0.3 ~ v boot +0.3 v lgate /ocset voltage (lgate to gnd) < 2 0ns pulse width > 2 0ns pulse width - 5 ~ v cc +0.3 - 0.3 ~ v cc +0.3 v v phase phase voltage (phase to gnd) < 2 0ns pulse width > 2 0ns pulse width - 5 ~ 3 5 - 1 ~ 30 v t j max imum junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering temperature, 10 seconds 260 o c note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja thermal resistance - junction to ambient (note 2) tdfn3x3 - 10 55 c/w n ote 2: q ja is measured with the component mounted on a high effective the thermal conductivity test board in free air. the exposed pad of package is soldered directly on the pcb. r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) symbol parameter range unit v in converter input voltage 1.8 ~ 28 v v cc vcc supply voltage 4.5 ~ 5.5 v converter output voltage (external refin input) 0.5 ~ 2.5 v v out converter output voltage (internal fb setting) 0.5 ~ 3.3 v i out converter output cu rrent ~ 25 a t a ambient temperature - 40 ~ 85 o c t j junction temperature - 40 ~ 125 o c note 3 : refer to the typical application circuit. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s these specifications apply over t a = -40 ~ 85c, unless otherwise specified. typical values are at t a = 25c, v cc =5v APW8821 symbol parameter test condition s min. typ. max. unit vout and vfb voltage external refin output voltage tolerance, refin=1v - 5 - 5 mv external refin adjustable output range 0.5 - 2.5 internal fb adjustable output range 0.5 3.3 v reference voltage - 0.5 - v t a = 25 o c -0.4 - +0.4 % v ref regulation accuracy t a = - 40 o c ~ 85 o c -0.6 - +0.6 % i fb fb input bias current fb=0.5v - 0.02 0.1 m a r dis v out d ischarge resistance - 20 32 w supply current i vcc vcc input bias current vcc current, refin=5v, vfb=0.55v, phase=0.5v - 250 400 m a i vcc_shd n vcc shutdown current refin =gnd, vcc=5v - 0 7 m a switching frequency and duty and i nternal s oft s tart f sw switching frequency v in =8v, vout=1v, i out =10a 315 350 385 khz t on (min) minimum on time - 110 - ns t off (min) minimum off time v fb =0.45v, v phase = - 0.1v 350 450 550 ns t ss internal s oft s tart t ime v out from 0% to 95%regu lation - 1.0 - ms gate driver ug pull - up resistance boot - ug=0.5v - 1.5 3 w ug sink resistance ug - phase=0.5v - 0.7 1.8 w l g pull - up resistance pvcc - lg=0.5v - 1.0 2.2 w l g sink resistance lg - pgnd=0.5v - 0.5 1.2 w ug to lg dead time ug falling to lg rising - 20 - ns lg to ug dead time lg falling to ug rising - 20 - ns bootstrap switch v f ron v vcc ? v boot - gnd , i f = 10ma - 0.3 0.4 v i r reverse leakage v boot - gnd = 30v, v phase = 25v, v vcc = 5v - - 0.5 m a vcc por threshold v vcc_thr ris ing vcc por threshold voltage 4.25 4.35 4.45 v vcc por hysteresis - 100 - mv free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 5 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) APW8821 symbol parameter test condition s min. typ. max. unit control inputs shutdown - - 0.4 external reference, v out =v refin 0.5 - 2.5 refin voltage threshold in ternal reference, v out = fb setting - 3 - v refin leakage refin =0v - 0.1 1.0 m a refin slew rate internal slew rate - 8 - mv/us power - ok indicator pok in from lower (pok goes high) 87 90 93 % v pok pok threshold pok out from normal pok out from normal with 30us noise filter (pok goes low) 120 125 130 % i pok p ok leakage current v pok = 5v - 0.1 1.0 m a p ok sink current v pok = 0. 5v 2.5 7.5 - m a p ok enable delay time v outfrom low to pok high - 1.6 - ms vcc power - on - reset ( por ) threshold i ocset i ocset ocp threshold i ocset sourc ing 9 10 11 a t ci ocset i ocset t emperature c oeffic ient on t he b asis of 25c - 4500 - ppm/ o c v r ocset maximum current l imit t hreshold r ocset open - 0.6 - v zero c rossing c omparator o ffset v gnd - phase voltage - 3 0 3 mv protection s v uv uvp threshold 60 70 80 % uvp debounce interval - 16 - s uvp en able delay v out from low to pok high - 1.6 - ms v ovr ovp rising threshold 120 125 130 % ovp hysteresis - 5 - % ovp propagation delay v fb rising, dv=10mv - 2 - s t otr otp rising threshold (note 4) - 140 - o c otp hyste r esis (note 4) - 25 - o c these specifications apply over t a = -40 ~ 85c, unless otherwise specified. typical values are at t a = 25c, v cc =5v note 4 : guaranteed by design, not production tested. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 6 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s 0 . 494 r e f e r e n c e v o l t a g e a c c u r a c y , v r e f ( v ) reference voltage accuracy vs . junction temperature - 50 - 30 10 50 110 130 150 90 30 - 10 junction temperature , t j ( o c ) 0 . 506 0 . 504 0 . 502 0 . 500 0 . 498 0 . 496 70 1 . 015 1 . 010 0 . 980 c o n v e r t e r o u t p u t v o l t a g e , v o u t ( v ) 3 converter output current , i out ( a ) 10 9 4 1 . 020 1 . 005 1 . 000 0 . 995 0 . 990 0 . 985 5 6 7 8 v out = 1 v , external mode v in = 8 v v in = 19 v converter output voltage vs . converter output current 0 . 1 s w i t c h i n g f r e q u e n c y , f s w ( k h z ) switching frequency vs . converter output current 0 . 001 0 . 010 0 . 100 1 . 000 10 . 00 converter output current , i out ( a ) 1000 100 10 1 v in = 8 v , v out = 1 v 9 c o n v e r t e r o u t p u t v o l t a g e , v o u t ( v ) converter input voltage , v in ( v ) converter output voltage vs . converter input voltage 13 17 21 5 25 1 . 04 1 . 02 0 . 94 1 . 06 1 . 00 0 . 98 0 . 96 i out = 0 a i out = 10 a v cc = 5 v , v out = 1 v , external mode 0 . 10 1 . 00 10 . 00 converter output current , i out ( a ) 0 10 e f f i c i e n c y ( % ) 70 80 90 60 50 100 40 30 20 efficiency vs load current v in = 8 v , v out = 1 . 05 v 0 . 01 100 . 00 h - side : sm 4370 x 1 l - side : sm 4373 x 1 0 . 10 1 . 00 10 . 00 0 10 e f f i c i e n c y ( % ) 70 80 90 60 50 100 40 30 20 0 . 01 100 . 00 converter output current , i out ( a ) efficiency vs load current v in = 19 v , v out = 1 . 05 v h - side : sm 4370 x 1 l - side : sm 4373 x 1 free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 7 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 9 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . e n a b l e a t z e r o i n i t i a l v o l t a g e o f v o u t e n a b l e b e f o r e e n d o f s o f t - s t o p s h u t d o w n a t i o u t = 2 0 a s h u t d o w n w i t h s o f t - s t o p a t n o l o a d 1 2 3 4 1 2 3 4 ch 2 : v out , 500 mv / div , dc ch 3 : v phase , 20 v / div , dc time : 500 m s / div ch 1 : v refin , 5 v / div , dc ch 4 : v pok , 5 v / div , dc ch 2 : v out , 500 mv / div , dc ch 3 : v phase , 20 v / div , dc time : 500 m s / div ch 1 : v refin , 5 v / div , dc ch 4 : v pok , 5 v / div , dc 1 4 2 3 ch 2 : v out , 500 mv / div , dc ch 3 : v phase , 20 v / div , dc time : 20 m s / div ch 1 : v refin , 5 v / div , dc ch 4 : v pok , 5 v / div , dc 1 4 2 3 ch 2 : v out , 500 mv / div , dc ch 3 : v phase , 20 v / div , dc time : 10 ms / div ch 1 : v refin , 5 v / div , dc ch 4 : v pok , 5 v / div , dc free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 8 o p e r a t i n g w a v e f o r m s ( c o n t . ) r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 9 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . 1 4 3 2 ch 2 : v lgate , 5 v / div , dc ch 3 : v out , 50 mv / div , ac time : 2 g s / div ch 1 : v phase , 20 v / div , dc ch 4 : iout , 10 a / div , dc operating at pfm mode 1 4 2 3 ch 2 : v lgate , 5 v / div , dc ch 3 : v out , 50 mv / div , ac time : 2 g s / div ch 1 : v phase , 20 v / div , dc ch 4 : i out , 20 a / div , dc operating at pwm mode current - limit and uv protections 1 4 2 3 ch 2 : v out , 1 v / div , dc ch 3 : v phase , 20 v / div , dc time : 20 g s / div ch 1 : v pok , 5 v / div , dc ch 4 : i l , 20 a / div , dc short circuit before enable 1 4 2 3 ch 2 : v out , 1 v / div , dc ch 3 : v phase , 10 v / div , dc time : 500 g s / div ch 1 : v refin , 5 v / div , dc ch 4 : i l , 20 a / div , dc free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 9 o p e r a t i n g w a v e f o r m s ( c o n t . ) r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 1 9 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . 1 2 3 4 load transient 0 a - > 17 . 5 a - > 0 a when total i mpedance of line = 20 mohm ch 2 : v out _ remote , 200 mv / div , dc ch 3 : i out , 10 a / div , dc time : 20 g s / div ch 1 : v out _ near , 200 mv / div , dc ch 4 : v gnd _ near - remote , 200 mv / div , dc 1 2 3 4 ch 2 : v out _ remote , 200 mv / div , dc ch 3 : i out , 10 a / div , dc time : 20 g s / div ch 1 : v out _ near , 200 mv / div , dc ch 4 : v gnd _ near - remote , 200 mv / div , dc load transient 5 a - > 20 a - > 5 a when total i mpedance of line = 20 mohm ch 2 : v out _ remote , 200 mv / div , dc ch 3 : i l , 10 a / div , dc time : 2 g s / div ch 1 : v out _ near , 200 mv / div , dc ch 4 : v gnd _ near - remote , 200 mv / div , dc 1 2 4 3 remote sense when total i mpedance of line = 20 mohm free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 1 0 p i n d e s c r i p t i o n pin no. name function 1 pok power good output. po k i s a n o pen d rain o utput used to in dicate the status of the output voltage. connect the pok in to +5v through a pull - high resistor. 2 refin enable/shutdown pin or external reference selection of the pwm controller. 3 vout this pin is the positive node of the differential remote voltage sensing. the vout pin should be connected to the remote load voltage sense point directly. 4 rtn this pin is the negative node of the differential remote voltage sensing . the rtn pin should be connected to the remote gnd sense point directly. 5 fb output v oltage f eedback p in. in internal mode, t his pin is connected to the resistive divider that set the desired output voltage. the p ok , uvp, and ovp circuits detect this si gnal to report output voltage status. 6 lgate/ocset output of t he l ow - side mosfet d river a nd over - current setting input. connect this pin to gate of the low - side mosfet. there is an internal source current 10 m a through a resistor from lgate/ocset pin to g nd before power on. this action is used to monitor the voltage drop across the drain and source of the low - side mo sfet for current limit. 7 vcc supply v oltage i nput p in for c ontrol c ircuitry. connect +5v from the vcc pin to the gnd. decoupling at least 1 f of a mlcc capacitor from the vcc pin to the gnd. 8 phase junction p oint of t he h igh - side mosfet source, o utput f ilter i nductor a nd t he l ow - side mosfet drain. connect this pin to the source of the high - side mosfet. phase serves as the lower supply rail f or the u g high - side gate driver. 9 ugate output of t he h igh - side mosfet d river. connect this pin to gate of the high - side mosfet. 10 boot supply input for t he ug ate driver a nd a n i nternal l evel - shift c ircuit. connect to an external capacitor to create a boosted voltage suitable to drive a logic - level n - channel mosfet. exposed pad gnd signal g round for t he ic free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 1 1 b l o c k d i a g r a m fb error comparator ov uv 70 % v ref 125 % v ref v ref por vcc refin digital soft start / soft sop p w m s i g n a l c o n t r o l l e r v cc boot ugate phase lgate thermal shutdown gnd pok fault latch logic on - time generator v ref x 9 0 % v ref x 125 % z c phase debounce time v cc sample and hold v rocset to lgate 10 m a v out v out ocp v rocse t sense low - side vout rtn diffout diffout free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 1 2 t y p i c a l a p p l i c a t i o n c i r c u i t for external mode application for internal mode application phase rtn gnd vcc lgate / ocset vout apw 8821 ( tdfn 3 * 3 - 10 ) c in 10 g f x 2 l 1 0 . 5 g h v in ugate vcc supply 5 v boot 7 2 4 3 6 8 9 10 r vcc 2 r 2 c vcc 1 g f q 1 apm 4350 q 2 apm 4358 c boot 0 . 1 g f r ocse t fb 5 pok 1 r pok 100 k [ refin on off q 3 2 n 7002 enable source exposed pad r top 11 k [ v out c out 330 g f r gnd 10 k [ phase rtn gnd vcc lgate / ocset vout apw 8821 ( tdfn 3 * 3 - 10 ) c in 10 g f x 2 l 1 0 . 5 g h v in v out ugate c out 330 g f vcc supply 5 v boot 7 2 4 3 6 8 9 10 r vcc 2 r 2 c vcc 1 g f q 1 apm 4350 q 2 apm 4358 c boot 0 . 1 g f r ocset c out mlcc 22 g fx 4 fb l o a d 5 pok 1 r pok 100 k [ v + _ near v - _ near v + _ remote v - _ remote refin on off q 3 2 n 7002 dac source exposed pad free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 1 3 f u n c t i o n d e s c r i p t i o n constant-on-time pwm controller with input feed-for- ward pulse-frequency modulation (pfm) the constant-on-time control architecture is a pseudo- fixed frequency with input voltage feed-forward. this ar- chitecture relies on the output filter capacitor?s effective series resistance (esr) to act as a current-sense resis- tor so the output ripple voltage provides the pwm ramp signal. in pfm operation, the high-side switch on-time is controlled by the on-time generator is determined solely by a one-shot whose pulse width is inversely propor- tional to the input voltage and directly proportional to the output voltage. in pwm operation, the high-side switch on-time is determined by a switching frequency control circuit in the on-time generator block. the switching frequency control circuit senses the switch- ing frequency of the high-side switch and keeps regulat- ing it at a constant frequency in pwm mode. the design improves the frequency variation and is more outstand- ing than a conventional constant-on-time controller, which has large switching frequency variation over input voltage, output current, and temperature. both in pfm and pwm, the on-time generator, which senses input voltage on phase pin, provides very fast on-time response to input line transients. another one-shot sets a minimum off-time (typical: 450ns). the on-time one-shot is triggered if the error com- parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time one- shot has timed out. in pfm mode, an automatic switchover to pulse-frequency modulation (pfm) takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero crossing. this mechanism causes the threshold between pfm and pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). the on-time of pfm is given by: where f sw is the nominal switching frequency of the con- verter in pwm mode. the load current at handoff from pfm to pwm mode is given by: in out sw pfm on v v f 1 t = - in out sw out in pfm on out in ) pfmtopwm ( load v v f 1 l 2 v v t l v v 2 1 i - = - = - power-on-reset (por) a power-on-reset (por) function is designed to prevent wrong logic controls when the vcc voltage is low. the por function continually monitors the bias supply volt- age on the vcc pin if at least one of the enable pins is set high. when the rising vcc voltage reaches the rising por voltage threshold (4.35v, typical), the por signal goes high and the chip initiates soft-start operations. when this voltage drops lower than 4.25v (typical), the por disables the chip. refin pin control the voltage (v refin ) applied to refin pin selects either enable-shutdown or adjustable external reference. when v refin is above the en high threshold (2.8v, typical), the pwm is enabled. when v refin is from 0.5v to 2.5v, the output voltage can be programmed as same as v refin voltage. when v refin is below the en low threshold, the chip is in the shutdown and only low leakage current is taken from vcc. once APW8821 has been operating at internal mode, it is unable to transform into external mode. on the other hand, it is able to transform into internal mode. the slew rate of v refin must be faster than 0.5v/ m s to avoid wrong output voltage. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 1 4 f u n c t i o n d e s c r i p t i o n ( c o n t . ) digital soft-start power ok indicator the APW8821 integrates digital soft-start circuits to ramp up the output voltage of the converter to the programmed regulation setpoint at a predictable slew rate. the slew rate of output voltage is internally controlled to limit the inrush current through the output capacitors during soft- start process. the figure 1 shows soft-start sequence. when the refin pin is pulled above the rising en threshold voltage, the v ocset voltage is equal to 10 m a x r ocset . when vcc rising por threshold is triggered, the device starts to sample and hold the current-limit setting threshold. the maximum sample time is 650us, so user must make sure that v ocset reaches set up value cor- rectly during this time. during soft-start stage before the pok pin is ready, the under-voltage protection is prohibited. the over-voltage and over-current protection functions are enabled. if the output capacitor has residue voltage before start-up, both low-side and high-side mosfets are in off-state until the internal digital soft-start voltage is equal to the v fb voltage. this will ensure that the output voltage starts from its existing voltage level. in the event of under-voltage or shutdown, the chip en- ables the soft-stop function. the soft-stop function dis- charges the output voltages to the gnd through an inter- nal 20 w switch. cycling the refin enable signal or vcc power-on-reset signal can reset the latch. figure 1. soft-start sequence the APW8821 features an open-drain pok pin to indi- cate output regulation status. in normal operation, when the output voltage rises above 90% of its target value, the pok goes high. when the output voltage returns 90% or outruns 125% of the target voltage, pok signal will be pulled low after 30 us noise filter. it is a latch operation. since the fb pin is used for both feedback and monitor- ing purposes, the output voltage deviation can be coupled directly to the fb pin by the capacitor in parallel with the voltage divider as shown in the typical applications. in order to prevent false pok from dropping, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient and the pok comparator has a built-in 30 m s noise filter. f r o m w h e n c u r r e n t - l i m i t s e t t i n g a c t i o n h a s f i n i s h e d , t h e d e v i c e i n i t i a t e s a s o f t - s t a r t p r o c e s s t o r a m p u p t h e o u t p u t v o l t a g e . t h e s o f t - s t a r t i n t e r v a l , t s s , i s a b o u t 1 m s ( t y p i c a l v a l u e ) . under-voltage protection (uvp) in the operational process, if a short-circuit occurs, the output voltage will drop quickly. when load current is big- ger than current-limit threshold value, the output voltage will fall out of the required regulation range. the under- voltage protection circuit continually monitors the v fb af- ter soft-start is completed. if a load step is strong enough to pull the output voltage lower than the under-voltage threshold, the device starts to soft-stop process to shut down the output gradually. the under-voltage threshold is 70% of the normal output voltage. the under-voltage comparator has a built-in 2 m s noise filter to prevent the chip from wrong uvp shutdown caused by noise. cy- cling the refin enable signal or vcc power-on-reset signal can reset the latch. t ss = t 2 - t 1 = 1 ms en v out v cc v pok t 1 t 3 95 % x v ref v t t 0 t 2 free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 1 5 f u n c t i o n d e s c r i p t i o n ( c o n t . ) over-voltage protection (ovp) the over-voltage function monitors the output voltage by the fb pin. when the fb voltage increases over 125% of the reference voltage due to the high-side mosfet fail- ure or for other reasons, the over-voltage protection com- parator designed with a 2 m s noise filter will force the low- side mosfet gate driver fully turn on. this action actively pulls down the output voltage. when the fb voltage falls below 120%, the ovp comparator is disengaged and both high-side and low-side drivers restore normal operation. this ovp scheme is a non-latch design, so user must take notice of some phenomenon of pok. that means when a ovp condition continues over 30us, it will cause pok goes low with latch no matter how whether ovp conditions is disengaged or not. over-temperature protection (otp) when the junction temperature increases over the rising threshold temperature t otr , the ic will enter the over- temperature protection state that suspends the pwm, which forces the ugate and lgate gate drivers output low. the thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 25 o c. the otp is designed with a 25 o c hysteresis to lower the average t j during continuous thermal overload conditions, which increases lifetime of the APW8821. c u r r e n t - l i m i t t h e c u r r e n t - l i m i t c i r c u i t e m p l o y s a ? v a l l e y ? c u r r e n t - s e n s - i n g a l g o r i t h m ( s e e f i g u r e 2 ) . t h e a p w 8 8 2 1 u s e s t h e l o w - s i d e m o s f e t r d s ( o n ) o f t h e s y n c h r o n o u s r e c t i f i e r a s a c u r r e n t - s e n s i n g e l e m e n t . i f t h e m a g n i t u d e o f t h e c u r r e n t - s e n s e s i g n a l a t p h a s e p i n i s a b o v e t h e c u r r e n t - l i m i t t h r e s h o l d , t h e p w m i s n o t a l l o w e d t o i n i t i a t e a n e w c y c l e . t h e a c t u a l p e a k c u r r e n t i s g r e a t e r t h a n t h e c u r r e n t - l i m i t t h r e s h o l d b y a n a m o u n t e q u a l t o t h e i n d u c t o r r i p p l e c u r r e n t . t h e r e f o r e , t h e e x a c t c u r r e n t - l i m i t c h a r a c t e r i s t i c a n d m a x i - m u m l o a d c a p a b i l i t y a r e t h e f u n c t i o n s o f t h e s e n s e r e s i s t a n c e , i n d u c t o r v a l u e , a n d i n p u t v o l t a g e . figure 2. current-limit algorithm a resistor (r ocset ), connected from the lgate/ocset to gnd, programs the current-limit threshold. before the ic initiates a soft-start process, an internal current source, i ocset (10 m a typical), flowing through the r ocset develops a voltage (v ocset ) across the r ocset . the device holds v ocset and stops the current source, i ocset , during normal operation. the relationship between the sampled volt- age v ocset and the current-limit threshold i limit is given by: 10 m a x r ocset = i limit x r ds(on) i limit can be expressed as i out minus half of peak-to-peak inductor current. the APW8821 has an internal current-limit voltage (v ocset_max ), and the value is 0.6v typically. when the r ocset x i ocset exceeds 0.6v or the r ocset is floating or not connected, the over current threshold will be the internal default value 0.6v. the pcb layout guidelines should ensure that noise and dc errors do not corrupt the current-sense signals at phase. place the hottest power mosefts as close to the ic as possible for best thermal coupling. when com- bined with the under-voltage protection circuit, this cur- rent-limit method is effective in almost every circumstance. time i n d u c t o r c u r r e n t 0 i peak i out i limit g i free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 1 6 a p p l i c a t i o n i n f o r m a t i o n where 0.5 is the reference voltage, r top is the resistor connected from converter?s output to fb, and r gnd is the resistor connected from fb to gnd. suggested r gnd is in the range from 1k to 20k w . to prevent stray pickup, lo- cate resistors r top and r gnd close to APW8821. similarly, when v refin is from 0.5v to 2.5v, the output voltage can be programmed as same as v refin voltage. o u t p u t i n d u c t o r s e l e c t i o n t h e d u t y c y c l e ( d ) o f a b u c k c o n v e r t e r i s t h e f u n c t i o n o f t h e i n p u t v o l t a g e a n d o u t p u t v o l t a g e . o n c e a n o u t p u t v o l t a g e i s f i x e d , i t c a n b e w r i t t e n a s : in out v v d = in out sw out in ripple v v l f v - v i = o u t p u t c a p a c i t o r s e l e c t i o n the inductor value (l) determines the inductor ripple current, i ripple , and affects the load transient response. higher inductor value reduces the inductor?s ripple cur- rent and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: esr ripple esr sw out ripple out c r i v f 8c i v = d = d w h e r e f s w i s t h e s w i t c h i n g f r e q u e n c y o f t h e r e g u l a t o r . a l t h o u g h t h e i n d u c t o r v a l u e a n d f r e q u e n c y a r e i n c r e a s e d a n d t h e r i p p l e c u r r e n t a n d v o l t a g e a r e r e d u c e d , a t r a d e o f f e x i s t s b e t w e e n t h e i n d u c t o r ? s r i p p l e c u r r e n t a n d t h e r e g u - l a t o r l o a d t r a n s i e n t r e s p o n s e t i m e . a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. increasing the switching frequency (f sw ) also reduces the ripple current and voltage, but it will increase the switching loss of the mosfets and the power dissipa- tion of the converter. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, selecting an inductor which is capable of carrying the required peak current without going into saturation. in some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this results in a larger output ripple voltage. besides, the inductor needs to have low dcr to reduce the loss of efficiency. output voltage ripple, the transient voltage deviation and the stability issue are factors which have to be taken into consideration when selecting an output capacitor. higher capacitor value and lower esr reduce the output ripple and the load transient drop. generally, selecting high per- formance low esr capacitors is recommended for switching regulator applications. in addition to high fre- quency noise related to mosfet turn-on and turn-off, the output voltage ripple includes the capacitance voltage drop d v cout and esr voltage drop d v esr caused by the ac peak-to-peak inductor?s current. these two voltages can be represented by: these two components constitute a large portion of the total output voltage ripple. in some applications, multiple capacitors have to be paralleled to achieve the desired esr value. if the output of the converter has to support another load with high pulsating current, more capaci- tors are needed in order to reduce the equivalent esr and suppress the voltage ripple to a tolerable level. nevertheless, the constant-on-time (cot) control archi- tecture relies on the output capacitor?s esr to act as a current-sense resistor, so the output ripple voltage pro- vides the pwm ramp signal. for stability issue, the output ripple also need to be considered. by stability experi- ment result, we suggest the feedback ripple is above 10mv. to support a load transient that is faster than the switch- ing frequency, more capacitors are needed for reducing ? ? ? ? ? + = gnd top out r r 1 0.5 v o u t p u t v o l t a g e s e t t i n g the output voltage is adjustable from 0.5v to 3.3v with a resistor-divider connected with fb, gnd, and converter?s output. the voltage (v refin ) applied to refin pin selects adjustable external reference from 0.5v to 2.5v. using 1% or better resistors for the resistor-divider is recommended. the output voltage is determined by: free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 1 7 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) o u t p u t c a p a c i t o r s e l e c t i o n ( c o n t . ) i n p u t c a p a c i t o r s e l e c t i o n t h e i n p u t c a p a c i t o r i s c h o s e n b a s e d o n t h e v o l t a g e r a t i n g a n d t h e r m s c u r r e n t r a t i n g . f o r r e l i a b l e o p e r a t i o n , s e l e c t - i n g t h e c a p a c i t o r v o l t a g e r a t i n g t o b e a t l e a s t 1 . 3 t i m e s h i g h e r t h a n t h e m a x i m u m i n p u t v o l t a g e . t h e m a x i m u m r m s c u r r e n t r a t i n g r e q u i r e m e n t i s a p p r o x i m a t e l y i o u t / 2 , w h e r e i o u t i s t h e l o a d c u r r e n t . d u r i n g p o w e r - u p , t h e i n p u t c a p a c i t o r s h a v e t o h a n d l e g r e a t a m o u n t o f s u r g e c u r r e n t . f o r l o w - d u t y n o t e b o o k a p p l i a c t i o n s , c e r a m i c c a p a c i t o r i s r e c o m m e n d e d . t h e c a p a c i t o r s m u s t b e c o n n e c t e d b e - t w e e n t h e d r a i n o f h i g h - s i d e m o s f e t a n d t h e s o u r c e o f l o w - s i d e m o s f e t w i t h v e r y l o w - i m p e a d a n c e p c b l a y o u t . m o s f e t s e l e c t i o n t h e s e l e c t i o n o f t h e n - c h a n n e l p o w e r m o s f e t s a r e d e t e r m i n e d b y t h e r ds(on) , r e v e r s i n g t r a n s f e r c a p a c i - t a n c e ( c r s s ) a n d m a x i m u m o u t p u t c u r r e n t r e q u i r e m e n t . t h e l o s s e s i n t h e m o s f e t s h a v e t w o c o m p o n e n t s : c o n d u c t i o n l o s s a n d t r a n s i t i o n l o s s . f o r t h e h i g h - s i d e a n d l o w - s i d e m o s f e t s , t h e l o s s e s a r e a p p r o x i m a t e l y g i v e n b y t h e f o l l o w i n g e q u a t i o n s : p high-side = i out 2 (1+ tc)(r ds(on) )d + (0.5)( i out )(v in )( t sw )f s w p low-side = i out 2 (1+ tc)(r ds(on) )(1-d) l a y o u t c o n s i d e r a t i o n during turn-off, current stops flowing in the mosfet and is freewheeling by the low side mosfet and parasitic diode. any parasitic inductance of the circuit generates a large voltage spike during the switching interval. in general, using short and wide printed circuit traces should minimize interconnecting impedances and the magni- tude of voltage spike. besides, signal and power grounds are to be kept separating and finally combined using ground plane construction or single point grounding. fig- ure 3 illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. com- ponents along the bold lines should be placed lose together. below is a checklist for your layout: where i out is the load current tc is the temperature dependency of r ds(on) f sw is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfets have conduction losses while the high-side mosfet includes an additional transition loss. the switching interval, t sw , is the function of the re- verse transfer capacitance c rss . the (1+tc) term is a factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs. temperature? curve of the power mosfet. = k e e p t h e s w i t c h i n g n o d e s ( u g a t e , l g a t e / o c s e t , b o o t , a n d p h a s e ) a w a y f r o m s e n s i t i v e s m a l l s i g n a l n o d e s s i n c e t h e s e n o d e s a r e f a s t m o v i n g s i g n a l s . t h e r e f o r e , k e e p t r a c e s t o t h e s e n o d e s a s s h o r t a s p o s - s i b l e a n d t h e r e s h o u l d b e n o o t h e r w e a k s i g n a l t r a c e s i n p a r a l l e l w i t h t h e s e s t r a c e s o n a n y l a y e r . = t h e s i g n a l s g o i n g t h r o u g h t h e s e s t r a c e s h a v e b o t h h i g h d v / d t a n d h i g h d i / d t w i t h h i g h p e a k c h a r g i n g a n d d i s - c h a r g i n g c u r r e n t . t h e t r a c e s f r o m t h e g a t e d r i v e r s t o t h e m o s f e t s ( u g a t e a n d l g a t e / o c s e t ) s h o u l d s h o r t a n d w i d e . = p l a c e t h e s o u r c e o f t h e h i g h - s i d e m o s f e t a n d t h e d r a i n o f t h e l o w - s i d e m o s f e t a s c l o s e a s p o s s i b l e . m i n i - m i z i n g t h e i m p e d a n c e w i t h w i d e l a y o u t p l a n e b e t w e e n t h e t w o p a d s r e d u c e s t h e v o l t a g e b o u n c e o f t h e n o d e . i n a d d i t i o n , t h e l a r g e l a y o u t p l a n e b e t w e e n t h e d r a i n o f t h e m o s f e t s ( v i n a n d p h a s e n o d e s ) c a n g e t b e t t e r h e a t s i n k i n g . in any high switching frequency converter, a correct lay- out is important to ensure proper operation of the regulator. with power devices switching at higher frequency, the resulting current transient will cause volt- age spike across the interconnecting impedance and parasitic circuit elements. as an example, consider the turn-off transition of the pwm mosfet. before turn-off condition, the mosfet is carrying the full load current. = d e c o u p l i n g c a p a c i t o r s , t h e r e s i s t o r - d i v i d e r , a n d b o o t c a p a c i t o r s h o u l d b e c l o s e t o t h e i r p i n s . ( f o r e x a m p l e , p l a c e t h e d e c o u p l i n g c e r a m i c c a p a c i t o r c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t a s c l o s e a s p o s s i b l e . ) the voltage excursion during load step change. another aspect of the capacitor selection is that the total ac cur- rent going through the capacitors has to be less than the rated rms current specified on the capacitors in order to prevent the capacitor from over-heating. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 1 8 = locate the resistor-divider close to the fb pin to mini- mize the high impedance trace. in addition, fb pin traces can?t be close to the switching signal traces (ugate, lgate/ocset, boot, and phase). = t h e i n p u t b u l k c a p a c i t o r s s h o u l d b e c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t , a n d t h e o u t p u t b u l k c a p a c i t o r s s h o u l d b e c l o s e t o t h e l o a d s . t h e i n p u t c a p a c i t o r ? s g r o u n d s h o u l d b e c l o s e t o t h e g r o u n d s o f t h e o u t p u t c a p a c i t o r s a n d l o w - s i d e m o s f e t . l a y o u t c o n s i d e r a t i o n ( c o n t . ) = the r ocset resistance should be placed near the ic as close as possible. figure 3. a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) close to ic vcc boot phase ugate lgate / ocset v in v out l o a d apw 8821 r ocset free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 1 9 p a c k a g e i n f o r m a t i o n t d f n 3 x 3 - 1 0 note : 1. followed from jedec mo-229 veed-5. aaa c nx a3 a1 b a k l e e 2 pin 1 corner d2 pin 1 e d s y m b o l min. max. 0.80 0.00 0.18 0.30 2.20 2.70 0.05 1.40 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tdfn3x3-10 0.30 0.50 1.75 0.008 ref min. max. inches 0.031 0.000 0.007 0.012 0.087 0.106 0.055 0.012 0.020 0.70 0.069 0.028 0.002 0.50 bsc 0.016 bsc 0.20 0.008 k 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122 0.08 0.003 aaa free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 2 0 c a r r i e r t a p e & r e e l d i m e n s i o n s a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d application a h t1 c d d w e1 f 178.0 ? 2.00 50 min. 8.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 8.0 ? 0.20 1.75 ? 0.10 3.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tdfn3x3 - 10 4.0 ? 0.10 4.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0 .40 3.35 ? 0.20 3.35 ? 0.20 1.30 ? 0.20 (mm) d e v i c e s p e r u n i t package type unit quantity tdfn3x3 - 10 tape & reel 3000 free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 2 1 t a p i n g d i r e c t i o n i n f o r m a t i o n tdfn3x3-10 c l a s s i f i c a t i o n p r o f i l e user direction of feed free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 2 2 c l a s s i f i c a t i o n r e f l o w p r o f i l e s ( c o n t . ) table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. free datasheet http:///
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 1 - f e b . , 2 0 1 1 a p w 8 8 2 1 w w w . a n p e c . c o m . t w 2 3 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8 free datasheet http:///
free datasheet http:///

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