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flash memory 1 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a k9xxg08xxa * samsung electronics reserves the right to c hange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. free datasheet http://www..net/
flash memory 2 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a document title 1g x 8 bit / 2g x 8 bit nand flash memory revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung elec tronics will evaluate and reply to your requests and questions about device. if you h ave any questions, please contact the samsung branch office near your office. revision no 0.0 0.1 remark advance preliminary history 1. initial issue 1. endurance is changed (10k->5k) draft date nov. 28st 2006 april 10th 2007 free datasheet http://www..net/
flash memory 3 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a general description features ? voltage supply - 2.7v device(k9g8g08b0a) : 2.5v ~ 2.9v - 3.3v device(k9g8g08u0a) : 2.7v ~ 3.6v ? organization - memory cell array : (1g + 32m) x 8bit - data register : (2k + 64) x8bit ? automatic program and erase - page program : (2k + 64)byte - block erase : (256k + 8k)byte ? page read operation - page size : (2k + 64)byte - random read : 60 s(max.) - serial access : 25ns(min.) ? memory cell : 2bit / memory cell 1g x 8 bit / 2g x 8 bit nand flash memory ? fast write cycle time - program time : 800 s(typ.) - block erase time : 1.5ms(typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology - endurance : 5k program/erase cycles(with 4bit/512byte ecc) - data retention : 10 years ? command register operation ? unique id for copyright protection ? package : - k9g8g08u0a-pcb0/pib0 : pb-free package 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - k9g8g08b0a-pcb0/pib0 : pb-free package 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - k9g8g08u0a-icb0/iib0 52 - pin ulga (12 x 17 / 1.00 mm pitch) - K9LAG08U1A-icb0/iib0 52 - pin ulga (12 x 17 / 1.00 mm pitch) offered in 1gx8bit, the k9g8g08x0a is a 8g-bit nand flash memo ry with spare 256m-bit. the device is offered in 2.7v and 3.3v vcc. its nand cell provides the most cost-effective solution for the solid state mass storage market. a program operation can b e per- formed in typical 800 s on the 2,112-byte page and an erase operation can be performed in typical 1.5ms on a (256k+8k)byte block. data in the data register can be read out at 25ns cycle time per byte. the i/o pins serve as the ports for address and data inp ut/out- put as well as command input. the on-chip write controller autom ates all program and erase func tions including pulse repetition , where required, and internal verification and margining of data. even the write-intensive systems can take advantage of the k9g8g08x0a s extended reliability of 5k program/erase cycles by providing ecc(error correc ting code) with real time mapping-out algorithm. the k9g8g08x0a is an optimum so lution for large nonvolatile storage applicati ons such as solid state file storage an d other portable applications requiring non-volatility. product list part number vcc range organization pkg type k9g8g08u0a-p 2.7v ~ 3.6v x8 tsop1 k9g8g08u0a-i 52ulga K9LAG08U1A-i k9g8g08b0a-p 2.5v ~ 2.9v tsop1 free datasheet http://www..net/
flash memory 4 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a pin configuration (tsop1) k9g8g08x0a-pcb0/pib0 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c n.c package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220af unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.16 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 0.20 +0.07 -0.03 free datasheet http://www..net/
flash memory 5 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a 1.00 1.00 1.00 1.00 2.00 7 6 5 4 3 2 1 1.00 1.00 1.00 12.00 0.10 #a1 17.00 0.10 17.00 0.10 b a 12.00 0.10 (datum b) (datum a) 12.0 0 10.00 2.50 2.50 2.00 0.50 1.30 a b c d e f g h j k l m n 12- ? 1.00 0.05 41- ? 0.70 0.05 side view 0.65 ( max .) 0.10 c 17.00 0.10 top view bottom view ab c d e f g h j k l m n 7 6 5 4 3 2 1 pin configuration (ulga) k9g8g08u0a-icb0/iib0 52-ulga (measured in millimeters) nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc vcc vcc vss vss vss /re nc /ce nc cle nc ale nc /we nc /wp nc r/b nc vss io0 nc io1 nc io2 io3 nc nc io4 nc io5 nc io6 nc io7 nc ? ab c m 0.1 ? ab c m 0.1 package dimensions free datasheet http://www..net/
flash memory 6 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a 1.00 1.00 1.00 1.00 2.00 7 6 5 4 3 2 1 1.00 1.00 1.00 12.00 0.10 #a1 17.00 0.10 17.00 0.10 b a 12.00 0.10 (datum b) (datum a) 12.0 0 10.00 2.50 2.50 2.00 0.50 1.30 a b c d e f g h j k l m n 12- ? 1.00 0.05 41- ? 0.70 0.05 side view 0.65 ( max .) 0.10 c 17.00 0.10 top view bottom view ab c d e f g h j k l m n 7 6 5 4 3 2 1 K9LAG08U1A-icb0/iib0 52-ulga (measured in millimeters) nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc vcc vcc vss vss vss /re1 /re2 /ce1 /ce2 cle1 cle2 ale1 ale2 /we1 /we2 /wp1 /wp2 r/b1 r/b2 vss io0-1 io0-2 io1-1 io1-2 io2-1 io3-1 io2-2 io3-2 io4-1 io4-2 io5-1 io5-2 io6-1 io6-2 io7-1 io7-2 ? ab c m 0.1 ? ab c m 0.1 package dimensions free datasheet http://www..net/
flash memory 7 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and dat a, and to output data during read operations. the i/ o pins float to high-z when the chip is des elected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for comm ands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for addres s to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase operation. regarding ce control during read operation, refer to ?page read? section of device operation. re read enable the re input is the serial data-out control, and when active drives the data onto t he i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands , address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection du ring power transitions. the internal high voltage generator is reset when the wp pin is active low. r/b ready/busy output the r/b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. free datasheet http://www..net/
flash memory 8 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a 2k bytes 64 bytes figure 1-1. k9g8g08x0a functional block diagram figure 2-1. k9g8g08x0a array organization note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than required. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 *l *l *l *l 3rd cycle a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 4th cycle a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 5th cycle a 28 a 29 a 30 *l *l *l *l *l v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 12 - a 30 a 0 - a 11 command ce re we cle wp i/0 0 i/0 7 v cc v ss 512k pages (=4,096 blocks) 2k bytes 8 bit 64 bytes 1 block = 128 pages (256k + 8k) byte i/o 0 ~ i/o 7 1 page = (2k + 64)bytes 1 block = (2k + 64)b x 128 pages = (256k + 8k) bytes 1 device = (2k+64)b x 128pages x 4,096 blocks = 8,448 mbits row address page register ale 8,192m + 256m bit nand flash array (2,048 + 64)byte x 524,288 y-gating row address column address column address data register & s/a row address free datasheet http://www..net/
flash memory 9 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a product introduction the k9g8g08x0a is a 8,448mbit(8,858,370,048 bit) memory organi zed as 524,288 rows(pages) by 2,112x8 columns. spare 64 col- umns are located from column address of 2,048~2,111. a 2,112-byte data register is connected to memory cell arrays for accommo- dating data transfer between the i/o buffers and memory cells dur ing page read and page program operations. the memory array is made up of 32 cells that are serially connected to form a nand st ructure. each of the 32 cells resides in a different page. a b lock consists of two nand structured strings. a nand structure consists of 32 cells. a cell has 2-bit data. total 1,081,344 nand cel ls reside in a block. the program and read oper ations are executed on a page basis, whil e the erase operation is executed on a blo ck basis. the memory array consists of 4,096 se parately erasable 256k-byte blocks. it indi cates that the bit by bit erase operatio n is pro- hibited on the k9g8g08x0a. the k9g8g08x0a has addresses multiplexed into 8 i/os. this scheme dramatically reduces pi n counts and allows system upgrades to future densities by maintaining cons istency in system board design. command, address and data are all written through i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively , via the i/o pins. some commands require one bus cycle. for example, reset command, status read command, etc require just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle fo r execution. the 1g-byte physical space requires 31 addresses, thereby requiring five cy cles for addressing : 2 cycles of column address, 3 cycles of row address, in t hat order. page read and page program need the same five address cycl es following the required comm and input. in block erase oper- ation, however, only three row address cy cles are used. device operations are select ed by writing specific commands into the co m- mand register. table 1 defines the sp ecific commands of the k9g8g08x0a. table 1. command sets note : 1. random data input/output can be executed in a page. 2. any command between 11h and 80h/81h/85h is prohibited except 70h/f1h and ffh. 3. two-plane random data msut be used after two-plane read operation caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st set 2nd set acceptable command during busy read 00h 30h read for copy back 00h 35h read id 90h - reset ffh - o page program 80h 10h copy-back program 85h 10h block erase 60h d0h random data input (1) 85h - random data output (1) 05h e0h read status 70h o read status 2 f1h o two-plane read (3) 60h----60h 30h two-plane read for copy-back 60h----60h 35h two-plane random data output (1) (3) 00h----05h e0h two-plane page program (2) 80h----11h 81h----10h two-plane copy-back program (2) 85h----11h 81h----10h two-plane block erase 60h----60h d0h free datasheet http://www..net/
flash memory 10 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a recommended operating conditions (voltage reference to gnd, k9xxg08xxm-xcb0 : t a =0 to 70 c, k9xxg08xxm-xib0 : t a =-40 to 85 c) parameter symbol k9g8g08b0a(2.7v) k9g8g08u0a(3.3v) unit min typ. max min typ. max supply voltage v cc 2.52.72.92.73.33.6v supply voltage v ss 000000v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during trans itions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet . exposure to absolute maximum rating conditions for extended peri ods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v cc -0.6 to + 4.6 v v in -0.6 to + 4.6 v i/o -0.6 to vcc+0.3 (<4.6v) temperature under bias k9xxg08xxm-xcb0 t bias -10 to +125 c k9xxg08xxm-xib0 -40 to +125 storage temperature k9xxg08xxm-xcb0 t stg -65 to +150 c k9xxg08xxm-xib0 short circuit current ios 5 ma dc and operating characteristics (recommended operating conditions otherwise noted.) note : 1. vil can undershoot to -0.4v and vih can overshoot to vcc + 0.4v for durations of 20 ns or less. 2. typical value is measured at vcc=2.7v/3.3v, ta=25c. not 100% tested. 3. the typical value of the K9LAG08U1A?s i sb 2 is 20 a and the maximum value is 100 a. parameter symbol test conditions k9g8g08x0a unit 2.7v 3.3v min typ max min typ max operating current page read with serial access i cc 1 trc=25ns, ce =v il i out =0ma - 15 30 - 15 30 ma program i cc 2 - - 15 30 - 15 30 erase i cc 3 - - 15 30 - 15 30 stand-by current(ttl) i sb 1ce =v ih , wp =0v/v cc --1--1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =0v/v cc - 10 50 - 10 50 a input leakage current i li v in =0 to vcc(max) - - 10 - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 - - 10 input high voltage v ih* - v cc -0.4 - v cc +0.3 0.8 x vcc - v cc +0.3 v input low voltage, all inputs v il* - -0.3 - 0.5 -0.3 - 0.2 x vcc output high voltage level v oh k9g8g08b0a :i oh =-100 a k9g8g08u0a :i oh =-400 a v cc -0.4 --2.4-- output low voltage level v ol k9g8g08b0a :i ol =100ua k9g8g08u0a :i ol =2.1ma --0.4--0.4 output low current(r/b )i ol (r/b ) k9g8g08b0a :v ol =0.1v k9g8g08u0a :v ol =0.4v 34- 810-ma free datasheet http://www..net/
flash memory 11 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a valid block note : 1. the device may include initial invalid blocks when first shi pped. additional invalid blocks may develop while being used. th e number of valid blocks is presented with both cases of inva lid blocks considered. invalid bloc ks are defined as blocks that contain one or more bad bits. do not erase or pro- gram factory-marked bad blocks. refer to the attached technical notes for appropriate management of initial invalid blocks. 2. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment. 3. the number of valid blocks is on the basis of single pla ne operations, and this may be de creased with two plane operations. * : each k9g8g08u0a chip in the K9LAG08U1A has maximum 100 invalid blocks. parameter symbol min typ. max unit k9g8g08x0a n vb 3,996 - 4,096 blocks K9LAG08U1A n vb 7,992 8,192 blocks capacitance ( t a =25 c, vcc=2.7v/3.3v , f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode hll hx read mode command input l h l h x address input(5clock) hll hh write mode command input l h l h h address input(5clock) l l l h h data input l l l h x data output xxxxhx during read(busy) xxxxxh during program(busy) xxxxxh during erase(busy) x x (1) x x x l write protect xxhxx 0v/v cc (2) stand-by ac test condition (k9xxg08xxm-xcb0 :ta=0 to 70 c, k9xxg08xxm-xib0:ta=-40 to 85 c, k9g8g08b0a: vcc=2.5v~2.9v, k9xxg08uxm: vcc=2.7v~3.6v unless otherwise) parameter k9g8g08b0a k9xxg08uxm input pulse levels 0v to vcc 0v to vcc input rise and fall times 5ns 5ns input and output timing levels vcc/2 vcc/2 output load 1 ttl gate and cl=30pf 1 ttl gate and cl=50pf free datasheet http://www..net/
flash memory 12 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a program / erase characteristics note 1. typical value is measured at vcc=3.3v , ta=25 c. not 100% tested. 2. typical program time is defined as the time within wh ich more than 50% of the whole pages are programmed at 3.3v vcc and 25 c temperature. 3. within a same block, program time(tprog) of page group a is faster than that of page group b. typical tprog is the average program time of the page group a and b(table 2). page group a: page 0, 1, 2, 3, 6, 7, 10, 11, ... , 110, 111, 114, 115, 118, 119, 122, 123 page group b: page 4, 5, 8, 9, 12, 13, 16, 17, ... , 116, 117, 120, 121, 124, 125, 126, 127 parameter symbol min typ max unit program time t prog -0.83 ms dummy busy time for multi plane program t dbsy 0.5 1 s number of partial program cycles in the same page nop - - 1 cycle block erase time t bers -1.510ms ac timing characteristics for command / address / data input notes : 1. the transition of the corresponding co ntrol pins must occur only once while we is held low. 2. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. parameter symbol min max unit cle setup time t cls (1) 12 - ns cle hold time t clh 5-ns ce setup time t cs (1) 20 - ns ce hold time t ch 5-ns we pulse width t wp 12 - ns ale setup time t als (1) 12 - ns ale hold time t alh 5- ns data setup time t ds (1) 12 - ns data hold time t dh 5-ns write cycle time t wc 25 - ns we high hold time t wh 10 - ns address to data loading time t adl (2) 100 (2) -ns free datasheet http://www..net/
flash memory 13 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5 s. parameter symbol min max unit data transfer from cell to register t r -60 s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 12 - ns we high to busy t wb - 100 ns read cycle time t rc 25 - ns re access time t rea -20ns ce access time t cea -25ns re high to output hi-z t rhz - 100 ns ce high to output hi-z t chz -30ns ce high to ale or cle don?t care t csd 10 - ns re high to output hold t rhoh 15 - ns re low to output hold t rloh 5-ns ce high to output hold t coh 15 - ns re high hold time t reh 10 - ns output hi-z to re low t ir 0-ns re high to we low t rhw 100 - ns we high to re low t whr 60 - ns device resetting time(read/program/erase) t rst - 5/10/500 (1) s free datasheet http://www..net/
flash memory 14 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a nand flash technical notes identifying initial invalid block(s) initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial inva lid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is called the initial invalid block inform ation. devices with initial in valid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invalid bl ock(s) does not affect the performance of valid bl ock(s) because it is isolated from the bi t line and the common source line by a sele ct tran- sistor. the system design must be able to mask out the initial in valid block(s) via address mappi ng. the 1st block, which is pl aced on 00h block address, is guaranteed to be a valid block at the time of shipment. all device locations are erased(ffh) except locations where the initial invalid block(s) information is written prior to shippi ng. the initial invalid block(s) status is defined by the 1st byte in the spare area. samsung makes sure that the last page of every in itial invalid block has non-ffh data at the column address of 2,048.the initial invalid block information is al so erasable in most cases, and it is impossible to recover the information once it has been erased. t herefore, the system must be able to recognize the initial inva lid block(s) based on the initial invalid bl ock information and create the initial inva lid block table via the following suggested flow chart(figure 3). any intentional erasure of the initial invalid block information is prohibited. * check "ffh" at the column address figure 3. flow chart to create initial invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no initial 2048 of the last page in the block invalid block(s) table free datasheet http://www..net/
flash memory 15 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes error in write or read operation within its life time, additional invalid bl ocks may develop with nand flash memory. refer to the qualification report for the a ctual data. block replacement should be done upon erase or program error. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read up to four bit failur e verify ecc -> ecc correction ecc : error correcting code --> rs code etc. example) 4bit correction / 512-byte : if program operation results in an error, map out the block including the page in error and copy the * target data to another block. free datasheet http://www..net/
flash memory 16 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) write 30h block replacement buffer memory of the controller. 1st block a block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2 * step1 when an error happens in the nth page of the bl ock ?a? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program block ?a? by creating an ?i nvalid block? table or other appropriate scheme. free datasheet http://www..net/
flash memory 17 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a within a block, the pages must be programmed consecutively from the lsb (least significant bit) page of the block to msb (most sig- nificant bit) pages of the block. random page address programming is prohibited. in this case, the definition of lsb page is th e lsb among the pages to be programmed. therefore, lsb doesn't need to be page 0. from the lsb page to msb page data in: data (1) data (128) (1) (2) (3) (32) (128) data register page 0 page 1 page 2 page 31 page 127 ex.) random page program (prohibition) data in: data (1) data (128) (2) (32) (3) (1) (128) data register page 0 page 1 page 2 page 31 page 127 nand flash technical notes (continued) addressing for program operation : : : : free datasheet http://www..net/
flash memory 18 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or serial access as shown below. the internal 2,112byte data registers are utilized as separate buf fers for this operation and the system desig n gets more flexible. in addition, for v oice or audio applications whic h use slow cycle time on the order of -seconds, de-activating ce during the data-loading and serial access would provide significant sa vings in power consumption. figure 4. program operation with ce don?t-care. ce we t wp t ch t cs address(5cycles) 80h data input ce cle ale we data input ce don?t-care 10h address(5cycle) 00h ce cle ale we data output(serial access) ce don?t-care r/b t r re t cea out t rea ce re i/o 0 ~ 7 figure 5. read operation with ce don?t-care. 30h i/ox i/ox free datasheet http://www..net/
flash memory 19 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a note device i/o data address i/ox data in/out col. add1 col. add2 row add1 row add2 row add3 k9g8g08x0a i/o 0 ~ i/o 7 ~2,112byte a0~a7 a8~a11 a12~a19 a20~a27 a28~a30 command latch cycle ce we cle ale command t cls t cs t clh t ch t wp t als t alh t ds t dh i/ox address latch cycle ce we cle ale col. add1 t c l s t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t ds t dh t wp i/ox col. add2 row add1 row add2 t wc t wh t alh t als t ds t dh row add3 t alh free datasheet http://www..net/
flash memory 20 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a input data latch cycle ce cle we din 0 din 1 din final ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp i/ox * serial access cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t rhoh (2) t rea t reh t rea t coh t rhz (1) i/ox t chz (1) t rhz (1) notes 1. transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 2. trloh is valid when frequency is higher than 20mhz. trhoh starts to be valid when frequency is lower than 20mhz. free datasheet http://www..net/
flash memory 21 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a re ce r/b i/ox t rr t cea t rea t rp t reh t rc t rhz (1) serial access cycle after read (edo type, cle=l, we =h, ale=l) t rhoh t coh t rloh (2) dout dout t rea notes 1. transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 2. trloh is valid when frequency is higher than 20mhz. trhoh starts to be valid when frequency is lower than 20mhz. t chz (1) status read cycle ce we cle re 70h/f1h status output t clr t clh t wp t ch t ds t dh t rea t ir t rhoh t coh t whr t cea t cls i/ox t chz t rhz t cs free datasheet http://www..net/
flash memory 22 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a read operation ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc row add2 30h t clr i/ox row add3 read operation (intercepted by ce ) ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h i/ox col. add1 col. add2 row add1 row add2 row add3 t coh t csd t csd free datasheet http://www..net/
flash memory 23 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t w b t ar t r t rr t r c 30h 05h column address dout m dout m+1 i/ox col. add1 col. add2 row add1 row add2 col add1 col add2 row add3 e0h t whr t rea t r h w t clr free datasheet http://www..net/
flash memory 24 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a page program operation ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc i/ox co.l add1 col. add2 row add1 row add2 row add3 t adl t whr free datasheet http://www..net/
flash memory 25 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a page program operation with random data input ce cle r/b we ale re 80h 70h i/o 0 di n din 10h m serial data input command column address row address serial input program command read status command t prog t wb t wc t wc 85h random data input command column address t wc din j din k serial input i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add3 t adl din n t adl t whr i/o 0 =0 successful program i/o 0 =1 error in program free datasheet http://www..net/
flash memory 26 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc auto block erase setup command i/ox row add1 row add2 row add3 t whr free datasheet http://www..net/
flash memory 27 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a two-plane read operation with two-plane random data output 00h column address tw row address a 12 ~a 19 a 20 ~a 27 a 28 ~a 30 a 8 ~a 11 a 0 ~a 7 twc column address a 8 ~a 11 a 0 ~a 7 05h dout n 00h column address tw row address a 12 ~a 19 a 20 ~a 27 a 28 ~a 30 a 8 ~a 11 a 0 ~a 7 twc column address a 8 ~a 11 a 0 ~a 7 05h e0h dout m 60h tw row address a 12 ~a 19 a 20 ~a 27 a 28 ~a 30 twc 60h tw row address a 12 ~a 19 a 20 ~a 27 a 28 ~a 30 twc 30h 1 1 ce cle r/b we ale re i/ox ce cle r/b we ale re i/ox busy t wb t r t rea t whr t clr t whr t clr a 12 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 12 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid a 0 ~ a 11 : fixed ?low? a 12 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 0 ~ a 11 : valid a 0 ~ a 11 : fixed ?low? a 12 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : fixed ?low? a 0 ~ a 11 : valid t rea e0h t rc t rc dout n+1 t rhw dout m+1 free datasheet http://www..net/
flash memory 28 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a two-plane page program operation 80h i/o 0 ~ 7 r/b 11h ex.) two-plane page program t dbsy address & data input 81h 10h address & data input 70h t prog ce cle r/b we ale re 80h din n din 11h m serial data input command column address program tdbsy twb twc command (dummy) din n 10h tprog twb i/o 0 program confirm command (true) 81h 70h page row address i/ox a 0 ~a 7 a 8 ~a 11 a 12 ~a 19 a 20 ~a 27 a 28 ~a 30 a 0 ~a 7 a 8 ~a 11 a 12 ~a 19 a 20 ~a 27 a 28 ~a 30 1 up to 2112 byte data serial input din m read status command t dbsy : typ. 500ns max. 1 s a 0 ~ a 11 : valid a 12 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 0 ~ a 11 : valid a 12 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid note: any command between 11h and 81h is prohibited except 70h/f1h and ffh. note i/o 0 =0 successful program i/o 0 =1 error in program free datasheet http://www..net/
flash memory 29 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a two-plane block erase operation block erase setup command1 erase confirm command read status command 60h row add1,2,3 i/o 0 ~ 7 r/b 60h a 9 ~ a 25 d0h t bers ex.) address restriction for tw o-plane block erase operation ce cle r/b i/o x we ale re 60h row add1 d0h 70h i/o 0 busy t wb t bers t wc d0h 70h address address row add1,2,3 i/o 0 = 0 successful erase i/o 0 = 1 error in erase row add2 row add3 a 12 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 12 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : valid 60h row add1 d0h row add2 row add3 row address t wc block erase setup command2 row address t whr free datasheet http://www..net/
flash memory 30 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a device device code(2nd cycle) 3rd cycle 4th cycle 5th cycle k9g8g08b0a d3h 14h a5h 64h k9g8g08u0a d3h 14h a5h 64h K9LAG08U1A same as each k9g8g08u0a in it read id operation ce cle we ale re 90h read id command maker code device code 00h ech t rea address. 1cycle i/ox t ar device 4th cyc. code 3rd cyc. 5th cyc. free datasheet http://www..net/
flash memory 31 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a 4th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area ) 1kb 2kb 4kb 8kb 0 0 0 1 1 0 1 1 block size (w/o redundant area ) 64kb 128kb 256kb 512kb 0 0 0 1 1 0 1 1 redundant area size ( byte/512byte) 8 16 0 1 organization x8 x16 0 1 serial access minimum 50ns/30ns 25ns reserved reserved 0 1 0 1 0 0 1 1 3rd id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between multiple chips not support support 0 1 cache program not support support 0 1 id definition table 90 id : access command = 90h description 1 st byte 2 nd byte 3 rd byte 4 th byte 5 th byte maker code device code internal chip number, cell type, number of simultaneously programed pages, etc page size, block size, redundant size, organization, serial access minimum plane number, plane size free datasheet http://www..net/
flash memory 32 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a 5th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (w/o redundant area) 64mb 128mb 256mb 512mb 1gb 2gb 4gb 8gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 reserved 0 0 0 free datasheet http://www..net/
flash memory 33 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a device operation page read page read is initiated by writing 00h-30h to the command register along with five address cycles. after initial power up, 00h c ommand is latched. therefore only five address cy cles and 30h command initiates that operation after initial power up. the 2,112 bytes of data within the selected page are transferred to the data registers in less than 60 s(t r ). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the co nsecutive sequential data by writing random data output command. the column address of next data, which is going to be out, ma y be changed to the address which follows random data output com- mand. random data output can be operated multiple time s regardless of how many times it is done in a page. figure 6. read operation address(5cycle) 00h col add1,2 & row add1,2,3 data output(serial access) data field spare field ce cle ale r/b we re t r 30h i/ox free datasheet http://www..net/
flash memory 34 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a figure 7. random data output in a page address 00h data output r/b re t r 30h address 05h e0h 5cycles 2cycles data output data field spare field data field spare field page program the device is programmed basical ly on a page basis, and the number of consecutiv e partial page programming operation within the same page without an intervening erase operation must not exceed 1 time for the page. the addressing should be done in sequenti al order in a block. a page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input command(80h) , followed by the fi ve cycle address input s and then serial data loading. the data other than those to be progra mmed does not need to be loaded. the device supports random dat a input in a page. the column address for the next data, which wi ll be entered, may be changed to the address which follows rando m data input command(85h). random data input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programming process. writing 10h alone wit hout previously entering the serial data will not initiate the programming process. the internal write state controller automat ically executes the algorithm s and tim- ings necessary for program and verify, thereb y freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status r egister. the system controller can detect the completion of a p ro- gram cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the p age program is complete, the write status bit(i/o 0) may be checked(figure 8). the internal write verify detects only errors for "1"s that are no t successfully programmed to "0"s. the com mand register remains in read status command mode until an other valid command is written to the command register. figure 8. program & read status operation 80h r/b address & data input i/o 0 pass data 10h 70h fail t prog i/ox i/ox col add1,2 & row add1,2,3 "0" "1" col add1,2 & row add1,2,3 free datasheet http://www..net/
flash memory 35 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a figure 9. random data input in a page 80h r/b address & data input i/o 0 pass 10h 70h fail t prog 85h address & data input i/ox col add1,2 & row add1,2,3 col add1,2 data data "0" "1" copy-back program note : 1. copy-back program operation is allowed only within the same memory plane. copy-back program with read for copy-back is configured to quickly and efficiently rewrite data stored in one page without data re- loading when the bit error is not in data stored. since the time-consuming re-loading cycles ar e removed, the system performanc e is improved. the benefit is especially obvious when a portion of a bl ock is updated and the rest of the block also needs to be cop ied to the newly assigned free block. copy-back oper ation is a sequential execution of read fo r copy-back and of copy-back program wit h the destination page address. a read operation with "35h" command and the address of the source page moves the whole 2,112-byte data into the internal data buffer. a bit error is checked by sequential reading the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore copy-back program oper ation is initiated by issuing page-copy data-input command (85h) with destination page address. actual programming operati on begins after program confirm command (10h) is issued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system contr ol- ler can detect the completion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. when the copy-back program is complete, the write status bit(i/o 0) may be checked(figure 10 & figure 11). the command register remains in read status command mode until another valid command is written to the command register. during copy-back program, data modification is possible us ing random data input command (85h) as shown in figure11. "0" "1" figure 10. page copy-back program operation 00h r/b add.(5cycles) i/o0 pass fail t prog t r source address destination address i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 35h data output 85h add.(5cycles) 10h 70h figure 11. page copy-back program operation with random data input r/b source address destination address there is no limitation for the number of repetition. i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 col. add.1,2 00h add.(5cycles) 35h t r data output 85h add.(5cycles) data 85h add.(2cycles) data 10h t prog 70h free datasheet http://www..net/
flash memory 36 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a figure 12. block erase operation block erase the erase operation is done on a block basis. bl ock address loading is accompli shed in three cycles initiated by an erase setup command(60h). only address a 19 to a 30 is valid while a 12 to a 18 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasi ng process. this two-step sequence of se tup followed by execution command ensures t hat memory contents are not accidentally er ased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles er ase and erase-verify. when the erase operation is completed, the write status bit( i/o 0) may be checked. figure 10 details the sequence. 60h row add. : a 12 ~ a 30 r/b address input(3cycle) i/o 0 pass d0h 70h fail t bers i/ox "0" "1" two-plane page read two-plane page read is an extension of page r ead, for a single plane with 2,112 byte page registers. since the device is equipp ed with two memory planes, activating the two sets of 2,112 byte page registers enables a random read of two pages. two-plane page read is initiated by repeating command 60h followed by three address cy cles twice. in this case only same page of same block ca n be selected from each plane. after read confirm command(30h) the 4,224 bytes of data within the selected two page are transferred to the data registers in l ess than 60us(tr). the system controller can detect the completi on of data transfer(tr) by monitoring the output of r/b pin. once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h with fiv e address cycles, command 05h with two column address and finally e0h. the data output of second plane can be read out using the identical command sequences. the restricti ons for two-plane page program are shown in figure 13. two-plane read must be used in the block which has been progr ammed with two-plane page program. figure 13. two-plane page read operation with two-plane random data out 60h i/o x r/b 60h 30h t r address (3 cycle) address (3 cycle) a 12 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 12 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 a 0 ~ a 11 : fixed ?low? a 12 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 0 ~ a 11 : valid 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 a 0 ~ a 11 : fixed ?low? a 12 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : fixed ?low? a 0 ~ a 11 : valid free datasheet http://www..net/
flash memory 37 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a figure 14. two-plane page program 80h 11h data input plane 0 (2048 block) block 0 block 2 block 4094 block 4092 a 0 ~ a 11 : valid a 12 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30: fixed ?low? a 0 ~ a 11 : valid a 12 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid note : 1. it is noticeable that physically same row address is applied to two planes . 81h 10h plane 1 (2048 block) block 1 block 3 block 4095 block 4093 2. any command between 11h and 81h is prohibited except 70h/f1h and ffh. 80h i/o 0 ~ 7 r/b address & data input 11h 81h 10h t dbsy t prog 70h address & data input note* 2 i/o 0 pass fail "0" "1" two-plane page program two-plane page program is an extension of page program, for a single plane with 2112 byte page registers. since the device is equipped with two memory planes, acti vating the two sets of 2112 byte page registers enables a simultaneous programming of two pages. after writing the first set of data up to 2112 byte into the selected page register, dummy page program command (11h) instead o f actual page program (10h) is inputted to finish data-loading of the first plane. sinc e no programming process is involved, r/b remains in busy state for a short period of time(tdbsy). read st atus command (70h/f1h) may be issued to find out when the devic e returns to ready state by polling the r eady/busy status bit(i/o 6). then the next se t of data for the other plane is inputted a fter the 81h command and address sequences. after inputting data for the last plane, actual true page program(10h) instead of dummy page program command (11h) must be followed to star t the programming process. the operation of r/b and read status is the same as that of page program. althougth two planes are programm ed simultaneously, pass/fail is not available for each page when the program operation completes. status bit of i/o 0 is set to "1" when any of the pages fails. restriction in addressing with two-plane page program is shown in figure14. two-plane copy-back program two-plane copy-back program is an extension of copy-back program, for a single plane with 2112 byte page registers. since the device is equipped with two memory planes, ac tivating the two sets of 2112 byte page registers enables a simultaneous program- ming of two pages. free datasheet http://www..net/
flash memory 38 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a figure 15. two-plane copy-back program operation r/b 85h 70h t prog add.(5cycles) destination address 10h i/ox col. add.1,2 & row add.1,2,3 81h add.(5cycles) destination address col. add.1,2 & row add.1,2,3 11h t dbsy a 0 ~ a 11 : fixed ?low? a 12 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 0 ~ a 11 : fixed ?low? a 13 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid 3 note3 60h i/o x r/b 60h 35h t r address (3 cycle) address (3 cycle) a 12 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 12 ~ a 18 : valid a 19 : fixed ?high? a 20 ~ a 30 : valid 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 a 0 ~ a 11 : fixed ?low? a 12 ~ a 18 : fixed ?low? a 19 : fixed ?low? a 20 ~ a 30 : fixed ?low? a 0 ~ a 11 : valid 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 a 0 ~ a 11 : fixed ?low? a 12 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : fixed ?low? a 0 ~ a 11 : valid 3 data field spare field (1) (3) plane0 source page target page (1) : two-plane read for copy back (2) : two-plane random data out (3) : two-plane copy-back program note : 1. copy-back program operation is allo wed only within the same memory plane. 2 . any command between 11h and 81h is prohibited except 70h/f1h and ffh. (2) data field spare field (1) (3) plane1 source page target page (2) free datasheet http://www..net/
flash memory 39 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a two-plane block erase basic concept of two-plane block erase operat ion is identical to that of two-plane pa ge program. up to two blocks, one from eac h plane can be simultaneously erased. standard block erase comm and sequences (block erase setup command(60h) followed by three address cycles) may be repeated up to twice for erasing up to two blocks. only one block should be selected from each pla ne. the erase confirm command(d0h) initiates the actual erasi ng process. the completion is detected by monitoring r/b pin or ready/ busy status bit (i/o 6). figure 16. two-plane erase operation 60h i/o x r/b 60h d0h i/o0 pass fail t bers address (3 cycle) address (3 cycle) 70h a 12 ~ a 18 : fixed ?low? a 19 : fixed ?low? "0" "1" a 20 ~ a 30 : fixed ?low? a 12 ~ a 18 : fixed ?low? a 19 : fixed ?high? a 20 ~ a 30 : valid free datasheet http://www..net/
flash memory 40 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a read status the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. after writing 70h or f1h command to the command register, a read cycl e outputs the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each dev ice in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 3 an d table 4 for specific f1h status register definitions. the com- mand register remains in status read mode until further commands ar e issued to it. therefore, if the status register is read du ring a random read cycle, the read command(00h) shoul d be given before starting read cycles. table 3. read status register definition note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. i/o no. page program block erase read definition i/o 0 pass/fail pass/fail not use pass : "0" fail : "1" i/o 1 not use not use not use don?t -cared i/o 2 not use not use not use don?t -cared i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready /busy busy : "0" ready : "1" i/o 7 write protect write protect write protect pro tected : "0" not protected : "1" table 4. f1h read status register definition note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. i/o no. page program block erase read definition i/o 0 chip pass/fail chip pass/fail not use pass : "0" fail : "1" i/o 1 plane0 pass/fail plane0 pass/fail not use pass : "0" fail : "1" i/o 2 plane1 pass/fail plane1 pass/fail not use pass : "0" fail : "1" i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy b usy : "0" ready : "1" i/o 7 write protect write protect write protect prote cted : "0" not protected : "1" free datasheet http://www..net/
flash memory 41 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a figure 18. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort th ese operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased . the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 5 for device stat us after reset operation. if the device is already in reset state a new reset command will be accepted by the command register. the r/b pin changes to low for trst after the reset command is written. refer to figure 18 below. ffh i/o x r/b t rst table 5. device status after power-up after reset operation mode 00h command is latched waiting for next command figure 17. read id operation ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea read id the device contains a product identification mode, initiated by wr iting 90h to the command register, followed by an address inp ut of 00h. five read cycles sequentially output the manufacturer code(e ch), and the device code and 3rd cycle id, 4th cycle id, 5th c ycle id respectively. the command register remains in read id mo de until further commands are issued to it. figure 17 shows the ope r- ation sequence. ech t whr t clr device device code(2nd cycle) 3rd cycle 4th cycle 5th cycle k9g8g08b0a d3h 14h a5h 64h k9g8g08u0a d3h 14h a5h 64h K9LAG08U1A same as each k9g8g08u0a in it device 4th cyc. code 3rd cyc. 5th cyc. free datasheet http://www..net/
flash memory 42 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a paired page address information paired page address paired page address 00h 04h 01h 05h 02h 08h 03h 09h 06h 0ch 07h 0dh 0ah 10h 0bh 11h 0eh 14h 0fh 15h 12h 18h 13h 19h 16h 1ch 17h 1dh 1ah 20h 1bh 21h 1eh 24h 1fh 25h 22h 28h 23h 29h 26h 2ch 27h 2dh 2ah 30h 2bh 31h 2eh 34h 2fh 35h 32h 38h 33h 39h 36h 3ch 37h 3dh 3ah 40h 3bh 41h 3eh 44h 3fh 45h 42h 48h 43h 49h 46h 4ch 47h 4dh 4ah 50h 4bh 51h 4eh 54h 4fh 55h 52h 58h 53h 59h 56h 5ch 57h 5dh 5ah 60h 5bh 61h 5eh 64h 5fh 65h 62h 68h 63h 69h 66h 6ch 67h 6dh 6ah 70h 6bh 71h 6eh 74h 6fh 75h 72h 78h 73h 79h 76h 7ch 77h 7dh 7ah 7eh 7bh 7fh note: when program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also paired page data may be damaged. free datasheet http://www..net/
flash memory 43 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 c , c l = 50pf 1k 2k 3k 4k 100n 200n 2m 1m 50 tf 100 150 200 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 2.7v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 2m 1m 30 tf 60 90 120 2.3 2.3 2.3 2.3 2.3 1.1 0.75 0.55 rp value guidance rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + i l = 3.2v 8ma + i l rp(min, 2.7v part) = v cc (max.) - v ol (max.) i ol + i l = 2.5v 3ma + i l figure 19. rp vs tr ,tf & rp vs ibusy where i l is the sum of the input currents of all devices tied to the r/b pin. rp(max) is determined by maximu m permissible limit of tr ready/busy the device has a r/b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/b pin is normally high but transitions to low after pr ogram or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal contro ller has finished the operation . the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropr iate value can be obtained with the follow ing reference chart(fig 19). its value can be determined by the following guidance. v cc r/b open drain output device gnd rp ibusy busy ready vcc voh tf tr vol c l 3.3v device - vol : 0.4v, voh : 2.4v 2.7v device - vol : 0.4v, voh : vcc-0.4v free datasheet http://www..net/
flash memory 44 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a data protection & power up sequence the device is designed to offer protection from any involuntar y program/erase during power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 1.8v(2.7 v device), 2v(3.3v device). wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 100 s is required before internal cir- cuit gets ready for any command sequences as shown in figure 21. the two step co mmand sequence for program/erase provides additional software protection. figure 20. ac waveforms for power transition v cc wp high we 100 s 3.3v device : ~ 2.5v 2.7v device : ~ 2.0v 3.3v device : ~ 2.5v 2.7v device : ~ 2.0v free datasheet http://www..net/
flash memory 45 preliminary k9g8g08u0a K9LAG08U1A k9g8g08b0a wp ac timing guide enabling wp during erase and program busy is prohibited. the eras e and program operations are enabled and disabled as follows: figure a-1. program operation 1. enable mode 80h 10h we i/o wp rnb tww(min.100ns) 2. disable mode 80h 10h tww(min.100ns) 1. enable mode 60h d0h tww(min.100ns) 2. disable mode 60h d0h tww(min.100ns) figure a-2. erase operation we i/o wp rnb we i/o wp rnb we i/o wp rnb free datasheet http://www..net/

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