View AK1572_7772338.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

[ak 1572 ] m s 1551 - e - 0 0 1 2013/ /8 1. over v iew AK1572 is the down - convert e r mixer with f ractional - n f requency synthesizer and i ntegrated vco . AK1572 is targeted at the application that requires a high linearity performance in frequency conversion. t he mixer block is comprised of the single input and the differential output. input frequency range is from 690mhz to 4000mhz and output frequency range is from 20mhz to 500mhz. the current consumption and the analog performance can be adjusted by a resistance connected to bias pin. the pow er supply voltage of mixer covers 4.75 to 5.25v. the local signal ou tput frequency range is from 262.5 mhz to 4400mhz generated by i nternal vco, s ynthesizer and divider . not only a local signal is supplied to an internal mixer, but also can be taken to outside. a power supply voltage rang e of vco/ s ynthesizer is 2.7v to 3.6v or 4.75v to 5.25v. the cpu interface is 24bit serial data and its voltage is ranging from 2.7v to 5 . 25v 2. features general ? rf input frequency range 6 90 mhz to 4.0 ghz ? if output frequency range 20mhz to 500mhz ? lo frequency range 262.5 mh z to 4.4ghz ? supply voltage : 4.75 v to 5.25 v (mixer) 2.7 to 3.6v / 4.75 to 5.25v (synth esizer / vco) ? current consumption : 1 5 0ma typ. ? package : 32 pin qfn ( 0.5mm pitch , 5 mm ? 5 mm ? 0.8 5mm) ? operating temperature : - 40 c ~ 85 c synth esizer /vco ? normalized phase noise - 21 8 dbc/hz ? phase noise - 11 1 dbc/hz @100khz f o =2 .1 ghz mixer ( f rf =2ghz ) ? conversion gain - 1.5 db typ. ? input 3 rd orders intercept point +23 dbm typ. ? noise f igure 14 d b typ . application microwave radio link cellular bts / repeater down co n verter mixer wi th fractional - n frequency synthesizer and vco ak 1572
[ak 1572 ] m s 1551 - e - 0 0 2 2013/ /8 3. table of content 1. overview ________________________________ ____________________________ 1 2. features ________________________________ ____________________________ 1 3. table of content ________________________________ _____________________ 2 4. block diagram and function ________________________________ ____________ 3 5. pin function description and assignment ________________________________ 4 6. absolute maximum rating ________________________________ _____________ 6 7. recommended operating range ________________________________ ________ 7 8. electrical characteristics ________________________________ ______________ 7 9. block functional descriptions ________________________________ _________ 11 10. loop filter /charge pump ________________________________ _____________ 12 11. register map ________________________________ _______________________ 13 12. lock detect ________________________________ ________________________ 22 13. frequenc y setup ________________________________ ____________________ 25 14. fast lock mode ________________________________ _____________________ 26 15. vco ________________________________ _______________________________ 27 16. power up sequenc e ________________________________ _________________ 28 17. typical evaluation board schematic ________________________________ ____ 29 18. interface circuit ________________________________ _____________________ 31 19. outer dimensions ________________________________ ___________________ 33 20. marking ________________________________ ____________________________ 34
[ak 1572 ] m s 1551 - e - 0 0 3 2013/ /8 4. block diagram and function fig . 1 AK1572 block diagram block function description block function m ixer frequency mixer which converts rf signal to if signal n divider frequ ency divider which divide s the signal of vco and pass it to p hase frequency detector ? modulator control the modulus of n divider and realize fraction al dividing r counter frequency divider which divide s the signal of reference clock and pass it to p hase frequency detector pfd ( phase frequency detector ) det ect a phase difference between the divided vco signal and comparison frequency , and then drive the charge pump charge pump output the electric charge according to the phase difference detected by pfd vco the voltage controlled oscillator divided into three bands dig ldo r counter 8bit phase frequency detector charge pump fast counter register 24bit ? modulator n - counter virefgen mux mux divider 1/n n=1,2,4,8 vco calibration lock detect pdn svdd cpbias cpvdd gnd test1 test2 cpbufvdd mixoutp mixoutn mixvdd lovdd vref2 vcnt lon oavdd gnd vcovdd ld cp lop gnd vref1 refin clk data le mixinp mixinn mixbias gnd pvdd mixer vco
[ak 1572 ] m s 1551 - e - 0 0 4 2013/ /8 5. pin function description and assignment 1. pin functions no name i/o pin function p ower down remarks 1 vref1 ao connecting a capacitor to the ground plane 2 pvdd p synthesizer power supply 3 gnd g 4 mixbias ai connecting a resistor to the ground plane 5 mixinn ai mixer i nput 6 mixinp ai mixer c omplementary i nput 7 mixvdd p mixer power supply 8 lovdd p mixer local power supply 9 mixoutp ao mixer o utput open collector 10 mixoutn ao mixer c omplementary o utput open collector 11 pdn di power control a logic low on this pin power s down the device schmidt trigger input 12 le di load enable schmidt trigger input 13 clk di serial clock input schmidt trigger input 14 data di serial data input schmidt trigger input 15 ld do lock detect output low 16 svdd p interface power supply 17 lop aio local complementary input / output 18 lon aio local input / output 19 oavdd p local output amplifier power supply 20 gnd g 21 vcnt ai control input to vco 22 vref2 ao connecting a capacitor to the ground plane 23 gnd g 24 vcovdd p vco power supply 25 cpbias ai connecting a resistor to the ground plane 26 cp ao charge pump output tri - st ate 27 gnd g 28 cpvdd p charge pump power supply 29 cpbufvdd p charge pump pre - buffer power supply
[ak 1572 ] m s 1551 - e - 0 0 5 2013/ /8 no name i/o pin function p ower down remarks 30 test1 di test enable a logic low on this pin test mode the device. pull down schmidt trigger input 31 test2 di test enable a logic low on this pin test mode the device. pull down schmidt trigger input 32 refin ai reference input note 1) the exposed pad at the center of the backside should be connected to ground. the following table shows the meaning of abbreviations used in the i/o column above . ai:analog input pin ao:analog output pin aio:analog i/o pin di:digital input pin do: digital output pin p: power supply pin g:ground pin 2. pin assignments 32 pin qfn (0.5mm pitch, 5 mm x 5 mm) fig . 2 package pin layout (top view) 1 2 3 4 5 6 7 8 32 25 26 27 28 2 9 30 31 16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 33
[ak 1572 ] m s 1551 - e - 0 0 6 2013/ /8 6. absolute maximum rating parameter symbol min. max. unit remarks supply voltage vdd1 - 0.3 5.5 v note1, note2 vdd2 - 0.3 5.5 v note 3 vdd3 - 0.3 5.5 v note4 ground level vss 0 0 v note5 maximum rf input level rfpow 12 dbm note6 maximum lo input level lopow 12 dbm note7 analog input voltage vain vss - 0.3 vdd 3 +0.3 v note1, note 8 digital input voltage1 vdin1 vss - 0.3 v dd1 +0.3 v note1, note 9 digital input voltage 2 vdin2 v ss - 0.3 v dd3 +0.3 v note1, note 10 input current iin - 10 10 ma storage temperature tstg - 55 125 ? c note1 all voltage reference ground l evel : 0v note2 applied to the [svdd] pin note3 applied to the [ mixvdd ] and [ lov dd ] pin s note4 applied to the [ cpvdd ], [ cpbufvdd ], [ pvdd ] , [ vcovdd ] and [ oavdd ] pins note5 applied to the all [ gnd ] pins note6 applied to the [ mixi n p ] and [ mix in n ] pin s note7 applied to the [ lop ] and [ lo n ] pin s note8 applied to the [ vcnt ] and [ refin ] pin s note9 applied to the [ clk ] , [ data ] , [ le ] and [ pdn ] pin s note10 applied to the [ test1 ] and [ test2 ] pin s exceeding these maximum ratings may result in damage to the AK1572 . normal operation is not guaranteed at these extremes .
[ak 1572 ] m s 1551 - e - 0 0 7 2013/ /8 7. recommended operating range parameter symbol min. typ. max. unit remarks operating temperature ta - 40 85 ? c supply voltage vdd1 2.7 3.0 5.25 v vdd2 4.75 5 5.25 v vdd3 2.7 3 3.6 v 4.75 5 5.25 v note1 applied to the [svdd] pin note2 applied to the [mixvdd] and [lovdd] pins note3 applied to the [cpvdd], [cpbufvdd], [pvdd], [vcovdd] and [oavdd] pins 8. electrical characteristics 1. digital dc characteristics parameter symbol conditions min. typ . max. unit remarks high level input voltage vih 0. 8 ? vdd 1 v note 1) low level input voltage v i l 0.2 ? vdd 1 v note 1) high level input current 1 iih1 vi h = vdd 1 = 5.25 v - 1 1 ? a note 1 ) high level input current 2 iih2 vih = vdd 2 = 5.25 v 27 5 3 106 ? a note 2 ) low level input current iil vil = 0v, vdd 1 = 5.25 v - 1 1 ? a note 1) high level output voltage voh ioh = - 500 ? a vdd 1 - 0.4 v note 3 ) low level output voltage vol iol = 500 ? a 0.4 v note 3 ) note1 applied to the [clk], [data], [le], and [pdn] pins note 2 applied to the [ test1 ] and [ test2 ] pins note 3 applied to the [ld] pin
[ak 1572 ] m s 1551 - e - 0 0 8 2013/ /8 2. serial interface timing fig.3 serial interface timing serial interface timing parameter symbol min. typ. max. unit remarks clock l level hold time tcl 25 ns clock h level hold time tch 25 ns clock setup time tcsu 10 ns data setup time tsu 10 ns data hold time thd 10 ns le s etup t ime tlesu 10 ns le p ulse w idth tle 25 ns le (input) clk (input) data (input) tsu thd tcsu d 19 d 18 6 d 0 a0 a1 a2 a3 tch tcl tlesu tle
[ak 1572 ] m s 1551 - e - 0 0 9 2013/ /8 3. analog circuit characteristics vdd1=2. 7 ~ 5 .25v, vdd2=4.75 5.25v , vdd3=2.7 ~ 3.6v or 4.75 ~ 5.25v , - 40 ta 85 , cpbias=27kohm, mixbias=33kohm, if output frequency =200mhz , internal vco using unless otherwise specified . item min . typ . max . unit remark rf frequency range 690 4000 mhz if frequency range 20 500 mhz internal lo frequency range 2 62.5 4400 mhz lo input level - 5 0 +5 dbm {mode}=2,differential input or {mode}=3 lo input level 2 - 5 + 1 dbm {mode}=2 , single input lo output level @1ghz 6 dbm {lolv}=3 3 dbm {lolv}=2 0 dbm {lolv}=1 - 6 dbm {lolv}=0 mixer mixer input impedance 50 k?
[ak 1572 ] m s 1551 - e - 0 0 10 2013/ /8 item min . typ . max . unit remark refin characteristics input sensitivity 0.4 2 vpp input frequency 10 300 mhz phase frequency detector pfd frequency 1.2 40 mhz charge pump cp maximum current 2400 a cp minimum current 300 a icp tri - state leak current 1 na ta=25 c cp output range 0.5 vdd3 - 0.5 v cp current adjusting resistance 22 27 33 k? connect to [ cp bias ] pin normalized phase noise - 21 8 dbc/hz vco operating frequency range 2 1 00 30 00 mhz vco1 30 00 3 4 00 mhz vco2 3 4 00 4400 mhz vco3 vco sensitivity fv 0.02 mhz/v fv: oscillation frequency phase noise @2.1ghz 10khz offset - 8 5 dbc/hz 100khz offset - 11 1 dbc/hz 1mhz offset - 13 2 dbc/hz 10mhz offset - 152 dbc/hz item min . typ . max . unit remark current consumption idd1 1 2 ma [ pdn ] = l idd2 140 20 0 ma [ pdn ] = h ,{mixen}=1, {mode}=0,{div}=0 idd3 150 21 0 ma [ pdn ] = h ,{mixen}=1, {mode}=0,{div} 2 idd4 1 90 270 ma [ pdn ] = h ,{mixen}=1, {mode}=1,{div} 2
[ak 1572 ] m s 1551 - e - 0 0 11 2013/ /8 9. block functional descriptions ? operation mode AK1572 operation is controlled as follows by the [pdn] pin and register s . function pin register s operating state [ pdn ] {mixen} mode[1] mode[2] mixer synthesizer vco local out standby1 standby1:stand - by mode. current consumption is minimized. it is available to write to the registers. func1 : vco and synthesizer are active and local signal output s from [lop] and [ l o n ] pin s . func2 : only synthesizer is active. pll operation is available with the external vco. stand b y2 : stand - by mode . current consumption is minimized. it is available to write to the register s . func3 : vco, synthesizer and mixer are active. func4 : vco, synthesizer and mixer are active and local signal output s from [lop] and [ l o n ] pin s . func5 : synthesizer and mixer are active. pll operation is available with the external vco. func6 : only mixer is active. a local signal needs to be input from [lop] and [ l o n ] pin s .
[ak 1572 ] m s 1551 - e - 0 0 12 2013/ /8 10. loop filter /charge pump fig. 4 loop filter schematic c2 phase detector up down timer vco loop filter c1 c3 r2 r3 cp
[ak 1572 ] m s1551 - e - 00 13 2013/8 11. register map name data address freq1 d19 - d0 0 0 0 1 freq2 0 0 1 0 freq3 0 0 1 1 function 0 1 0 0 name d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address freq1 0 0 0 vco [1] vco [0] div [1] div [0] 0 int [11] int [10] int [9] int [8] int [7] int [6] int [5] int [4] int [3] int [2] int [1] int [0] 0x01 freq2 0 cp1 [2] cp1 [1] cp1 [0] 0 cp2 [2] cp2 [1] cp2 [0] frac [11] frac [10] frac [9] frac [8] frac [7] frac [6] frac [5] frac [4] frac [3] frac [2] frac [1] frac [0] 0x02 freq3 r [7] r [6] r [5] r [4] r [3] r [2] r [1] r [0] mod [11] mod [10] mod [9] mod [8] mod [7] mod [6] mod [5] mod [4] mod [3] mod [2] mod [1] mod [0] 0x03 function caltm [3] caltm [2] caltm [1] caltm [0] 0 ldcnt sel ld mtld fast en fast [3] fast [2] fast [1] fast [0] cp hiz dsm on mix en mode [1] mode [0] lolv [1] lolv [0] 0x04
[AK1572] ms1551 - e - 0 0 14 2013/8 notes for writing into registers 1) the setting of and

is reflected to each circ uit when writing to . 2) < address 0x04 > behavior is reflected by itself . when AK1572 powers on , the i nitial register s value is not defined. it is required to write the data in all addresses in order to commit it.
[AK1572] ms1551 - e - 0 0 15 2013/8 < address0x01: freq1 > d [ 16:15] vco[1:0] : select vco in accordance with the use d frequency , select the vco . vco[1:0] vco oscillating range dec frequency 0 2 .1 ghz ~ 3.0 ghz 1 3.0 ghz ~ 3. 4 ghz 2 3. 4 ghz ~ .4ghz 3 prohibit ed d [ 14:13] div[1:0] : lodivi d er in accordance with the use d frequency, select the division number . div[1:0] lodivider dec divide number 0 no divide 1 2 divide 2 4 divide 3 8 divide d [11:0] int[11:0] : ndivide r n divider divided number . the allowed range is 35 to 4091 .
[AK1572] ms1551 - e - 0 0 16 2013/8 < address0x02:freq2 > d [ 18: 16] cp1[2:0] set the charge pump current for normal status d [ 14 : 12 ] cp2 [2:0] set the charge pump current for fast lock cp1 is the charge pump current setting of the normal mode . cp2 is the charge pump current setting of the fast lock mode charge pump current is determined by the following formula. charge pump current [a] = icp_min [a] (cp1 or cp2 setting value+1) icp_min [a] = 8.1 / r [ohm] r: the resistance value which is connected to [ cp bias] pin charge pump current (typ) unit : a cp1[2:0] r cp2[2:0] 33k 245 300 368 1 491 600 736 2 736 900 1105 3 982 1200 1473 4 1227 1500 1841 5 1473 1800 2209 6 1718 2100 2577 7 1964 2400 2945 d [ 11:0] frac[11:0] set the numerator of fractional divider . the allowed range is from 0 to ( mod[ 11:0] - 1 ) .
[AK1572] ms1551 - e - 0 0 17 2013/8 < address0x03:freq3 > d[19 ? ? ? ? ? ? set the denominator of fractional divider . the allowed range is from 2 to 4095 .
[AK1572] ms1551 - e - 0 0 18 2013/8 < address0x04: function > d[19 the register { caltm [ 3:0]} determines the calibration precision and time for vco . when { caltm [ 3:0]} is larger, the calibration precision increases, but the required time becomes long as trade - off. the value calculated by the following formula is recommended to get enough calibration precision. however, { caltm [ 3:0]} should be set between from 1 to 11. 0 and o ver 1 1 is prohibited . {caltm[3:0]} R log 2 (f pfd /2 0000) f pfd : pfd frequency the calibration time can be estimated as following calculation; calibration time = 1 /f pfd { ( 6 + 2^{caltm[3:0]} ) 8 + 3} d [ 14] ldcntsel: lock detect precision set the counter value for digital lock detect. ldcntsel function 0 15 times count unlocked to locked 3 times count locked to unlocked 1 31 times count unlocked to locked 7 times count locked to unlocked d [ 13] ld: lock detect function set the lock detect function . 0 : digital l ock detect 1: analog lock detect d [ 12] mtld: local signal mute 0: dont mute local signal in unlock state . 1: mute local signal in unlock state . please use {mtld} =0 at the time of { ld}=1.
[AK1572] ms1551 - e - 0 0 19 2013/8 d [ 11] fasten : fast lock mode setting e nable / disable fast lock mode . 0: disable fast lock mode 1: enable fast lock mode please refer to "1 4 . fast lock mode" for details. d[10 : 7] fast [ 3:0 ] : f ast lock timer setting set the count number of fast lock timer . count number = 511 + fast[3:0] 512 timer[3:0] count number 0 511 1 1023 2 1535 3 2047 4 2559 5 3071 6 3583 7 4095 8 4607 9 5119 10 5631 11 6143 12 6655 13 7167 14 7679 15 8191 d [ 6] cphiz: charge pump tri - state set the charge pump output in tri - state . 0: normal 1: tri - state
[AK1572] ms1551 - e - 0 0 20 2013/8 d [ 5] dsmon : ? - modulator activation in integer - n setting s et t he ? - modulator to active . 0: ? - modulator inactive 1: ? - modulator active d [ 4] mixen: mixer enable 0: stand - by 1: enable
[AK1572] ms1551 - e - 0 0 21 2013/8 d [ 3:2] mode [ 1:0 ]: local operation mode set the operation of synthesizer, vco and lop/lon pin s. mode[1:0] local operating mode 0 internal synthesizer and vco are active. 1 internal synthesizer and vco are active and the local signal outputs from lop/lon pin s. 2 the mode operating external vco with internal synthesizer . 3 the mode using an external local signal . d [ 1:0] lolv [ 1:0 ]: local output p ower at the state of { mode [ 1:0] } = 1 , set the power of the local signal output from lop/lon pin s. lolv[1:0] lop, lon output power [dbm] 0 - 6 1 0 2 3 3 6
[AK1572] ms1551 - e - 0 0 22 2013/8 12. lock detect lock detect output can be selected by {ld} in d [ 13] of

. when {ld} is set to 1 , t he [ ld ] pin outputs a phase comparison result which is from phase detector directly . (this is called analog lock detect .) when {ld} is set to 0, the output is the lock detect signal according to the on - chip logic. (this is called digital lock detect .) the digital lock detect can be done as following : the [ ld ] pin is in unlocked state (which outputs l ) when a frequency setup is made. in the digital lock detect, the [ ld ] pin outputs h (which means the locked state) when a phase error smaller than a cycle of [ refin ] clock (t) is detected for n times consecutively. when a phase error larger than t is detected for n times consecutively w hile the [ ld ] pin outputs h , then the [ ld ] pin outputs l (which means the unlocked state). the counter value n can be set by {ldcntsel} in d [ 14] of . the n is different between unlocked to lock ed and locked to unlocked. {ldcntsel} unlocked to locked locked to unlocked 0 n=15 n=3 1 n=31 n=7 the lock detect signal is shown below case of r = 1 reference clock this is ignored because it cannot be sampled. valid phase comparison signal divided vco signal phase detector output signal valid ignore ld output t he [ ld ] pin outputs high w hen a phase error which is smaller than t /2 is detected for n times consecutively. ignore ignore d t/2
[AK1572] ms1551 - e - 0 0 23 2013/8 case of r > 1 fig6. . digital lock detect operations reference clock this is ignored because it cannot be sampled. valid phase com parison si g nal divide d signal of rf signal pfd output signal this is ignored because it cannot be sampled. valid ignore ld output t he [ ld ] pin outputs will be high w hen a phase error which is smaller than t is detected for n times consecutively. t phase error < t flag=flag+1 lock(ld=high) unlock(ld=low) yes no flag>n flag=0 yes no u nlock ?
[AK1572] ms1551 - e - 0 0 24 2013/8 phase error > t yes flag=0 flag=flag+1 flag>n no yes unlock(ld=low) no lock ? lock(ld=high)
[AK1572] ms1551 - e - 0 0 25 2013/8 13. frequency setup the following formula is used to calculate the frequency setting for the AK1572 . frequency setting ref frequency (int+frac/mod) ref frequency pfd fequency int integer divide number ( refer to int[11:0] ) frac numenator setting number ( refer to frac[11:0] ) mod denominator setting number ( refer to mod[11:0] ) set in the range of 35 to 4091 for int[ 11:0] . set in the range of 0 to (mod - 1) for frac[ 11:0] set in the range of 2 to 409 5 for mod[ 11:0] example to complete ref frequency=19.2mhz , frequency setting =2460.1mhz , set as follows int = 128 frac = 25 mod = 192 frequency setting = 19.2mhz (128 + (25 / 192 ) ) = 2460 .1 mhz by writing

, frequency is set. when is written , the setting of

and is reflected in the internal circuit. at the time of the writing of , it is necessary for a synthesizer block to be power ed on. the writing of < address 0x01 > as a trigger, f requency setting and vco calibration are carried out, and f ast lock counter starts operat ion . to set frequency definitely, should be written in the state that { mode [1:0] } in is 0 or 1 or 2 and [ pdn ] pin is h .
[AK1572] ms1551 - e - 0 0 26 2013/8 14. fast lock mode the fast lock mode becomes ef fective when set {fasten} of to 1 . fast lock mode when writing in

with {fasten} =1 , fast lock up mode starts after calibration. the fast lock up mode is valid only during the time period set by the timer according to the counter value in { fast [ 3:0]} in

, and t he charge pump current is set to the value specified by { cp2 }. w hen the specified time period elapses , t he fast lock up mode operation is switched to the normal operation , and the charge pump current returns to {cp1} setting fig.7. fast lock up mode timing chart timer period { fast [ 3 :0] } in < address 0x04 > is used to set the time period for this mode. the following formula is used to calculate the time period counter value = 511 fast[3:0] 512 fast lock up cp2 normal normal cp1 cp1 operation mode charge pump current frequency setting write in

fast lock up time specified by the timer calibration hi - z
[AK1572] ms1551 - e - 0 0 27 2013/8 15. vco calibr ation AK1572 has three vco core in uses several overlapping bands to allow low phase noise, low vco sensitivity (k vco ) and wide frequency range. the selection which vco should be used can be done by the register { vco[1:0] } in . moreover, t he correct band is chosen automatically at frequency setting , which is called calibration . the calibration starts when

are written in the condition that { mode[1] } in = 0 and [pdn ] pin= h . during the calibration, v tune of vco is disconnected from the output of the loop filter and connected to an internal reference voltage. the charge pump output is disabled. the internal bias must be stable so that the calibration is done correctly. therefore, it is necessary to wait 500 ? sec at least until < address0x01> writing after [pdn] rises up. the register { caltm [ 3:0]} determines the calibration time. when { caltm [ 3:0]} is larger, the calibration precision increases, but the required time becomes long as a trade - off . the value calculat ed by the following formula is recommended to get enough calibration precision. however, { caltm [ 3:0]} should be set at from 1 to 11 . 0 and over 1 1 is prohibited. {caltm[3:0]} log 2 (f pfd / 2 0000) f pfd : pfd frequency the calibration time can be estimated as following calculation; calibration time = 1 /f pfd { ( 6 + 2 ^ {caltm [ 3:0]} ) 8 + 3}
[AK1572] ms1551 - e - 0 0 28 2013/8 16. power up sequence 1) set [ pdn ] pin to l and turn on power suppl ie s (vdd1/vdd2/vdd3) 2) the stabilization time for [ vref1 ] (ldo) is 10msec. a fter ldo is stabilize d , write the data to the registers of < address 0x01, 0x02, 0x03, 0x04> 3) set [ pdn ] pin to h . in this state, the internal circuits are in an op erating state, b ut pl l/synth is unstable yet . 4) the stabilization time of internal bias circuits is 500usec. after bias circuit is stabilize d , write the data to . vco calibration start s and pll status will be l ock ed. refer to 14. fast lock mode and 15. vco contents regarding fast lock mode and vco calibration. note1) the initial register values are not defined. therefore, it is required to write the data in all addresses of the register. note2) the stabilization time for ldo is required more than 10ms. min. 10msec min. 500usec 2) 4) pdn pin vdd1, vdd2, vdd3 vref1(ldo) register writing pll/synth unstable vco calibration fast lock lock mixer prohibit 3) power down active 1) power down active
[AK1572] ms1551 - e - 0 0 29 2013/8 17. typical evaluation board schematic 1. evaluation board schematic and t he list of external parts fig.9. typical evaluation board schematic ref. value ref. value ref. value ref. value ref. value c1 100pf c10 2.7nf c19 10nf c28 loop filter l2 matching c2 220nf c11 100pf c20 100pf c29 loop filter l3 matching c3 10nf c12 matching c21 100pf c30 loop filter l4 matching c4 100pf c13 matching c22 10nf c31 100pf l5 matching c5 matching c14 matching c23 100pf c32 10nf r1 33k ? c6 matching c15 matching c24 10nf c33 10nf r2 27k ? c7 10nf c16 matching c25 470nf c34 100pf r3 loop filter c8 100pf c17 matching c26 100pf c35 100pf r4 loop filter c9 10nf c18 matching c27 10nf l1 matching note 1 ) exposed pad at the center of the backside is should be connected to ground. note 2 ) [test1] and [test2] pins should be connected to ground.
[AK1572] ms1551 - e - 0 0 30 2013/8 2. external circuit to input the external local signal to [ lop ] and [ lon ] pins. fig 7 circuit for local input ref value c 36 100pf c 37 10 0nf 3 . external circuit to output the internal local signal from [ lop ] and [ lon ] pins fig 8 circuit for local output example of the external components for this mode ref value c38 100pf c39 100pf l7 180nh l8 180nh r5 50
[AK1572] ms1551 - e - 0 0 31 2013/8 18. interface circuit pin no. name i/o r0( ? ) (typ.) cur( ? a) function 11 pdn di 300 digital input pin 12 le di 300 13 clk di 300 14 data di 300 30 test1 di 300 digital input pin pull - down 31 test2 di 300 15 ld do digital output pin 21 vcnt i 100 analog input pin 32 refin i 300 r0 r0 100k (typ.) r0
[AK1572] ms1551 - e - 0 0 32 2013/8 pin no. name i/o r0( ? ) (typ.) cur( ? a) function 1 vref1 ao 300 analog input/output pin 4 mixbias ao 300 22 vref2 ai 300 25 cpbias ai 300 23 cp o analog output pin 9 mixoutn o rf open collector output pin 10 mixoutp o 17 lop io rf open collector input/output pin 18 lon io 5 mixinn io rf input pin 6 mixinp io r0
[AK1572] ms1551 - e - 0 0 33 2013/8 19. outer dimensions qfn32 - 5x5 - 0.50 note) t he exposed pad at the center of the backside should be connected to ground. 5 . 0 0 5 . 0 0 0 . 1 0 0 . 1 0 0 . 4 0 0 . 1 0 3 . 1 0 0 . 1 0 3 . 1 0 0 . 1 0 0 . 0 5 0 . 8 5 0 . 0 5 m a x b 0 . 2 5 m 0 . 1 0 0 . 0 5 1 8 9 1 6 1 7 2 4 2 5 3 2 c a b c 0 . 3 5 0 . 5 0 r e f 0 . 0 8 c a c ( 0 . 2 0 )
[AK1572] ms1551 - e - 0 0 34 2013/8 20. marking (a) style : qfn (b) number of pins : 32 (c) 1 pin marking: : (d) product number : 15 72 (e) date code : ywwl (4 digits) y : lower 1 digit of calendar year (year 201 3 3 , 201 4 4 ...) ww : week l : lot identification, given to each product lot which is made in a week ? lot id is given in alphabetical order (a, b, c). 1572 (d) ywwl (e) (c)
[AK1572] ms1551 - e - 01 35 2013/8 important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in this document ( product ) , please make inquiries the sales office of akm or authorized distributor s as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm p roducts . akm neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the informatio n in this document. you are fully responsible for use of such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information i n your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for the above u se unless specifically agreed by akm in writing . 3. though akm works continually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise mak e available the product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. pleas e contact akm sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substan ces, including without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different from the statement and/ or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm .

▲Up To Search▲

Price & Availability of AK1572

	To Download AK1572 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .