View NT512D72S8PB0G_7728146.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) 512mb, 256mb and 128mb pc3200, pc2700 and pc2100 unbuffered ddr dimm rev 2.2 1 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. 184 pin unbuffered ddr dimm based on ddr400/333/266 256m bit b die device features ? 184 dual in-line memory module (dimm) unbuffered ddr dimm based on 256m bit die b device, organized as either 32mbx8 or 16mbx16 performance: pc3200 pc2700 pc2100 speed sort 5t 6k 75b dimm cas latency 3 2.5 2.5 unit f ck clock frequency 200 166 133 mhz t ck clock cycle 5 6 7.5 ns f dq dq burst frequency 400 333 266 mhz intended for 133, 166 and 200 mhz applications inputs and outputs are sstl-2 compatible v dd = v ddq = 2.5v 0.2v (2.6v 0.1v for pc3200) sdrams have 4 internal banks for concurrent operation differential clock inputs data is read or written on both clock edges dram dll aligns dq and dqs trans itions with clock transitions address and control signals are fully synchronous to positive clock edge programmable operation: - dimm cas latency: 2, 2.5, 3 - burst type: sequential or interleave - burst length: 2, 4, 8 - operation: burst read and write auto refresh (cbr) and self refresh modes automatic and controlled precharge commands 7.8 s max. average periodic refresh interval serial presence detect eeprom gold contacts sdrams are packaged in tsop packages ?green? packaging ? lead free description nt512d64s8hb0g, nt512d64s8hb1g, nt512d64s8hb1gy, NT512D72S8PB0G, nt256d64sh88b0g, nt256d64sh88b1g, nt256d64sh88b1gy, nt256d72s89b0g and nt128d64sh4b1g are unbuffe red 184-pin double data rate (ddr) synchronous dram dual in-line memory modules (dimm). nt512d64s8hb1gy and nt256d64sh88b1gy are packaged us ing lead free technology. nt512d64s8hb0g, nt512d64s8hb1g and nt512d64s8hb1gy are 512mb modules organized as dual ranks using sixteen 32mx8 tsop devices. NT512D72S8PB0G has ecc and is organized as dual ranks using eighteen 32mx8 tsop devices. nt256d64sh88b0g, nt256d64sh88b1g and nt256d64sh88b1gy are 256mb modules organi zed as single rank using eight 32mx8 tsop devices. nt256d72s89b0g has ecc and is organized as single rank using nine 32mx8 tsop dev ices. nt128d64sh4b1g are 128mb modules, organized as single rank usi ng four 16mx16 tsop devices. depending on the speed grade, these dimms are intended for use in app lications operating up to 200 mhz clock speeds and achieve s high-speed data transfer rates of up to 400 mhz. prior to any access operation, the device cas latency and burst type/ length/operation type must be programmed into the dimm by address inputs and i/o inputs ba0 and ba1 using the mode register set cycle. the dimm uses a serial eeprom and through the use of a standard iic protocol the serial presenc e-detect implementation (spd) ca n be accessed. the first 128 bytes of the spd data are programme d with the module characteristics as defined by jedec.
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 2 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ordering information part number organization speed power leads NT512D72S8PB0G-5t 64mx72 nt512d64s8hb1g-5t nt512d64s8hb1gy-5t (lead free) 64mx64 nt256d72s890g-5t 32mx72 nt256d64s88b1g-5t nt256d64s88b1gy-5t (lead free) 32mx64 nt128d64sh4b1g-5t 16mx64 ddr400 pc3200 3-3-3 200mhz (5ns @ cl = 3) 166mhz (6ns @ cl = 2.5) 2.6v nt512d64s8hb1g-6k nt512d64s8hb1gy-6k (lead free) 64mx64 nt256d64s88b1gy-6k (lead free) nt256d64s88b0g-6k 32mx64 nt128d64sh4b1g-6k 16mx64 ddr333 pc2700 2.5-3-3 166mhz (6ns @ cl = 2.5) 133mhz (7.5ns @ cl = 2) nt512d64s8hb0g-75b 64mx64 nt256d64s88b0g-75b 32mx64 nt128d64sh4b1g-75b 16mx64 ddr266b pc2100 2.5-3-3 133mhz (7.5ns @ cl = 2.5) 100mhz (10ns @ cl = 2) 2.5v gold for the closest sales office or information, please visit: www.nanya.com nanya technology corporation hwa ya technology park 669 fu hsing 3rd rd., kueishan, taoyuan, 333, taiwan, r.o.c. tel: +886-3-328-1688
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 3 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. pin description ck0, ck1, ck2, ck0 , ck1 , ck2 differential clock inputs. dq0-dq63 data input/output cke0, cke1 clock enable dqs0-dqs7 bidirectional data strobes ras row address strobe dm0-dm7 input data mask cas column address strobe v dd power we write enable v ddq supply voltage for dqs s0 , s1 chip selects v ss ground a0-a9, a11, a12 address inputs nc no connect a10/ap address input/auto-precharge scl serial presence detect clock input ba0, ba1 sdram bank address inputs sda serial presence detect data input/output v ref ref. voltage for sstl_2 inputs sa0-2 serial presence detect address inputs v ddid v dd identification flag. v ddspd serial eeprom positive power supply pinout pin front pin back pin front pin back pin front pin back 1 v ref 93 v ss 32 a5 124 v ss 62 v ddq 154 ras 2 dq0 94 dq4 33 dq24 125 a6 63 we 155 dq45 3 v ss 95 dq5 34 v ss 126 dq28 64 dq41 156 v ddq 4 dq1 96 v ddq 35 dq25 127 dq29 65 cas 157 s0 5 dqs0 97 dm0/dqs9 36 dqs3 128 v ddq 66 v ss 158 s1 6 dq2 98 dq6 37 a4 129 dm3/dqs12 67 dqs5 159 dm5/dqs14 7 v dd 99 dq7 38 v dd 130 a3 68 dq42 160 v ss 8 dq3 100 v ss 39 dq26 131 dq30 69 dq43 161 dq46 9 nc 101 nc 40 dq27 132 v ss 70 v dd 162 dq47 10 nc 102 nc 41 a2 133 dq31 71 nc 163 nc 11 v ss 103 nc 42 v ss 134 nc 72 dq48 164 v ddq 12 dq8 104 v ddq 43 a1 135 nc 73 dq49 165 dq52 13 dq9 105 dq12 44 nc 136 v ddq 74 v ss 166 dq53 14 dqs1 106 dq13 45 nc 137 ck0 75 ck2 167 nc 15 v ddq 107 dm1/dqs10 46 v dd 138 ck0 76 ck2 168 v dd 16 ck1 108 v dd 47 nc 139 v ss 77 v ddq 169 dm6/dqs15 17 ck1 109 dq14 48 a0 140 nc 78 dqs6 170 dq54 18 v ss 110 dq15 49 nc 141 a10 79 dq50 171 dq55 19 dq10 111 cke1 50 v ss 142 nc 80 dq51 172 v ddq 20 dq11 112 v ddq 51 nc 143 v ddq 81 v ss 173 nc 21 cke0 113 nc 52 ba1 144 nc 82 v ddid 174 dq60 22 v ddq 114 dq20 key key 83 dq56 175 dq61 23 dq16 115 a12 53 dq32 145 v ss 84 dq57 176 v ss 24 dq17 116 v ss 54 v ddq 146 dq36 85 v dd 177 dm7/dqs16 25 dqs2 117 dq21 55 dq33 147 dq37 86 dqs7 178 dq62 26 v ss 118 a11 56 dqs4 148 v dd 87 dq58 179 dq63 27 a9 119 dm2/dqs11 57 dq34 149 dm4/dqs13 88 dq59 180 v ddq 28 dq18 120 v dd 58 v ss 150 dq38 89 v ss 181 sa0 29 a7 121 dq22 59 ba0 151 dq39 90 wp 182 sa1 30 v ddq 122 a8 60 dq35 152 v ss 91 sda 183 sa2 31 dq19 123 dq23 61 dq40 153 dq44 92 scl 184 v ddspd note: all pin assignments are consistent for all 8-byte unbuffered versions.
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 4 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. input/output functional description symbol type polarity function ck0, ck1, ck2, ck0 , ck1 , ck2 (sstl) cross point the system clock inputs. all address and comm and lines are sampled on the cross point of the rising edge of ck and falling edge of ck. a delay locked loop (dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. cke0, cke1 (sstl) active high activates the ddr sdram ck signal when hi gh and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s0 , s1 (sstl) active low enables the associated ddr sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operati ons continue. physical bank 0 is selected by s 0; bank 1 is selected by s1. ras , cas , we (sstl) active low when sampled at the positive rising edge of the clock, ras , cas , we define the operation to be executed by the sdram. v ref supply reference voltage for sstl-2 inputs v ddq supply isolated pow er supply for the ddr sdram output buffers to provide improved noise immunity ba0, ba1 (sstl) - selects which sdram bank is to be active. a0 - a9 a10/ap a11, a12 (sstl) - during a bank activate command cycle, a0-a 12 defines the row address (ra0-ra12) whe n sampled at the rising clock edge. during a read or write command cycle, a0-a9 defines the column address (ca0-ca9 ) when sampled at the rising clock edge. in additi on to the column address, ap is used to invoke auto-precharge operation at the end of the b urst read or write cycle. if ap is high, auto- precharge is selected and ba0/ba1 defines t he bank to be precharged. if ap is low, auto-precharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0/ba1 to control which bank(s) t o precharge. if ap is high all 4 ban ks will be precharged regardless of the state of ba0/ba1. if ap is low, then ba0/ba1 are used to define which bank to pre-charge. dq0 - dq63 (sstl) - data and check bit input/output pins operate in the same manner as on conventional drams. dqs0 - dqs7, dqs9 ? dqs16 (sstl) active high data strobes: output with read data, input with write data. edge aligned with read data, centered on write data. used to capture write data. cb0 ? cb7 (sstl) - data check bit input/output pins. used on ecc modules and is not used on x64 modules. dm0 ? dm8 input active high the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write op eration if it is high. in read mode, dm lines have no effect. dm 8 is associated with check bits cb0- cb7, and is not used on x64 modules. v dd , v ss supply power and ground for the ddr sdram input buffers and core logic sa0 ? sa2 - address inputs. connected to either v dd or v ss on the system board to configure the serial presence detect eeprom address. sda - this bi- directional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v dd to act as a pull-up. scl - this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to v dd to act as a pull-up. v ddspd supply serial eeprom positive power supply.
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 5 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram 2 ranks, 16 devices, 32mx8 ddr sdrams serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 a0-a13 ras ba0-ba1 ba0-ba1 : sdrams d0-d15 a0-a13 : sdrams d0-d15 ras : sdrams d0-d15 cke0 we cas cas : sdrams d0-d15 cke : sdrams d0-d7 cke : sdrams d8-d15 we : sdrams d0-d15 cke1 v ddspd v ss v ref v ddid v dd /v ddq strap: see note 4 spd d0-d15 d0-d15 d0-d15 * wire per clock loading table/ wiring diagrams * clock wiring clock input sdrams *ck0/ ck0 *ck1/ ck1 *ck2/ ck2 4 sdrams 6 sdrams 6 sdrams notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd is not equal to v ddq . s0 dm0/dqs9 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq8 dq9 dq10 dq15 dq12 dq14 dq13 dq11 dq16 dq17 dq18 dq23 dq20 dq22 dq21 dq19 dq24 dq25 dq26 dq31 dq28 dq30 dq29 dq27 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d3 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d2 dqs0 dm4/dqs13 dqs4 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d0 dm1/dqs10 dqs1 dqs dm2/dqs11 dqs2 dm3/dqs12 dqs3 dqs dq32 dq33 dq34 dq39 dq36 dq38 dq37 dq35 dq40 dq41 dq42 dq47 dq44 dq46 dq45 dq43 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d1 dqs dqs5 dm5/dqs14 dq48 dq49 dq50 dq55 dq52 dq54 dq53 dq51 dq56 dq57 dq58 dq63 dq60 dq62 dq61 dq59 dqs6 dm6/dqs15 dqs7 dm7/dqs16 dqs s1 i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d8 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d9 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d10 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d11 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d7 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d6 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d4 dqs dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d5 dqs dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d12 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d13 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d14 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d15 dqs
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 6 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram 1 rank, 8 devices, 32mx8 ddr sdrams serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 a0-a13 ras ba0-ba1 ba0-ba1 : sdrams d0-d7 a0-a13 : sdrams d0-d7 ras : sdrams d0-d7 cke0 cas cas : sdrams d0-d7 cke : sdrams d0-d7 we we : sdrams d0-d7 v ddspd v ss v ref v ddid v dd /v ddq strap: see note 4 spd d0-d7 d0-d7 d0-d7 * wire per clock loading table/ wiring diagrams * clock wiring clock input sdrams *ck0/ ck0 *ck1/ ck1 *ck2/ ck2 2 sdrams 3 sdrams 3 sdrams notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd is not equal to v ddq . s0 dm0/dqs9 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq8 dq9 dq10 dq15 dq12 dq14 dq13 dq11 dq16 dq17 dq18 dq23 dq20 dq22 dq21 dq19 dq24 dq25 dq26 dq31 dq28 dq30 dq29 dq27 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d3 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d2 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d4 dqs0 dm4/dqs13 dqs4 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d0 dqs dm1/dqs10 dqs1 dqs dm2/dqs11 dqs2 dm3/dqs12 dqs3 dqs dq32 dq33 dq34 dq39 dq36 dq38 dq37 dq35 dq40 dq41 dq42 dq47 dq44 dq46 dq45 dq43 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d1 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d5 dqs dqs5 dm5/dqs14 dq48 dq49 dq50 dq55 dq52 dq54 dq53 dq51 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d6 dqs dq56 dq57 dq58 dq63 dq60 dq62 dq61 dq59 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d7 dqs dqs6 dm6/dqs15 dqs7 dm7/dqs16
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 7 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram 1 rank, 4 devices, 16mx16 ddr sdrams serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 a0-a13 ras ba0-ba1 ba0-ba1 : sdrams d0-d3 a0-a13 : sdrams d0-d3 ras : sdrams d0-d3 cke0 cas cas : sdrams d0-d3 cke : sdrams d0-d3 we we : sdrams d0-d3 v ddspd v ss v ref v ddid v dd /v ddq strap: see note 4 spd d0-d3 d0-d3 d0-d3 * wire per clock loading table/ wiring diagrams * clock wiring clock input sdrams *ck0/ ck0 *ck1/ ck1 *ck2/ ck2 nc 2 sdrams 2 sdrams s0 dm1/dqs10 dq8 dq9 dq10 dq15 dq12 dq14 dq13 dq11 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq24 dq25 dq26 dq31 dq28 dq30 dq29 dq27 dq16 dq17 dq18 dq23 dq20 dq22 dq21 dq19 dqs1 dm5/dqs14 dqs5 dm0/dqs9 dqs0 dm3/dqs12 dqs3 dm2/dqs11 dqs2 dq40 dq41 dq42 dq47 dq44 dq46 dq45 dq43 dq32 dq33 dq34 dq39 dq36 dq38 dq37 dq35 dqs4 dm4/dqs13 dq56 dq57 dq58 dq63 dq60 dq62 dq61 dq59 dq48 dq49 dq50 dq55 dq52 dq54 dq53 dq51 dqs7 dm7/dqs16 dqs6 dm6/dqs15 i/o 6 i/o 4 i/o 5 i/o 0 i/o 2 i/o 3 i/o 1 i/o 7 ldm cs d0 i/o 8 i/o 10 i/o 11 i/o 14 i/o 12 i/o 13 i/o 15 i/o 9 udm udqs ldqs i/o 6 i/o 4 i/o 5 i/o 0 i/o 2 i/o 3 i/o 1 i/o 7 ldm cs d2 i/o 8 i/o 10 i/o 11 i/o 14 i/o 12 i/o 13 i/o 15 i/o 9 udm udqs ldqs i/o 6 i/o 4 i/o 5 i/o 0 i/o 2 i/o 3 i/o 1 i/o 7 ldm cs d3 i/o 8 i/o 10 i/o 11 i/o 14 i/o 12 i/o 13 i/o 15 i/o 9 udm udqs ldqs i/o 6 i/o 4 i/o 5 i/o 0 i/o 2 i/o 3 i/o 1 i/o 7 ldm cs d1 i/o 8 i/o 10 i/o 11 i/o 14 i/o 12 i/o 13 i/o 15 i/o 9 udm udqs ldqs notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd is not equal to v ddq .
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 8 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram 2 ranks, 18 devices (ecc), 32mx8 ddr sdrams serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 3. dq/dqs/dm/dqs resistors are 22 ohms. notes : 1. dq-to-i/o wring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships are maintained as shown. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd is not equal to v ddq . v ddspd v ss v ref v ddid v dd /v ddq strap: see note 4 spd d0-d8 d0-d8 d0-d8 a0-a13 ras ba0-ba1 ba0-ba1 : sdrams d0-d17 a0-a13 : sdrams d0-d17 ras : sdrams d0-d17 cke0 we cas cas : sdrams d0-d17 cke : sdrams d0-d8 cke : sdrams d9-d17 we : sdrams d0-d17 cke1 * wire per clock loading table/ wiring diagrams * clock wiring clock input sdrams *ck0/ ck0 *ck1/ ck1 *ck2/ ck2 6 sdrams 6 sdrams 6 sdrams s0 dm0/dqs9 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq8 dq9 dq10 dq15 dq12 dq14 dq13 dq11 dq16 dq17 dq18 dq23 dq20 dq22 dq21 dq19 dq24 dq25 dq26 dq31 dq28 dq30 dq29 dq27 dqs0 dm4/dqs13 dqs4 dm1/dqs10 dqs1 dm2/dqs11 dqs2 dm3/dqs12 dqs3 dq32 dq33 dq34 dq39 dq36 dq38 dq37 dq35 dq40 dq41 dq42 dq47 dq44 dq46 dq45 dq43 dqs5 dm5/dqs14 dq48 dq49 dq50 dq55 dq52 dq54 dq53 dq51 dq56 dq57 dq58 dq63 dq60 dq62 dq61 dq59 dqs6 dm6/dqs15 dqs7 dm7/dqs16 s1 cb0 cb1 cb2 cb7 cb4 cb6 cb5 cb3 dm8/dqs17 dqs8 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d0 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d9 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d1 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d10 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d2 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d11 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d3 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d12 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d8 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d17 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d4 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d13 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d5 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d14 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d6 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d15 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d7 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d16 dqs
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 9 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram 1 rank, 9 devices (ecc), 32mx8 ddr sdrams s0 dm0/dqs9 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq8 dq9 dq10 dq15 dq12 dq14 dq13 dq11 dqs0 dm4/dqs13 dqs4 dm1/dqs10 dqs1 dm2/dqs11 dqs2 dm3/dqs12 dqs3 dq32 dq33 dq34 dq39 dq36 dq38 dq37 dq35 dqs5 dm5/dqs14 dqs6 dm6/dqs15 dqs7 dm7/dqs16 dq16 dq17 dq18 dq23 dq20 dq22 dq21 dq19 dq24 dq25 dq26 dq31 dq28 dq30 dq29 dq27 dq40 dq41 dq42 dq47 dq44 dq46 dq45 dq43 dq48 dq49 dq50 dq55 dq52 dq54 dq53 dq51 dq56 dq57 dq58 dq63 dq60 dq62 dq61 dq59 serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 notes : 1. dq-to-i/o wring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships are maintained as shown. 3. dq/dqs/dm/dqs resistors are 22 ohms. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd is not equal to v ddq . cb0 cb1 cb2 cb7 cb4 cb6 cb5 cb3 dm8/dqs17 dqs8 v ddspd v ss v ref v ddid v dd /v ddq strap: see note 4 spd d0-d8 d0-d8 d0-d8 a0-a13 ras ba0-ba1 ba0-ba1 : sdrams d0-d8 a0-a13 : sdrams d0-d8 ras : sdrams d0-d8 cke0 cas cas : sdrams d0-d8 cke : sdrams d0-d8 we we : sdrams d0-d8 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d0 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d1 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d2 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d3 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d8 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d4 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d5 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d6 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d7 dqs * wire per clock loading table/ wiring diagrams * clock wiring clock input sdrams *ck0/ ck0 *ck1/ ck1 *ck2/ ck2 3 sdrams 3 sdrams 3 sdrams
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 10 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. serial presence detect spd description byte description byte description 0 number of serial pd bytes written during production 26 maximum data access time from clock at cl=1 1 total number of bytes in serial pd device 27 minimum row precharge time (t rp ) 2 fundamental memory type 28 minimum row active to row active delay (t rrd ) 3 number of row addresses on assembly 29 minimum ras to cas delay (t rcd ) 4 number of column addresses on assembly 30 minimum ras pulse width (t ras ) 5 number of dimm rank 31 module bank density 6 data width of assembly 32 address and command setup time before clock 7 data width of assembly (cont?) 33 address and command hold time after clock 8 voltage interface level of this assembly 34 data input setup time before clock 9 ddr sdram device cycle time cl=2.5 35 data input hold time after clock 10 ddr sdram device access time from clock cl=2.5 36-40 reserved 11 dimm configuration type 41 minimum active/auto-refresh time (t rc ) 12 refresh rate/type 42 auto-refresh to active/auto-refresh command period (t rfc ) 13 primary ddr sdram width 43 max cycle time (t ck max ) 14 error checking ddr sdram device width 44 maximum dqs-dq skew time (t dqsq ) 15 ddr sdram device attr: min clk delay, random col access 45 maximum read data hold skew factor (t qhs ) 16 ddr sdram device attributes: burst length supported 46-61 reserved 17 ddr sdram device attributes: number of device banks 62 spd revision 18 ddr sdram device attributes: cas latencies supported 63 checksum data 19 ddr sdram device attributes: cs latenc y 64-71 manufacturer?s jedec id code 20 ddr sdram device attributes: we latency 72 module manufacturing location 21 ddr sdram device attributes: 73-90 module part number 22 ddr sdram device attributes: general 91-92 module revision code 23 minimum clock cycle cl=2.5 93-94 module manufacturing data yy= binary coded decimal ye ar code, 0-99(decimal), 00-63(hex) ww= binary coded decimal y ear code, 01-52(decimal), 01-34(hex) 24 maximum data access time from clock at cl=2 95-98 module serial number 25 minimum clock cycle time at cl=1 99-127 reserved
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 11 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. spd values for nt512d64s8hbxgx pc3200 (5t) pc2700 (6k) pc2100 (75b) byte value hex value hex value hex 0 128 80 128 80 128 80 1 256 08 256 08 256 08 2 sdram ddr 07 sdram ddr 07 sdram ddr 07 3 13 0d 13 0d 13 0d 4 10 0a 10 0a 10 0a 5 2 0 2 2 0 2 2 0 2 6 x64 40 x64 40 x64 40 7 x64 00 x64 00 x64 00 8 sstl 2.5v 04 sstl 2.5v 04 sstl 2.5v 04 9 5 .0ns 5 0 6.0ns 60 7.5ns 75 10 6. 0ns 60 7 .0ns 7 0 7.5ns 75 11 non - parity 00 non - parity 00 non - parity 00 12 sr/1x( 7.8 us) 8 2 sr/1x( 7.8 us) 8 2 sr/1x( 7.8 us) 8 2 13 x8 08 x8 08 x8 08 14 n/a 00 n/a 00 n/a 00 15 1 clock 01 1 clock 01 1 clock 01 16 2,4,8 0e 2,4,8 0e 2,4,8 0e 17 4 04 4 04 4 04 18 2/ 2.5 /3 1 c 2/2.5 0c 2/2.5 0c 19 0 01 0 01 0 01 20 1 02 1 02 1 02 21 differential clock 20 differential clock 20 differential clock 20 22 0. 1 v tolerance 00 0.2v tolerance 00 0.2v tolerance 00 23 6 ns 6 0 7.5ns 75 10 ns a0 24 0. 7 0 ns 7 0 0.7 0 ns 70 0.7 5ns 75 25 7.5 ns 75 n/a 00 n/a 00 26 7.5 ns 75 n/a 00 n/a 00 27 1 5 ns 3c 18 ns 48 20ns 50 28 1 0 ns 28 1 2 ns 30 15ns 3c 29 1 5 ns 3c 18 ns 48 20ns 50 30 4 0 ns 28 4 2 ns 2a 45ns 2d 31 256 mb 4 0 256 mb 4 0 256 mb 4 0 32 0. 6 0ns 60 0. 75 ns 75 0.90ns 90 33 0. 6 0ns 60 0. 75 ns 7 5 0.90ns 90 34 0. 4 0ns 40 0. 4 5ns 45 0.50ns 50 35 0. 4 0ns 40 0. 4 5ns 45 0.50ns 50 36 - 40 reserved 00 reserved 00 reserved 00 41 55 ns 37 60ns 3c 6 5 ns 41 42 7 0 ns 4 6 72ns 48 7 5 ns 4b 43 8 ns 20 12ns 30 12ns 30 44 0.4ns 28 0.4ns 28 0. 5 ns 32 45 0.5 0 ns 50 0.55 ns 55 0. 7 5ns 7 5 46 - 61 reserved 00 reserved 00 reserved 00 62 initial 00 initial 00 initial 00 63 checksum 8f checksum 3c checksum 23 64-71 nanya 7f7f7f0b 00000000 nanya 7f7f7f0b 00000000 nanya 7f7f7f0b 00000000 72 assembly -- assembly -- assembly -- 73 - 90 module pn -- module pn -- module pn -- 91 - 92 revision -- revision -- revision -- 93 - 94 year/week code -- year/week code -- year/week code -- 95 - 98 serial number -- serial number -- serial number -- 99 - 127 reserved -- reserved -- reserved --
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 12 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. spd values for nt256d64s88bxgx pc3200 (5t) pc2700 (6k) pc2100 (75b) byte value hex value hex value hex 0 128 80 128 80 128 80 1 256 08 256 08 256 08 2 sdram ddr 07 sdram ddr 07 sdram ddr 07 3 13 0d 13 0d 13 0d 4 10 0a 10 0a 10 0a 5 1 0 1 1 0 1 1 0 1 6 x 64 40 x64 40 x64 40 7 x64 00 x64 00 x64 00 8 sstl 2.5v 04 sstl 2.5v 04 sstl 2.5v 04 9 5 .0ns 5 0 6.0ns 60 7.5ns 75 10 6.0ns 60 7 .0ns 7 0 7.5ns 75 11 non - parity 00 non - parity 00 non - parity 00 12 sr/1x( 7.8 us) 8 2 sr/1x( 7.8 us) 8 2 sr/1x( 7.8 us) 8 2 13 x8 08 x 8 08 x8 08 14 n/a 00 n/a 00 n/a 00 15 1 clock 01 1 clock 01 1 clock 01 16 2,4,8 0e 2,4,8 0e 2,4,8 0e 17 4 04 4 04 4 04 18 2.5 /3 18 2/2.5 0c 2/2.5 0c 19 0 01 0 01 0 01 20 1 02 1 02 1 02 21 differential clock 20 differential clock 20 differential clo ck 20 22 0. 1 v tolerance 00 0.2v tolerance 00 0.2v tolerance 00 23 5 ns 50 7.5ns 75 10 ns a0 24 0. 6 0 ns 6 0 0.7 0 ns 70 0.75ns 75 25 n/a 00 n/a 00 n/a 00 26 n/a 00 n/a 00 n/a 00 27 1 5 ns 3c 18 ns 48 20ns 50 28 1 0 ns 28 1 2 ns 30 15ns 3c 29 1 5 ns 3c 18 ns 48 2 0ns 50 30 4 0 ns 28 4 2 ns 2a 45ns 2d 31 256 mb 4 0 256 mb 4 0 256 mb 4 0 32 0. 6 0ns 60 0. 75 ns 75 0.90ns 90 33 0. 6 0ns 60 0. 75 ns 75 0.90ns 90 34 0. 4 0ns 40 0. 4 5ns 45 0.50ns 50 35 0. 4 0ns 40 0. 4 5ns 45 0.50ns 50 36 - 40 reserved 00 reserved 00 reserved 00 41 60ns 3c 60ns 3c 60ns 3c 42 72ns 48 72ns 48 72ns 48 43 12ns 30 12ns 30 12ns 30 44 0.4ns 28 0.4ns 28 0.4ns 28 45 0.55ns 55 0.55ns 55 0.55ns 55 46 - 61 reserved 00 reserved 00 reserved 00 62 initial 00 initial 00 initial 00 63 checksum 9c checksum 3b checksum f 0 64-71 nanya 7f7f7f0b 00000000 nanya 7f7f7f0b 00000000 nanya 7f7f7f0b 00000000 72 assembly -- assembly -- assembly -- 73 - 90 module pn -- module pn -- module pn -- 91 - 92 revision -- revision -- revision -- 93 - 94 year/week code -- year/week code -- ye a r/week code -- 95 - 98 serial number -- serial number -- serial number -- 99 - 127 reserved -- reserved -- reserved --
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 13 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. spd values for nt128d64sh4b1g pc3200 (5t) pc2700 (6k) pc2100 (75b) byte value hex value hex value hex 0 128 80 128 80 128 80 1 256 0 8 256 08 256 08 2 sdram ddr 07 sdram ddr 07 sdram ddr 07 3 13 0d 13 0d 13 0d 4 9 09 9 09 9 09 5 1 0 1 1 0 1 1 0 1 6 x64 40 x64 40 x64 40 7 x64 00 x64 00 x64 00 8 sstl 2.5v 04 sstl 2.5v 04 sstl 2.5v 04 9 5 .0ns 5 0 6.0ns 60 7.5ns 75 10 6.0ns 60 7 .0ns 7 0 7.5ns 75 11 non - parity 00 non - parity 00 non - parity 00 12 sr/1x( 7.8 us) 8 2 sr/1x( 7.8 us) 8 2 sr/1x( 7.8 us) 8 2 13 x16 10 x16 10 x16 10 14 n/a 00 n/a 00 n/a 00 15 1 clock 01 1 clock 01 1 clock 01 16 2,4,8 0e 2,4,8 0e 2,4,8 0e 17 4 04 4 04 4 04 18 2.5 /3 1 8 2/2.5 0c 2/2.5 0c 19 0 01 0 01 0 01 20 1 02 1 02 1 02 21 differential clock 20 differential clock 20 differential clock 20 22 0. 1 v tolerance 00 0.2v tolerance 00 0.2v tolerance 00 23 5 ns 50 7.5ns 75 10 ns a0 24 0. 6 0 ns 6 0 0.7 0 ns 70 0.75ns 75 25 n /a 00 n/a 00 n/a 00 26 n/a 00 n/a 00 n/a 00 27 1 5 ns 3c 18 ns 48 20ns 50 28 1 0 ns 28 1 2 ns 30 15ns 3c 29 1 5 ns 3c 18 ns 48 20ns 50 30 4 0 ns 28 4 2 ns 2a 45ns 2d 31 128 mb 20 128 mb 20 128 mb 20 32 0. 6 0ns 60 0. 75 ns 75 0.90ns 90 33 0. 6 0ns 60 0. 75 ns 75 0.90ns 90 34 0. 4 0ns 40 0. 4 5ns 45 0.50ns 50 35 0. 4 0ns 40 0. 4 5ns 45 0.50ns 50 36 - 40 reserved 00 reserved 00 reserved 00 41 60ns 3c 60ns 3c 60ns 3c 42 72ns 48 72ns 48 72ns 48 43 12ns 30 12ns 30 12ns 30 44 0.4ns 28 0.4ns 28 0.4ns 28 45 0.55ns 55 0.55ns 55 0.55ns 55 46 - 61 reserved 00 reserved 00 reserved 00 62 initial 00 initial 00 initial 00 63 checksum 83 checksum 22 checksum d7 64-71 nanya 7f7f7f0b 00000000 nanya 7f7f7f0b 00000000 nanya 7f7f7f0b 00000000 72 assembly -- assembly -- assembly -- 73 - 90 module pn -- module pn -- module pn -- 91 - 92 revision -- revision -- revision -- 93 - 94 year/week code -- year/week code -- year/week code -- 95 - 98 serial number -- serial number -- serial number -- 99 - 127 reserved -- reserved -- reserved --
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 14 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. spd values for NT512D72S8PB0G pc3200 (5t) byte value hex 0 128 80 1 256 08 2 sdram ddr 07 3 13 0d 4 10 0a 5 2 0 2 6 x74 48 7 x74 00 8 sstl 2.5v 04 9 5 .0ns 5 0 10 6.0ns 60 11 parity 0 2 12 sr/1x( 7.8 us) 8 2 13 x8 08 14 ecc width 08 15 1 clock 01 16 2,4,8 0e 17 4 04 18 2.5 /3 18 19 0 01 20 1 02 21 differential clock 20 22 0. 1 v tolerance 00 23 5 ns 50 24 0. 6 0 ns 6 0 25 n/a 00 26 n/a 00 27 1 5 ns 3c 28 1 0 ns 28 29 1 5 ns 3c 30 4 0 ns 28 31 256 mb 4 0 32 0. 6 0ns 60 33 0. 6 0ns 60 34 0. 4 0ns 40 35 0. 4 0ns 40 3 6 - 40 reserved 00 41 60ns 3c 42 72ns 48 43 12ns 30 44 0.4ns 28 45 0.55ns 55 46 - 61 reserved 00 62 initial 00 63 checksum af 64-71 nanya 7f7f7f0b 00000000 72 assembly -- 73 - 90 module pn -- 91 - 92 revision -- 93 - 94 year/week code -- 95 - 98 serial n umber -- 99 - 127 reserved --
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 15 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. spd values for nt256d72s89b0g pc3200 (5t) byte value hex 0 128 80 1 256 08 2 sdram ddr 07 3 13 0d 4 10 0a 5 1 0 1 6 x72 4 8 7 x72 00 8 sstl 2.5v 04 9 5 .0ns 5 0 10 6.0ns 60 11 parity 0 2 12 sr/1x( 7.8 us) 8 2 13 x8 08 14 ecc width 08 15 1 clock 01 16 2,4,8 0e 17 4 04 18 2.5 /3 18 19 0 01 20 1 02 21 differential clock 20 22 0. 1 v tolerance 00 23 5 ns 50 24 0. 6 0 ns 6 0 25 n/a 00 26 n/a 00 27 1 5 ns 3c 28 1 0 ns 28 29 1 5 ns 3c 30 4 0 ns 28 31 256 mb 4 0 32 0. 6 0ns 60 33 0. 6 0ns 60 34 0. 4 0ns 40 35 0. 4 0ns 40 36 - 40 reserved 00 41 60ns 3c 42 72ns 48 43 12ns 30 44 0.4ns 28 45 0.55ns 55 46 - 61 reserved 00 62 initial 00 63 checksum ae 64-71 nanya 7f7f7f0b 00000000 72 assembly -- 73 - 90 module pn -- 91 - 92 revis ion -- 93 - 94 year/week code -- 95 - 98 serial number -- 99 - 127 reserved --
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 16 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. absolute maximum ratings symbol parameter rating units v in , v out voltage on i/o pins relative to v ss -0.5 to v ddq +0.5 v v in voltage on input relative to v ss -0.5 to +3.6 v v dd voltage on v dd supply relative to v ss -0.5 to +3.6 v v ddq voltage on v ddq supply relative to v ss -0.5 to +3.6 v t a operating temperature (ambient) 0 to +70 c t stg storage temperature (plastic) -55 to +150 c p d power dissipation (per device component) 1 w i out short circuit output current 50 ma note : stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational s ecti ons of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristi cs and operating conditions t a = 0c ~ 70c; v ddq = v dd = 2.5v0.2v(pc2100,pc2700); t a = 0c ~ 70c; v ddq = v dd = 2.6v0.1v(pc3200) symbol parameter min max units notes supply voltage pc2100, pc2700 2.3 v dd pc3200 2.5 2.7 v 1 i/o supply voltage pc2100, pc2700 2.3 v ddq pc3200 2.5 2.7 v 1 v ss , v ssq supply voltage, i/o supply voltage 0 0 v v ref i/o reference voltage 0.49 x v ddq 0.51 x v ddq v 1, 2 v tt i/o termination voltage (system) v ref ? 0.04 v ref + 0.04 v 1, 3 v ih (dc) input high (logic1) voltage v ref + 0.15 v ddq + 0.3 v 1 v il (dc) input low (logic0) voltage -0.3 v ref - 0.15 v 1 v in (dc) input voltage level, ck and ck inputs -0.3 v ddq + 0.3 v 1 v id (dc) input differential voltage, ck and ck inputs 0.30 v ddq + 0.6 v 1, 4 i i input leakage current any input 0v v in v dd ; all other pins not under test = 0v -10 10 a 1 i oz output leakage current dqs are disabled; 0v v out v ddq -10 10 a 1 i oh output high current (v out = v ddq -0.373v, min v ref , min v tt ) -16.8 - ma 1 i ol output low current (v out = 0.373, max v ref , max v tt ) 16.8 - ma 1 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variati ons in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the dimm. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck .
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 17 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac characteristics notes 1-5 apply to the following tables; electrical c haracteristics and dc operatin g conditions, ac operating conditions, operating, standby, a nd refresh currents, and electrical characteristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac timing, idd, and electric al, ac and dc characteristics, may be conduc ted at nominal reference/supply voltage le vels, but the related specifications and devic e operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load. re fer to the ac output load circuit below. 4. ac timing and idd tests may use a v il to v ih swing of up to 1.5v in the test environmen t, but input timing is still referenced to v ref (or to the crossing point for ck, ck ), and parameter specifications ar e guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il (ac) and v ih (ac) unless otherwise specified. 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc inp ut low (high) level. ac output load circuits timing reference point v tt 50 ohms 30 pf output v out ac operating conditions t a = 0 c ~ 70 c; v ddq = v dd = 2.5v 0.2v (pc2100/pc2700); v ddq = v dd = 2.6v 0.1v (pc3200) symbol parameter/condition min max unit notes v ih (ac) input high (logic 1) voltage. v ref + 0.31 v 1, 2 v il (ac) input low (logic 0) voltage. v ref ? - 0.31 v 1, 2 v id (ac) input differential voltage, ck and ck inputs 0.62 v ddq + 0.6 v 1, 2, 3 v ix (ac) input differential pair cross point voltage, ck and ck inputs (0.5* v ddq ) - 0.2 (0.5* v ddq ) + 0.2 v 1, 2, 4 1. input slew rate = 1v/ ns. 2. inputs are not recognized as valid until v ref stabilizes. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track va riations in the dc level of the same.
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 18 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. operating, standby, and refresh currents t a = 0 c ~ 70 c; v ddq = v dd = 2.5v 0.2v (pc2100/pc2700); v ddq = v dd = 2.6v 0.1v (pc3200) symbol parameter/condition notes idd0 operating current: one bank; active/precharge; t rc = t rc (min) ; t ck = t ck (min) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control i nputs changing once per clock cycle 1,2 idd1 operating current: one bank; active /read/precharge; burst = 2; t rc = t rc (min) ; cl=2.5; t ck = t ck (min) ; i out = 0ma; address and control inputs changing once per clock cycle 1,2 idd2p precharge power-down standby current: all banks idle; power-down mode; cke v il (max) ; t ck = t ck (min) 1,2 idd2n idle standby current: cs v ih (min) ; all banks idle; cke v ih (min) ; t ck = t ck (min) ; address and control inputs changing once per clock cycle 1,2 idd3p active power-down standby current: one bank active; power-down mode; cke v il (max) ; t ck = t ck (min) 1,2 idd3n active standby current: one bank; active/precharge; cs v ih (min) ; cke v ih (min) ; t rc = t ras (max) ; t ck = t ck (min) ; dq, dm, and dqs inputs changing twice per clock cycle; addre ss and control inputs changing once per clock cycle 1,2 idd4r operating current: one bank; burst = 2; reads ; continuous burst; a ddress and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2.5; t ck = t ck (min) ; i out = 0ma 1,2 idd4w operating current: one bank; burst = 2; writes; continuous burst; address and control inputs changi ng once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl=2.5; t ck = t ck (min) 1,2 idd5 auto-refresh current: t rc = t rfc (min) 1,2,3 idd6 self-refresh current: cke 0.2v 1,2 idd7 operating current: four bank; four bank interleaving with bl = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t rc = t rc (min) ; i out = 0ma. 1,2 1. idd specifications are tested afte r the device is properly initialized. 2. input slew rate = 1v/ ns. 3. current at 7.8 s is time averaged value of idd5 at t rfc (min) and idd2p over 7.8 s. all idd current values are calculated from device level.
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 19 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. nt512d64s8hb1gx nt256d64s88b1gx nt128d64sh4b1g symbol pc3200 (5t) pc2700 (6k) pc2100 (75b) pc3200 (5t) pc2700 (6k) pc2100 (75b) pc3200 (5t) pc2700 (6k) pc2100 (75b) idd0 1915 1755 1585 995 915 825 460 420 380 idd1 1995 1995 1825 1035 1035 945 480 480 440 idd2p 340 340 340 180 180 180 80 80 80 idd2n 765 765 680 405 405 360 180 180 160 idd3p 357 357 306 189 189 162 84 84 72 idd3n 1275 1275 1105 675 675 585 300 300 260 idd4r 3275 3275 2705 1675 1675 1385 800 800 660 idd4w 3195 3195 2625 1635 1635 1345 780 780 640 idd5 3675 2875 2785 1875 1475 1425 900 700 680 idd6 51 51 51 27 27 27 12 12 12 idd7 5275 5275 4065 2675 2675 2065 1300 1300 1000 NT512D72S8PB0G nt256256d64s89b0g symbol pc3200 (5t) pc2700 (6k) pc2100 (75b) pc3200 (5t) pc2700 (6k) pc2100 (75b) idd0 1915 1755 1585 995 915 825 idd1 1995 1995 1825 1035 1035 945 idd2p 340 340 340 180 180 180 idd2n 765 765 680 405 405 360 idd3p 357 357 306 189 189 162 idd3n 1275 1275 1105 675 675 585 idd4r 3275 3275 2705 1675 1675 1385 idd4w 3195 3195 2625 1635 1635 1345 idd5 3675 2875 2785 1875 1475 1425 idd6 51 51 51 27 27 27 idd7 5275 5275 4065 2675 2675 2065
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 20 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing specifications for d dr sdram devices used on module t a = 0 c ~ 70 c; v ddq = v dd = 2.5v 0.2v (pc2100/pc2700); v ddq = v dd = 2.6v 0.1v (pc3200) (part 1 of 2) symbol parameter 5t pc3200 6k pc2700 75b pc2100 unit notes min. max. min. max. min. max. t ac dq output access time from ck/ ck -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 ns 1-4 t dqsck dqs output access time from ck/ ck -0.55 +0.55 -0.7 +0.7 -0.75 +0.75 ns 1-4 t ch ck high-level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck 1-4 t cl ck low-level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck 1-4 t ck clock cycle time cl=3 5 8 - - - - t ck clock cycle time cl=2.5 6 12 6 12 7.5 12 ns 1-4 t ck clock cycle time cl=2 - - 7.5 12 10 12 ns 1-4 t dh dq and dm input hold time 0.4 0.45 0.5 ns 1-4, 15, 16 t ds dq and dm input setup time 0.4 0.45 0.5 ns 1-4, 15, 16 t dipw dq and dm input pulse width (each input) 1.75 1.75 1.75 ns 1-4 t hz data-out high-impedance time from ck/ ck -0.6 +0.6 -0.7 +0.7 -0.75 +0.75 ns 1-4, 5 t lz data-out low-impedance time from ck/ ck -0.6 +0.6 -0.7 +0.7 -0.75 +0.75 ns 1-4, 5 t dqsq dqs-dq skew (dqs & associated dq signals) 0.4 0.45 0.5 ns 1-4 t hp minimum half clk period for any given cycle; defined by clk high (t ch ) or clk low (t cl ) time t ch or t cl t ch or t cl t ch or t cl t ck 1-4 t qh data output hold time from dqs t hp - t qhs t hp - t qhs t hp - t qhs t ck 1-4 t qhs data hold skew factor 0.5 0.55 0.75 ns 1-4 t dqss write command to 1st dqs latching transition 0.75 1.25 0.75 1.25 0.75 1.25 t ck 1-4 t dqsl , t dqsh dqs input low (high) pulse width (write cycle) 0.35 0.35 0.35 t ck 1-4 t dss dqs falling edge to ck setup time (write cycle) 0.2 0.2 0.2 t ck 1-4 t dsh dqs falling edge hold time from ck (write cycle) 0.2 0.2 0.2 t ck 1-4 t mrd mode register set command cycle time 2 2 2 t ck 1-4 t wpres write preamble setup time 0 0 0 ns 1-4, 7 t wpst write postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck 1-4, 6 t wpre write preamble 0.25 0.25 0.25 t ck 1-4 t ih address and control input hold time (fast slew rate) 0.6 0.75 0.9 ns 2-4, 9, 11, 12 t is address and control input setup time (fast slew rate) 0.6 0.75 0.9 ns 2-4, 9, 11, 12 t ih address and control input hold time (slow slew rate) 0.7 0.8 1.0 ns 2-4, 10, 11, 12, 14
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 21 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing specifications for d dr sdram devices used on module t a = 0 c ~ 70 c; v ddq = v dd = 2.5v 0.2v (pc2100/pc2700); v ddq = v dd = 2.6v 0.1v (pc3200) (part 2 of 2) 5t pc3200 6k pc2700 75b pc2100 unit notes symbol parameter min. max. min. max. min. max. t is address and control input setup time (slow slew rate) 0.7 0.8 1.0 ns 2-4, 10-12, 14 t ipw input pulse width 2.2 2.2 2.2 ns 2-4, 12 t rp re read preamble 0.9 1.1 0.9 1.1 0.9 1.1 t ck 1-4 t rp st read postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck 1-4 t ras active to precharge command 42ns 120us 42ns 120us 45ns 120us 1-4 t rc active to active/auto-refresh command period 55 60 65 ns 1-4 t rfc auto-refresh to active/auto-refresh command period 70 72 75 ns 1-4 t rcd active to read or write delay 15 18 20 ns 1-4 t rap active to read command with auto-precharge 15 18 20 ns 1-4 t rp precharge command period 15 18 20 ns 1-4 t rrd active bank a to active bank b command 10 12 15 ns 1-4 t wr write recovery time 15 15 15 ns 1-4 t dal auto-precharge write recovery + precharge time (t wr / t ck ) + (t rp / t ck ) (t wr / t ck ) + (t rp / t ck ) (t wr / t ck ) + (t rp / t ck ) t ck 1-4, 13 t wtr internal write to read command delay 1 1 1 t ck 1-4 t pdex power down exit time 5 6 7.5 ns 1-4 t xsnr exit self-refresh to non-read command 75 75 75 ns 1-4 t xsrd exit self-refresh to read command 200 200 200 t ck 1-4 t refi average periodic refresh interval 7.8 7.8 7.8 s 1-4, 8
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 22 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing specification notes 1. input slew rate = 1v/ns. 2. the ck/ ck input reference level (for timing reference to ck/ ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ ck is v ref . 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limi t. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input sl ew rate specifications of the device. when no writes were previously in progres s on the bus, dqs will be transitioning from hi-z to l ogic low. if a previous write was in prog ress, dqs could be high, low, or transiti oning from high to low at this time, depending on t dqss . 8. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 9. for command/address input slew rate >= 1.0 v/ns. slew rate is measured between v oh (ac) and v ol (ac) . 10. for command/address input slew rate >= 0.5 v/ns and < 1.0 v/ns. slew rate is measured between v oh (ac) and v ol (ac) . 11. ck/ ck slew rates are >= 1.0 v/ns. 12. these parameters guarantee device timing, but they are not nec essarily tested on each device, and they may be guaranteed by design or tester characterization. 13. for each of the terms in parentheses, if not al ready an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. for example, for pc2100 at cl= 2.5, t dal = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. an input setup and hold time de rating table is used to increase t is and t ih in the case where the input slew rate is below 0.5 v/ns. input slew rate delta (t is ) delta (t ih ) unit note 0.5 v/ns 0 0 ps 1, 2 0.4 v/ns +50 0 ps 1, 2 0.3 v/ns +100 0 ps 1, 2 1. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. these derating parameters may be guaranteed by design or test er characterization and are not necessarily tested on each devi ce. 15. an input setup and hold time de rating table is used to increase t ds and t dh in the case where the i/o slew rate is below 0.5 v/ns. input slew rate delta (t ds ) delta (t dh ) unit note 0.5 v/ns 0 0 ps 1, 2 0.4 v/ns +75 +75 ps 1, 2 0.3 v/ns +150 +150 ps 1, 2 1. i/o slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. these derating parameters may be guaranteed by design or test er characterization and are not necessarily tested on each devi ce. 16. an i/o delta rise, fall derating table is used to increase t ds and t dh in the case where dq, dm, and dqs slew rates differ. delta rise and fall rate delta (t ds ) delta (t dh ) unit note 0.0 ns/v 0 0 ps 1-4 0.25 ns/v +50 +50 ps 1-4 0.5 ns/v +100 +100 ps 1-4 1. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. input slew rate is based on the larger of ac to ac delta rise, fall rate and dc to dc delta rise, fall rate. 3. the delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] for example: slew rate 1 = 0.5 v/ns; slew rate 2 = 0.4 v/ns. delta rise, fall = (1/0.5) - (1/0.4) [ns/v] = -0.5 ns/v using the table above, this would result in an increase in t ds and t dh of 100 ps. 4. these derating parameters may be guaranteed by design or test er characterization and are not necessarily tested on each devi ce.
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 23 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions non-ecc, 16 tsop devices 133.35 128.93 1.250 0.157 0.700 front side 0.394 1.27+/- 0.10 detail a 1.27 pitch detail b 1.00 width 4.00 detail a detail b 0.91 2.50 3.80 1.80 6.35 5.250 5.076 2.30 (2x)4.00 17.80 31.75 10.0 0.098 0.157 max 0.050 +/- 0.004 0.05 0.039 0.071 0.250 0.150 4.00 0.157 back note: all dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. units: millimeters (inches)
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 24 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions non-ecc, 8 tsop devices 133.35 128.93 1.250 0.157 0.700 front side 0.394 1.27+/- 0.10 detail a 1.27 pitch detail b 1.00 width 3.18 detail a detail b 0.91 2.50 3.80 1.80 6.35 5.250 5.076 2.30 (2x)4.00 17.80 31.75 10.0 0.098 0.125 max 0.050 +/- 0.004 0.05 0.039 0.071 0.250 0.150 4.00 0.157 back note: all dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. units: millimeters (inches)
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 25 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions non-ecc, 4 tsop devices 133.35 128.93 1.250 0.157 0.700 front side 0.394 1.27+/- 0.10 detail a 1.27 pitch detail b 1.00 width 3.18 detail a detail b 0.91 2.50 3.80 1.80 6.35 5.250 5.076 2.30 (2x)4.00 17.80 31.75 10.00 0.098 0.125 max 0.050 +/- 0.004 0.05 0.039 0.071 0.250 0.150 4.00 0.157 back note: all dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. units: millimeters (inches)
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 26 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions ecc, 18 tsop devices 133.35 128.95 1.250 0.157 0.700 front side 0.394 1.27+/- 0.10 detail a 1.27 pitch detail b 1.00 width 4.00 detail a detail b 0.091 (2) 2.50 3.80 1.80 6.35 5.25 5.077 2.30 (2x)4.00 17.80 31.75 10.0 0.098 0.157 max. 0.050 +/- 0.004 0.05 0.039 0.071 0.250 0.150 4.00 0.157 back note: all dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. units: millimeters (inches)
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 27 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions ecc, 9 tsop devices 133.35 128.95 1.250 0.157 0.700 front side 0.394 1.27+/- 0.10 detail a 1.27 pitch detail b 1.00 width 2.59 detail a detail b 0.091 (2) 2.50 3.80 1.80 6.35 5.25 5.077 2.30 (2x)4.00 17.80 31.75 10.0 0.098 0.157 max. 0.050 +/- 0.004 0.05 0.039 0.071 0.250 0.150 4.00 0.157 back note: all dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. units: millimeters (inches)
nt512d64s8hb1g / nt512d64s8h b1gy / nt512d64s8hb0g nt256d64s88b1g / nt256d64s88b1gy nt256d64s88b0g nt128d64sh4b1g / NT512D72S8PB0G (ecc) / nt256d72s89b0g (ecc) unbuffered ddr dimm rev 2.2 28 aug 3, 2004 preliminary ? nanya technology corporation nanya reserves the right to change products and specifications without notice. revision log rev date modification 0.1 12/2003 updated format. 1.0 dec 19,2003 release 1.1 feb 11, 2004 correction to block diagram label. correction to spd bank and checksum values. package dimension added for x8 wide devices. 2.0 mar 4, 2004 document reorganized by order of b die generation / size and dimm format. dimm: unbuffered dimm speed grades: 5t, 6k, 75b modules: nt512d64s8hb1g, nt256d64s88b1g, nt128d64sh4b1g modules: NT512D72S8PB0G, nt256d72s89b0g modules: nt512d64s8hb1gy, nt256d64s88b1gy 2.1 may 11, 2004 added nt256d64s88b0g-6k speed grade to ordering information. 2.2 aug 3, 2004 corrected spd contents. nanya technology corporation hwa ya technology park 669 fu hsing 3rd rd., kueishan, taoyuan, 333, taiwan, r.o.c. tel: +886-3-328-1688 please visit our home page for more information: www.nanya.com nanya reserves the right to make changes or deletions without any notice to any of its products. nanya makes no guarantee, warr anty or representation regarding the suitability of its products for any particular purpose. nanya assumes no liab ility arising out of the application or use of its products. al l parameters can and do vary in its application and must be validated for each customer application by the customer?s techni cian. by purchasing nanya prod ucts, nanya does not convey a ny license under its patent rights not the rights of others. nanya products are not designed or intended or aut horized for use in systems intended for the military or surgical implants or any other applications where life is involved or where injury or death may occur or the loss/corruption of data or the loss of sy stem reliability or mission critical applica tions. should the buyer purchase or use nanya products in such unintended or unauthorized application, the buyer and user shall indemnify and hold nanya and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, all fees and expenses directly or indirectly arising from any claim of loss, injury or deat h associated with unintended or unauthorized use even if such claims alleges nanya was negligent regarding design or manufacture of the part. nanya and the nanya logo are trademark s of the nanya technology corporation. printed in taiwan ?2004

▲Up To Search▲

Price & Availability of NT512D72S8PB0G

	To Download NT512D72S8PB0G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .