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numicro ? NUC122 data sheet arm cortex ? -m0 32-bit microcontroller publication release date: june 21, 2011 - 1 - revision v1.08 numicro ? family NUC122 data sheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation.
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 2 - revision v1.08 contents 1 general description ......................................................................................................... 6 2 features ................................................................................................................................. 7 2.1 numicro ? NUC122 features ........................................................................................... 7 3 parts information list and pin configuration .................................................... 10 3.1 numicro ? NUC122 products selection guide .............................................................. 10 3.2 numicro ? NUC122 pin diagram ................................................................................... 11 3.2.1 numicro ? NUC122 lqfp 64-pin ....................................................................................11 3.2.2 numicro ? NUC122 lqfp 48-pin ....................................................................................12 3.2.3 numicro ? NUC122 qfn 33-pin ......................................................................................13 3.3 numicro ? NUC122 pin description .............................................................................. 14 3.3.1 numicro ? NUC122 pin description for lqfp64/lqfp48/qfn33 ..................................14 4 block diagram .................................................................................................................... 18 4.1 numicro ? NUC122 block diagram ............................................................................... 18 5 functional description .................................................................................................. 19 5.1 arm ? cortex ? -m0 core ............................................................................................... 19 5.2 system manager ........................................................................................................... 21 5.2.1 overview ........................................................................................................................21 5.2.2 system reset .................................................................................................................21 5.2.3 system power distribution .............................................................................................22 5.2.4 system timer (systick) .................................................................................................23 5.2.5 nested vectored interrupt controller (nvic) ..................................................................24 5.3 clock controller ............................................................................................................ 28 5.3.1 overview ........................................................................................................................28 5.3.2 clock generator .............................................................................................................29 5.3.3 system clock & systick clock .......................................................................................31 5.3.4 peripherals clock ...........................................................................................................32 5.3.5 power down mode clock ...............................................................................................32 5.4 usb device controller (usb) ....................................................................................... 33 5.4.1 overview ........................................................................................................................33 5.4.2 features .........................................................................................................................33 5.5 general purpose i/o (gpio) ........................................................................................ 34 5.5.1 overview and features ..................................................................................................34 5.5.2 function description .......................................................................................................34 5.6 i 2 c serial interface controller (master/slave) (i 2 c) ...................................................... 36 5.6.1 overview ........................................................................................................................36 5.7 pwm generator and capture timer (pwm) ................................................................ 38 5.7.1 overview ........................................................................................................................38 5.7.2 features .........................................................................................................................39 5.8 real time clock (rtc) ................................................................................................. 40 5.8.1 overview ........................................................................................................................40
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 3 - revision v1.08 5.8.2 features .........................................................................................................................40 5.9 serial peripheral interface (spi) ................................................................................... 41 5.9.1 overview ........................................................................................................................41 5.9.2 features .........................................................................................................................41 5.10 timer controller (tmr) ................................................................................................. 42 5.10.1 overview ......................................................................................................................42 5.10.2 features .......................................................................................................................42 5.11 watchdog timer (wdt) ................................................................................................ 43 5.11.1 features .......................................................................................................................44 5.12 uart interface controller (uart) ............................................................................... 45 5.12.1 overview ......................................................................................................................45 5.12.2 features .......................................................................................................................47 5.13 ps/2 device controller (ps2d) ..................................................................................... 48 5.13.1 overview ......................................................................................................................48 5.13.2 features .......................................................................................................................48 6 flash memory controller (fmc) ................................................................................ 49 6.1 overview ....................................................................................................................... 49 6.2 features ........................................................................................................................ 49 7 electrical characteristics ......................................................................................... 50 7.1 absolute maximum ratings .......................................................................................... 50 7.2 dc electrical characteristics ........................................................................................ 51 7.2.1 numicro ? NUC122 dc electrical characteristics ...........................................................51 7.3 ac electrical characteristics ........................................................................................ 55 7.3.1 external 4~24 mhz high speed crystal ac electrical characteristics ...........................55 7.3.2 external 4~24 mhz high speed crystal .........................................................................55 7.3.3 external 32.768 khz low speed crystal ........................................................................55 7.3.4 internal 22.1184 mhz high speed oscillator ..................................................................56 7.3.5 internal 10 khz low speed oscillator ............................................................................56 7.4 analog characteristics .................................................................................................. 57 7.4.1 specification of ldo & power management ..................................................................57 7.4.2 specification of low voltage reset ................................................................................58 7.4.3 specification of brownout detector .................................................................................58 7.4.4 specification of power-on reset (5 v) ...........................................................................58 7.4.5 specification of usb phy ..............................................................................................59 7.5 spi dynamic characteristics ........................................................................................ 60 7.5.1 dynamic characteristics of data input and output pin ...................................................60 8 package dimensions ......................................................................................................... 62 8.1 64l lqfp (7x7x1.4mm footprint 2.0 mm) .................................................................... 62 8.2 48l lqfp (7x7x1.4mm footprint 2.0mm) ..................................................................... 63 8.3 33l qfn (5x5x0.8mm) ................................................................................................. 64 9 revision history ................................................................................................................ 65
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 4 - revision v1.08 figures figure 5-1 functional controller diagram ...................................................................................... 19 figure 5-2 numicro ? NUC122 power distribution diagram ........................................................... 22 figure 5-3 clock generator global view diagram ......................................................................... 29 figure 5-4 clock generator block diagram ................................................................................... 30 figure 5-5 system clock block diagram ....................................................................................... 31 figure 5-6 systick clock control block diagram .......................................................................... 31 figure 5-7 push-pull output ........................................................................................................... 34 figure 5-8 open-drain output ....................................................................................................... 35 figure 5-9 quasi-bidirectional i/o mode ........................................................................................ 35 figure 5-10 i 2 c bus timing ............................................................................................................ 36 figure 5-11 timing of interrupt and reset signals ........................................................................ 44 figure 7-1 typical crystal application circuit ................................................................................ 55 figure 7-2 spi master mode timing .............................................................................................. 60 figure 7-3 spi slave mode timing ................................................................................................ 61
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 5 - revision v1.08 tables table 1-1 connectivity supported table .......................................................................................... 6 table 5-1 exception model ............................................................................................................ 25 table 5-2 system interrupt map ..................................................................................................... 25 table 5-3 vector table format ...................................................................................................... 27 table 5-4 watchdog timer time-out interval selection ................................................................. 43 table 5-5 uart baud rate equation ............................................................................................ 45 table 5-6 uart baud rate setting table ..................................................................................... 45
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 6 - revision v1.08 1 general description the numicro ? NUC122 series are 32-bit microcontrollers with cortex ? -m0 core runs up to 60 mhz, up to 32k/64k-byte embedded flash, 4k/8k-byte em bedded sram, and 4k-byte loader rom for the in system program (isp) function. it also integr ates timers, watchdog timer, rtc, uart, spi, i 2 c, pwm timer, gpio, usb 2.0 full speed device, low voltage reset controller and brownout detector. table 1-1 connectivity supported table product line uart spi i 2 c usb ps/2 NUC122 y y y y y
numicro ? NUC122 data sheet 2 features 2.1 numicro ? NUC122 features ? core C arm ? cortex ? -m0 core runs up to 60 mhz C one 24-bit system timer C support low power sleep mode C single-cycle 32-bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4-levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? wide operating voltage ranges from 2.5 v to 5.5 v ? flash memory C 32k/64k bytes flash for program code C 4kb flash for isp loader C support in system program (isp) function to update application code C 512 bytes page erase for flash C 4kb data flash C support 2 wire in circuit program (icp) func tion to update code through swd/ice interface C support fast parallel programming mode by external programmer ? sram memory C 4k/8k bytes embedded sram ? clock control C flexible selection from different clock sources C built-in 22.1184 mhz high speed osc for system operation ? trimmed to 1 % at +25 and v dd = 3.3 v ? trimmed to 5 % at -40 ~ +85 and v dd = 2.5 v ~ 5.5 v C built-in 10 khz low speed osc for watchdog timer and wake-up operation C support one pll, up to 60 mhz, for high performance system operation C external 4~24 mhz high speed crystal input for usb and precise timing operation C external 32.768 khz low speed crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi bi-direction ? push-pull output ? open-drain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin can be configured as interr upt source with edge/level setting C high driver and high sink io mode support ? timers C 4 sets of 32-bit timers with 24-bit counters and one 8-bit prescaler C counter auto reload publication release date: june 21, 2011 - 7 - revision v1.08
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 8 - revision v1.08 ? watchdog timer C multiple clock sources C 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depends on clock source) C wdt can wake-up from power down or idle mode C interrupt or reset selectable while watchdog timer time-out ? rtc C support software compensation by setting frequency compensate register (fcr) C support rtc counter (second, minute, hour ) and calendar counter (day, month, year) C support alarm registers (second, minute, hour, day, month, year) C 12-hour or 24-hour mode C automatic leap year recognition C support time tick interrupt C support wake-up function ? pwm/capture C built-in up to two 16-bit pwm generators provi de four pwm outputs or two complementary paired pwm outputs C each pwm generator equipped with one clock sour ce selector, one clock divider, one 8-bit prescaler and one dead-zone generator for complementary paired pwm C up to four 16-bit digital capture timers (sha red with pwm timers) provide four rising/falling capture inputs C support capture interrupt ? uart C two uart controllers C uart ports with flow control (txd, rxd, cts and rts) C uart ports with 16-byte fifo for standard device C support irda (sir) function C support rs-485 9-bit mode and direction control C programmable baud-rate generator up to 1/16 system clock ? spi C up to two sets of spi device C master up to 25 mhz, and slave up to 12 mhz (chip is working @ 5 v) C support spi master/slave mode C full duplex synchronous serial data transfer C variable length of transfer data from 1 to 32 bits C msb or lsb first data transfer C 2 slave/device select lines when it is as the master, and 1 slave/device select line when it is as the slave C byte suspend mode in 32-bit transmission
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 9 - revision v1.08 ? i 2 c C one set of i 2 c device C master/slave mode C bidirectional data transfer between masters and slaves C multi-master bus (no central master) C arbitration between simultaneously transmitting ma sters without corruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow versatile rate control C i 2 c-bus controller supports multiple address recognition (four slave address with mask option) ? usb 2.0 full-speed device C one set of usb 2.0 fs device 12mbps C on-chip usb transceiver C provide 1 interrupt source with 4 interrupt events C support control, bulk in/out, in terrupt and isochronous transfers C auto suspend function when no bus signaling for 3 ms C provide 6 programmable endpoints C include 512 bytes internal sram as usb buffer C provide remote wake-up capability ? brownout detector C with 4 levels: 4.5 v/3.8 v/2.7 v/2.2 v C support brownout interrupt and reset options ? one built-in ldo ? low voltage reset ? operating temperature: -40 ~ 85 ? packages: C all green package (rohs) C lqfp 64-pin (7mmx7mm) C lqfp 48-pin C qfn 33-pin
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 10 - revision v1.08 3 parts information list and pin configuration 3.1 numicro ? NUC122 products selection guide connectivity part number flash (kb) isp rom (kb) sram (kb) i/o timer uart spi i 2 c usb lin ps/2 i 2 s comp. pwm adc rtc isp icp package NUC122zd2an 64 kb 4kb 8 kb up to 18 4x32-bit 1 2 1 1 - - - - - - - v qfn33 NUC122zc1an 32 kb 4kb 4 kb up to 18 4x32-bit 1 2 1 1 - - - - - - - v qfn33 NUC122ld2an 64 kb 4kb 8 kb up to 30 4x32-bit 2 2 1 1 - 1 - - 4 - v v lqfp48 NUC122lc1an 32 kb 4kb 4 kb up to 30 4x32-bit 2 2 1 1 - 1 - - 4 - v v lqfp48 NUC122sd2an 64 kb 4kb 8 kb up to 41 4x32-bit 2 2 1 1 - 1 - - 4 - v v lqfp64 NUC122sc1an 32 kb 4kb 4 kb up to 41 4x32-bit 2 2 1 1 - 1 - - 4 - v v lqfp64
numicro ? NUC122 data sheet 3.2 numicro ? NUC122 pin diagram 3.2.1 numicro ? NUC122 lqfp 64-pin figure 3-1 numicro ? NUC122 lqfp 64-pin pin diagram publication release date: june 21, 2011 - 11 - revision v1.08
numicro ? NUC122 data sheet 3.2.2 numicro ? NUC122 lqfp 48-pin figure 3-2 numicro ? NUC122 lqfp 48-pin pin diagram publication release date: june 21, 2011 - 12 - revision v1.08
numicro ? NUC122 data sheet 3.2.3 numicro ? NUC122 qfn 33-pin int0/pb.14 i2c1scl/pa.11 i2c1sda/pa.10 ldo vdd vss ice_ck ice_dat pc.10/miso10 pc.11/mosi10 pc.12 pc.13 8 7 6 5 4 3 2 1 19 20 21 22 23 24 spiss11/rxd1/pb.4 txd1/pb.5 pc.8/spiss10 pc.9/spiclk1 17 18 figure 3-3 numicro ? NUC122 qfn 33-pin pin diagram publication release date: june 21, 2011 - 13 - revision v1.08
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 14 - revision v1.08 3.3 numicro ? NUC122 pin description 3.3.1 numicro ? NUC122 pin description for lqfp64/lqfp48/qfn33 pin no. lqfp 64 lqfp 48 qfn 33 pin name pin type description pb.14 i/o general purpose input/output digital pin 1 1 /int0 i /int0: external interrupt1 input pin 2 2 x32o o 32.768 khz low speed crystal output pin 3 3 x32i i 32.768 khz low speed crystal input pin pa.11 i/o general purpose input/output digital pin 4 4 2 i2c1scl i/o i2c1scl: i 2 c1 clock pin pa.10 i/o general purpose input/output digital pin 5 5 3 i2c1sda i/o i2c1sda: i 2 c1 data input/output pin 6 pd.8 i/o general purpose input/output digital pin 7 pd.9 i/o general purpose input/output digital pin 8 pd.10 i/o general purpose input/output digital pin 9 pd.11 i/o general purpose input/output digital pin pb.4 i/o general purpose input/output digital pin rxd1 i rxd1: data receiver input pin for uart1 10 6 4 spiss11 i/o spiss11: spi1 slave select pin (for qfn33 only) pb.5 i/o general purpose input/output digital pin 11 7 5 txd1 o txd1: data transmitter output pin for uart1 pb.6 i/o general purpose input/output digital pin 12 8 rts1 o rts1: request to send output pin for uart1 pb.7 i/o general purpose input/output digital pin 13 9 cts1 i cts1: clear to send input pin for uart1 14 10 6 ldo p ldo output pin 15 11 7 vdd p power supply for i/o ports and ldo source for internal pll and digital function 16 12 8 vss p ground 17 13 9 vbus p power supply: from usb host or hub. 18 14 10 vdd33 p internal power regulator output 3.3 v decoupling
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 15 - revision v1.08 pin no. lqfp 64 lqfp 48 qfn 33 pin name pin type description pin 19 15 11 d- usb usb differential signal d- 20 16 12 d+ usb usb differential signal d+ pb.0 i/o general purpose input/output digital pin 21 17 rxd0 i rxd0: data receiver input pin for uart0 pb.1 i/o general purpose input/output digital pin 22 18 txd0 o txd0: data transmitter output pin for uart0 pb.2 i/o general purpose input/output digital pin 23 rts0 o rts0: request to send output pin for uart0 pb.3 i/o general purpose input/output digital pin 24 cts0 i cts0: clear to send input pin for uart0 25 pc.5 i/o general purpose input/output digital pin 26 pc.4 i/o general purpose input/output digital pin pc.3 i/o general purpose input/output digital pin 27 19 13 mosi00 o mosi00: spi0 mosi (master out, slave in) pin pc.2 i/o general purpose input/output digital pin 28 20 14 miso00 i miso00: spi0 miso (master in, slave out) pin pc.1 i/o general purpose input/output digital pin 29 21 15 spiclk0 i/o spiclk0: spi0 serial clock pin pc.0 i/o general purpose input/output digital pin 30 22 16 spiss00 i/o spiss00: spi0 slave select pin pb.10 i/o general purpose input/output digital pin tm2 o tm2: timer2 external counter input 31 23 spiss01 i/o spiss01: spi0 2 nd slave select pin pb.9 i/o general purpose input/output digital pin tm1 o tm1: timer1 external counter input 32 24 spiss11 i/o spiss11: spi1 2 nd slave select pin 33 vss p ground 34 25 17 pc.13 i/o general purpose input/output digital pin
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 16 - revision v1.08 pin no. lqfp 64 lqfp 48 qfn 33 pin name pin type description 35 26 18 pc.12 i/o general purpose input/output digital pin pc.11 i/o general purpose input/output digital pin 36 27 19 mosi10 o mosi10: spi1 mosi (master out, slave in) pin pc.10 i/o general purpose input/output digital pin 37 28 20 miso10 i miso10: spi1 miso (master in, slave out) pin 38 vdd p power supply for i/o ports pc.9 i/o general purpose input/output digital pin 39 29 21 spiclk1 i/o spiclk1: spi1 serial clock pin pc.8 i/o general purpose input/output digital pin 40 30 22 spiss10 i/o spiss10: spi1 slave select pin pa.15 i/o general purpose input/output digital pin 41 31 pwm3 o pwm3: pwm output pin 42 vss p ground pa.14 i/o general purpose input/output digital pin 43 32 pwm2 o pwm2: pwm output pin pa.13 i/o general purpose input/output digital pin 44 33 pwm1 o pwm1: pwm output pin pa.12 i/o general purpose input/output digital pin 45 34 pwm0 o pwm0: pwm output pin 46 35 23 ice_dat i/o serial wired debugger data pin 47 36 24 ice_ck i serial wired debugger clock pin 48 37 25 avdd ap power supply for internal analog circuit 49 38 pd.0 i/o general purpose input/output digital pin pd.1 i/o general purpose input/output digital pin 50 39 26 spiss01 i/o spiss01: spi0 2 nd slave select pin (for qfn33 only) 51 40 27 pd.2 i/o general purpose input/output digital pin 52 41 28 pd.3 i/o general purpose input/output digital pin 53 42 pd.4 i/o general purpose input/output digital pin 54 43 pd.5 i/o general purpose input/output digital pin
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 17 - revision v1.08 pin no. lqfp 64 lqfp 48 qfn 33 pin name pin type description pb.15 i/o general purpose input/output digital pin 55 /int1 i /int1: external interrupt 1 input pin 56 44 29 xt1_out o crystal output pin 57 45 30 xt1_in i crystal input pin 58 46 31 /reset i external reset input: low acti ve, set this pin low reset chip to initial state. with internal pull-up. 59 33 vss p ground 60 vdd p power supply for i/o ports 61 47 ps2dat i/o ps/2 data pin 62 48 ps2clk i/o ps/2 clock pin 63 1 32 pvss p pll ground pb.8 i/o general purpose input/output digital pin 64 tm0 o tm0: timer0 external counter input note: pin type i=digital input, o=digital outpu t; ai=analog input; p=power pin; ap=analog power
numicro ? NUC122 data sheet 4 block diagram 4.1 numicro ? NUC122 block diagram flash 64 kb cortex-m0 60 mhz clk_ctl isp 4 kb sram 8 kb gpio a,b,c,d ps/2 uart 1 -115k timer 2/3 rtc wdt i 2 c 1 spi 0/1 pwm 0~3 timer 0/1 por brownout lvr p l l ldo 2.5 v~ 5.5 v usb-fs ram 512 b usbphy 10 khz 32.768 khz 22.1184 mhz 4~24 mhz uart 0 -115k figure 4-1 numicro ? NUC122 block diagram publication release date: june 21, 2011 - 18 - revision v1.08
numicro ? NUC122 data sheet 5 functional description 5.1 arm ? cortex ? -m0 core the cortex ? -m0 processor is a configurable, multistage, 32-bit risc processor. it has an amba ahb- lite interface and includes an nvic component. it al so has optional hardware debug functionality. the processor can execute thumb code and is compatible with other cortex ? -m profile processor. following figure shows the function al controllers of processor. cortex-m0 processor core nested vectored interrupt controller (nvic) breakpoint and watchpoint unit debugger interface bus matrix debug access port (dap) debug cortex-m0 processor cortex-m0 components wakeup interrupt controller (wic) interrupts serial wire or jtag debug port ahb-lite interface figure 5-1 functional controller diagram the implemented device provides: ? a low gate count processor that features: C the arm ? v6-m thumb ? instruction set C thumb-2 technology C arm ? v6-m compliant 24-bit systick timer C a 32-bit hardware multiplier C the system interface supports little-endian data accesses C the ability to have deterministic, fi xed-latency, and interrupt handling C load/store-multiples and multicycle-multiplies t hat can be abandoned and restarted to facilitate rapid interrupt handling C c application binary interface compliant exception model. this is the arm ? v6-m, c application binary interface (c-abi) compliant exception model that enables the use of pure c functions as interrupt handlers C low power sleep mode entry using wait for interrupt (wfi), wait for event (wfe) instructions, or the return from interrupt sleep-on-exit feature ? nvic that features: C 32 external interrupt inputs, each with four levels of priority C dedicated non-maskable interrupt (nmi) input. C support for both level-sensitive and pulse-sensitive interrupt lines C wake-up interrupt controller (wic), prov iding ultra-low power sleep mode support. publication release date: june 21, 2011 - 19 - revision v1.08
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 20 - revision v1.08 ? debug support C four hardware breakpoints. C two watchpoints. C program counter sampling register (pcs r) for non-intrusive code profiling. C single step and vector catch capabilities. ? bus interfaces: C single 32-bit amba-3 ahb-lite system interface t hat provides simple integration to all system peripherals and memory. C single 32-bit slave port that suppo rts the dap (debug access port).
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 21 - revision v1.08 5.2 system manager 5.2.1 overview system management includes these following sections: y system resets y system memory map y system management registers for part number id, chip reset and on-chip controllers reset, multi-functional pin control y system timer (systick) y nested vectored interrupt controller (nvic) y system control registers 5.2.2 system reset the system reset can be issued by one of the below listed events. these reset event flags can be read from rstsrc register. y the power-on reset y the low level on the /reset pin y watchdog timer time-out reset y low voltage reset y brownout detector reset y cortex ? -m0 reset y system reset both system reset and power-on reset can reset the whole chip including all peripherals. the difference between system reset and power-on rese t is external crystal circuit and ispcon.bs bit. system reset doesn?t reset external crystal circ uit and ispcon.bs bit, but power-on reset does.
numicro ? NUC122 data sheet 5.2.3 system power distribution in this chip, the power distribution is divided into three segments. y analog power from avdd and avss provides t he power for analog co mponents operation. y digital power from vdd and vss supplies the power to the inter nal regulator which provides a fixed 1.8 v power for digital operation and i/o pins. y usb transceiver power from vbus offers the power for operating the usb transceiver. the outputs of internal voltage regulators, ldo and vdd33, require an external capacitor which should be located close to the corresponding pin. analog power (avdd) should be the same voltage level of the digital power (vdd). the following di agram shows the power distribution of this chip. 5v to 1.8v ldo usb transceiver 5v to 3.3v ldo pll brown out detector por50 por18 low voltage reset rtc 32k osc. flash digital logic 3.3v 1.8v irc 22.1184mhz & 10khz osc. avdd avss vdd vss vbus vdd33 d+ d- ldo 1uf 10uf io cell gpio x32o x32i pvss power distribution figure 5-2 numicro ? NUC122 power distribution diagram publication release date: june 21, 2011 - 22 - revision v1.08
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 23 - revision v1.08 5.2.4 system timer (systick) the cortex ? -m0 includes an integrated system timer, sy stick. systick provides a simple, 24-bit clear-on-write, decrementing, wrap -on-zero counter with a flexible control mechanism. the counter can be used in several different ways, for example: y an rtos tick timer which fires at a programmable rate (for example 100hz) and invokes a systick routine. y a high speed alarm timer using core clock. y a variable rate alarm or signal timer ? the duration range dependent on the reference clock used and the dynamic range of the counter. y a simple counter. software can use this to measure time to completion and time used. y an internal clock source control based on miss ing/meeting durations. the countflag bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynami c clock management control loop. when enabled, the timer will count down from the value in the systick current value register (syst_cvr) to zero, and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock cycle, then decre ment on subsequent cloc ks. when the counter transitions to zero, the countflag status bi t is set. the countflag bit clears on reads. the syst_cvr value is unknown on reset. software shou ld write to the register to clear it to zero before enabling the feature. this ensures the timer will count from the syst_rvr value rather than an arbitrary value when it is enabled. if the syst_rvr is zero, the timer will be maintained wi th a current value of zero after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to the documents ?arm ? cortex ? -m0 technical reference manual? and ?arm ? v6-m architecture reference manual?.
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 24 - revision v1.08 5.2.5 nested vectored interrupt controller (nvic) cortex ? -m0 provides an interrupt controller as an int egral part of the exception mode, named as ?nested vectored interrupt controller (nvic)?. it is closely coupled to the processor kernel and provides following features: y nested and vectored interrupt support y automatic processor stat e saving and restoration y dynamic priority changing y reduced and deterministic interrupt latency the nvic prioritizes and handles all supported exc eptions. all exceptions are handled in ?handler mode?. this nvic architecture suppor ts 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most of the system exceptions ca n be configured to different priority levels. when an interrupt occurs, the nvic will co mpare the priority of the new interrupt to the current running one?s priority. if the priority of the new interrupt is hi gher than the current one, the new interrupt handler will override the current handler. when any interrupts is accepted, t he starting address of the interrupt service routine (isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the starting address of the corr elated isr by software. while the starting address is fetched, nvic will also automatically save processor state includi ng the registers ?pc, psr, lr, r0~r3, r12? to the stack. at the end of the is r, the nvic will restore the mentioned registers fr om stack and resume the normal execution. thus it will take less and deterministic time to process the interrupt request. the nvic supports ?tail chaining? which handles back-to-back interrupts efficiently without the overhead of states saving and re storation and therefore reduces del ay time in switching to pending isr at the end of current isr. the nvic also supports ?late arrival? which improves the efficiency of concurrent isrs. when a higher priority interrupt r equest occurs before the current isr starts to execute (at the stage of state savi ng and starting address fetching), the nvic will give priority to the higher one without delay penalty. thus it advances the real-time capability. for more detailed information, please refer to the documents ?arm ? cortex ? -m0 technical reference manual? and ?arm ? v6-m architecture reference manual?.
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 25 - revision v1.08 5.2.5.1 exception model and system interrupt map the following table lists the exception model supported by numicro ? NUC122. software can set four levels of priority on some of these exceptions as well as on all interrupts. the highest user- configurable priority is denoted as ?0? and the lowest priority is denoted as ?3?. the default priority of all the user-configurable interrupts is ?0?. note that priority ?0? is tr eated as the fourth priority on the system, after three system exceptions ?reset?, ?nmi? and ?hard fault?. table 5-1 exception model exception name vector number priority reset 1 -3 nmi 2 -2 hard fault 3 -1 reserved 4 ~ 10 reserved svcall 11 configurable reserved 12 ~ 13 reserved pendsv 14 configurable systick 15 configurable interrupt (irq0 ~ irq31) 16 ~ 47 configurable table 5-2 system interrupt map vector number interrupt number (bit in interrupt registers) interrupt name source ip interrupt description 0 ~ 15 - - - system exceptions 16 0 bod_out brownout brownout low voltage detected interrupt 17 1 wdt_int wdt watchdog timer interrupt 18 2 eint0 gpio external signal interrupt from pb.14 pin 19 3 eint1 gpio external signal interrupt from pb.15 pin 20 4 gpab_int gpio external signal interr upt from pa[15:0]/pb[13:0] 21 5 gpcd_int gpio external interrupt from pc[15:0]/pd[15:0] 22 6 pwma_int pwm0~3 pwm0, pwm1, pwm2 and pwm3 interrupt 23 7 reserved reserved reserved 24 8 tmr0_int tmr0 timer 0 interrupt 25 9 tmr1_int tmr1 timer 1 interrupt 26 10 tmr2_int tmr2 timer 2 interrupt
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 26 - revision v1.08 vector number interrupt number (bit in interrupt registers) interrupt name source ip interrupt description 27 11 tmr3_int tmr3 timer 3 interrupt 28 12 reserved reserved reserved 29 13 uart1_int uart1 uart1 interrupt 30 14 spi0_int spi0 spi0 interrupt 31 15 spi1_int spi1 spi1 interrupt 32 16 reserved reserved reserved 33 17 reserved reserved reserved 34 18 reserved reserved reserved 35 19 i2c1_int i 2 c1 i 2 c1 interrupt 36 20 reserved reserved reserved 37 21 reserved reserved reserved 38 22 reserved reserved reserved 39 23 usb_int usbd usb 2.0 fs device interrupt 40 24 ps2_int ps/2 ps/2 interrupt 41 25 reserved reserved reserved 42 26 reserved reserved reserved 43 27 reserved reserved reserved 44 28 pwrwu_int clkc power down wake-up interrupt 45 29 reserved reserved reserved 46 30 reserved reserved reserved 47 31 rtc_int rtc real time clock interrupt
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 27 - revision v1.08 5.2.5.2 vector table when any interrupts is accepted, the processor will autom atically fetch the st arting address of the interrupt service routine (isr) from a vector table in memory. for arm ? v6-m, the vector table base address is fixed at 0x00000000. the ve ctor table contains the initializ ation value for the stack pointer on reset, and the entry point addresses for all exc eption handlers. the vector number on previous page defines the order of entries in the vector t able associated with ex ception handler entry as illustrated in previous section. table 5-3 vector table format vector table word offset description 0 sp_main ? the main stack pointer vector number exception entry po inter using that vector number 5.2.5.3 operation description nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set-enable or interrupt clear-enable register bit-field. the registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. when an interrupt is disabled, interrupt assertion will cause the interrupt to become pending, however, the interrupt will not activate. if an interrupt is active when it is disabled, it remains in its active state until cleared by reset or an exception return. cleari ng the enable bit prevents new activations of the associated interrupt. nvic interrupts can be pended/un-pended using a comp lementary pair of registers to those used to enable/disable the interrupts, named the set-p ending register and clear-pending register respectively. the registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current pended state of t he corresponding interrupts. the clear-pending register has no effect on the execution status of an active interrupt. nvic interrupts are prioritized by updating an 8-bi t field within a 32-bit register (each register supporting four interrupts). the general registers associated with the nvic ar e all accessible from a block of memory in the system control space and will be described in next section.
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 28 - revision v1.08 5.3 clock controller 5.3.1 overview the clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. the clock controller also implements the po wer control function with the individually clock on/off control, clock source selection and clock di vider. the chip will not enter power down mode until cpu sets the power down enable bit (pwr_down_en) and cortex ? -m0 core executes the wfi instruction. after that, chip enter s power down mode and wait for wake-up interrupt source triggered to leave power down mode. in the power down mode, t he clock controller turns off the external 4~24 mhz high speed crystal and internal 22.1184 mhz high speed oscillator to reduce the overall system power consumption.
numicro ? NUC122 data sheet 1 0 pllcon[19] 22.1184 mhz 4~12 mhz pllfout 111 011 010 001 4~24 mhz 32.768 khz 4~24 mhz hclk 22.1184 mhz 000 1/2 1/2 1/2 clksel0[5:3] 1 0 systick tmr 3 uart 0-1 i 2 c 1 spi 0-1 usb rtc ps2 wdt pwm 0-1 pwm 2-3 tmr 0 tmr 1 tmr 2 cpu fmc 32.768 khz 10 khz 111 010 001 000 hclk 32.768 khz 4~24 mhz 111 011 010 001 pllfout 32.768 khz 4~24 mhz 10 khz 22.1184 mhz 000 clksel0[2:0] syst_csr[2] cpuclk 1/(hclk_n+1) pclk cpuclk hclk 11 01 00 pllfout 4~24 mhz 22.1184 mhz clksel1[25:24] 22.1184 mhz clksel1[22:20] clksel1[18:16] clksel1[14:12] clksel1[10:8] 1/(usb_n+1) pllfout 11 10 01 00 hclk 4~24 mhz 22.1184 mhz 32.768 khz clksel1[31:28] 22.1184 mhz 32.768 khz bod 10 khz 11 10 clksel1[1:0] hclk 1/2048 1/(uart_n+1) 22.1184 mhz 4~24 mhz figure 5-3 clock generator global view diagram 5.3.2 clock generator the clock generator consists of 5 clock sources which are listed as below: ? one external 32.768 khz low speed crystal ? one external 4~24 mhz high speed crystal publication release date: june 21, 2011 - 29 - revision v1.08
numicro ? NUC122 data sheet ? one programmable pll fout (pll source consists of external 4~24 mhz high speed crystal and internal 22.1184 mhz high speed oscillator) ? one internal 22.1184 mhz high speed oscillator ? one internal 10 khz low speed oscillator xt_out external 4~24 mhz crystal xtl12m_en (pwrcon[0]) xt_in internal 22.1184 mhz oscillator osc22m_en (pwrcon[2]) 0 1 pll pll_src (pllcon[19]) pll fout x32o external 32.768 khz crystal 32.768 khz xtl32k_en (pwrcon[1]) x32i internal 10 khz oscillator osc10k_en(pwrcon[3]) 4~24 mhz 22.1184 mhz 10 khz figure 5-4 clock generator block diagram publication release date: june 21, 2011 - 30 - revision v1.08
numicro ? NUC122 data sheet 5.3.3 system clock & systick clock the system clock has 5 clock sour ces which were generated from cl ock generator block. the clock source switch depends on the register hclk_s (c lksel0[2:0]). the block diagram is listed below. figure 5-5 system clock block diagram the clock source of systick in cortex ? -m0 core can use cpu clock or external clock (syst_csr[2]). if using external clock, the systick clock (stclk) has 5 clock sources. the clock source switch depends on the setting of the register stclk_s (c lksel0[5:3]. the block diagram is listed below. 111 011 010 001 4~24 mhz 32.768 khz 4~24 mhz hclk stclk_s (clksel0[5:3]) stclk 22.1184 mhz 000 1/2 1/2 1/2 figure 5-6 systick clock control block diagram publication release date: june 21, 2011 - 31 - revision v1.08
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 32 - revision v1.08 5.3.4 peripherals clock the peripherals clock had different clock source switch setting which depends on the different peripheral. 5.3.5 power down mode clock when chip enters into power down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. some clock sources and peripherals clock are still active in power down mode. these clocks which still keep activi ty that are listed as below: z clock generator ? internal 10 khz low speed oscillator clock ? external 32.768 khz low speed crystal clock z peripherals clock (when wdt adopts 10 khz low speed as clock source and rtc adopts 32.768 khz low speed as clock source)
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 33 - revision v1.08 5.4 usb device controller (usb) 5.4.1 overview there is one set of usb 2.0 full-speed device controll er and transceiver in this device. it is compliant with usb 2.0 full-speed device specification and s upport control/bulk/interrupt/isochronous transfer types. in this device controller, there are two main in terfaces: the apb bus and usb bus which comes from the usb phy transceiver. for the apb bus, the cpu can program control registers through it. there are 512 bytes internal sram as data buffer in this c ontroller. for in or out transfer, it is necessary to write data to sram or read data from sram through the apb interface or sie. users need to set the effective starting address of sram for each endpoi nt buffer through ?buffer segmentation register (bufsegx)?. there are six endpoints in this controller. each of the endpoint can be configured as in or out endpoint. all the operations including control, bulk, interrupt and isochronous transfer are implemented in this block. the block of endpoi nt control is also used to manage the data sequential synchronization, endpoint states, current start address, transaction status and data buffer status for each endpoint. there are four different interrupt events in this c ontroller. they are the wake-up function, device plug- in or plug-out event, usb events, like in ac k, out ack etc, and bus events, like suspend and resume, etc. any event will cause an interrupt, and us ers just need to check the related event flags in interrupt event status register (usb_intsts) to acknowledge what ki nd of interrupt occurring, and then check the related usb endpoi nt status register (usb_epsts) to acknowledge what kind of event occurring in this endpoint. a software-disable function is also support for this usb controller. it is used to simulate the disconnection of this device fr om the host. if user enables dr vse0 bit (usb_drvse0), the usb controller will force the output of usb_dp and usb_dm to level low and its function is disabled. after disable the drvse0 bit, host will enumerate the usb device again. reference: universal serial bus specification revision 1.1 5.4.2 features this universal serial bus (usb) performs a serial interface with a single connector type for attaching all usb peripherals to the host system. followi ng is the feature listing of this usb. y compliant with usb 2.0 full-speed specification y provide 1 interrupt vector with 4 different interrupt events (wakeup, fldet, usb and bus) y support control/bulk/interr upt/isochronous transfer type y support suspend function when no bus activity existing for 3 ms y provide 6 endpoints for configurable control/bu lk/interrupt/isochronous transfer types and maximum 512 bytes buffer size y provide remote wake-up capability
numicro ? NUC122 data sheet 5.5 general purpose i/o (gpio) 5.5.1 overview and features numicro ? NUC122 has up to 41 general purpose i/o pins can be shared with other function pins; it depends on the chip configuration. these 41 pins ar e arranged in 4 ports named with gpioa, gpiob, gpioc and gpiod. each port equips maximum 16 pins. each one of the 41 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each of i/o pins can be configured by software individually as input, output, open-drain or quasi-bidirectional mode. after reset, the i/o type of all pins stay in quasi-bidirectional mode and port data register gpiox_dout[15:0] resets to 0x0000_ffff. each i/o pin equips a very weakly individual pull-up resistor which is about 110k ~300k for v dd is from 5.5 v to 2.5 v. 5.5.2 function description 5.5.2.1 input mode explanation set gpiox_pmd (pmdn[1:0]) to 00b the gpiox port [n] pin is in input mode and the i/o pin is in tri- state (high impedance) wit hout output drive capability. the gpiox_pin value reflects the status of the corresponding port pins. 5.5.2.2 output mode explanation set gpiox_pmd ( pmdn[1:0]) to 01b the gpiox port [n] pin is in output mode and the i/o pin supports digital output function with source/sink current capabi lity. the bit value in the corresponding bit [n] of gpiox_dout is driven on the pin. port pin input data port latch data p n vdd figure 5-7 push-pull output publication release date: june 21, 2011 - 34 - revision v1.08
numicro ? NUC122 data sheet 5.5.2.3 open-drain mode explanation set gpiox_pmd (pmdn[1:0]) to 10b the gpiox port [n ] pin is in open-drain mode and the digital output function of i/o pin supports only sink curr ent capability, an additional pull-up resister is needed for driving high state. if the bit value in the corres ponding bit [n] of gpiox_dout is 0, the pin drive a ?low? output on the pin. if the bit value in the corresponding bit [n] of gpiox_dout is 1, the pin output drives high that is controlled by external pull high resistor. port pin port latch data n input data figure 5-8 open-drain output 5.5.2.4 quasi-bidirectional mode explanation set gpiox_pmd (pmdn[1:0]) to 11b the gpiox port [n] pin is in quasi-bidirectional mode and the i/o pin supports digital output and input function at the sa me time but the source current is only up to hundreds ua. before the digital input function is performed the corresponding bit in gpiox_dout must be set to 1. the quasi-bidirectional output is common on the 80c51 and most of its derivatives. if the bit value in the corresponding bit [n] of gpiox_dout is 0, the pin drive a ?low ? output on the pin. if the bit value in the corresponding bit [n] of gpiox_do ut is 1, the pin will check the pin value. if pin value is high, no action takes. if pin state is low, then pin will drive strong high with 2 clock cycles on the pin and then disable the strong out put drive and then the pin status is control by internal pull-up resistor. note that the source cu rrent capability in quasi-bidirectional mode is only about 200 ua to 30 ua for vdd is form 5.0 v to 2.5 v. port pin 2 cpu clock delay input data port latch data pp p n vdd strong very weak weak figure 5-9 quasi-bidirectional i/o mode publication release date: june 21, 2011 - 35 - revision v1.08
numicro ? NUC122 data sheet 5.6 i 2 c serial interface controller (master/slave) (i 2 c) 5.6.1 overview i 2 c is a two-wire, bi-directional serial bus that pr ovides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi-master bus including collision detection and arbitration that prevent s data corruption if two or more masters attempt to control the bus simultaneously. data is transferred between a master and a slave synchronously to scl on the sda line on a byte- by-byte basis. each data byte is 8 bits long. th ere is one scl clock pulse for each data bit with the msb being transmitted first. an acknowledge bit follows each transferred byte. each bit is sampled during the high period of scl; therefore, the sd a line may be changed only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line while scl is high is interpreted as a command (start or stop). please refer to the following figure for more detail i 2 c bus timing. t buf stop sda scl start t hd;sta t low t hd;dat t high t f t su;dat repeated start t su;sta t su;sto stop t r figure 5-10 i 2 c bus timing the device?s on-chip i 2 c logic provides the serial interface that meets the i 2 c bus standard mode specification. the i 2 c port handles byte transfers autonomously. to enable this port, the bit ens1 in i2con should be set to '1'. the i 2 c h/w interfaces to the i 2 c bus via two pins: sda (pa10, serial data line) and scl (pa11, serial clock line). pull up resistor is needed for pin pa10 and pa11 for i 2 c operation as these are open drain pins . when the i/o pins are used as i 2 c port, user must set the pins function to i 2 c in advance. the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus are: y master/slave mode y bidirectional data transfer between masters and slaves y multi-master bus (no central master) y arbitration between simultaneously transmitting mast ers without corruption of serial data on the bus y serial clock synchronization allows devices with different bit rates to communicate via one serial bus y serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer y built-in a 14-bit time-out counter will request the i 2 c interrupt if the i 2 c bus hangs up and timer- out counter overflows. publication release date: june 21, 2011 - 36 - revision v1.08
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 37 - revision v1.08 y external pull-up are needed for high output y programmable clocks allow versatile rate control y supports 7-bit addressing mode y i 2 c-bus controllers support multiple address reco gnition ( four slave address with mask option)
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 38 - revision v1.08 5.7 pwm generator and capture timer (pwm) 5.7.1 overview numicro ? NUC122 only support 1 set of pwm group supports total 2 sets of pwm generators which can be configured as 4 independent pwm outputs, pwm0~pwm3, or as 2 complementary pwm pairs, (pwm0, pwm1) and (pwm2, pwm3) with 2 programmable dead-zone generators. each pwm generator has one 8-bit prescaler, one cl ock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two pwm timers including two clock selectors, two 16-bit pwm down-counters for pwm period control, two 16-bit comparators for pwm duty control and one dead-zone generator. the 4 sets of pwm generators provide eight independent pwm interrupt flags which are set by hardware when the corresponding pwm period down counter reac hes zero. each pwm interrupt source with its corresponding enable bit can cause cpu to request pwm interrupt. the pwm generators can be configured as one-shot mode to produce only one pwm cycle signal or auto-reload mode to output pwm waveform continuously. when pcr.dzen01 is set, pwm0 and pwm1 perfo rm complementary pwm paired function; the paired pwm period, duty and dead-time are determined by pwm0 timer and dead-zone generator 0. similarly, the complementary pwm pairs of (pwm 2, pwm3), are controlled by pwm2, timer and dead-zone generator 2. refer to figures be llowed for the architecture of pwm timers. to prevent pwm driving output pin with unsteady wa veform, the 16-bit period down counter and 16-bit comparator are implemented with double buffer. when user writes data to counter/comparator buffer registers the updated value will be load into the 16-b it down counter/ comparator at the time down counter reaching zero. the double buffering feature avoids glitch at pwm outputs. when the 16-bit period down counter reaches zero, t he interrupt request is generated. if pwm-timer is set as auto-reload mode, when the down counter reaches zero, it is reloaded with pwm counter register (cnrx) automatically t hen start decreasing, repeatedly. if the pwm-timer is set as one-shot mode, the down counter will stop and generate o ne interrupt request when it reaches zero. the value of pwm counter comparator is used for pulse high width modulation. the counter control logic changes the output to high level when do wn-counter value matches the value of compare register. the alternate feature of the pwm-timer is digital input capture function. if capture function is enabled the pwm output pin is switched as capture input mode. the capture0 and pwm0 share one timer which is included in pwm0 and the capture1 and pwm1 share pwm1 timer, and etc. therefore user must setup the pwm-timer before enable capture f eature. after capture feature is enabled, the capture always latched pwm-counter to capture ri sing latch register (crlr) when input channel has a rising transition and latched pwm-counter to capture falling latch register (cflr) when input channel has a falling transition. capture chan nel 0 interrupt is programmable by setting ccr0.crl_ie0[1] (rising latch interrupt enable) and ccr0.cfl_ie0[2]] (falling latch interrupt enable) to decide the condition of interrupt occur. capture channel 1 has the same feature by setting ccr0.crl_ie1[17] and ccr0.cfl_ie1[18]. and capt ure channel 2 to channel 3 on each group have the same feature by setting the corresponding co ntrol bits in ccr2. for each group, whenever capture issues interrupt 0/1/2/3, the pwm c ounter 0/1/2/3 will be reload at this moment. the maximum captured frequency that pwm can captur e is confined by the capture interrupt latency. when capture interrupt occurred, software will do at least three steps, they are: read piirx to get interrupt source and read crlrx/cf lrx(x=0~3) to get capture value and finally write 1 to clear piirx to zero. if interrupt latency will take time t0 to fi nish, the capture signal mustn?t transition during this interval (t0). in this case, the maximum c apture frequency will be 1/t0. for example: hclk = 50 mhz, pwm_clk = 25 mhz, interrupt latency is 900 ns so the maximum capture frequency will is 1/900 ns 1000 khz
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 39 - revision v1.08 5.7.2 features 5.7.2.1 pwm function features: y pwm group has two pwm generators. each pwm generator supports one 8-bit prescaler, one clock divider, two pwm-timers (down counter ), one dead-zone generator and two pwm outputs. y up to 16 bits resolution y pwm interrupt request synchronized with pwm period y one-shot or auto-reload mode pwm y up to 1 pwm group to support 4 pwm channels or 2 pwm paired channels 5.7.2.2 capture function features: y timing control logic shar ed with pwm generators y 4 capture input channels shared with 4 pwm output channels y each channel supports one rising latch register (crlr), one falling latch register (cflr) and capture interrupt flag (capifx)
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 40 - revision v1.08 5.8 real time clock (rtc) 5.8.1 overview real time clock (rtc) controller provides user the real time and calendar message. the clock source of rtc is from an external 32.768 khz low speed crys tal connected at pins x32i and x32o (reference to pin descriptions) or from an external 32.768 khz low speed oscillator output fed at pin x32i. the rtc controller provides the time message (second, minute, hour) in time loading register (tlr) as well as calendar message (day, month, year) in calendar loading register (clr). the data message is expressed in bcd format. it also offers alarm fu nction that user can preset the alarm time in time alarm register (tar) and alarm calendar in calendar alarm register (car). the rtc controller supports periodic time tick and al arm match interrupts. the periodic interrupt has 8 period options 1/128, 1/64, 1/ 32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by ttr (ttr[2:0]). when rtc counter in tlr and clr is eq ual to alarm setting time registers tar and car, the alarm interrupt flag (riir.aif) is set and the alarm interrupt is requ ested if the alarm interrupt is enabled (rier.aier=1). both rtc time tick and alarm match can cause chip be woken-up from power down mode if wake-up function is enabled (twke (ttr[3])=1). 5.8.2 features y there is a time counter (second, minute, hour) and calendar counter (day, month, year) for user to check the time y alarm register (second, minut e, hour, day, month, year) y 12-hour or 24-hour mode is selectable y leap year compensation automatically y day of week counter y frequency compensate register (fcr) y all time and calendar message is expressed in bcd code y support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second y support rtc time tick and alarm match interrupt y support wake-up chip from power down mode
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 41 - revision v1.08 5.9 serial peripheral interface (spi) 5.9.1 overview the serial peripheral interface (spi) is a sync hronous serial data communication protocol which operates in full duplex mode. devices communicate in master/slave mode with 4-wire bi-direction interface. the numicro ? NUC122 contains up to two sets of spi controller performing a serial-to- parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. each set of spi controller can be set as a master that can drive up to 2 external peripheral slave devices; it also can be configured as a slave device controlled by an off-chip master device. this controller also supports a variable serial clock for special application. 5.9.2 features y up to two sets of spi controller for numicro ? NUC122 y support master or slave mode operation y support 1-bit transfer mode y configurable bit length up to 32 bits of a transfe r word and configurable word numbers up to 2 of a transaction, so the maximum bit length is 64 bits for each data transfer y provide burst mode operation, transmit/rec eive can be transferred up to two times word transaction in one transfer y support msb or lsb first transfer y 2 device/slave select lines in master mode, but 1 device/slave select line in slave mode y support byte reorder in data register y support byte or word suspend mode y variable output serial clock frequency in master mode y support two programmable serial clock frequencies in master mode y support fifo mode
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 42 - revision v1.08 5.10 timer controller (tmr) 5.10.1 overview the timer controller includes four 32-bit timers , timer0~timer3, which allows user to easily implement a timer control for applications. the timer can perform functions like frequency measurement, event counting, inte rval measurement, clock generati on, delay timing, and so on. the timer can generates an interrupt signal upon timeout, or provide the current value during operation. 5.10.2 features ? 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter ? independent clock source for each timer ? provides one-shot, periodic, toggle an d continuous counting operation modes ? time out period = (period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit tcmp) ? maximum counting cycle time = (1 / t mhz) * (2 8 ) * (2 24 ), t is the period of timer clock ? 24-bit timer value is readable through tdr (timer data register) ? support event counting function to count the event from external pin
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 43 - revision v1.08 5.11 watchdog timer (wdt) the purpose of watchdog timer is to perform a system reset when system runs into an unknown state. this prevents system from hanging for an infinite period of time. besides, this watchdog timer supports another function to wake-up chip from power down mode. the watchdog timer includes an 18-bit free running counter with programmable time-out intervals. table 5-4 show the watchdog timer time-out interval selection and figure 5-11 shows the timing of watchdog interrupt signal and reset signal. setting wte (wdtcr [7]) enables the watchdog time r and the wdt counter starts counting up. when the counter reaches the selected time-out interv al, watchdog timer interrupt flag wtif will be set immediately to request a wdt interrupt if the watc hdog timer interrupt enable bit wtie is set, in the meanwhile, a specified delay time (1024 * t wdt ) follows the time-out event. user must set wtr (wdtcr [0]) (watchdog timer reset) high to rese t the 18-bit wdt counter to avoid chip from watchdog timer reset before the delay time expire s. wtr bit is cleared automatically by hardware after wdt counter is reset. there are eight time-out intervals with specific delay time which are selected by watchdog timer interval select bits wtis (wdtcr [10:8]). if the wdt counter has not been cleared after the specific delay time expires, the watchdog timer will set watchdog timer reset flag (wtrf) high and reset chip. this reset will last 63 wdt clocks (t rst ) then chip restarts executing program from reset vector (0x0000_0000). wtrf will not be cleared by watchdog reset. user may poll wtrf by software to recognize the reset source. wdt also provides wake-up function. when chip is powered down and the watchdog timer wake -up function enable bit (wdtr[4]) is set, if the wdt counter reaches the specific time interval defined by wtis (wdtcr [10:8]) , the chip is woken- up from power down state. first example, if wtis is set as 000, the specific time interval for chip to be woken-up from power down state is 2 4 * t wdt . when power down command is set by software, then, chip enters power down state. after 2 4 * t wdt time is elapsed, chip is woken-up from power down state. second example, if wtis (wd tcr [10:8]) is set as 111, the specif ic time interval for chip to be woken-up from power down state is 2 18 * t wdt . if power down command is set by software, then, chip enters power down state. after 2 18 * t wdt time is elapsed, chip is woken-up from power down state. notice if wtre (wdtcr [1]) is set to 1, after ch ip is woken-up, software should clear the watchdog timer counter by setting wtr(wdtc r [0]) to 1 as soon as possible. otherwise, if the watchdog timer counter is not cleared by setting wtr (wdtcr [0 ]) to 1 before time starting from waking up to software clearing watchdog timer counter is over 1024 * t wdt , the chip is reset by watchdog timer. table 5-4 watchdog timer time-out interval selection wtis time-out interval selection t tis interrupt period t int wtr time-out interval (wdt_clk=10 khz) min. t wtr ~ max. t wtr 000 2 4 * t wdt 1024 * t wdt 1.6 ms ~ 104 ms 001 2 6 * t wdt 1024 * t wdt 6.4 ms ~ 108.8 ms 010 2 8 * t wdt 1024 * t wdt 25.6 ms ~ 128 ms 011 2 10 * t wdt 1024 * t wdt 102.4 ms ~ 204.8 ms 100 2 12 * t wdt 1024 * t wdt 409.6 ms ~ 512 ms 101 2 14 * t wdt 1024 * t wdt 1.6384 s ~ 1.7408 s 110 2 16 * t wdt 1024 * t wdt 6.5536 s ~ 6.656 s 111 2 18 * t wdt 1024 * t wdt 26.2144 s ~ 26.3168 s
numicro ? NUC122 data sheet t tis rst int 1024 * t wdt 63 * t wdt minimum t wtr t int t rst maximum t wtr t wdt t wdt : watchdog engine clock time period t tis : watchdog timeout interval selection period t int : watchdog interrupt period t rst : watchdog reset period t wtr : watchdog timeout interval period figure 5-11 timing of interrupt and reset signals 5.11.1 features z 18-bit free running counter to avoid chip from watchdog timer reset before the delay time expires. z selectable time-out interval (2^4 ~ 2^18) and the time-out interval is 104 ms ~ 26.3168 s (if wdt_clk = 10 khz). z reset period = (1 / 10 khz) * 63, if wdt_clk = 10 khz. publication release date: june 21, 2011 - 44 - revision v1.08
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 45 - revision v1.08 5.12 uart interface controller (uart) numicro ? NUC122 provides two channels of univer sal asynchronous receiver/transmitters (uart0/1). both of uart0 and uart1 perform normal speed uart, besides, uart0 and uart1 also support flow control function. 5.12.1 overview the universal asynchronous receiver/transmitter (uart0/1) performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the cpu. the uart controller also supports irda si r function and rs-485 mode functions. each uart channel supports seven types of interrupts including transmitter fifo empty interrupt (int_thre), receiver threshold level reaching interrupt (int_rda), line status interrupt (par ity error or framing error or break interrupt) (int_rls), receiver buffer time-out interrupt (int _tout), modem/wake-up status interrupt (int_modem), buffer error interr upt (int_buf_err). interrupt number 13 (vector number is 29) supports uart0/1 interrupt. refer to nested vectored interrupt controller chapter for system interrupt map. the uart0/1 are equipped 16-byte transmitter fi fo (tx_fifo) and 16-byte receiver fifo (rx_fifo). the cpu can read the st atus of the uart at any time during the operation. the reported status information includes the type and condition of the transfer operations being performed by the uart, as well as 4 error conditions (parity erro r, framing error, break interrupt and buffer error) probably occur while receiving data. the uart includes a programmable baud rate generator that is capable of dividing clock input by divisors to prod uce the serial clock that transmitter and receiver need. the baud rate equation is baud rate = ua rt_clk / m * [brd + 2], where m and brd are defined in baud rate divider register (ua_baud). below table lists the equations in the various conditions and the uart baud rate setting table. table 5-5 uart baud rate equation mode div_x_en div_x_one divider x brd baud rate equation 0 0 0 b a uart_clk / [16 * (a+2)] 1 1 0 b a uart_clk / [(b+1) * (a+2)] , b must >= 8 2 1 1 don?t care a uart_clk / (a+2), a must >=3 table 5-6 uart baud rate setting table system clock = 22.1184 mhz high speed baud rate mode0 mode1 mode2 921600 x a=0,b=11 a=22 460800 a=1 a=1,b=15 a=2,b=11 a=46 230400 a=4 a=4,b=15 a=6,b=11 a=94 115200 a=10 a=10,b=15 a=14,b=11 a=190 57600 a=22 a=22,b=15 a=30,b=11 a=382
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 46 - revision v1.08 system clock = 22.1184 mhz high speed baud rate mode0 mode1 mode2 38400 a=34 a=62,b=8 a=46,b=11 a=34,b=15 a=574 19200 a=70 a=126,b=8 a=94,b=11 a=70,b=15 a=1150 9600 a=142 a=254,b=8 a=190,b=11 a=142,b=15 a=2302 4800 a=286 a=510,b=8 a=382,b=11 a=286,b=15 a=4606 the uart0/1 controllers support auto-flow control function that uses two low-level signals, /cts (clear-to-send) and /rts (request-to -send), to control the flow of da ta transfer between the uart and external devices (ex: modem). when auto-flow is enabled, the uart is not allowed to receive data until the uart asserts /rts to external device. w hen the number of bytes in the rx fifo equals the value of rts_tri_lev (ua_fcr [19:16]), the /rts is de-asserted. the uart sends data out when uart controller detects /cts is asserted from exte rnal device. if a valid asserted /cts is not detected the uart controller will not send data out. the uart controllers also provides serial irda (s ir, serial infrared) function (user must set irda_en (ua_fun_sel [1]) to enable irda function). the sir specification defines a short-range infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. the maximum data rate is 115.2 kbps (half duplex). the irda sir block contains an irda sir protocol encoder/decoder. the irda sir protocol is half-duplex only. so it cannot transmit and receive data at the same time. the irda sir physical layer sp ecifies a minimum 10 ms transfer delay between transmission and reception. this delay feat ure must be implemented by software. for numicro ? NUC122, another alternate func tion of uart controllers is rs-485 9-bit mode function, and direction control provided by rts pin or can program gpio (pb.2 for rts0 and pb.6 for rts1) to implement the function by software. the rs -485 mode is selected by setting the ua_fun_sel register to select rs-485 function. the rs-485 dr iver control is implemented using the rts control signal from an asynchronous serial port to en able the rs-485 driver. in rs-485 mode, many characteristics of the rx and tx are same as uart.
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 47 - revision v1.08 5.12.2 features z full duplex, asynchronous communications z separate receive / transmit 16 byte s entry fifo for data payloads z support hardware auto flow control/flow cont rol function (cts, rts) and programmable rts flow control trigger level z programmable receiver buffer trigger level z support programmable baud-rate generator for each channel individually z support cts wake-up function z support 8 bits receiver buffer time-out detection function z programmable transmitting data delay time between the last stop and the next start bit by setting ua_tor [dly] register z support break error, frame error, parity e rror and receive / transmit buffer overflow detect function z fully programmable serial-interface characteristics ? programmable number of data bit, 5, 6, 7, 8 bits character ? programmable parity bit, even, odd, no parity or stick parity bit generation and detection ? programmable stop bit, 1, 1.5, or 2 stop bits generation z support irda sir function mode ? support for 3/16 bits duration for normal mode z support rs-485 function mode. ? support rs-485 9-bit mode ? support hardware or software direct enable control provided by rts pin
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 48 - revision v1.08 5.13 ps/2 device controller (ps2d) 5.13.1 overview ps/2 device controller provides basic timing cont rol for ps/2 communication. all communication between the device and the host is managed throug h the clk and data pins. unlike ps/2 keyboard or mouse device controller, the received/transmit code needs to be translated as meaningful code by firmware. the device controller generates the clk si gnal after receiving a request to send, but host has ultimate control over communication. data sent fr om the host to the device is read on the rising edge and data sent from device to the host is change after rising edge. a 16 bytes fifo is used to reduce cpu intervention. s/w can select 1 to 16 bytes for a continuous transmission. 5.13.2 features y host communication inhibit and request to send detection y reception frame error detection y programmable 1 to 16 bytes transmit buffer to reduce cpu intervention y double buffer for data reception y s/w override bus
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 49 - revision v1.08 6 flash memory controller (fmc) 6.1 overview numicro ? NUC122 equips with 64/32k bytes on chip embedded flash for application program memory (aprom) that can be updated through isp pr ocedure. in system programming (isp) function enables user to update program memory when chip is soldered on pcb. after chip power on, cortex ? - m0 cpu fetches code from aprom or ldrom decided by boot select (cbs) in config0. by the way, numicro ? NUC122 also provides additional data flash for user, to store some application dependent data before chip power off. for 64k/32k bytes aprom device, the data flash is fixed at 4k bytes. 6.2 features z run up to 60 mhz with zero wait state for continuous address read access z 64/32kb application program memory (aprom) z 4kb in system programming (isp) loader program memory (ldrom) z fixed 4kb data flash with 512 bytes page erase unit z in system program (isp) to update on chip flash
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 50 - revision v1.08 7 electrical characteristics 7.1 absolute maximum ratings symbol parameter min. max. unit dc power supply vdd? vss -0.3 +7.0 v input voltage vin vss-0.3 vdd+0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature ta -40 +85 c storage temperature tst -55 +150 c maximum current into vdd - 120 ma maximum current out of vss 120 ma maximum current sunk by a i/o pin 35 ma maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions bey ond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 51 - revision v1.08 7.2 dc electrical characteristics 7.2.1 numicro ? NUC122 dc electrical characteristics (v dd -v ss =3.3 v, ta = 25 c, fosc = 60 mhz unless otherwise specified.) specification parameter sym. min. typ. max. unit test conditions operation voltage v dd 2.5 5.5 v v dd =2.5 v ~ 5.5 v up to 60 mhz ldo output voltage v ldo 1.6 1.8 2.1 v v dd R 2.5 v analog operating voltage av dd 0 v dd v i dd1 26 ma v dd = 5.5 v @ 60 mhz, enable all ip and pll, xtal=12 mhz i dd2 21 ma v dd = 5.5 v @ 60 mhz, disable all ip and enable pll, xtal=12 mhz i dd3 24 ma v dd = 3.3 v @ 60 mhz, enable all ip and pll, xtal=12 mhz operating current normal run mode @ 60 mhz i dd4 19 ma v dd = 3.3 v @ 60 mhz, disable all ip and enable pll, xtal=12 mhz i dd5 6.5 ma v dd = 5.5 v @ 12mhz, enable all ip and disable pll, xtal=12 mhz i dd6 5 ma v dd = 5.5 v @ 12 mhz, disable all ip and pll, xtal=12 mhz i dd7 4.5 ma v dd = 3.3 v @ 12 mhz, enable all ip and disable pll, xtal=12 mhz operating current normal run mode @ 12 mhz i dd8 3.5 ma v dd = 3.3 v @ 12 mhz, disable all ip and pll, xtal=12 mhz operating current normal run mode i dd9 3.5 ma v dd = 5.5 v @ 4 mhz, enable all ip and disable pll, xtal=4 mhz
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 52 - revision v1.08 specification parameter sym. min. typ. max. unit test conditions i dd10 3 ma v dd = 5.5 v @ 4 mhz, disable all ip and pll, xtal=4 mhz i dd11 3 ma v dd = 3.3 v @ 4 mhz, enable all ip and disable pll, xtal=4 mhz @ 4 mhz i dd12 2 ma v dd = 3.3 v @ 4 mhz, disable all ip and pll, xtal=4 mhz i idle1 17 ma v dd = 5.5 v @ 60 mhz, enable all ip and pll, xtal=12 mhz i idle2 12 ma v dd = 5.5 v @ 60 mhz, disable all ip and enable pll, xtal=12 mhz i idle3 15 ma v dd = 3.3 v @ 60 mhz, enable all ip and pll, xtal=12 mhz operating current idle mode @ 60 mhz i idle4 11 ma v dd = 3.3 v @ 60 mhz, disable all ip and enable pll, xtal=12 mhz i idle5 4.5 ma v dd = 5.5 v @ 12 mhz, enable all ip and disable pll, xtal=12 mhz i idle6 3.5 ma v dd = 5.5 v @ 12 mhz, disable all ip and pll, xtal=12 mhz i idle7 3 ma v dd = 3.3 v @ 12 mhz, enable all ip and disable pll, xtal=12 mhz operating current idle mode @ 12 mhz i idle8 2 ma v dd = 3.3 v @ 12 mhz, disable all ip and pll, xtal=12 mhz i idle9 3 ma v dd = 5.5 v @ 4 mhz, enable all ip and disable pll, xtal=4 mhz i idle10 2.5 ma v dd = 5.5 v @ 4 mhz, disable all ip and pll, xtal=4 mhz operating current idle mode @ 4 mhz i idle11 2 ma v dd = 3.3 v @ 4 mhz, enable all ip and disable pll, xtal=4 mhz
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 53 - revision v1.08 specification parameter sym. min. typ. max. unit test conditions i idle12 1 ma v dd = 3.3 v @ 4 mhz, disable all ip and pll, xtal=4 mhz i pwd1 13 a v dd = 5.5 v, rtc off, no load @ disable bov function i pwd2 12 a v dd = 3.3 v, rtc off, no load @ disable bov function i pwd3 15 a v dd = 5.5 v, rtc run , no load @ disable bov function standby current power down mode i pwd4 13 a v dd = 3.3 v, rtc run , no load @ disable bov function input current pa, pb, pc, pd (quasi-bidirectional mode) i in1 -60 - +15 a v dd = 5.5 v, v in = 0 v or v in =v dd input current at /reset [1] i in2 -55 -45 -30 a v dd = 3.3 v, v in = 0.45 v input leakage current pa, pb, pc, pd i lk -2 - +2 a v dd = 5.5 v, 0 numicro ? NUC122 data sheet publication release date: june 21, 2011 - 54 - revision v1.08 specification parameter sym. min. typ. max. unit test conditions i sr22 -4 -6 -8 ma v dd = 2.7 v, v s = 2.2 v pd (push-pull mode) i sr22 -3 -5 -7 ma v dd = 2.5 v, v s = 2.0 v i sk1 10 17 20 ma v dd = 4.5 v, v s = 0.45 v i sk1 7 10 13 ma v dd = 2.7 v, v s = 0.45 v sink current pa, pb, pc, pd(quasi-bidirectional and push-pull mode) i sk1 6 9 12 ma v dd = 2.5 v, v s = 0.45 v brownout voltage with bov_vl [1:0] =00b v bo2.2 2.1 2.2 2.3 v brownout voltage with bov_vl [1:0] =01b v bo2.7 2.6 2.7 2.8 v brownout voltage with bov_vl [1:0] =10b v bo3.8 3.6 3.75 3.9 v brownout voltage with bov_vl [1:0] =11b v bo4.5 4.2 4.4 4.6 v hysteresis range of bod voltage v bh 30 - 150 mv v dd = 2.5 v ~ 5.5 v note: 1. /reset pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. pins of pa, pb, pc and pd can source a transition current w hen they are being externally driven from 1 to 0. in the conditio n of v dd =5.5 v, the transition current reaches its maximum value when v in approximates to 2 v.
numicro ? NUC122 data sheet 7.3 ac electrical characteristics 7.3.1 external 4~24 mhz high speed crystal ac electrical characteristics t clcl t clcx t chcx t clch t chcl note: duty cycle is 50 %. symbol parameter condition min. typ. max. unit t chcx clock high time 20 - - ns t clcx clock low time 20 - - ns t clch clock rise time - - 10 ns t chcl clock fall time - - 10 ns 7.3.2 external 4~24 mhz high speed crystal parameter condition min. typ. max. unit input clock frequency external crystal 4 12 24 mhz temperature - -40 - 85 7.3.2.1 typical crystal application circuits crystal c1 c2 r 4 mhz ~ 24 mhz without without without error! objects cannot be created from editing field codes. figure 7-1 typical crystal application circuit 7.3.3 external 32.768 khz low speed crystal parameter condition min. typ. max. unit input clock frequency external crystal - 32.768 - khz temperature - -40 - 85 publication release date: june 21, 2011 - 55 - revision v1.08
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 56 - revision v1.08 7.3.4 internal 22.1184 mhz high speed oscillator parameter condition min. typ. max. unit center frequency - - 22.1184 - mhz +25 ; v dd = 3.3 v -1 - +1 % calibrated internal oscillator frequency -40 ~ +85 ; v dd = 2.5 v ~ 5.5 v -5 - +5 % 7.3.5 internal 10 khz low speed oscillator parameter condition min. typ. max. unit center frequency - - 10 - khz +25 ; v dd = 5 v -30 - +30 % calibrated internal oscillator frequency -40 ~ +85 ; v dd = 2.5 v ~ 5.5 v -50 - +50 %
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 57 - revision v1.08 7.4 analog characteristics 7.4.1 specification of ldo & power management parameter min. typ. max. unit note input voltage 2.5 5 5.5 v v dd input voltage output voltage 1.6 1.8 2.1 v v dd 2.5 v temperature -40 25 85 quiescent current (pd=0) - 100 - a quiescent current (pd=1) - 5 - a iload (pd=0) - - 100 ma iload (pd=1) - - 100 a cbp - 4.7 - f resr=1 ohm note: 1. it is recommended that a 10 f or higher capacitor and a 100 nf bypass capacitor are connected between vdd and the closest vss pin of the device. 2. for ensuring power stability, a 4.7 f or higher capacitor must be connected between ldo pin and the closest vss pin of the device.
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 58 - revision v1.08 7.4.2 specification of low voltage reset parameter condition min. typ. max. unit quiescent current v dd =5.5 v - - 5 a temperature - -40 25 85 temperature=25 1.7 2.0 2.3 v temperature=-40 - - v threshold voltage temperature=85 - - v hysteresis - 0 0 0 v 7.4.3 specification of brownout detector parameter condition min. typ. max. unit quiescent current av dd =5.5 v - - 140 a temperature - -40 25 85 bov_vl[1:0]=11 4.2 4.4 4.6 v bov_vl [1:0]=10 3.6 3.75 3.9 v bov_vl [1:0]=01 2.6 2.7 2.8 v brownout voltage bov_vl [1:0]=00 2.1 2.2 2.3 v hysteresis - 30 - 150 mv 7.4.4 specification of power-on reset (5 v) parameter condition min. typ. max. unit temperature - -40 25 85 reset voltage v+ - 2 - v quiescent current vin>reset voltage - 1 - na
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 59 - revision v1.08 7.4.5 specification of usb phy 7.4.5.1 usb dc electrical characteristics symbol parameter conditions min. typ. max. unit v ih input high (driven) 2.0 v v il input low 0.8 v v di differential input sensitivity |padp-padm| 0.2 v v cm differential common-mode range includes v di range 0.8 2.5 v v se single-ended receiver threshold 0.8 2.0 v receiver hysteresis 200 mv v ol output low (driven) 0 0.3 v v oh output high (driven) 2.8 3.6 v v crs output signal cross voltage 1.3 2.0 v r pu pull-up resistor 1.425 1.575 k ? r pd pull-down resistor 14.25 15.75 k ? v trm termination voltage for upstream port pull up (rpu) 3.0 3.6 v z drv driver output resistance steady state drive* 10 ? c in transceiver capacitance pin to gnd 20 pf *driver output resistance doesn?t in clude series resistor resistance. 7.4.5.2 usb full-speed driver electrical characteristics symbol parameter conditions min. typ. max. unit t fr rise time c l =50p 4 20 ns t ff fall time c l =50p 4 20 ns t frff rise and fall time matching t frff =t fr /t ff 90 111.11 % 7.4.5.3 usb power dissipation symbol parameter conditions min. typ. max. unit standby 50 a input mode a i vddreg (full speed) v ddd and v ddreg supply current (steady state) output mode a
numicro ? NUC122 data sheet 7.5 spi dynamic characteristics 7.5.1 dynamic characteristics of data input and output pin symbol parameter min. typ. max. unit spi master mode (vdd = 4.5 v ~ 5.5 v, 30 pf loading capacitor) t ds data setup time 16 10 - ns t dh data hold time 0 - - ns t v data output valid time - 5 8 ns spi master mode (vdd = 3.0 v ~ 3.6 v, 30 pf loading capacitor) t ds data setup time 20 13 - ns t dh data hold time 0 - - ns t v data output valid time - 7 14 ns spi slave mode (vdd = 4.5 v ~ 5.5 v, 30 pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+4 - - ns t v data output valid time - 2*pclk+11 2*pclk+20 ns spi slave mode (vdd = 3.0 v ~ 3.6 v, 30 pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+8 - - ns t v data output valid time - 2*pclk+20 2*pclk+32 ns figure 7-2 spi master mode timing publication release date: june 21, 2011 - 60 - revision v1.08
numicro ? NUC122 data sheet figure 7-3 spi slave mode timing publication release date: june 21, 2011 - 61 - revision v1.08
numicro ? NUC122 data sheet 8 package dimensions 8.1 64l lqfp (7x7x1.4mm footprint 2.0 mm) publication release date: june 21, 2011 - 62 - revision v1.08
numicro ? NUC122 data sheet 8.2 48l lqfp (7x7x1.4mm footprint 2.0mm) publication release date: june 21, 2011 - 63 - revision v1.08
numicro ? NUC122 data sheet 8.3 33l qfn (5x5x0.8mm) 1 8 8 9 16 1 16 17 17 9 24 24 32 25 25 32 publication release date: june 21, 2011 - 64 - revision v1.08
numicro ? NUC122 data sheet publication release date: june 21, 2011 - 65 - revision v1.08 9 revision history version date page/ chap. description v1.00 nov. 15, 2010 - preliminary version initial issued v1.01 dec. 7, 2010 chap. 3 corrected the selection guide table for qfn33. v1.02 jan. 13, 2011 chap. 5 chap. 7 1. corrected the watchdog timer clock source selection 2. corrected the electrical characteristics. v1.03 march 14, 2011 chap. 3 chap. 7 chap. 8 1. added the lqfp 64-pin part number for 7x7x1.4mm package. (NUC122sd2an, NUC122sc1an) 2. corrected the lqfp 64-pin pin diagram. 3. updated dc and ac e lectrical characteristics and added the spi dynamic characteristics. 4. updated lqfn 48-pin package dimensions. v1.04 march 31, 2011 chap. 2 chap. 3 chap. 4 chap. 5 chap. 8 1. removed the lqfp 64-pin part number for 10x10x1.4mm package. 2. replaced ?12 mhz? with ?4~24 mhz? in some contents and block diagrams. v1.05 apr.29 , 2011 chap. 1 chap. 2 chap. 3 chap. 5 chap. 7 1. updated the table of s pecification of ldo and power management. 2. removed the lin function from uart controller. 3. corrected the ?pwm_ crlx/pwm_cflx(x=0~3)? to ?crlrx/cflrx(x=0~3)? in the ov erview of pwm generator and capture timer chapter. 4. corrected the ?1xx? to ?111? in system clock and systick clock control block diagram. 5. added the clock generator global view diagram. 6. corrected the ?rx0/1? and ?tx0/1? to ?rxd0/1? and ?txd0/1? in pin configuration and pin description. v1.06 may 30, 2011 chap. 3 all 1. corrected the pin description of pins 17 and 18 for lqfp 48-pin. 2. corrected the typo of year on the footer. v1.07 june 8, 2011 chap. 2 chap. 7 1. corrected the trimmed condition for the internal 22.1184 mhz high speed oscillator in the ?clock control? item of feature list. 2. corrected the specif ication of the ?inter nal 22.1184 mhz high speed oscillator?. v1.08 june 21, 2011 chap. 2 1. added the condition and corrected the speed of spi in master/slave mode in the ? spi? item of feature list.
numicro ? NUC122 data sheet important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, ?insecure usage?. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for ve hicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customer?s risk, and in the event that third parties lay claims to nuvoton as a result of customer?s insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton. publication release date: june 21, 2011 - 66 - revision v1.08

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