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www.ams.com/dc-dc_step-up/as1324 revision 1.06 1 - 21 a s1 3 2 4 1 .5 m h z, 6 0 0m a s yn ch r o n o u s d c/ dc c o n v e r te r 1 general description the as1324 is a high-efficiency, constant-frequency synchronous buck converter available in adjustable- and fixed-v oltage versions. the wide input voltage range (2.7v to 5.5v), automa tic powersave mode and minimal external component requirements ma ke the as1324 perfect for any single li-ion battery-powere d application. typical supply current with no load is 30a and dec reases to 1a in shutdown mode. the as1324 is available as the standard versions li sted in table 1 . an internal synchronous switch increases efficiency and eliminates the need for an external schottky diode. the intern ally fixed switching frequency (1.5mhz) allows for the use of small surface mount external components. very low output voltages can be delivered with the internal 0.6v feedback reference voltage. the as1324 is available in a 5-pin tsot-23 package. figure 1. typical application diagram C high effic iency step down converter 2 key features high efficiency: up to 96% output current: 600ma input voltage range: 2.7v to 5.5v constant frequency operation: 1.5mhz variable- and fixed-output voltages no schottky diode required automatic powersave operation low quiescent current: 30a internal reference: 0.6v shutdown mode supply current: 1a thermal protection 5-pin tsot-23 package 3 applications the device is ideal for mobile communication device s, laptops and pdas, ultra-low-power systems, threshold detectors/ discriminators, telemetry and remote systems, medical instruments, or any other space-limited application with low power-consumptio n requirements. table 1. standard versions model output voltage as1324-ad adjustable via external resistors as1324-12 fixed: 1.2v as1324-15 fixed: 1.5v as1324-18 fixed: 1.8v as1324-18 c out 10f c in 10f gnd 2 v in = 2.7v to 5.5v v out = 1.8v, 600ma 4.7h 1 en 5 vout 4 vin 3 sw 5 v out as1324-18 4 v in 2 gnd 3 sw 1 en
www.ams.com/dc-dc_step-up/as1324 revision 1.06 2 - 21 as1324 datasheet - p i n a s s i g n m e n t s 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 2. pin descriptions pin number pin name description 1 en enable input . driving this pin above 1.5v enables the device. d riving this pin below 0.3v puts the device in shutdown mode. in shutdown mode all funct ions are disabled while sw goes high impedance, drawing <1a supply current. note: this pin should not be left floating. 2 gnd ground. 3 sw switch node connection to inductor. this pin connects to the drains of the internal ma in and synchronous power mosfet switches. 4 v in input supply voltage . this pin must be closely decoupled to gnd with a 3 4.7f ceramic capacitor. connect to any supply voltage between 2.7 to 5.5v. 5 v fb feedback pin . this pin receives the feedback voltage from the e xternal resistor divider across the output. (adjustable voltage variant only.) v out output voltage feedback pin . an internal resistor divider steps the output vol tage down for comparison to the internal reference voltage. (fixe d voltage variants only.) 5 v fb as1324 4 v in 2 gnd 3 sw 1 en 5 v out as1324-12/ as1324-15/ as1324-18 4 v in 2 gnd 3 sw 1 en
www.ams.com/dc-dc_step-up/as1324 revision 1.06 3 - 21 as1324 datasheet - a b s o l u t e m a x i m u m r a t i n g s 5 absolute maximum ratings stresses beyond those listed in table 3 may cause permanent damage to the device. these ar e stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in section 6 electrical characteristics on page 4 is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. table 3. absolute maximum ratings parameter min max units comments vin to gnd -0.3 6 v sw, en, fb to gnd -0.3 v in + 0.3 v thermal resistance q ja 207.4 oc/w on pcb esd 2 kv hbm mil-std. 883e 3015.7 methods latch-up -100 +100 ma jedec 78 operating temperature range -40 +85 oc storage temperature range -65 +125 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020 moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices. the lead finish for pb-free leaded packages is matt e tin (100% sn). junction temperature 125 oc junction temperature (t j ) is calculated from the ambient temperature (t amb ) and power dissipation (pd) as: t j = t amb + (pd)(207.4oc/w) (eq 1) moisture sensitive level 1 represents an unlimited fl oor life time
www.ams.com/dc-dc_step-up/as1324 revision 1.06 4 - 21 as1324 datasheet - e l e c t r i c a l c h a r a c t e r i s t i c s 6 electrical characteristics v in = en = 3.6v, v out < v in - 0.5v, t amb = -40 to +85c, typ. values @ t amb = +25oc (unless otherwise specified) . note: all limits are guaranteed. the parameters with min and max values are guaranteed with production tests or sqc (statistical quality control) methods. table 4. electrical characteristics symbol parameter conditions min typ max units v in input voltage range 2.7 5.5 v i q quiescent current powersave mode; v fb = 0.62v or v out = 103%, i out = 0ma, t amb = +25oc 30 35 a i shdn shutdown current shutdown mode; v en = 0v, t amb = +25oc 0.1 1 regulation v fb regulated feedback voltage 1 1. the device is tested in a proprietary test mode w here v fb is connected to the output of the error amplifier. as1324, i out = 100ma 0.585 0.6 0.615 v d v fb reference voltage line regulation v in = 2.7v to 5.5v 0.1 1 %/v i vfb feedback current t amb = +25oc -30 30 na v out regulated output voltage as1324-ad, i out = 100ma 2 2. please see feedback resistor selection on page 13 for resistor values. v fb v as1324-12, i out = 100ma 1.164 1.20 1.236 as1324-15, i out = 100ma 1.455 1.50 1.545 as1324-18, i out = 100ma 1.746 1.80 1.854 d v out output voltage line regulation v in = 2.7 to 5.5v 0.1 1 %/v v loadreg output voltage load regulation i out = 0 to 100ma 0.02 %/ma dc-dc switches i pk peak inductor current v in = 3v, v fb = 0.5v or v out = 90%, t amb = 25oc 0.5 0.75 1 a r pfet p-channel fet r ds(on) i lsw = 100ma 0.4 w r nfet n-channel fet r ds(on) i lsw = -100ma 0.35 w i lsw sw leakage v en = 0v, v sw = 0v or 5v 0.01 1 a control inputs v en en threshold 0.3 1 1.5 v i en en leakage current 0.01 1 a oscillator f osc oscillator frequency v fb = 0.6v or v out = 100% 1.2 1.5 1.8 mhz v fb = 0v or v out = 0v, t amb = 25oc 115 khz
www.ams.com/dc-dc_step-up/as1324 revision 1.06 5 - 21 as1324 datasheet - ty p i c a l o p e r a t i n g c h a r a c t e r i s t i c s 7 typical operating characteristics parts used for measurement: 4.7h (mos6020-472) ind uctor, 10f (grm188r60j106me47) c in and c out . figure 3. efficiency vs. input voltage; v out = 1.8v figure 4. efficiency vs. output current; v out = 1.2v 50 55 60 65 70 75 80 85 90 95 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) efficiency (%) . iout = 600ma iout = 100ma iout = 10ma iout = 1ma 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 output current (ma) efficiency (%) . vin = 2.5v vin = 2.7v vin = 3.7v vin = 4.2v vin = 5.5v figure 5. efficiency vs. output current; v out = 1.5v figure 6. efficiency vs. output current; v out = 1.8v 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 output current (ma) efficiency (%) . vin = 2.5v vin = 2.7v vin = 3.7v vin = 4.2v vin = 5.5v 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 output current (ma) efficiency (%) . vin = 2.5v vin = 2.7v vin = 3.7v vin = 4.2v vin = 5.5v figure 7. efficiency vs. output current; v out = 2.5v figure 8. efficiency vs. output current; v out = 3.3v 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 output current (ma) efficiency (%) . vin = 3.7v vin = 4.2v vin = 5.5v 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 output current (ma) efficiency (%) . vin = 4.2v vin = 5.5v
www.ams.com/dc-dc_step-up/as1324 revision 1.06 6 - 21 as1324 datasheet - ty p i c a l o p e r a t i n g c h a r a c t e r i s t i c s figure 9. switching frequency vs. supply voltage fi gure 10. switching frequency vs. temperature 1.4 1.45 1.5 1.55 1.6 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) switching frequency (mhz) . 1.4 1.45 1.5 1.55 1.6 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) switching frequency (mhz) . figure 11. feedback voltage vs. temperature figure 12. output voltage vs. input voltage 0.59 0.595 0.6 0.605 0.61 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) feedback voltage (v) . 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) output voltage (v) . iout = 600ma iout = 100ma iout = 10ma iout = 1ma iout = 100a figure 13. v out vs. i out ; v outnom = 1.2v figure 14. v out vs. i out ; v outnom = 1.5v 1.1 1.15 1.2 1.25 1.3 0 100 200 300 400 500 600 output current (ma) output voltage (v) . vin=2.5v vin=2.7v vin=5.5v 1.4 1.45 1.5 1.55 1.6 0 100 200 300 400 500 600 output current (ma) output voltage (v) . vin=2.5v vin=2.7v vin=5.5v
www.ams.com/dc-dc_step-up/as1324 revision 1.06 7 - 21 as1324 datasheet - ty p i c a l o p e r a t i n g c h a r a c t e r i s t i c s figure 15. quiescent current vs. input voltage figu re 16. quiescent current vs. temperature 0 5 10 15 20 25 30 35 40 45 50 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) quiescent current (a) . 0 5 10 15 20 25 30 35 40 45 50 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) quiescent current (a) . figure 17. load step 0ma to 600ma figure 18. load step 10ma to 200ma i sw v out i out 500ma/div 200mv/div 500s/div 600ma/div 500ma/div 200mv/div i sw 500s/div v out i out 200ma/div figure 19. startup figure 20. powersave mode 560ma/div 5v/div en i sw 1ms/div v out 1v/div 100mv/div 5v/div v sw i sw 5s/div v out 200ma/div
www.ams.com/dc-dc_step-up/as1324 revision 1.06 8 - 21 as1324 datasheet - d e t a i l e d d e s c r i p t i o n 8 detailed description the as1324 is a high-efficiency buck converter that uses a constant-frequency current-mode architectur e. the device contains two internal mosfet switches and is available in adjustable- and fixed-output voltage versions. figure 21. as1324 - block diagram as1324 osc frequency shift 0.6v reference + C error amp shutdown ramp compensator r 2 0.6v fb oscn digital logic 0.6v + d v ovl 0.6v - d v ovl C ovdet + C + C icomp + C ircmp + anti- shoot through not applicable to as1324 as1324-12: r 1 + r 2 = 600k w as1324-15: r 1 + r 2 = 750k w as1324-18: r 1 + r 2 = 900k w r 1 pmos 1 en 5 v out /v fb 4v in 3 sw 2 gnd nmos c out 10f v out 4.7h c in 10f v in
www.ams.com/dc-dc_step-up/as1324 revision 1.06 9 - 21 as1324 datasheet - d e t a i l e d d e s c r i p t i o n 8.1 main control loop during pwm operation the converters use a 1.5mhz fi xed-frequency, current-mode control scheme. basis o f the current-mode pwm controller is an open-loop, multiple input comparator that compar es the error-amp voltage feedback signal against th e sum of the amplified current-sense signal and the slope-compensation ramp. at the begi nning of each clock cycle, the internal high-side p mos turns on until the pwm comparator trips. during this time the current in the inductor ramps up, sourcing current to the output and stori ng energy in the inductors magnetic field. when the pmos turns off, the internal low-side nmos turns on. now the inductor releases the stored ene rgy while the current ramps down, still providing current to the output. the output capacit or stores charge when the inductor current exceeds the load and discharges when the inductor current is lower than the load. under overload cond itions, when the inductor current exceeds the curre nt limit, the high-side pmos is turned off and the low-side nmos remains on until the next clo ck cycle. when the pmos is off, the nmos is turned on until t he inductor current starts to reverse (as indicated by the current reversal comparator (ircmp)), or the next clock cycle begins. the ircmp detects the zero crossing. the peak inductor current (i pk ) is controlled by the error amplifier. when i out increases, v fb decreases slightly relative to the internal 0.6v reference, causing the error amplifiers output vol tage to increase until the average inductor current matches the new load current. the over-voltage detection comparator (ovdet) guard s against transient overshoots by turning the main switch off and keeping it off until the transient is removed. 8.2 powersave operation the as1324 uses an automatic powersave mode where t he peak inductor current (i pk ) is set to approximately 200ma while independent o f the output load. in powersave mode, load current is sup plied solely from the output capacitor. as the outp ut voltage drops, the error amplifier output rises above the powersave threshold signaling to sw itch into pwm fixed frequency mode and turn the pmo s on. this process repeats at a rate determined by the load demand. each burst event can last from a few cycles at ligh t loads to almost continuous cycling (with short sl eep intervals) at moderate loads. in between bursts, the power mosfets are turned off, as is any unneeded circuitry, reducing quiescent current to 30a. 8.3 short-circuit protection in cases where the as1324 output is shorted to grou nd, the oscillator frequency (f osc ) is reduced to 1/13 the nominal frequency ( @ 115khz). this frequency reduction ensures that the inductor current has more time to decay, thus preventing run away conditions. f osc will progressively increase to 1.5mhz when v fb /v out > 0v. 8.4 shutdown connecting en to gnd or logic low places the as1324 in shutdown mode and reduces the supply current to 0.1a. in shutdown the control circuitry and the internal nmos and pmos turn off a nd sw becomes high impedance disconnecting the inpu t from the output. the output capacitance and load current determine the voltage decay rate. for normal operation connect en to v in or logic high. note: pin en should not be left floating.
www.ams.com/dc-dc_step-up/as1324 revision 1.06 10 - 21 as1324 datasheet - a p p l i c a t i o n i n f o r m a t i o n 9 application information the as1324 is perfect for mobile communications equ ipment like cell phones and smart phones, digital c ameras and camcorders, portable mp3 and dvd players, pdas and palmtop computers and an y other handheld instruments. figure 22. single li-ion 1.2v/600ma regulator for high-efficiency figure 23. 5v input to 3.3v/600ma buck regulator figure 24. single li-ion 1.5v/600ma regulator for high-efficiency as1324 c out 10f c in 2.2f v in 2.7 to 4.2v v out 1.2v 600ma 4.7h 301k w 22pf 301k w r 2 r 1 3 sw 4 v in 1 en 5 v fb gnd 2 c out 10f c in 4.7f v in 5v v out 3.3v 600ma 4.7h 66.5k w 22pf 301k w r 2 r 1 as1324 3 sw 4 v in 1 en 5 v fb gnd 2 c out 10f c in 4.7f v in 2.7 to 4.2v v out 1.5v 600ma 4.7h as1324-15 3 sw 4 v in 1 en 5 v out gnd 2
www.ams.com/dc-dc_step-up/as1324 revision 1.06 11 - 21 as1324 datasheet - a p p l i c a t i o n i n f o r m a t i o n figure 25. single li-ion 1.8v/600ma regulator for low output ripple 9.1 external component selection 9.2 inductor selection for most applications the value of the external ind uctor should be in the range of 2.2 to 6.8h as the inductor value has a direct effect on the ripple current. the selected inductor must be rated for its dc resistance and saturation current. the inductor ripple current ( d i l ) decreases with higher inductance and increases with higher v in or v out . in equation (eq 2) the maximum inductor current in pwm mode under sta tic load conditions is calculated. the saturation c urrent of the inductor should be rated higher than the maxim um in ductor current as calculated with equation (eq 3) . this is recommended because the inductor current will rise above the calculated value during heavy load transients. where: f = switching frequency (1.5 mhz typical) l = inductor value i lmax = maximum inductor current d i l = peak to peak inductor ripple current the recommended starting point for setting ripple c urrent is d i l = 240ma (40% of 600ma). the dc current rating of the inductor should be at least equal to the maximum load current plus half t he ripple current to prevent core saturation. thus, a 720ma rated inductor should be sufficient f or most applications (600ma + 120ma). a easy and fa st approach is to select the inductor current rating fitting to the maximum switch curren t limit of the converter. note: for highest efficiency, a low dc-resistance inducto r is recommended. accepting larger values of ripple current allows th e use of low inductance values, but results in high er output voltage ripple, greater core losses, and lower output current capability. the total losses of the coil have a strong impact o n the efficiency of the dc/dc conversion and consis t of both the losses in the dc resistance and the following frequency-dependent components: 1. the losses in the core material (magnetic hyste resis loss, especially at high switching frequencie s) 2. additional losses in the conductor from the ski n effect (current displacement at high frequencies) 3. magnetic field losses of the neighboring windin gs (proximity effect) 4. radiation losses c out 22f c in 10f v out 1.8v 600ma 4.7h v in 2.7 to 4.2v as1324-18 3 sw 4 v in 1 en 5 v out gnd 2 (eq 2) d i l v out 1 v out v in -------------- C l f ------------------------ = (eq 3) i lmax i outmax d i l 2 -------- + =
www.ams.com/dc-dc_step-up/as1324 revision 1.06 12 - 21 as1324 datasheet - a p p l i c a t i o n i n f o r m a t i o n figure 26. efficiency comparison of different indu ctors, v in = 2.7v, v out = 1.8v and 1.2v 9.3 output capacitor selection the advanced fast-response voltage mode control sch eme of the as1324 allows the use of tiny ceramic ca pacitors. because of their lowest output voltage ripple low esr ceramic capacitors ar e recommended. x7r or x5r dielectric output capacit or are recommended. at high load currents, the device operates in pwm m ode and the rms ripple current is calculated as: while operating in pwm mode the overall output volt age ripple is the sum of the voltage spike caused b y the output capacitor esr plus the voltage ripple caused by charging and discharging t he output capacitor: higher value, low cost ceramic capacitors are avail able in very small case sizes, and their high rippl e current, high voltage rating, and low esr make them ideal for switching regulator application s. because the as1324 control loop is not dependant on the output capacitor esr for stable operation, ceramic capacitors can be used to achiev e very low output ripple and accommodate small circ uit size. at light loads, the converter operates in powersave mode and the output voltage ripple is in direct re lation to the output capacitor and inductor value used. larger output capacitor and inductor va lues minimize the voltage ripple in powersave mode and tighten dc output accuracy in powersave mode. table 5. recommended inductors part number l dcr current rating dimensions (l/w/t) manufacturer lqh32cn2r2m33 2.2h 97m w 790ma 3.2x2.5x2.0mm murata www.murata.com lqh32cn4r7m33 4.7h 150m w 650ma 3.2x2.5x2.0mm lps3008-222mlc 2.2h 175m w 1100ma 3.1x3.1x0.8mm coilcraft www.coilcraft.com lps3015-222mlc 2.2h 110m w 2000ma 3.1x3.1x1.5mm mos6020-222mlc 2.2h 35m w 3260ma 6.0x6.8x2.4mm mos6020-472mlc 4.7h 50m w 1820ma 6.0x6.8x2.4mm cdrh3d16np-2r2n 2.2h 72m w 1200ma 4.0x4.0x1.8mm sumida www.sumida.com cdrh3d16nd-4r7n 4.7h 105m w 900ma 4.0x4.0x1.8mm 70 75 80 85 90 95 1 10 100 1000 output current (ma) efficiency (%) . lqh32cn2r2 lps3008-222 lps3015-222 m os6020-222 lqh32cn4r7 m os6020-472 70 75 80 85 90 95 1 10 100 1000 output current (ma) efficiency (%) . lqh32cn2r2 lps3008-222 lps3015-222 m os6020-222 lqh32cn4r7 m os6020-472 v out = 1.8v v out = 1.2v (eq 4) i rmsc out v out 1 v out v in -------------- C l f ------------------------ 1 2 3 ----------------- = (eq 5) d v out v out 1 v out v in -------------- C l f ------------------------ 1 8 c out f -------------------------------- esr + ? ? ? ? =
www.ams.com/dc-dc_step-up/as1324 revision 1.06 13 - 21 as1324 datasheet - a p p l i c a t i o n i n f o r m a t i o n 9.4 input capacitor selection in continuous mode, the source current of the pmos is a square wave of the duty cycle v out /v in . to prevent large voltage transients while minimizing the interference with other circuits cau sed by high input voltage spikes, a low esr input c apacitor sized for the maximum rms current must be used. the maximum rms capacitor cur rent is given as: where the maximum average output current i max equals the peak current minus half the peak-to-pea k ripple current, i max = i lim - d i l /2 this formula has a maximum at v in = 2v out where i rms = i out /2. this simple worst-case condition is commonly us ed for design because even significant deviations only provide negligible affects. the input capacitor can be increased without any li mit for better input voltage filtering. take care w hen using small ceramic input capacitors. when a small ceramic capacitor is used at the input , and the power is being supplied through long wire s, such as from a wall adapter, a load step at the output, or v in step on the input, can induce ringing at the vin p in. this ringing can then couple to the output and be mistaken as loop instability, or could even damage the part by excee ding the maximum ratings. 9.4.1 ceramic input and output capacitors when choosing ceramic capacitors for c in and c out , the x5r or x7r dielectric formulations are recomm ended. these dielectrics have the best temperature and voltage characteristics for a given value and size. y5v and z5u dielectric capaci tors, aside from their wide variation in capacitance over temperature, become resistive at h igh frequencies and therefore should not be used. because ceramic capacitors lose a lot of their init ial capacitance at their maximum rated voltage, it is recommended that either a higher input capacity or a capacitance with a higher rated volta ge is used. 9.5 feedback resistor selection in the as1324-ad, the output voltage is set by an e xternal resistor divider connected to v fb (see figure 27) . this circuitry allows for remote voltage sensing and adjustment. figure 27. setting the as1324 output voltage resistor values for the circuit shown in figure 27 can be calculated as: the output voltage can be adjusted by selecting dif ferent values for r 1 and r 2 . for r 1 a value between 10k w and 500k w is recommended. a higher resistance of r 1 and r 2 will result in a lower leakage current at the outp ut. it is recommended to keep v in 500mv higher than v out . table 6. recommended input and output capacitor part number c tc code rated voltage dimensions (l/w/t) manufacturer jmk212bj226mg-t 22f x5r 6.3v 0805 taiyo yuden www.t-yuden.com grm188r60j106me47 10f x5r 6.3v 0603 murata www.murata.com grm21br71a475ka73 4.7f x7r 10v 0805 (eq 6) i rms i max v out v in v out C ( ) v in --------------------------------------------------- --------- = r 2 0.6v v out 5.5v r 1 as1324 5v fb 2 gnd r 1 < www.ams.com/dc-dc_step-up/as1324 revision 1.06 14 - 21 as1324 datasheet - a p p l i c a t i o n i n f o r m a t i o n 9.6 efficiency the efficiency of a switching regulator is equivale nt to: efficiency = (p out /p in )100% (eq 8) for optimum design, an analysis of the as1324 is ne eded to determine efficiency limitations and to det ermine design changes for improved efficiency. efficiency can be expressed as: efficiency = 100% C (l 1 + l 2 + l 3 + ...) (eq 9) where: l 1 , l 2 , l 3 , etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit pr oduce losses, those four main sources should be con sidered for efficiency calculation: 9.6.1 input voltage quiescent current losses the v in current is the dc supply current given in the elec trical characteristics which excludes mosfet driver and control currents. v in current results in a small (<0.1%) loss that increases with v in , even at no load. the v in quiescent current loss dominates the efficiency lo ss at very low load currents. 9.6.2 i2r losses most of the efficiency loss at medium to high load currents are attributed to i2r loss, and are calcul ated from the resistances of the internal switches (r sw) and the external inductor (r l ). in continuous mode, the average output current f lowing through inductor l is split between the internal switches. therefore, the series resistance looking into the sw pin is a function of both nmos & pmos r ds(on) as well as the duty cycle (dc) and can be calculated as follows: r sw = (r ds(on)pmos )(dc) + (r ds(on)nmos )(1 C dc) (eq 10) the r ds(on) for both mosfets can be obtained from the electrical characteristics on page 4 . thus, to obtain i2r losses calculate as follows: i2r losses = i out 2(r sw + r l ) (eq 11) 9.6.3 switching losses the switching current is the sum of the control cur rents and the mosfet driver. the mosfet driver curr ent results from switching the gate capacitance of the power mosfets. if a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias cur rent. in continuous mode: i gc = f(q pmos + q nmos ) (eq 12) where: q pmos and q nmos are the gate charges of the internal mosfet switch es. the losses of the gate charges are proportional to v in and thus their effects will be more visible at hig her supply voltages. 9.6.4 other losses basic losses in the design of a system should also be considered. internal battery resistances and cop per trace can account for additional efficiency degradations in battery operated systems . by making sure that c in has adequate charge storage and very low esr at th e given switching frequency, the internal battery and fuse resistance losses can be minimized. c in and c out esr dissipative losses and inductor core losses generally account for less than 2% total add itional loss. 9.7 thermal shutdown due to its high-efficiency design, the as1324 will not dissipate much heat in most applications. howev er, in applications where the as1324 is running at high ambient temperature, uses a low sup ply voltage, and runs with high duty cycles (such a s in dropout) the heat dissipated may exceed the maximum junction temperature of the devi ce. as soon as the junction temperature reaches approxi mately 150oc the as1324 goes in thermal shutdown. i n this mode the internal pmos & nmos switch are turned off. the device will power u p again, as soon as the temperature falls below +14 5c again. 9.8 checking transient response the main loop response can be evaluated by examinin g the load transient response. switching regulators normally take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equivalent to: v drop = d i out x esr (eq 13) where: esr is the effective series resistance of c out . d i out also begins to charge or discharge c out , which generates a feedback error signal. the regu lator loop then acts to return v out to its steady-state value. during this recovery time v out can be monitored for overshoot or ringing that wou ld indicate a stability problem.
www.ams.com/dc-dc_step-up/as1324 revision 1.06 15 - 21 as1324 datasheet - a p p l i c a t i o n i n f o r m a t i o n 9.9 design example figure 28 shows the as1324 used in a single lithium-ion (3.7 v typ) battery-powered mobile phone application. th e load current requirement is 600ma (max) but most of the time the device will re quire only 2ma (standby mode current). figure 28. design example for the circuit shown in figure 28 , efficiency at low- and high-load currents is an i mportant consideration when selecting the value for the external inductor, which is calculated as: from (eq 14) , substituting v out = 2.2v, v in = 3.7v, d i l = 240ma and f = 1.5mhz gives: therefore, a standard 2.2h inductor should be used for this design. for best overall efficiency use an inductor with a rating of 720ma or greater and less than 0.2 w series resistance. c in will require an rms current rating of at least 0.3a @ i load(max) /2, whereas c out will require an esr of less than 0.25 w . in most cases, a ceramic capacitor will satisfy this requirement. for the feedback resistors, select the value for r 1 = 375k w . r 2 can then be calculated from (eq 7) to be: r 2 = (v out /0.6 - 1)375k = 1000k w c out 10f cer c in 4.7f cer v in 3.7v v out 2.2v 2.2h 375k w 22pf 1m w r 2 r 1 as1324 3 sw 4 v in 1 en 5 v fb gnd 2 (eq 14) l v out f d i l -------------- 1 v out v in -------------- C ? ? ? ? = (eq 15) l 2,2v 1,5mhz 240ma ( ) --------------------------------------------------- - 1 2,2v 3 7v , ------------ C ? ? ? ? 2,48 m h = =
www.ams.com/dc-dc_step-up/as1324 revision 1.06 16 - 21 as1324 datasheet - a p p l i c a t i o n i n f o r m a t i o n 9.10 layout considerations the as1324 requires proper layout and design techni ques for optimum performance. the power traces (gnd, sw, and v in ) should be kept as short, direct, and wide as is p ractical. pin v fb (as1324 only) should be connected directly to the feedback resistors (r 1 and r 2 ). a potentiometer as replacement for r 1 and r 2 should be avoided to minimize the output voltage ri pple and to maintain the stability of the regulator . the resistive divider (r 1 /r 2 ) must be connected between the positive plate of c out and ground. the positive plate of c in should be connected as close to v in as is practical since c in provides the ac current to the internal power mos- fets. switching node sw should be kept far away from the sensitive v fb node. the negative plates of c in and c out should be kept as close to each other as is practi cal. a starpoint to ground is recommended. figure 29. as1324 basic pcb layout figure 30. as1324 basic diagram 5 as1324 4 3 2 1 via to gnd via to v out v out sw gnd v in via to v in c out c in l 1 r 1 r 2 c fwd as1324 1 en 4 v in 3 sw 5 v fb 2 gnd c in l 1 r 1 r 2 c fwd high current path v in c out v out
www.ams.com/dc-dc_step-up/as1324 revision 1.06 17 - 21 as1324 datasheet - a p p l i c a t i o n i n f o r m a t i o n figure 31. as1324-18 basic pcb layout figure 32. as1324-18 basic diagram 5 as1324-18 4 3 2 1 v out sw gnd v in c out c in l 1 via to v in via to v out as1324-18 1 en 4 v in 3 sw 5 v out 2 gnd v in c in l 1 high current path c out v out
www.ams.com/dc-dc_step-up/as1324 revision 1.06 18 - 21 as1324 datasheet - p a c k a g e d r a w i n g s a n d m a r k i n g s 10 package drawings and markings the device is available in an 5-pin tsot-23 package . figure 33. 5-pin tsot-23 package
www.ams.com/dc-dc_step-up/as1324 revision 1.06 19 - 21 as1324 datasheet - p a c k a g e d r a w i n g s a n d m a r k i n g s figure 34. 5-pin tsot-23 marking zzzz xxxx top bottom pin1 pin1 package code: zzzz - marking xxxx - encoded datecode
www.ams.com/dc-dc_step-up/as1324 revision 1.06 20 - 21 as1324 datasheet 11 ordering information the device is available as the following standard v ersions. note: all products are rohs compliant. buy our products or get free samples online at icdi rect: http://www.ams.com/icdirect technical support is found at http://www.ams.com/technical-support for further information and requests, please contac t us mailto:sales@ams.com or find your local distributor at http://www.ams.com/distributor ams table 7. ordering information ordering code marking output description delivery form package as1324-bttt-ad askr adjustable 1.5mhz, 600ma synchronous dc/dc converter tape and reel 5-pin tsot-23 AS1324-BTTT-12 askt 1.2v 1.5mhz, 600ma synchronous dc/dc converter tape and reel 5-pin tsot-23 as1324-bttt-15 asku 1.5v 1.5mhz, 600ma synchronous dc/dc converter tape and reel 5-pin tsot-23 as1324-bttt-18 asks 1.8v 1.5mhz, 600ma synchronous dc/dc converter tape and reel 5-pin tsot-23
www.ams.com/dc-dc_step-up/as1324 revision 1.06 21 - 21 as1324 datasheet - o r d e r i n g i n f o r m a t i o n copyrights copyright ? 1997-2010, ams ag, tobelbaderstrasse 30 , 8141 unterpremstaetten, austria-europe. trademark s registered ?. all rights reserved. the material herein may not be reproduced , adapted, merged, translated, stored, or used with out the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective compa nies. disclaimer devices sold by ams ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. ams ag makes no warranty, express, statutory, implied, or by descri ption regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams ag reserves t he right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is nece ssary to check with ams ag for current information. this product is intended for use in normal commercial applications. applications requiring ext ended temperature range, unusual environmental requ irements, or high reliability applications, such as military, medical life-suppor t or life-sustaining equipment are specifically not recommended without additional processing by ams ag for each application. for shipments of le ss than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location . the information furnished here by ams ag is believe d to be correct and accurate. however, ams ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indi- rect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech- nical data herein. no obligation or liability to re cipient or any third party shall arise or flow out of ams ag rendering of technical or other services. contact information headquarters ams ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives , please visit: http://www.ams.com/contact

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