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low pow e r s t e r e o a udi o co de c w i t h h e a d phon e a m pl i f i e r r ev i s i on 1. 0 a p r i l 2 0 1 1 1 es83 23 general description features e s 8323 i s a hi gh pe r f or m anc e, l ow pow er an d l o w c o s t audi o c o d e c . i t co n si st s o f 2 - c h ad c , 2 - c h d a c, m i c r oph one a m pl i f i er , hea d phon e am pl i f i er , di gi t al s ou nd ef f e c t s , an d anal o g m i x i ng and gai n f unc t i on s . the dev ic e u s e s adv an c e d m ult i - b i t del t a - s i g m a m odul at io n t ec hni que t o c onv er t da t a bet w e en di gi t al and anal o g. the mult i - bit del t a - s ig ma m odul at o r s m ak e t he d ev ic e w i t h lo w s e n s it iv it y t o c lo c k jit t e r a n d lo w out of band n ois e . adc ? 24 - bit , 8 k h z t o 96 k h z s a m pl i ng f r eque nc y ? 95 db dy nam i c r an ge, 95 d b s i gnal t o no i s e r at io, - 85 db t h d + n ? s t er eo or m o no m ic r op hon e int er f ac e w i t h m ic r oph one a m pl i f i er ? a ut o lev el c o nt r ol and n ois e gat e ? 2 - t o - 1 anal og input s ele c t i o n ? v ar io us a nal o g i nput m i x ing and gai ns d ac ? 24 - b i t , 8 k h z t o 9 6 k h z s a m pling f r e que nc y ? 96 db dy nam i c r an ge, 96 d b s i gnal t o no i s e r at io, - 83 db t h d + n ? 40 m w h ead phon e amplif i er , pop n oi s e f r ee, c apl es s opt io n ? s t er eo en han c eme nt ? b as s a nd t r e bl e ? v ar io us a nal o g out put m i x i ng and g ai n s l o w p ow er ? 1. 8v t o 3. 3v oper at i on ? 7 m w pl ay ba c k ; 16 m w pl ay bac k an d r ec o r d sy s t e m ? i 2 c o r spi u c i n t e r f a c e ? 256f s , 384f s , u s b 12 m h z or 24 m h z ? m as t e r or s la v e s er i al p or t ? i 2 s, l e f t j u s t if ie d , d sp/ pcm m o d e applications or d e r in g in f or m a t ion ? m i d ? m p3 , m p4 , p m p ? w i r el es s au di o ? d ig i t a l c a me r a , c a m c or der ? gps ? b l uet oot h ? p or t abl e audi o dev i c e s e s 8323 - 40 c ~ +8 5 c qfn - 28 http://
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 2 1 bl o ck di ag ram ..................................................................................... 4 2 28 - pi n q f n and pi n desc r ip t ion s .................................................... 5 3 t ypi cal a ppl i c a t i o n ci rcu i t ............................................................ 7 4 cl o ck m o des an d sam pl i ng f req uen ci es .................................. 7 5 m i cro - co nt ro l l er co nf i g ura t i o n i nt erf ace ......................... 9 5. 1 spi ...................................................................................................... 9 5. 2 2 - wir e ................................................................................................ 10 6 co nf i g ura t i o n r eg i st er def i ni t i o n .......................................... 11 6. 1 c hi p c ontr ol and p o w er m anagem ent .............................................. 12 6. 1. 1 r egi st er 0 ? ch ip co n t r o l 1 , de f a ul t 0000 01 10 .......................... 12 6. 1. 2 r egi st er 1 ? c hi p c o n t r ol 2, def a ul t 0001 1 1 00 .......................... 13 6. 1. 3 r egi st er 2 ? c hi p p o w er m anagem ent, def a ul t 1 100 0 0 11 ......... 13 6. 1. 4 r egi st er 3 ? a d c po w er m anagem ent, def a ul t 1 1 1 1 1 1 00 ......... 14 6. 1. 5 r egi st er 4 ? d a c po w er m anagem ent, def aul t 1 100 0 00 0 ........ 14 6. 1. 6 r egi st er 5 ? c hi p lo w pow er 1, d ef aul t 000 0 0000 .................... 14 6. 1. 7 r egi st er 6 ? c hi p lo w pow er 2, d ef aul t 000 0 0000 .................... 15 6. 1. 8 r egi st er 7 ? a nal og v ol t age m an agem ent, d ef aul t 01 1 1 1 100 .... 15 6. 1. 9 r egi st er 8 ? m ast er m ode c ontr o l , def aul t 1000 0000 ............... 15 6. 2 adc co n t r o l ...................................................................................... 16 6. 2. 1 r egi st er 9 ? a d c con t r ol 1, def a ul t 0000 00 00 .......................... 16 6. 2. 2 r egi st er 10 ? a d c co nt r ol 2, def aul t 0000 0 000 ........................ 16 6. 2. 3 r egi st er 1 1 ? a d c co nt r ol 3, def aul t 0000 0 1 10 ........................ 17 6. 2. 4 re g ist e r 12 ? a d c co nt r ol 4, def aul t 0000 0 000 ........................ 17 6. 2. 5 r egi st er 13 ? a d c co nt r ol 5, def aul t 0000 0 1 10 ........................ 18 6. 2. 6 r egi st er 14 ? adc co n t r ol 6, def aul t 001 1 0 000 ........................ 18 6. 2. 7 r egi st er 15 ? a d c co nt r ol 7, def aul t 001 1 0 000 ........................ 18 6. 2. 8 r egi st er 16 ? adc co n t r o l 8 , de f a u lt 1 1 00 0 000 ........................ 19 6. 2. 9 r egi st er 17 ? a d c co nt r ol 9, def aul t 1 100 0 000 ........................ 19 6. 2. 10 r egi st er 18 ? a d c co nt r ol 10, def aul t 001 1 1000 ...................... 19 6. 2. 1 1 r egi st er 19 ? a d c co nt r ol 1 1, def aul t 101 1 0000 ...................... 20 6. 2. 12 r egi st er 20 ? a d c co nt r ol 12, def aul t 001 1 0010 ...................... 20 6. 2. 13 r egi st er 21 ? a d c co nt r ol 13, def aul t 0000 01 10 ...................... 21 6. 2. 14 r egi st er 22 ? a d c co nt r ol 14, def aul t 0000 0000 ...................... 21 6. 3 dac co n t r o l ...................................................................................... 21 6. 3. 1 r egi st er 23 ? d a c co nt r ol 1, def aul t 0000 0 000 ........................ 21 6. 3. 2 r egi st er 2 4 ? d a c co nt r ol 2, def aul t 0000 0 1 10 ........................ 22 6. 3. 3 r egi st er 25 ? d a c co nt r ol 3, def aul t 001 1 0 010 ........................ 22 6. 3. 4 r egi st er 26 ? dac co n t r o l 4, def aul t 1 100 0 000 ........................ 23 6. 3. 5 r egi st er 27 ? d a c co nt r ol 5, def aul t 1 100 0 000 ........................ 23 6. 3. 6 r egi st er 28 ? d a c co nt r ol 6, def aul t 0000 1 000 ........................ 23 6. 3. 7 r egi st er 29 ? d a c co nt r ol 7, def aul t 0000 0 1 10 ........................ 23 6. 3. 8 r egi st er 30 ? d a c co nt r ol 8, def aul t 0001 1 1 1 1 ........................ 24 6. 3. 9 r egi st er 31 ? dac co n t r o l 9 , de f a u lt 1 1 1 1 0 1 1 1 ......................... 24
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 3 6. 3. 10 r egi st er 32 ? d a c c o nt r ol 10, d ef aul t 1 1 1 1 1 101 ....................... 24 6. 3. 1 1 r egi st er 33 ? dac co n t r o l 1 1 , de f a u lt 1 1 1 1 1 1 1 1 ....................... 24 6. 3. 12 r egi st er 34 ? d a c c o nt r ol 12, d ef aul t 0001 1 1 1 1 ...................... 24 6. 3. 13 r egi st er 35 ? d a c c o nt r ol 13, d ef aul t 1 1 1 1 01 1 1 ....................... 24 6. 3. 14 r egi st er 36 ? d a c c o nt r ol 14, d ef aul t 1 1 1 1 1 101 ....................... 24 6. 3. 15 r egi st er 37 ? d a c c o nt r ol 15, d ef aul t 1 1 1 1 1 1 1 1 ....................... 25 6. 3. 16 r egi st er 38 ? d a c c o nt r ol 16, d ef aul t 0000 0000 ...................... 25 6. 3. 17 r egi st er 39 ? d a c c o nt r ol 17, d ef aul t 001 1 1000 ...................... 25 6. 3. 18 r egi st er 40 ? d a c c o nt r ol 18, d ef aul t 001 1 1000 ...................... 25 6. 3. 19 r egi st er 41 ? d a c c o nt r ol 19, d ef aul t 001 1 1000 ...................... 25 6. 3. 20 r egi st er 42 ? d a c c o nt r ol 20, d ef aul t 001 1 1000 ...................... 25 6. 3. 21 r egi st er 43 ? d a c c o nt r ol 21, d ef aul t 001 1 1000 ...................... 26 6. 3. 22 r egi st er 44 ? d a c c o nt r ol 22, d ef aul t 001 1 1000 ...................... 26 6. 3. 23 r egi st er 45 ? dac co n t r ol 23, d ef aul t 0000 0000 ...................... 26 6. 3. 24 r egi st er 46 ? d a c c o nt r ol 24, d ef aul t 0000 0000 ...................... 26 6. 3. 25 r egi st er 47 ? dac co n t r o l 2 5 , de f a u l t 0000 0000 ...................... 26 6. 3. 26 r egi st er 48 ? d a c c o nt r ol 26, d ef aul t 0000 0000 ...................... 27 6. 3. 27 r egi st er 49 ? d a c c o nt r ol 27, d ef aul t 0000 0000 ...................... 27 6. 3. 28 r egi st er 50 ? d a c c o nt r ol 28, d ef aul t 0000 0000 ...................... 27 6. 3. 29 r egi st er 51 ? d a c c o nt r ol 29, d ef aul t 0000 0000 ...................... 27 6. 3. 30 r egi st er 52 ? d a c c o nt r ol 30, d ef aul t 0000 0000 ...................... 27 7 d i g i t al a ud i o i nt er f ace .............................................................................. 27 8 el ec t ri c al char a ct er is t ic s ........................................................ 29 8. 1 a bso l ut e m axim um rat i ngs ............................................................... 29 8. 2 r eco m m en ded o perat i ng c on di t i ons ............................................... 29 8. 3 a d c a n al o g and fi l t er charact er i st i cs and s pecif i ca t i o n s ................ 29 8. 4 d a c a n al o g and fi l t er charact er i st i cs and s pecif i ca t i o n s ................ 30 8. 5 p ow er con su m pt i on c haract er i st i cs ................................................. 31 8. 6 s er i al a u di o p or t sw i t ch i ng s pec i f i ca t i ons ........................................ 31 8. 7 se r ia l c o n t r o l po r t swit ch in g s p e ci f ica t io n s ...................................... 31 9 p ac kag e i nf o rm a t i o n ...................................................................... 33 10 c or p oa r a t ion in f or ma t io n ....................................................... 34
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 4 1 bl oc k di ag ra m mi c a mp adc m ux a lc lin m ux lin1 mi c l m i c l+ m i c r se da c dacl mi c a mp a dc m ux a lc rin m ux rin1 mi c r m i c l + m i c r se dac da cr mixl + lin rin da cl da cr m i xr + lin rin da cl da cr m i xl m i xr l o u t 1 rout1 dv dd p v dd dg nd avdd agnd hpvdd hpgnd vref vmid micbias mclk clock m anager uc inter fac e ce cclk c da t a s er i al a udi o dat a a lrck a s dout dlrck dsdin sclk rin1 lin1
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 5 2 28 - p i n qf n an d p i n d e s cri p t i o ns cclk cdata ce nc nc nc lin 1 rin1 vmi d da cv re f a g nd av d d hp v dd lo u t 1 asd o u t nc vr ef nc nc hp g nd ro u t 1 m clk dv dd pvd d dg n d s clk ds din lrck 8 9 10 11 12 13 14 21 20 19 18 17 16 15 28 27 26 25 24 23 22 1 2 3 4 5 6 7
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 6 es8 3 2 3 is p in and siz e co m p at i bl e t o w m 89 88. pi n n am e i / o d esc r i pt i o n 1 mc l k i master clock 2 d v d d s uppl y digital core supply 3 p vd d s uppl y digital io supply 4 d g n d s uppl y digital gro und (return path for both dvdd and p vdd) 5 s c lk i / o audio data bit clock 6 d sd i n i dac audio data 7 l r c k i / o a udio data left and right clock 8 asd o u t o a d c au di o d at a 9 n c n o c onn ec t 10 vr ef o d ecoupling capacitor 11 n c o no connect 12 n c o no con nect 13 h p g nd s uppl y ground for analog output drivers (lout1, rout1 ) 14 r o u t 1 o right output 1 ( l ine or speaker/ headphone) 1 5 lo u t 1 o left output 1 ( l ine or speaker/ headphone) 1 6 h pvd d s uppl y supply for analog output drivers (lout1, rout1 ) 1 7 av d d su p p l y analog supply 1 8 ag n d s uppl y analog ground 19 ad c vr e f o d ecoupling capacitor 2 0 vm i d o d ecoupling capacitor 2 1 r i n 1 ai right channel input 1 2 2 l i n 1 i left channel input 1 2 3 n c i no connect 2 4 n c i no connect 2 5 n c n o c onn ec t 26 c e i control select or d evice address selection 27 c da t a i / o control data input or output 28 c cl k i control clock input
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 7 3 typical application circuit avdd avdd i2s_mclk i 2s_sclk i 2s_dsdi n i 2s_lrck i2s_asdout gnd 0. 1uf gnd i 2 c/ sp i dat a i 2c/sp i clk 1uf + 100 uf o r 47uf + 100 uf o r 47uf 330 330 1uf 0. 01uf 0. 01uf gnd 22 22 mi c 1k 2k 0. 1uf + 10u f gnd avdd gnd 2k headphone jack 4. 7uf 0. 1uf 4. 7uf 0. 01uf 0. 01uf 0. 1uf 4. 7uf gnd 10 4. 7uf 0. 1uf gnd i 2 c a d 0 / s p i ce bead 4. 7uf 0. 1uf 0. 1uf gnd avdd gnd avdd vi n 1 g nd 2 vout 3 lm 111 7- 3 . 3v gnd vcc avdd + 10u f + 10u f 0. 1uf 0. 1uf one ldo is recommended to provide power supply to ES8323 mclk 1 dvdd 2 dgnd 4 p vd d 3 sclk 5 dsdin 6 lrck 7 asdout 8 nc 9 hpvdd 16 lout1 15 rout 1 14 hpgnd 13 nc 12 nc 11 avdd 17 agnd 18 vmid 20 ri n1 21 lin1 22 nc 23 nc 24 nc 25 ce 26 cdat a 27 cclk 28 d a cv re f 19 vref 10 e s8 323 0. 1uf gnd 4. 7uf gnd 4 cl oc k m od e s and s a m p l i ng f r e q ue nci e s a cco r di ng t o t he i npu t se r i al au di o dat a s am pl i ng f r e quency , t he device c a n w or k i n t w o sp eed m odes: singl e sp eed or doubl e sp eed. the r anges of t h e sa m pl i ng f r equency i n t hese t w o m odes ar e l i st ed i n t abl e 1. th e device c an w or k ei t her in m ast er clock m ode or slave clock m ode. i n slave m ode, lr c k and s c l k ar e su p pl i e d e x t er nal l y . l r c k and s c lk m ust be sy nch r onousl y deri ve d f r om t he sys t em clock w i t h sp ecif i c r at es. th e device ca n aut o det e ct m c lk / l r c k r at i o acco r di ng t o t abl e 1. the devic e onl y su pp o r t s t he m cl k/ l rck r a t io s list e d in t a b le 1 . the lr c k / s c lk r at i o i s norm al l y 6 4. t abl e 1 s l a ve m ode s am pl i ng fr equenci es and m cl k / l rck r a t i o s peed m o de s ampl i ng f r e quen c y mc l k / l r c k r a t i o s i ngl e s peed 8khz ? 50khz 256, 384, 512, 768, 1024 d ou bl e s pee d 50khz ? 100khz 128, 192, 256, 384, 512 i n m ast er m ode, lr c k and s c lk ar e d er i ve d i nt e r nal l y f r om m c lk . the ava i l abl e m c lk / lr c k r at i os and s c lk / l r c k r at i os ar e l i st ed i n t a bl e 2.
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 8 t abl e 2 m ast er m ode s am pl i ng fr equencies and m cl k / l rck ra t i o m c lk clkdiv2=0 m c lk clk div 2= 1 a d c s a mpl e r a te ( a lrck ) a d c fs rati o [4 :0 ] d a c s a mpl e r a te ( dlrck ) da c fs rati o [4 :0 ] s clk rat io n or ma l mode 12.288 mhz 24.576m hz 8 k hz ( m clk /15 36) 01010 8 k hz ( m clk /15 36) 01010 m clk /6 8 k hz ( m clk /15 36) 01010 48 k hz ( m clk /2 56) 00010 mclk/4 12 k hz ( m clk /1 024) 0 0 111 12 k hz ( m clk /1 024) 00111 mclk/4 16 k hz ( m clk /7 68) 001 10 16 k hz ( m clk /7 68) 001 10 m clk /6 24 k hz ( m clk /5 12) 00100 24 k hz ( m clk /5 12) 00100 mclk/4 32 k hz ( m clk /3 84) 0001 1 32 k hz ( m clk /3 84) 0001 1 mclk/6 48 k hz ( m clk /2 56) 00010 8 k hz ( m clk /15 36) 01010 mclk/4 48 k hz ( m clk /2 56) 00010 48 k hz ( m clk /2 56) 0 0010 mclk/4 96 k hz ( m clk /1 28) 00000 96 k hz ( m clk /1 28) 00000 mclk/2 1 1.2896 mhz 22.5792m hz 8.0182 k hz ( m c lk /1408) 01001 8.0182 khz (mclk/1408) 01001 mclk/4 8.0182 k hz ( m clk/1408) 01001 44.1 k hz ( m clk / 256) 00010 mclk/4 1 1.025 k hz ( m clk/1024) 0 0 111 1 1.025 k hz ( m clk/1024) 00111 mclk/4 22.05 k hz ( m cl k /512) 00100 22.05 k hz ( m cl k /512) 00100 mclk/4 44.1 k hz ( m clk / 256) 00010 8.0182 khz (mclk/1408) 01001 mclk/4 44.1 k hz ( m clk / 256) 00010 44.1 k hz ( m clk / 256) 00010 mclk/4 88.2 k hz ( m clk / 128) 00000 88.2 k hz ( m clk / 128) 00000 mclk/2 18.432 mhz 36.864m hz 8 k hz ( m clk /23 04) 01 100 8 k hz ( m clk /23 04) 01 100 m clk /6 8 k hz ( m clk /23 04) 01 100 48 k hz ( m clk /3 84) 0001 1 mclk/6 12 k hz ( m clk /1 536) 01010 12 k hz ( m clk /1 536) 01010 mclk/6 16 k hz ( m clk /1 152) 01000 16 k hz ( m clk /1 152) 01000 mclk/6 24 k hz ( m clk /7 68) 001 10 24 k hz ( m clk /7 68) 001 10 mclk/6 32 k hz ( m clk /5 76) 00101 32 k hz ( m clk /5 76) 00101 mclk/6 48 k hz ( m clk /3 84) 0001 1 8 k hz ( m clk /23 04) 01 100 mclk/6 48 k hz ( m clk /3 84) 0001 1 48 k hz ( m clk /3 84) 0001 1 mclk/6 96 k hz ( m clk /1 92) 00001 96 k hz ( m clk /1 92) 00001 mclk/3 16.9344 m hz 33.8688m hz 8.0182 k hz ( m clk/2112) 01011 8.0182 khz (mclk/2112) 0101 1 mclk/6 8.0182 k hz ( m c lk /21 12) 0101 1 44.1 k hz ( m clk / 384) 0001 1 mclk/6 1 1.025 k hz ( m c lk /1536) 01010 11.025 khz (mclk/1536) 01010 mclk/6 22.05 k hz ( m cl k /768) 001 10 22.05 k hz ( m cl k /768) 001 10 mclk/6 44.1 k hz ( m clk / 384) 0001 1 8.0182 khz (mclk/2112) 0101 1 mclk/6 44.1 k hz ( m clk / 384) 0001 1 44.1 k hz ( m clk / 384) 0001 1 mclk/6 88.2 k hz ( m clk / 192) 00001 88.2 k hz ( m clk / 192) 00001 mclk/3 us b m o d e 12 m hz 24m hz 8 k hz ( m clk /15 00) 11 0 11 8 k hz ( m clk /15 00) 11 0 11 mclk 8 k hz ( m clk /15 00) 11 0 11 48 k hz ( m clk /2 50) 10010 m clk 8.0214 k hz ( m clk/1496) 1 1010 8.0214 khz (mclk/1496) 1 1010 mclk 8.0214 k hz ( mclk/1496) 11 010 44.1 18 k hz ( m c lk /272) 1001 1 mclk 1 1.0259 k hz ( m clk /1088 ) 1 1001 1 1.0259 khz (mclk/1088 ) 1 1001 m clk
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 9 12 k hz ( m clk /1 000) 1 1000 12 k hz ( m clk /1 000) 1 1000 mclk 16 k hz ( m clk /7 50) 1 0 111 16 k hz ( m clk /7 50) 1 0 111 mclk 22.0588 khz (mclk/544) 101 10 22.05 88 khz (mclk/544) 101 10 mclk 24 k hz ( m clk /5 00) 10101 24 k hz ( m clk /5 00) 10101 mclk 32 k hz ( m clk /3 75) 10100* 32 k hz ( m clk /3 75) 10100* mclk 44.1 18 k hz ( m c lk /272) 1001 1 8.0214 khz (mclk/1496) 1 1010 mclk 44.1 18 k hz ( m c lk /272) 1001 1 44.1 18 k hz ( m c lk /272) 1001 1 m clk 48 k hz ( m clk /2 50) 10010 8 k hz ( m clk /15 00) 11 0 11 m clk 48 k hz ( m clk /2 50) 10010 48 k hz ( m clk /2 50) 10010 m clk 88.235 k hz ( m c lk /136) 10001 88.235 k hz ( m c lk /136) 10001 m clk 96 k hz ( m clk /1 25) 10000 96 k hz ( m clk /1 25) 10000 m clk 5 m i cr o - con t ro l l e r c on f i gu ra t i on i nt e r f a ce the devic e su ppor t s st andar d s p i and 2 - wir e m icr o - co nt r ol l er co nf i gurat i o n i n te rfa ce . e x te rn a l mi cr o - co nt r ol l er ca n co m pl et el y co nf i gure t he device t hr ough w r i t i ng t o i nt er nal co nf i gu r at i on r egi st er s. p l ease se e se ct i on 8 f or t he det ai l s of co nf i gurat i o n r egi st er d ef i ni t i on. the i dent i c al device pi ns ar e use d t o co nf i gure ei t her spi or 2 - w i r e i nt er f ace . i n s p i m ode, pi n ce, c cl k a n d cda t a f uncti on as s p i _c s n, s p i _c lk an d spi _ di n. i n 2 - w i r e m ode, p in c e, ccl k a n d cd a t a f un ct io n a s ad0 , scl and sda. t o s el ect s p i m ode, appl y hi gh t o l ow t r ansit i on signal t o ce p in . o t herw i se the device w i l l oper at e in 2 - w i r e i n t er f ace m o de. 5. 1 spi es8 3 2 3 ha s a s p i ( s er i al p er i p heral i nt er f ace ) co m pl i ant syn ch r onous se r i al slave co nt r ol l er i n si d e t he ch i p. i t pr ovides t he abi l i t y t o al l o w t he e x t er na l m ast er s p i co nt r ol l er t o acce ss t he i nt er nal r egi st er s, and t hus co nt r ol t h e oper at i ons of ch ip . a l l l i nes on t he s p i b us ar e uni d i r ect i onal : the s p i _c lk i s gene r at ed by t h e m ast er co nt r ol l er an d i s pr i m a r i l y use d t o syn ch r oni ze dat a t r ansfer , t h e s p i _d i n l i ne ca r r i es dat a f r om t he m ast er t o t he slave ; s p i _c s n i s gener at e d by t he m as t er t o se l ect e s 8323 . the t i m i ng di agram of t hi s i nt er f ace i s gi ve n i n fi gure 1. the hi gh t o l ow t r ansit i on at s p i _c s n pi n i n di c at es t he s p i i nt er f ace se l ect ed. e ach w r i t e pr oce dure co nt ai ns 3 w or ds, i . e. c hi p a ddre ss pl us r / w bi t , i nt er nal r egi st er addr ess and i nt er nal r egi st er dat a. e ve r y w or d l engt h i s f i x ed at 8 bi t s. the i nput s p i _ d i n dat a a r e sa m pl ed at t he r i sing edge of s p i _c lk clock. the m s b bi t i n each w or d i s t r ansfer r ed f i r st l y . the t r ansfer r at e ca n be up t o 10 m b ps.
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 10 chip address 7 bits - 0010000 0 spi _ d i n spi _ c l k spi_csn 1 r/ wb 5 6 7 8 9 14 15 16 17 22 23 ra m 8 bits re g i s t e r d a t a 8 bits 5. 2 2 - wir e 2 - w i r e i nt er f ace i s a bi - di r ect i onal se r i al bus t hat use s a se r i al dat a l i ne ( s d a ) and a se r i al clock l i n e ( s c l) f or dat a t r an sf er . the t i m i ng di agram f o r dat a t r ansfer o f t hi s i nt er f ace i s gi ve n i n fi gure 2. d at a ar e t r ansmi t t ed syn ch r ono usly t o s c l clock on t he s d a l i n e on a byt e - by - byt e basis. e ach b i t i n a byt e i s sa m pl ed dur i ng s c l hi gh w i t h m s b bi t bei n g tra n sm i tte d fi rs tl y . e ach t r ansfer r ed byt e i s f ol l o w ed by an ack now l edge bi t f r om r e ce i ve r t o p u l l t he s d a lo w . the t r ansfer r a t e of t hi s i nt er f ace ca n be up t o 100k bp s. a m ast er c ont r ol l er init i at es t he t r ansm i ssi on by se ndi n g a ? st ar t ? s i gna l , w h ic h i s def i ned as a hi gh - to - l ow t r ansit i on at s d a w hi l e s c l i s hi gh. t he f i r st byt e t r ansf er r ed i s t he slave addr ess. i t i s a se v en - bi t ch i p addr ess f ol l ow e d by a r w bi t . the ch i p addr ess m ust b e 001000 x , w her e x e qual s a d 0 ( p in ce) . the r w bi t i ndi ca t es t he s l ave dat a t r ansf er di r ect i on. o nce an ackn ow l ed ge bi t i s r ece i ve d, t he dat a t r a nsf er st a r t s t o pr oce ed on a byt e - by - byt e basis i n t he di r ect i on sp ecif i ed by t he r w bi t . the m ast er ca n t er m i nat e t he co m m uni ca t i o n by gener at i ng a ? s t op? signal , w hi ch i s def i ned as a l ow - to - hi gh t r ansit i on at sda wh ile scl is h ig h . i n 2 - w i r e i n t er f ace m o de, t he r egi st er s ca n b e w r i t t en a nd r ead. t he f or m at s of ? w r i t e? and ? r ead? i nst r uct i ons ar e sh ow n i n t abl e 3 a n d t abl e 4. p l ease note t hat, t o r ead dat a f r om a r egi st er , yo u m u st se t r / w bi t t o 0 t o acce ss t he r egi st er addr ess and t hen se t r / w t o 1 t o r ead dat a f r om t he r egi st er . ther e ar e no ackn ow l edge bi t af t er dat a t o be w r i t t en or r ead, t hi s i s t he onl y figure 1 s p i confi gurat i on i nt er f ace t i m i ng d i agr am r a m = r egi st er a ddr ess m appi n g fi gur e 2 complete data transf er f or 2 - w i r e int er f ace
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 11 di f f er ence f r om t he i 2 c pr ot oco l . t abl e 3 w r i t e d at a t o r egi st er i n 2 - w i r e i nt er f ace m ode c hi p a d dr e ss r / w r egi st er a dd r ess d at a t o be w r i t t en 001000 ad0 0 ack ram ack data t abl e 4 r e ad d at a f r om r egi st er i n 2 - w i r e i nt er f ace m o de c hi p a d dr e ss r / w r egi st er a dd r ess 001000 ad0 0 ack ram ch i p a d dr e ss r / w d at a t o be r e ad 001000 ad0 1 ack d at a 6 con f i g ura t i o n re gi s t e r d e f i ni t i on s p i and 2 - w i r e co nf i g ur at i on i nt er f ace sh ar e t he sa m e r egi st er s beca use t here i s onl y one i nt er f a ce act i ve at any t i m e. ther e ar e t ot a l of 53 u se r pr ogram m ab le 8 - bi t r egi st er s i n t hi s device . these r egi st er s co nt r ol t he oper at i ons of a d c and d a c . e x t er na l m ast er co nt r ol l er ca n a cce ss t hese r egi st er s b y using t he slave addr ess sp ecif i ed i n r a m ( r egi st er a ddress m a p) r egi st er as sh ow n i n t h e t abl e 5. t abl e 5 b i t content of r egi st er a ddress m ap b7 b6 b5 b4 b3 b2 b1 b0 reg . 00 s cp res et lrcm da cm clk s am ef s s eqe n e nref vmi d sel reg . 01 l pvc mmo d lp v r efb uf p dna na p dnibi as gen v r efr lo p dnv r efbuf reg . 02 adc _di gp dn dac _di gp dn adc _s tm _r s t dac _s tm _r s t a dcdll_p d n da cdll_p d n adc v r ef_p dn dac v r ef_p dn reg . 03 p dna inl p dna inr p dna dcl p dna dcr p dnm icb p dna dcb i as gen fl as hlp i nt1lp reg . 04 p dnda cl p dnda cr l o u t 1 rout 1 reg . 05 lp da cl lp da cr lp lo u t1 reg . 06 l ppg a lplm ix lp a dcv r p lp da cv r p reg . 07 vsel reg . 08 msc m clk div 2 b clk _inv bclk div reg. 09 micampl micampr reg . 10 lins e l rins e l d ssel ds r reg . 1 1 ds m o n o m i x tr i reg . 12 d atsel a dclrp a dcw l a dcf o rm a t reg. 13 adcfsmode adcfsratio reg . 14 adc_invl a dc_i nv r a dc_hp f _ l a dc_hp f _ r reg . 15 a dcram pr ate a dcs of tram p adcler a dcmute reg . 16 la dcv o l reg . 17 ra dcv o l reg. 18 alc sel maxg ai n m ing a in reg . 19 a lclvl alchld
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 12 reg. 20 alcdcy alcatk reg. 21 alcmode alczc time_out win_size reg. 22 ngth ngg ngat reg . 23 da clrs w a p da clrp da cw l da cf o rm a t reg . 24 da cf s m ode da cf s rati o reg . 25 da cram pr ate da cs of tram p da cler da cm ute reg . 26 da cv ol um el ( l da cv o l ) reg . 27 dacvolumer (rdacvol) reg . 28 deem phas i s m ode da c_i nv l da c_i nv r c l i c k fre e reg. 29 ze ro l ze ro r m ono se v pp_s c al e reg . 30 s hel v i ng_a[29:24] reg . 31 s hel v i ng_a[23:16] reg . 32 s hel v i ng_a[15:8] reg . 33 s hel v i ng_a[7:0] reg . 34 s hel v ing_b[29:24] reg. 35 s hel v i ng_b[23:16] reg . 36 s hel v i ng_b[15:8] reg . 37 s hel v i ng_b[7:0] reg . 38 l mi xsel r mi xsel reg . 39 ld2lo li2lo li2lovol reg . 40 reg . 41 reg . 42 rd2ro ri2ro ri2ro v o l reg . 43 slrck lr c k _s el of fs et_di s , m c l k _di s a dc _dl l _pw d dac _dl l _pw d reg . 44 offset reg. 45 v r o i reg . 46 reg. 47 reg. 48 l o u t 1vo l reg . 49 r o u t 1 v o l reg . 50 reg . 51 hplout1_r ef1 hplout1_ref2 reg . 52 s pklout2_ref1 spklout2_r ef2 m i x er _r ef1 m i x er _r ef2 mr ef 1 mr ef 2 6. 1 c hi p c ont r ol and p ow er m ana gem ent 6.1.1 r egist er 0 ? c hip c ont r ol 1 , d ef ault 0000 01 10 b i t na m e b i t d e s c ri pt i on sc pr e s e t 7 0 ? nor m al ( d ef aul t ) 1 ? r es et c ont r ol po r t r egi s t er t o def aul t l r c m 6 0 ? a lr c k disabled when both adc disabled; dlrck disabled when both dac disabled (default)
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 13 1 ? alrck and dlrck disabled when all adc and dac disabled dacmclk 5 0 ? when samefs=1, adcmclk is the chip master clock sour ce (default) 1 ? when samefs=1, dacmclk is the chip master clock source samefs 4 0 ? adc fs differs from dac fs (default) 1 ? adc fs is the same as dac fs s eq e n 3 0 ? internal power up/down sequence disable (default) 1 ? internal power up/down sequence e nable e nr ef 2 0 ? di s a bl e r e f er en c e 1 ? enable reference (default) vm i d sel 1 : 0 00 ? v m i d di s abl ed 01 ? 50 k ? di v i der ena bl ed 10 ? 500 k ? divider enabled (default) 11 ? 5 k ? divider enabled 6.1.2 r egist er 1 ? c hip c ont r ol 2, d ef ault 0001 1 1 00 b i t na m e b i t d e s c ri pt i on lpvcmmod 5 0 ? normal (default) 1 ? low power l pv r e f bu f 4 0 ? nor m al 1 ? l o w p ow er ( def a ul t ) p dna na 3 0 ? nor m al 1 ? entire analog power down (default) p dn i bi as gen 2 0 ? nor m al 1 ? ibiasgen power down (default) v reflo 1 0 ? normal (default) 1 ? low power p dnvrefbuf 0 0 ? normal (default) 1 ? power down 6.1.3 r egist er 2 ? c hip p ow er m anage m ent , d ef ault 1 100 001 1 b i t na m e b i t d e s c ri pt i on adc _d i gp d n 7 0 ? nor m al 1 ? r es et s a d c d e m , f i l t er and s er i al d at a por t ( d ef aul t ) dac _d i gp d n 6 0 ? nor m al 1 ? r es et s d a c d sm , d e m , f i l t er and s er i al dat a po r t ( def aul t ) adc _s t m _ r s t 5 0 ? nor m al ( d ef aul t ) 1 ? r es et a dc s t at e m ac hi ne t o pow er d ow n s t a t e dac _s t m _ r s t 4 0 ? nor m al ( d ef aul t ) 1 ? r es et d a c s t at e m ac hi ne t o pow er d ow n s t a t e ad c d ll _p d n 3 0 ? nor m al ( d ef aul t ) 1 ? a d c _d ll pow e r do w n , st o p a d c cl o ck d ac d ll _ p d n 2 0 ? nor m al ( d ef aul t ) 1 ? dac dll power down, stop dac clock
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 14 adc v r ef _p d n 1 0 ? a dc a nal og r ef e r en c e pow er up 1 ? adc analog reference power down (default) dac v r ef _p d n 0 0 ? d a c an al og r ef e r en c e pow er up 1 ? d a c an al og r ef e r en c e pow er do w n ( def aul t ) 6.1.4 r egist er 3 ? a d c p ow er m anage m ent , d ef ault 1 1 1 1 1 10 0 b i t na m e b i t d e s c ri pt i on p dn ai n l 7 0 ? nor m al 1 ? left analog input power down (default) p dn ai n r 6 0 ? nor m al 1 ? right analog input power down (default) p dn a d c l 5 0 ? l ef t a d c pow er up 1 ? left adc power down (default) p dn a d c r 4 0 ? r i ght a d c pow e r up 1 ? right adc power down (default) p dn m i c b 3 0 ? m i c r oph o ne bi a s po w e r on 1 ? m i c r oph o ne bi a s po w e r dow n ( hi gh i m peda nc e ou t put , def aul t ) p dna d c b i as gen 2 0 ? nor m al 1 ? pow er d ow n ( d ef aul t ) f l as hlp 1 0 ? nor m al ( d ef aul t ) 1 ? flash adc low power int1lp 0 0 ? normal (default) 1 ? int1 low power 6.1.5 r egist er 4 ? d a c p ow er m anage m ent , d ef ault 1 100 00 00 b i t na m e b i t d e s c ri pt i on p dn da c l 7 0 ? l ef t d a c pow er up 1 ? left dac power down (default) p dn da c r 6 0 ? r i ght d a c pow e r up 1 ? right dac power down (default) lout 1 3 0 ? lout 1 disabled (default) 1 ? lout 1 enabled rout 1 2 0 ? rout 1 disabled (default) 1 ? rout 1 enabled 6.1.6 r egist er 5 ? c hip low p ow er 1 , d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on lpdacl 7 0 ? normal (default) 1 ? low power lpdacr 6 0 ? normal (default) 1 ? low power lplout 1 3 0 ? normal (default) 1 ? low power
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 15 6.1.7 r egist er 6 ? c hip low p ow er 2 , d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on lppga 7 0 ? normal (default) 1 ? low power lplmix 6 0 ? normal (default) 1 ? low power lpadcvrp 1 0 ? normal (default) 1 ? low power lpdacvrp 0 0 ? normal (default) 1 ? low power 6.1.8 r egist er 7 ? a nalog v olt age m anagem ent , d ef ault 01 1 1 1 100 b i t na m e b i t d e s c ri pt i on vsel 6 :0 111110 0 ? normal (default) 6.1.9 r egist er 8 ? m ast er m ode c ont r o l, d ef ault 1000 0000 b i t na m e b i t d e s c r ip t io n ms c 7 0 ? s l av e s er i al por t m o de 1 ? m a s t er s er i a l p or t m ode ( def aul t ) m c lkdiv2 6 0 ? mclk not divide (default) 1 ? mclk divide by 2 bc l k_inv 5 0 ? normal (default) 1 ? bclk inverted bc l kd i v 4: 0 0000 0 ? m as t er m od e bc l k gener at ed aut om at i c al l y bas ed on t h e cl o ck t a b l e ( d ef aul t ) 0000 1 ? m c l k/ 1 0001 0 ? m c l k/ 2 000 1 1 ? m c l k/ 3 0010 0 ? m c l k/ 4 0010 1 ? m c l k/ 6 001 10 ? m c lk / 8 001 1 1 ? m c l k/ 9 0100 0 ? m c l k/ 1 1 0100 1 ? m c l k/ 1 2 0101 0 ? m c l k/ 1 6 010 1 1 ? m c l k/ 1 8 01 1 00 ? m c l k/ 2 2 01 1 01 ? m c l k/ 2 4 01 1 10 ? m c l k/ 3 3 0 11 11 ? m c l k/ 3 6 1000 0 ? m c l k/ 4 4 1000 1 ? m c l k/ 4 8 1001 0 ? m c l k/ 6 6 100 1 1 ? m c l k/ 7 2 1010 0 ? m c l k/ 5
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 16 10101 ? mclk/10 10110 ? mclk/15 10111 ? mclk/17 11000 ? mclk/20 11001 ? mclk/25 11010 ? mclk/30 11011 ? mclk/32 11100 ? mclk/34 o thers ? mclk/4 6. 2 adc co n t r o l 6.2.1 r egist er 9 ? a d c c ont r ol 1, d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on mi c a mp l 7 : 4 lef t c ha nnel p g a gai n 0000 ? 0 db ( def aul t ) 0 001 ? + 3 db 00 10 ? + 6 db 001 1 ? + 9 db 0 100 ? + 12 db 0101 ? + 15 db 0 11 0 ? + 18 db 0 11 1 ? + 21 db 1000 ? + 24 db mi c a mp r 3 : 0 r i ght c han nel p g a gai n 0000 ? 0d b ( def aul t ) 0 001 ? + 3 db 0010 ? + 6 db 001 1 ? + 9 db 0 100 ? + 12 db 0101 ? + 15 db 0 11 0 ? + 18 db 0 11 1 ? + 21 db 1000 ? + 24 db 6.2.2 r egist er 10 ? a d c c ont r ol 2, d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on l i n sel 7 : 6 lef t c ha nnel i nput s el ec t 00 ? r es er v e d ( def aul t ) 01 ? l i n pu t 1 10 ? r eserved 11 ? reserved r i n sel 5:4 right channel input select 00 ? reserved ( defaul t )
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 17 01 ? rinput1 10 ? reserved 11 ? reserved dssel 3 0 ? use one ds reg11[7] ( default ) 1 ? dsl=reg11[7], dsr=reg10[2] dsr 2 differential input select 0 ? reserved (default) 1 ? rese rve d 6.2.3 r egist er 1 1 ? adc co n t ro l 3 , d ef ault 0000 01 10 b i t na m e b i t d es cr i pt i on ds 7 differential input select 0 ? reserved (default) 1 ? reserved mo n o mi x 4 : 3 00 ? s t e r eo ( def aul t ) 01 ? analog mono mix to left adc 10 ? analog mono mix to right adc 11 ? reserved tr i 2 0 ? a s d o u t i s a d c nor m al out put ( def aul t ) 1 ? asdout tri - st ated , alrc k , dlrc k and sclk are inputs 6.2.4 r egist er 12 ? adc co n t ro l 4 , d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on datsel 7:6 00 ? left data = left adc, right data = right adc 01 ? left data = left adc, right data = left adc 10 ? left data = right adc, right data = right adc 11 ? left data = right adc, right data = left adc a dc l rp 5 i 2s , l ef t j us t i f i ed or r i ght j us t i f i ed m ode : 0 ? l ef t and r i ght nor m al po l ar i t y 1 ? l ef t and r i ght i nv er t ed p o l a r i t y d sp / pc m m o d e : 0 ? msb is available on 2nd bclk rising edge after a lrc k rising edge 1 ? msb is available on 1st bclk rising edge after a lrc k rising edge adcwl 4:2 000 ? 24 - bit serial audio data word length 001 ? 20 - bit serial audio data word length 010 ? 18 - bit serial audio data word length 011 ? 16 - bit serial audio data word length 100 ? 32 - bit serial audio data word length a dc f o r m a t 1 : 0 00 ? i 2 s s er i al audi o d at a f or m at 01 ? l e f t j u s t i f y s er i al au di o dat a f or m at 10 ? r i g h t j u s t i f y s er i al audi o dat a f or m at 11 ? dsp/pcm mode serial audio data format
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 18 6.2.5 r egist er 13 ? adc co n t ro l 5 , d ef ault 0000 01 10 b i t na m e b i t d e s c ri pt i on adc fsmode 5 0 ? single speed mode (default) 1 ? double speed mode adcfsratio 4 : 0 m aster mode adc mclk to sampling frequency ratio 0000 0 ? 128 0000 1 ? 192 0001 0 ? 256 000 1 1 ? 3 84 0010 0 ? 512 0010 1 ? 576 001 10 ? 76 8 ( def aul t ) 001 1 1 ? 1 024 0100 0 ? 11 5 2 0100 1 ? 140 8 0101 0 ? 153 6 010 1 1 ? 2 11 2 01 1 00 ? 23 04 1000 0 ? 125 1000 1 ? 136 1001 0 ? 250 100 1 1 ? 2 72 1010 0 ? 375 1010 1 ? 500 101 10 ? 5 44 101 1 1 ? 75 0 1 10 00 ? 10 00 1 10 01 ? 10 88 1 10 10 ? 14 96 11 0 11 ? 1 500 o t her ? r es er v ed 6.2.6 r egist er 14 ? adc co n t ro l 6 , d ef ault 001 1 00 00 b i t na m e b i t d e s c ri pt i on a d c _i nv l 7 0 ? nor m al ( d ef aul t ) 1 ? l ef t c han n el pol ar i t y i nv er t ed a d c _i nv r 6 0 ? nor m al ( d ef aul t ) 1 ? r i ght c h an nel pol a r i t y i nv er t ed a d c_ h pf _l 5 0 ? di s a bl e a d c l ef t c han n el hi gh p as s f i l t er 1 ? enable adc left channel high pass filter (default) a dc _ h pf _r 4 0 ? di s a bl e a d c r i ght c h an nel hi gh p a s s f i l t er 1 ? enable adc right channel high pass filter (default) 6.2.7 r egist er 15 ? adc co n t ro l 7 , d ef ault 001 1 00 00 b i t na m e b i t d e s c ri pt i on a d c r a m p r a t e 7 : 6 00 ? 0. 5 db p er 4 lr c k di gi t al v ol um e c ont r ol r am p r at e ( def aul t ) 01 ? 0. 5 db p er 8 lr c k di gi t al v ol um e c ont r ol r am p r at e 10 ? 0.5 db per 16 lrck digital volume control ramp rate 11 ? 0.5 db per 32 lrck digi tal volume control ramp rate a dc s o f t ra m p 5 0 ? di s a bl ed di gi t al v ol um e c ont r ol s of t r am p 1 ? enabled digital volume control soft ramp (default) a dc l e r 3 0 ? nor m al ( d ef aul t ) 1 ? both channel gain control is set by adc left gain control register ad c m u t e 2 0 ? nor m al ( d ef aul t ) 1 ? mute adc digital output
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 19 6.2.8 r egist er 16 ? adc co n t ro l 8 , d ef ault 1 100 00 00 b i t na m e b i t d e s c ri pt i on la d c v o l 7 : 0 d i gi t al v ol um e c ont r ol at t enuat e s t he s i gnal i n 0. 5 db i nc r e m ent al f r om 0 t o ? 96 db . 0000 0000 ? 0 db 0000 0001 ? - 0 . 5 db 0000 0010 ? - 1 db ? 1 10 000 00 ? - 96 db ( def a ul t ) 6.2.9 r egist er 17 ? adc co n t ro l 9 , d ef ault 1 100 00 00 b i t na m e b i t d e s c ri pt i on r ad c vo l 7 : 0 d i gi t al v ol um e c ont r ol at t enuat e s t he s i gnal i n 0. 5 db i nc r e m ent al f r om 0 t o ? 96 db . 0000 0000 ? 0 db 0000 0001 ? - 0 . 5 d b 0000 0010 ? - 1 db ? 11000000 ? - 96 db (default) 6.2.10 r egist er 18 ? adc co n t ro l 10, d ef ault 001 1 1 000 b i t na m e b i t d e s c ri pt i on al c sel 7 : 6 00 ? a lc of f 01 ? alc right channel only 10 ? alc left channel only 11 ? alc stereo m axg ai n 5 : 3 s et m ax i m um gai n of p g a 000 ? - 6 . 5 db 001 ? - 0.5 db 010 ? 5.5 db 011 ? 11.5 db 100 ? 17.5 db 101 ? 23.5 db 110 ? 29.5 db 111 ? 35.5 db m i n g ai n 2 : 0 s et m i ni m um gai n of p g a 000 ? - 12 db 001 ? - 6 db 010 ? 0 db 011 ? +6 db 100 ? +12 db 101 ? +18 db 110 ? +24 db 111 ? +30 db
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 20 6.2.11 r egist er 19 ? adc co n t ro l 11 , d ef ault 101 1 0 000 b i t na m e b i t d e s c ri pt i on al c l vl 7 : 4 a lc t ar get 0000 ? - 16. 5 db 0001 ? - 15 db 0010 ? - 13. 5 db ?? 0111 ? - 6 db 1000 ? - 4.5 db 1001 ? - 3 db 1010 - 1111 ? - 1.5 db al c h l d 3 : 0 a lc hol d t i m e bef or e g ai n i s i nc r ea s e d 0000 ? 0 ms 0001 ? 2. 6 7m s 0010 ? 5. 3 3m s ?? ( t im e do ubl e s w it h ev er y s t ep ) 1001 ? 0. 6 8s 1 010 o r hi gh e r ? 1. 36 s 6.2.12 r egist er 20 ? adc co n t ro l 1 2 , d ef ault 001 1 0 010 b i t na m e b i t d e s c ri pt i on al c d c y 7 : 4 a lc de c ay ( g ai n r am p up) t i m e, a lc m o de / l imit e r mo d e : 0000 ? 41 0 us / 90. 8 us 0001 ? 82 0 us / 182 us 0010 ? 1 . 64 ms / 363 us ?? ( t i m e do ubl e s w i t h ev er y s t ep ) 1001 ? 21 0 m s / 4 6 . 5 ms 1010 o r higher ? 420 ms/93 ms al c at k 3 : 0 a lc at t a c k ( g ai n r am p do w n) t i m e, a lc m ode / l imit e r mo d e : 0000 ? 10 4 us / 22. 7 us 0001 ? 20 8 us / 45. 4 u s 0 010 ? 41 6 us / 90. 8 u s ?? ( t i m e do ubl e s w i t h v er y s t ep) 1001 ? 53 . 2 ms / 11 . 6 ms 1010 o r higher ? 106 ms/ 23.2 ms
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 21 6.2.13 r egist er 21 ? adc co n t ro l 1 3 , d ef ault 0000 01 10 6.2.14 r egist er 22 ? adc co n t ro l 1 4 , d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on n g th 7 : 3 n oi s e gat e t h r es hol d 0000 0 ? - 76. 5 db f s 0000 1 ? - 75 db f s ?? 11110 ? - 31.5 dbfs 11111 ? - 30 db fs n g g 2 : 1 n oi s e gat e t y pe x0 ? p g a gai n hel d c on s t a nt 01 ? m ut e a d c out put 11 ? reserved n g at 0 n oi s e gat e f u nc t i on e nabl e 0 ? d i s a b le 1 ? enable 6. 3 dac co n t r o l 6.3.1 r egist er 23 ? d a c con tr ol 1, d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on d a c l rs w a p 7 0 ? no r ma l 1 ? left and right channel data swap d a c l rp 6 i 2s , l ef t j us t i f i ed or r i ght j us t i f i ed m ode : 0 ? l ef t and r i ght nor m al po l ar i t y 1 ? left and right invert ed polarity b i t na m e b i t d e s c ri pt i on a l cm o d e 7 d et er m i ne s t he a lc m o de of oper at i on: 0 ? a lc m od e (n o rm a l o p er at i on ) 1 ? limiter mode. a l c zc 6 a lc us es z e r o c r o s s det e c t i on c i r c ui t . 0 ? d i s a b le ( r ec om m en ded ) 1 ? e nable t i m e_ o u t 5 z er o c r o s s t i m e out 0 ? di s a bl e ( d ef aul t ) 1 ? enabl e w i n _ si z e 4 : 0 w i nd ow s s i z e f or pea k det e c t or s et t he w i nd ow s i z e t o n * 16 s am p l e s 001 10 ? 96 s am pl e s ( de f au l t ) 001 1 1 ? 1 02 s am pl es ? . . 11111 ? 496 samples
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 22 d sp / pc m m o d e : 0 ? m s b i s av ai l abl e on 2 nd b c lk r i s i n g edge af t e r a lr c k r i s i n g edge 1 ? msb is available on 1st bclk rising edge after a lrc k rising edgelrck polarity d a c wl 5 : 3 000 ? 24 - b i t s er i al au di o da t a w o r d l engt h 001 ? 20 - b i t s er i al au di o da t a w o r d l engt h 010 ? 18 - b i t s er i al au di o da t a w o r d l engt h 01 1 ? 16 - b i t s er i al au di o da t a w o r d l engt h 100 ? 32 - b i t s er i al au di o da t a w o r d l engt h d a c f o r m a t 2 : 1 00 ? i 2 s s er i al audi o d at a f or m at 01 ? le f t ju s t i f y s er i al au dio dat a f or m at 10 ? r ig h t j u s t if y s er i al audi o dat a f or m at 11 ? d sp/ pc m m ode s er ia l audi o dat a f or m at 6.3.2 r egist er 24 ? dac con t ro l 2, d ef ault 0000 01 10 b i t na m e b i t d e s c ri pt i on d ac fs m o d e 5 0 ? s i ngl e s p eed m od e ( d ef aul t ) 1 ? doubl e s p eed m od e d a c f s r a t i o 4 : 0 m aster mode dac mclk to sampling frequency ratio 0000 0 ? 128 ; 0000 1 ? 192 ; 0001 0 ? 256 ; 000 1 1 ? 3 84; 0010 0 ? 512 ; 0010 1 ? 576 ; 001 10 ? 7 68; ( def aul t ) 001 1 1 ? 10 24 ; 0100 0 ? 1 152 ; 0100 1 ? 140 8; 0101 0 ? 153 6; 010 1 1 ? 21 12 ; 01 1 00 ? 2 304 ; 1000 0 ? 125 ; 1000 1 ? 136 ; 1001 0 ? 250 ; 100 1 1 ? 2 72; 1010 0 ? 375 ; 1010 1 ? 500 ; 101 10 ? 5 44; 101 1 1 ? 7 50; 1 10 00 ? 1 000 ; 1 10 01 ? 1 088 ; 1 10 10 ? 1 496 ; 11 0 11 ? 15 00 ; o t her ? r eserved. 6.3.3 r egist er 25 ? dac co n t ro l 3 , d ef ault 001 1 00 10 b i t na m e b i t d e s c ri pt i on d a c r a m p r a t e 7 : 6 00 ? 0. 5 db p er 4 lr c k di gi t al v olume c ont r ol r amp r at e ( def aul t ) 01 ? 0. 5 db p er 32 l r c k d i git al v olume c ont r ol r am p r at e 10 ? 0. 5 db p er 64 l r c k d i git al v olume c ont r ol r am p r at e 11 ? 0. 5 db p er 128 l r c k di git al v ol ume c ont r ol r amp r at e d a c s o f t ra m p 5 0 ? di s a bl ed di gi t al v ol um e c ont r ol s of t r am p 1 ? enabl ed d i gi t al v olume c ont r ol s o f t r a m p ( def a ult ) d a c l e r 3 0 ? nor m al ( defau lt ) 1 ? bot h c h an nel gai n c ont r ol i s s et by d a c l ef t gai n c ont r ol r egi s t er
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 23 d ac m u t e 2 0 ? nor m al ( d ef aul t ) 1 ? mute analog outputs for both channels 6.3.4 r egist er 26 ? d a c c on t r ol 4, d ef ault 1 100 00 00 b i t na m e b i t d e s c ri pt i on ld a c v o l 7 : 0 d i gi t al v ol um e c ont r ol at t enuat e s t he s i gnal i n 0. 5 db i nc r e m ent al f r om 0 t o ? 96 db . 0000 0000 ? 0 db 0000 0001 ? - 0 . 5 db 0000 0010 ? - 1 db ? 1 10 000 00 ? - 96 db ( def a ul t ) 6.3.5 r egist er 27 ? dac co n t ro l 5 , d ef ault 1 100 00 00 b i t na m e b i t d e s c ri pt i on r da cv o l 7 : 0 d i gi t al v ol um e c ont r ol at t enuat e s t he s i gnal i n 0. 5 db i nc r e m ent al f r om 0 t o ? 96 db . 0000 0000 ? 0 db 0000 0001 ? - 0 . 5 db 0000 0010 ? - 1 db ? 11000000 ? - 96 db (default) 6.3.6 r egist er 28 ? dac co n t ro l 6 , d ef ault 0000 1000 b i t na m e b i t d e s c ri pt i on d eem pha s i s m ode ( d eem p) 7 : 6 00 ? d e - em p has i s f r eq uen c y di s a bl ed ( def aul t ) 01 ? 32 khz de - emphasis frequency in single speed mode 10 ? 44.1 khz de - emphasis frequency in single speed mode 11 ? 48 khz de - emphasis frequency in single speed mode d a c _i nv l 5 0 ? nor m al d a c l ef t c ha nn el anal o g out put no pha s e i nv er s i on ( def aul t ) 1 ? nor m al d a c l ef t c ha nn el anal o g out put 180 de gr ee pha s e i nv er s i on d a c _i nv r 4 0 ? nor m al d a c r i ght c han nel anal og ou t put no pha s e i nv er s i o n ( d e f aul t ) 1 ? nor m al d a c r i ght an al og out put 18 0 degr e e pha s e i nv er s i on c li c k fr e e 3 0 ? di s a bl e di gi t al c l i c k f r e e pow e r up an d dow n 1 ? enabl e di gi t al c l i c k f r e e pow e r up an d dow n ( def a ul t ) 6.3.7 r egist er 29 ? dac co n t ro l 7 , d ef ault 0000 01 10 b i t na m e b i t d e s c ri pt i on z e r ol 7 0 ? nor m al ( d ef aul t ) 1 ? set l eft channel dac output all zero z e r or 6 0 ? nor m al ( d ef aul t ) 1 ? set right channel dac output all zero m ono 5 0 ? s t er eo ( d ef aul t ) 1 ? m ono ( l + r ) / 2 i nt o d a c l an d d a c r s e 4 : 2 se s t r e n g t h 000 ? 0 (default)
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 24 ?? 111 ? 7 v pp_s c al e 1 : 0 00 ? v pp s et at 3. 5v ( 0. 7 m odul at i o n i n dex ) ( d ef au l t ) 01 ? v pp s et at 4. 0v 10 ? vpp set at 3.0v 11 ? vpp set at 2.5v 6.3.8 r egist er 30 ? dac co n t ro l 8 , d ef ault 0001 1 1 1 1 b i t na m e b i t d e s c ri pt i on s hel v i ng_a[ 2 9: 24] 5 : 0 30 - b i t a c oef f i c i ent f or s hel v i ng f i l t er d ef aul t v al ue i s {5'h 0f , 5'h1 f , 5'h0f , 5'h1f , 5'h0f , 5'h1f } 6.3.9 r egist er 31 ? dac co n t ro l 9 , d ef ault 1 1 1 1 01 1 1 b i t na m e b i t d e s c ri pt i on s hel v i ng_a[ 2 3: 16] 7 : 0 30 - b i t a c oef f i c i ent f or s hel v i ng f i l t er d ef aul t v al ue i s {5'h 0f , 5'h1 f , 5'h0f , 5'h1f , 5'h0f , 5'h1f } 6.3.10 r egist er 32 ? dac co n t ro l 10, d ef ault 1 1 1 1 1 1 01 b i t na m e b i t d e s c ri pt i on s hel v i ng_a[ 1 5: 8] 7 : 0 30 - b i t a c oef f i c i ent f or s hel v i ng f i l t er d ef aul t v al ue i s {5'h 0f , 5'h1 f , 5'h0f , 5'h1f , 5'h0f , 5'h1f } 6.3.11 r egist er 33 ? dac co n t ro l 11 , d ef ault 1 1 1 1 1 1 1 1 b i t na m e b i t d e s c ri pt i on s hel v i ng _a[ 7: 0] 7 : 0 30 - b i t a c oef f i c i ent f or s hel v i ng f i l t er d ef aul t value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.12 r egist er 34 ? dac co n t ro l 12, d ef ault 0001 1 1 1 1 b i t na m e b i t d e s c ri pt i on s hel v i ng_b[ 2 9: 24] 5 : 0 30 - b i t a c oef f i c i ent f or s hel v i ng f i l t er d ef aul t v al ue i s {5'h 0f , 5'h1 f , 5'h0f , 5'h1f , 5'h0f , 5'h1f } 6.3.13 r egist er 35 ? dac co n t ro l 13, d ef ault 1 1 1 1 01 1 1 b i t na m e b i t d e s c ri pt i on s hel v i ng_b[ 2 3: 16] 7 : 0 30 - b i t a c oef f i c i ent f or s hel v i ng f i l t er d ef aul t v al ue i s {5'h 0f , 5'h1 f , 5'h0f , 5'h1f , 5'h0f , 5'h1f } 6.3.14 r egist er 36 ? da c co n t ro l 14, d ef ault 1 1 1 1 1 1 01 b i t na m e b i t d e s c ri pt i on s hel v i ng_b[ 1 5: 8] 7 : 0 30 - b i t a c oef f i c ient f or s hel v ing f il t er d ef aul t v alue is {5'h 0f , 5'h1 f , 5'h0f , 5'h1f , 5'h0f , 5'h1f }
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 25 6.3.15 r egist er 37 ? dac co n t ro l 15, d ef ault 1 1 1 1 1 1 1 1 b i t na m e b i t d e s c ri pt i on s hel v i ng_b[ 7: 0] 7 : 0 30 - b i t a c oef f i c i ent f or s hel v i ng f i l t er d ef aul t v al ue i s {5'h 0f , 5'h1 f , 5'h0f , 5'h1f , 5'h0f , 5'h1f } 6.3.16 r egist er 38 ? dac co n t ro l 16, d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on l m i xsel 5 : 3 lef t i nput s el ec t f or out p ut m i x 000 ? r es er v ed ( def aul t ) 001 ? l i n 1 010 ? r es er v ed 01 1 ? left adc input (after mic amplifier) r m i xsel 2 : 0 r i ght i np ut s e l ec t f or out put m i x 000 ? r es er v ed ( def aul t ) 001 ? r i n 1 010 ? r es er v ed 01 1 ? right adc input (after mic amplifier) 6.3.17 r egist er 39 ? dac co n t ro l 17 , d ef ault 001 1 1 000 b i t na m e b i t d e s c ri pt i on ld 2 lo 7 0 ? left dac to left mixer disable (default) 1 ? left dac to left mixer enable li 2lo 6 0 ? lin signal to left mixer disable (default) 1 ? lin signal to left mixer enable li 2lo v o l 5 : 3 li n s i g nal t o l ef t mix e r g a i n 000 ? 6 db 001 ? 3 db 010 ? 0 db 01 1 ? - 3 db 100 ? - 6 db 101 ? - 9 db 1 10 ? - 12 db 1 11 ? - 15 db (default) 6.3.18 r egist er 40 ? dac co n t ro l 18, d ef ault 001 1 1 000 b i t na m e b i t d e s c ri pt i on 6.3.19 r egist er 41 ? dac co n t ro l 19, d ef ault 001 1 1 000 b i t na m e b i t d e s c ri pt i on 6.3.20 r egist er 42 ? dac co n t ro l 20, d ef ault 001 1 1 000 b i t na m e b i t d e s c ri pt i on r d2 r o 7 0 ? right dac to right mixer disable (default) 1 ? right dac to right mixer enable
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 26 ri2ro 6 0 ? rin signal to right mixer disable (default) 1 ? rin signal to right mixer enable r i 2r o v o l 5 : 3 r i n s i gnal t o r i ght m i x er ga i n 000 ? 6 db 001 ? 3 db 010 ? 0 db 01 1 ? - 3 db 100 ? - 6 db 101 ? - 9 db 1 10 ? - 12 db 111 ? - 15 db (default) 6.3.21 r egist er 43 ? dac co n t ro l 21, d ef ault 001 1 1 000 b i t na m e b i t d e s c ri pt i on slrck 7 0 ? daclrc and adclrc separate (default) 1 ? daclrc and adclrc same lrck_sel 6 master mode , if slrck = 1 then 0 ? use dac lrck (default) 1 ? use adc lrck offset_dis 5 0 ? disable offset (default) 1 ? enable offset mc l k _ d i s 4 0 ? nor m al ( d ef aul t ) 1 ? disa ble mclk input from pad adc _dl l _p w d 3 0 ? nor m al ( d ef aul t ) 1 ? adc dll power down dac _dl l _p w d 2 0 ? nor m al ( d ef aul t ) 1 ? dac dll power down 6.3.22 r egist er 44 ? dac co n t ro l 22, d ef ault 001 1 1 000 b i t na m e b i t d e s c ri pt i on of fset 7 :0 dc offset 6.3.23 r egist er 45 ? dac co n t ro l 23, d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on vr o i 4 0 ? 1.5k vref to analog output resistance (default) 1 ? 40k vref to analog output resistance 6.3.24 r egist er 46 ? dac co n t ro l 24, d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on 6.3.25 r egist er 47 ? dac c on t r ol 25, d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 27 6.3.26 r egist er 48 ? dac co n t ro l 26, d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on lo u t 1 vo l 5 : 0 lo u t 1 v o l u me 0000 00 ? - 30 d b ( def aul t ) 0000 01 ? - 29 db 0000 10 ? - 28 db ? 0 11 11 0 ? 0 db 0 11 11 1 ? 1 db ? 100001 ? 3d b 6.3.27 r egist er 49 ? dac co n t ro l 27, d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on r o u t 1 v o l 5 : 0 r o u t 1 v o l u me 0000 00 ? - 30 d b ( def aul t ) 0000 01 ? - 29 db 0000 10 ? - 28 db ? 0 11 11 0 ? 0 db 0 11 11 1 ? 1 db ? 1000 01 ? 3 db 6.3.28 r egist er 50 ? dac co n t ro l 28, d ef ault 0000 0000 b i t n a me b i t d e s c ri pt i on 6.3.29 r egist er 51 ? dac co n t ro l 29, d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on hplout1_ref1 7 reserved hplout1_ref2 6 reserved 6.3.30 r egist er 52 ? dac co n t ro l 30, d ef ault 0000 0000 b i t na m e b i t d e s c ri pt i on s p k lo ut 2_r ef 1 7 reserved sp kl o ut 2_r ef 2 6 reserved m i x er _r ef 1 3 reserved m i x er _r ef 2 2 reserved m r ef 1 1 reserved m r ef 2 0 reserved 7 d ig it a l au d i o i n terface the device pr ovides f our f or m at s of se r i al audi o dat a i nt er f ace t o t he i nput of
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 28 t h e dac or out put f r o m t he a d c t hr ough lr c k , sc lk and s d i n/ sdo ut pi ns. the f our f o r m at s ar e i 2 s, le f t j u s t if ie d , r ig h t ju st if ie d a n d dsp/ pcm m o d e . dac i nput dsdi n is sa m p le d b y es8 3 2 3 on t he r i sing edge of d s c lk . a d c dat a i s out on a s d o u t and ch anges o n t he f al l i n g edge of a s c l k . the r el at i ons hi p of sd at a ( sdi n/ sdo ut ) , s c lk and l rck w i t h t he t hr ee f or m a t s i s sh ow n t hr ough fi g ur e 3 t o fi gur e 7. n- 2 n-1 n 3 2 1 1 s c l k ms b lsb left channel n- 2 n-1 n 3 2 1 1 s c l k ms b ls b right channel s dat a s cl k l rck fi gur e 3 i 2 s s er i al a u di o d at a f or m at u p t o 24 - b it n- 2 n-1 n 3 2 1 ms b lsb left channel n- 2 n-1 n 3 2 1 ms b lsb right channel s dat a s cl k l rck fi gur e 4 le f t ju st i f i ed s er i al a u di o d at a for m at u p t o 24 - b it n- 2 n-1 n 3 2 1 ms b lsb left channel n- 2 n-1 n 3 2 1 ms b ls b right channel s dat a s cl k l rck fi gur e 5 r i ght ju st i f i ed s er i al a u di o d at a f or m at u p t o 24 - b it fi gur e 6 d sp/ pcm m ode a
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 29 fi gur e 7 d sp/ pcm m ode b 8 e l e c t ri cal ch ara c t e r i s t i cs 8. 1 a bsol ut e m a xi m um rat i ngs c onti nu ous oper at i on at or beyo nd t hese c ondi t i on s m a y perm anent ly damag e t he device . p ar am et e r m i n m ax a nal og s up pl y voltage level - 0.3v +5.0v d ig i t a l supply voltage level - 0.3v +5.0v i nput v ol t age range dgnd - 0.3v dvdd+0.3v o per at i ng t emperature range - 40 c +85 c s t or age t em perature - 65 c + 150 c 8. 2 r ecom m e nded o per at i ng c ondi t i ons p ar am et e r min typ max unit a nal og s up pl y voltage level 1.7 3.3 3.6 v d ig i t a l supply voltage level 1.5 1.8 3.6 v 8. 3 adc a n al og and fi l t er c har act er i st i cs an d s peci f i cat i ons t est co ndi t i ons ar e as t he f ol l ow i n g unl ess ot her w i se sp ecif y: a vd d= + 3 . 3 v , dvdd= + 1 . 8 v , ag nd= 0 v , dg nd= 0 v , am b ie n t t em per at ur e= + 25 c , fs= 48 khz , 96 k h z or 192 k h z , m c lk / lr c k = 256. p ar am et e r m i n t yp m ax u ni t a d c performance d y nam i c r ange (note 1) 85 95 98 db th d + n - 88 - 85 - 75 db c ha nnel s e p aration ( 1khz) 80 85 90 db si g n al t o noise ratio 85 95 98 db i nt er c h ann el gain mismatch 0.1 db g ai n e r r or 5 % fil t er f r e que nc y r e s p on s e ? s i ngl e s p eed p as s ban d 0 0. 4535 fs
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 30 s t opband 0. 5465 fs p as s ban d r i ppl e 0. 05 db s t opband a t t enuat i o n 50 db filter frequency response ? double speed p as s ban d 0 0. 4167 fs s t opband 0. 5833 fs p as s ban d r i ppl e 0. 005 db s t opband a t t enuat i o n 50 db analog input f ul l s c al e i np ut lev el a vd d / 3 . 3 vr m s i nput i m peda nc e 20 k n ot e 1. t he v al ue i s m ea s u r ed u s ed a - w ei ght ed f i l t er . 8. 4 dac a n al og and fil t er c har acteri st i cs an d s peci f i cati ons t est co ndi t i ons ar e as t he f ol l ow i n g unl ess ot herw i se sp ecif y: a vd d= + 3 . 3 v , dvdd= + 1 . 8 v , ag nd= 0 v , dg nd= 0 v , am b ie n t t em perat ur e=+ 25 q c , fs= 48 khz , 96 kh z or 192 k h z , m cl k/ l rc k= 256. p ar am et e r m i n t yp m ax u ni t d a c p e rf o rm a n c e d y nam i c r a n ge ( note 1) 83 96 98 db th d + n - 85 - 83 - 75 db c ha nnel s e p ar at i on ( 1khz) 80 85 90 db si g n al t o n oi s e r atio 83 96 98 db i nt er c h ann el g ai n m ismatch 0. 0 5 db f i l t er f r e que nc y r e s p on s e ? s i ngl e s p eed p as s ban d 0 0. 4535 fs s t opband 0. 5465 fs p as s ban d r i ppl e 0. 05 db s t opband a t t enuatio n 40 db f i l t er f r e que ncy r e s p on s e ? d ou bl e s peed passband 0 0.4167 fs s t opband 0. 5833 fs p as s ban d r i ppl e 0. 005 db s t opband a t t enuatio n 40 db d e - em pha s i s e rror at 1 k h z ( s i ngl e s pe ed m ode o nl y ) f s = 3 2 k h z f s = 4 4 . 1 kh z f s = 4 8 k h z 0. 002 0. 013 0.0009 db a nalog o ut p u t full s c al e o u t put lev el a vd d / 3 . 3 vr m s n ot e 1. t he v al ue is m ea s u r ed u s ed a - w ei ght ed f il t er .
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 31 8. 5 p ow er c onsum pt i on c har act er i st i cs parameter min typ max unit normal operation mode d vd d = 1 . 8 v , a vd d = 1 . 8 v : p l ay bac k p l ay bac k a n d r ec or d d vd d = 3 . 3 v , a vd d = 3 . 3 v : p l ay bac k p l ay bac k a n d r ec or d 7 16 31 59 m w power down mode d vd d = 1 . 8 v , a vd d = 1 . 8 v d vd d = 3 . 3 v , a vd d = 3 . 3 v 0 . 3 1 . 9 m w 8. 6 se r i al a udi o p or t s w i t chi ng s peci f i cat i on s p ar am et e r s y m bol m i n m ax unit m c lk f r eq ue nc y 51. 2 mh z m c l k d u ty cyc l e 40 60 % lr c k f r equ e nc y 200 kh z lr c k dut y c y c l e 40 60 % s c lk f r equ e nc y 26 mh z s c lk pul s e w i d t h l o w t scl kl 15 ns s c lk p ul s e w i d t h hi gh t scl kh 15 ns s c lk f al l i ng t o lr c k edge t s lr C 10 10 ns s c lk f al l i ng t o s d o u t v al i d t sdo 0 ns s d i n v al i d t o s c lk r i s i ng s et up t i m e t sdis 10 ns s c lk r i s i ng t o s d i n hol d t i m e t sdih 10 ns 8. 7 s er i al c ont r ol p or t s w i t chi ng s peci f i cat i o ns p ar am et e r s y m bol m i n m ax u ni t figure 8 serial audio port timing
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 32 spi mode s p i _c lk c l o c k f r eque nc y 10 mh z spi _ c l k e d g e t o spi _ c sn f a l l i n g t spics 5 ns s p i _c s n h i g h t i m e b et w e en t r an s m i s s i ons t spish 500 ns spi _ c sn f a l l i n g t o spi _ c l k e d g e t spisc 10 ns spi _ c l k l o w t i m e t spicl 4 5 ns spi _ c l k h i g h t i m e t spich 45 ns spi _ d i n t o spi _ c l k r i s i n g s e t u p t i m e t spids 10 ns s p i _c lk r i s i ng t o d a t a h ol d t i m e t spidh 15 ns 2 - wire mode s c l c l oc k f r eque nc y f scl 100 kh z b us f r ee t i m e b et w een t r ans m i s s i on s t tw i d 4 . 7 us s t ar t c on di t i o n h o l d t i m e t tw s t h 4 . 0 us c l oc k lo w t i m e t tw c l 4 . 0 us c lo c k h i g h t i me t tw c h 4 . 0 us s et up t i m e f or r e peat e d s t ar t c on di t i o n t tw s t s 4 . 7 us s d a h o l d t i me f r o m s c l f a ll i n g t tw d h 0 . 1 us s d a s et up t i m e t o s c l r i s i ng t tw d s 100 ns r is e t ime o f s c l t tw r 25 us f a ll t i me s c l t tw f 25 ns spi _ d i n spi _ c l k spi _ c sn t spi c s t spi sc t spids t spidh t spich t spicl t spish s p sd a sc l t twsts t twsth t twch t t wc l t twdh t twds t twf t twr s t twid fi gur e 10 s er i a l c ont r ol p or t 2 - w ir e t im in g fi gur e 9 s er i al co n t r o l po r t spi t im in g
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 33 9 package information
e ver est s e m i conduct or es8 3 2 3 r ev i s i on 1. 0 a p r i l 2 0 1 1 34 10 cor p o ara t i o n i nf or m a t i o n e ve r est s em i co nduct o r c o. , l t d. ??? 328 ?????? 6a ? 2 15028 e m ai l : i nf o @ eve r est - se m i . co m

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