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MP6922A dual, fast-turn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 1 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. the future of analog ic technology description the MP6922A is a dual, fast-turn?off, intelligent rectifier for synchronous rectification in llc resonant converters. the ic drives two n-channel mosfets and regulates their forward voltage drop to about 30mv and turns it off before the switching current goes negative. MP6922A has a light-load function to latch off the gate driver under light-load conditions, thus limiting the current to below 600 a. the MP6922A?s fast turn-off enables both continuous-conduction mode and discontinuous-conduction mode. an internal reverse-current protection function ensures safe mosfet operation under high-frequency continuous-current conditions. MP6922A requires a minimal number of readily- available standard external components and is available in soic8e, soic8, and soic14 packages. features ? works with both standard and logic-level mosfets ? compatible with energy star?s 0.5w standby requirements ? v dd range from 8v to 24v ? fast turn-off total delay of 20ns ? reverse-current?protection function ? maximum switching frequency of 300khz ? <600 a quiescent current in light-load mode ? supports ccm, crcm and dcm operation ? available in soic8e, soic8, and soic14 packages applications ? ac-dc adapters ? lcds & pdp tvs ? telecom smps all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under products, quality assurance page. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application soic8
MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 2 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. soic8e soic14
MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 3 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ordering information part number package top marking MP6922Agse* soic8 MP6922A MP6922Agn** soic8e MP6922A MP6922Ags*** soic14 MP6922A *for tape & reel, add suffix ?z (e.g. MP6922Agse?z); **for tape & reel, add suffix ?z (e.g. MP6922Agn?z); ***for tape & reel, add suffix ?z (e.g. MP6922Ags?z); package reference absolute maxi mum ratings (1) v dd to v s1 ,v s2 , v ss ........................ -0.3v to +26v pgnd to v s1 ,v s2 , v ss ................... -0.3v to +0.3v v g1 to v s1 , v ss ................................. -0.3v to v dd v g2 to v s2 , v ss ................................. -0.3v to v dd v d1 to v s1 , v ss ............................. -0.7v to +180v v d2 to v s2 , v ss ............................. -0.7v to +180v ll, en to v s1 ,v s2 , v ss .................. -0.3v to +6.5v maximum operating frequency ............ 300 khz continuous power dissipation .. (t a = +25c) (2) soic8 ........................................................ 1.4w soic8e ...................................................... 2.5w soic14 ...................................................... 1.5w junction temperature ............................... 150c lead temperature (solder)....................... 260c storage temperature .............. -55c to +150c recommended operation conditions (3) v dd to v s1 ,v s2 , v ss ............................... 8v to 24v operating junction temp. (t j ). -40c to +125c thermal resistance (4) ja jc soic8 ..................................... 90 ...... 45 ... c/w soic8e ................................... 50 ...... 10 ... c/w soic14 ................................... 86 ...... 38 ... c/w notes: 1) exceeding these ratings may damage the device. 2) t a =+25 . the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to-ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous powe r dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb. without heatsink.
MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 4 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. electrical characteristics v dd = 12v, -40c t j 125c, unless otherwise noted. parameter symbol conditions min typ max units v dd voltage range 8 24 v v dd uvlo threshold rising 4.8 6.0 7.0 v hysteresis 0.5 1 1.5 v operating current i cc c load =5nf, f sw =100khz 12 18 23 ma c load =10nf, f sw =100khz 24 27 31 ma shutdown current v dd =20v, en=0v 600 a light-load mode current 600 a thermal shutdown 150 c thermal shutdown hysteresis 30 c enable shutdown threshold rising 1.1 1.5 2.0 v hysteresis 0.2 0.45 v enable uvlo threshold rising 2.3 3 3.6 v hysteresis 0.2 0.45 v internal pull-up current on en 10 16 a control circuitry section v s1,2 ?v d1,2 forward voltage v fwd 15 30 45 mv turn-on delay don c load =5nf -20c t j 125c 150 200 ns -40c t j <-20c 250 don c load =10nf -20c t j 125c 250 300 ns -40c t j <-20c 350 input bias current on v d1,2 pin v d1,2 = 180v 1.5 a minimum on-time min c load = 5nf 1 s minimum off-time off 1.6 s light-load?enter delay ll-dela y r ll =100k ? 80 160 260 s light-load?enter pulse width ll r ll =100k ? 2.2 s light-load turn-on pulse width hysteresis ll-h r ll =100k ? 0.2 s light-load?enter off period width ll-off r ll =100k ? 50 s light-load exit-pulse width threshold (v d1 , 2 -v s1 , 2 ) v ll-ds -450 -300 -140 mv light-load enter-pulse width threshold (v g1 , 2 -v s1 , 2 ) v ll-gs 1.0 v reverse-current?protection threshold v rcp 2.5 3 3.5 v reverse-current?protection latch time rcp 80 150 230 s gate driver section v g1 , 2 (low) i load =1ma 0.1 v v g1,2 (high) v dd >16v 13 14.5 16 v v dd <16v v dd -2.2 turn-off threshold (v s1,2 - v d1 , 2 ) -30 mv turn-off propagation delay v d1 , 2 = v ss 15 ns
MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 5 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. electrical characteristics (continued) v dd = 12v, -40c t j 125c, unless otherwise noted. parameter symbol conditions min typ max units turn-off total delay doff v d1,2 = v ss , c load =5nf, r gate =0 ? 50 75 ns v d1,2 = v ss , c load =10nf, r gate =0 ? 50 75 ns pull-down impedance 1 2 ? pull-down current 3v MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 6 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. pin functions pin # (soic8) pin # (soic8e) pin # (soic14) name description 1 1 2 v g2 mosfet 2 gate driver output. 3 2 3 en enable pin. enables the internal ic logic when the en pin voltage exceeds the en shutdown threshold; the gate driver remains latched until the en voltage exceeds the en uvlo threshold. 4 3 6 v d2 mosfet 2 drain voltage sense . - 4 7 v s2 source pin used as reference for v d2 . - 5 8 v s1 source pin used as reference for v d1 . 6 6 9 v d1 mosfet 1 drain voltage sense. 7 7 12 v dd supply voltage. 8 8 13 v g1 mosfet 1 gate driver output. 2 exposed pad 1,14 pgnd power ground. power switch return. - - 5,10 nc no connection. - - 4 ll light-load?timing set. connect a resistor to set the light-load timing. - - 11 rcp reverse current protection. internal 5v reference. 5 - - v ss common source. used as reference for both channels.
MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 7 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical characteristics 225 230 235 240 245 250 255 260 265 -50 -30 -10 10 30 50 70 90 110130150 5.7 5.75 5.8 5.85 5.9 5.95 6 6.05 6.1 6.15 -50 -30 -10 10 30 50 70 90 110 130150 370 380 390 400 410 420 430 440 450 -50 -30 -10 10 30 50 70 90 110130150 0 50 100 150 200 250 -50 0 50 100 150 0 50 100 150 200 250 300 350 -50 0 50 100 150 0 5 10 15 20 25 30 35 40 45 50 -50 0 50 100 150 0 5 10 15 20 25 30 35 40 45 50 -50 0 50 100 150 30 31 32 33 34 35 -50 0 50 100 150
MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 8 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v dd = 12v, unless otherwise noted. v ds1 20v/div. v gs1 5v/div. i sd1 5a/div. v ds1 20v/div. v gs1 5v/div. i sd1 5a/div. v ds1 20v/div. v gs1 5v/div. i sd1 5a/div. v ds2 20v/div. v gs2 5v/div. i sd2 2a/div. v ds2 20v/div. v gs2 5v/div. i sd2 5a/div.
MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 9 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. block diagram figure 1: functional block diagram
MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 10 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. operation the MP6922A operates in discontinuous- conduction mode (dcm), continuous-conduction mode (ccm), and critical conduction mode (crcm) condition. operating in either dcm or crcm, the control circuitry controls the gate in forward mode; it turns the gate off when the mosfet current is low. in ccm, the control circuitry turns off the gate during very fast transients. blanking the control circuitry contains a blanking function that ensure that when the mosfet turns on/off, the mosfet remains in that state for ~1 s, which determines the minimum on-time. during the turn-on blanking period, the turn-off threshold is not totally blanked, but changes to ~+100mv (instead of +30mv). this ensures that the part can always turn off even during the turn-on blanking period (albeit slower, so avoid setting the synchronous period to less than 1 s at ccm condition in the llc converter to eliminate shoot-through). vd clamp the MP6922A uses a high-voltage jfet at its input because v d1,2 can go as high as 180v. connect a small resistor between the v d1,2 pin and the external mosfet drain to avoid excessive currents when v g goes below -0.7v. under-voltage lockout (uvlo) when v dd goes below the uvlo threshold, the part enters sleep mode and a 10k ? resistor pulls down v g . enable pin if en is pulled low, the part enters sleep mode. thermal shutdown if the junction temperature of the ic exceeds 150c, v g is pulled low and the part stops switching. the part resumes normal operation after the junction temperature has dropped to 120c. turn-on phase v ds (v d ?v ss ) goes negative (<-500mv) when the switch current flows through the mosfet?s body diode. if v ds is much lower than the turn-on threshold of the control circuitry (-30mv), then the mosfet turns on after about 200ns turn-on delay (figure 2). triggering the turn-on threshold (-30mv) causes the circuit to add a blanking time (minimum on- time 1 s), during which the turn-off threshold changes from +30v to +100mv. this blanking time avoids erroneous triggering caused by ringing on the synchronous power switch. v ds v gate t don t doff -30mv 2v 0mv figure 2: turn-on and turn-off delay conducting phase when the mosfet turns on, v ds (-i sd r ds(on) ) rise relative to the switch current (i sd ) drop. when v ds rises above the turn-on threshold (?30mv), the control circuitry stops pulling up the gate driver and the mosfet driver voltage drops, which increases the mosfet?s r ds(on) . this adjusts v ds (-i sd r ds(on) ) to around -30mv even when the switch current i sd is fairly small, and can prevent the internal driver from triggering until the current through the mosfet has dropped to near zero. turn-off phase when v ds rises to trigger the turn-off threshold (30mv), the control circuitry pulls down the driver switch voltage after a 20ns turn-off delay (shown in figure 2). similarly, a 1.6 s blanking time occurs after the switch turns off, during which the mosfet does not turn on to avoid erroneous triggering. figure 3 shows the MP6922A operating under a heavy-load. the high current initially saturates the driver voltage. after v ds goes above ?30mv, the driver voltage decreases to adjust the v ds to around ?30mv.
MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 11 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. figure 4 shows the MP6922A operating at light- load. the low current prevents the driver voltage from saturating but decreases when the synchronous power switch turns on and adjusts v ds . -30mv 0mv vds vgs isd figure 3: synchronous rectification operation at heavy load -30mv 0mv vds vgs isd figure 4: synchronous rectification operation at light load light-load latch-off function the gate driver of MP6922A is latched to limit driver losses under light-load condition to improve light-load efficiency. normal operation latch off when the mosfet?s switching-cycle conducting period falls below 2.2 s ( ll ), the MP6922A enters light-load mode and latches off the mosfet after a 160 s delay (light-load-enter delay, ll-delay ) after entering light-load mode, the MP6922A monitors the mosfet?s body diode conducting period by sensing v ds (when v ds exceeds ? 300mv (v ll-ds ), MP6922A treats the the mosfet?s body-diode conducting period as finished). if the mosfet?s body diode conducting period exceeds 2.4 s ( ll + ll-h ), light- load mode ends and the mosfet unlatches to restart the synchronous rectification. for the soic14 package. the MP6922A has an ll pin that allows ll to be adjusted by an external resistor: ll ll r 2.2 s 100k ?? ?? ? latch off during burst operation the ic also monitors the synchronous mosfet off period. if the off period exceeds the light- load?enter off period width ( ll-off ), the MP6922A enters light-load mode and latches off the gate driver. the gate driver is unlatched when the drain- source voltage of the synchronous mosfet v ds drops below ?30mv. reverse current?protection function when the llc system operates in ccm at a very high frequency, the synchronous current may reverse before the ic turns off the gate driver, which can lead to shoot-through (in center- tapped outputs with full-wave rectification topologies). the MP6922A has a protection function to latch off the gate driver when the current reverses before the driver signal is pulled low. when the synchronous current reverses, the high spike can be observed between the mosfet?s drain/source. the MP6922A monitors the voltage through the rcp pin using a voltage divider. when the voltage of rcp pin exceeds v rcp , MP6922A latches the driver signal of both channels for ~150 s ( rcp ) to protect the synchronous mosfet. at the end of rcp , MP6922A restarts the synchronous rectification.
MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 12 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical application circuit agnd agnd agnd pgnd pgnd agnd agnd agnd 5 4 l1 agnd 3 2 4 1 6 7 8 5 t1 cs vcc vcc burst cs cs 6 ct 3 bo 7 latch 8 fset 4 burst 5 ss 1 timer 2 lg 11 sw 14 gnd 10 n.c. 13 vcc 12 bst 16 hg 15 pfc 9 u1 hr1000a vd2 3 vd1 6 vs2 4 en 2 vs1 5 vdd 7 vg2 1 vg1 8 u2 MP6922Agn nc 5 vd2 6 pgnd 1 vg2 2 nc 10 rcp 11 vd1 9 pgnd 14 vg1 13 en 3 vs2 7 vs1 8 vdd 12 ll 4 u3 MP6922Ags pgnd pgnd pgnd vg1 vg2 vg1 vg2 pgnd vd1 vd2 vs1 vs2 vs2 vg1 vg2 vs1 vd1 burst pgnd vd2 10 r23 0 r4 2.21k r2 820k r3 9.53k r1 3.57k r5 1m r6 10k r7 1m r8 10 r10 10 r9 10k r12 10k r11 1 r14 1 r15 1 r13 1k r16 51 r17 1k r21 1k r22 10k r25 10k r27 10 r28 10 r26 10 r24 10k r19 2k r20 100k r18 10k r29 137k r30 10k r36 38.3k r35 3.3k r31 1k r34 1.8k r33 40.2k r32 1 2 cn1 1 2 cn2 ss-5-1a 2 1 f1 3 4 2 1 cr1 1uf c1 0.47uf c2 470pf c3 10nf c4 100n c7 2.2uf c8 1 2 100uf c9 10nf c10 120nf cx1 2.2nf c13 2.2nf c14 1nf c12 2.2uf c15 470pf c19 0.1uf c21 22nf c16 10uf c17 1 2 2200uf c20 1 2 2200uf c18 1 2 100uf c5 1 2 100uf c6 1 2 d1 1 2 d2 1 2 d4 1 2 d5 1 2 d6 2 3 1 m2 2 3 1 m1 1 2 4 3 u4 pc817a 1 2 3 u5 1nf c11 1 2 d3 4 m3 4 m4 1nf c22 1nf c23 vg1 vg2 vs1 vs2 vd1 vd2 vdd vdd pgnd vd2 3 vd1 6 4 en 2 vss 5 vdd 7 vg2 1 vg1 8 u6 MP6922Ags e pgnd 50uh 800uh figure 5?synchronous rectification in llc with MP6922A
MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 13 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. package information soic8 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0.0075(0.19) 0.0098(0.25) 0.150(3.80) 0.157(4.00) pin 1 id 0.050(1.27) bsc 0.013(0.33) 0.020(0.51) seating plane 0.004(0.10) 0.010(0.25) 0.189(4.80) 0.197(5.00) 0.053(1.35) 0.069(1.75) top view front view 0.228(5.80) 0.244(6.20) side view 14 85 recommended land pattern 0.213(5.40) 0.063(1.60) 0.050(1.27) 0.024(0.61) note: 1) control dimension is in inches. dimension in bracket is in millimeters. 2) package length does not include mold flash, protrusions or gate burrs. 3) package width does not include interlead flash or protrusions. 4) lead coplanarity (bottom of leads after forming) shall be 0.004" inches max. 5) drawing conforms to jedec ms-012, variation aa. 6) drawing is not to scale. 0.010(0.25) bsc gauge plane
MP6922A?dual, fast-t urn?off, intelligent rectifier MP6922A rev. 1.02 www.monolithicpower.com 14 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. soic8e (exposed pad)
MP6922A?dual, fast-t urn?off, intelligent rectifier notice: the information in this document is subject to change wi thout notice. users should warrant and guarantee that third party intellectual property rights are not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP6922A rev. 1.02 www.monolithicpower.com 15 11/30/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. soic14 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0.0075(0.19) 0.0098(0.25) 0.150 (3.80) 0.157 (4.00) pin 1 id 0.050(1.27) bsc 0.013(0.33) 0.020(0.51) seating plane 0.004(0.10) 0.010(0.25) 0.338(8.55) 0.344(8.75) 0.053(1.35) 0.069(1.75) top view front view 0.228 (5.80) 0.244 (6.20) side view 1 7 14 8 recommended land pattern 0.213 (5.40) 0.063 (1.60) 0.050(1.27) 0.024(0.61) note: 1) control dimension is in inches. dimension in bracket is in millimeters. 2) package length does not include mold flash, protrusions or gate burrs. 3) package width does not include interlead flash or protrusions. 4) lead coplanarity (bottom of leads after forming) shall be 0.004" inches max. 5) drawing conforms to jedec ms-012, variation ab. 6) drawing is not to scale. 0.010(0.25) bsc gauge plane

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