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october 2013 ? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination fan23sv04t tinybuck? 4 a integrated synchronous buck regulator for ddr termination features ? v in range: 7 v to 15 v using internal linear regulator for bias ? v in range: 4.5 v to 5. 5 v with v in /p vin /p vcc connected to bypass internal regulator ? high efficiency ? continuous o utput c urrent : 4 a ? mosfets r ds, on (t yp ical ): hs : 9.67 m , ls : 5.46 m ? internal linear bias regulator ? internal v ddq resistor divider ? excellent l ine and l oad t ransient r esponse ? output v oltage range: 0. 5 to 1.5 v ? programmable f requency : 200 k hz to 1 .5 mhz ? programmable soft - start ? low shutdown current ? adjustable s ourcing c urrent l imit ? internal boot diode ? thermal s hutdown ? halogen and lead free, rohs c ompliant applications ? bus t ermination ? servers and d esktop c omputers ? nvdc notebooks, netbooks ? game consoles description the fan23sv04t is a highly efficient, integrated tinybuck? synchronous buck regulator for use in tracking applications, such as ddr termination rails. the v ddq input includes an internal 2:1 resistive voltage divider to reduce total circuit size and component count. the regulator operates with an input range from 7 v to 15 v and s upports up to 4 a load currents. the device can operate from a 5 v rail (10%) if v in , p vin , and p vcc are connected together to bypass the internal linear regulator. this device utilize s fairchild ? s constant on - time control architecture to provide excellen t transient response and to maintain a relatively constant switching frequency. s witching frequency and sourcing over - current protection can be programmed to provide a flexible solution for various applications. output over - current , and t hermal shutdown protections help prevent damage during fault conditions . a hysteresis feature restarts the device when normal operating temperature is reached. order ing information part number configuration operating temperature range output current package FAN23SV04TMPX pwm m ode with v ddq t rack ing i nput - 40 to 85c 4 a 34- lead, pqfn , 5.5 mm x 5.0 mm please address requests and support questions to tinybucksupport@fairchildsemi.com .
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 2 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination typical application diagrams v out =0.6v r2 1k r9 27.4k r7 61.9 k r5 1.02k c3 0.1f c2 10f c10 0.1 f c9 2.2f c4 0.1f r11 10 r3 10k c5 470pf c10a 47f c10b 47f c10d 47f 1 9 27 26 18 34 2 3 8 7 4 5 6 28 29 30 31 32 33 19 20 21 22 23 24 25 11 14 12 pvin agnd pvin pvin pvin pvin pvin sw sw sw sw sw pgnd pgnd pgnd pgnd sw vcc pvcc ilim fb nc nc nc vddq en freq ss agnd boot sw vin pvin 10 17 16 15 13 sw l1 1h v in =12v vddq fan23sv 04t c7 15nf c10d 47f r8 10k figure 1. typical application with v in = 12 v r2 1k r9 27.4k r7 0? r5 1.02k c3 0.1f c2 10f c10 0.1f c9 2.2f c4 0.1f r11 10 r3 10k c5 470pf c10a 47f c10b 47f c10d 47f 1 9 27 26 18 34 2 3 8 7 4 5 6 28 29 30 31 32 33 19 20 21 22 23 24 25 11 14 12 pvin agnd pvin pvin pvin pvin pvin sw sw sw sw sw pgnd pgnd pgnd pgnd sw vcc pvcc ilim fb nc nc nc vddq en freq ss agnd boot sw vin pvin 10 17 16 15 13 sw l1 1h v in =5v v out =0.6v vddq fan23sv04t c7 15nf c10d 47f r8 open figure 2. typical application with v in = 5 v
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 3 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination functional block diagram control logic pv cc pv cc modulator thermal shutdown fb comparator current limit comparator hs gate driver ls gate driver v cc linear regulator vcc uvlo pv cc sw pgnd freq vddq fb vcc pvcc vin boot pvin agnd v cc en enable 20a ilim v cc ss figure 3. block diagram
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 4 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination pin configuration 9 34 17 26 18 27 10 8 7 2 3 6 5 4 16 15 14 13 12 11 19 20 21 22 23 24 25 33 28 29 30 31 32 pgnd pgnd pgnd pgnd pvin pvin sw sw sw sw sw sw agnd sw vcc pvcc ilim fb nc nc nc vddq en freq ss pvin pvin pvin pvin pvin agnd boot sw vin agnd (p1) pvin (p2) sw (p3) 1 pvin agnd pvin pvin pvin pvin pvin sw sw sw sw sw sw pgnd pgnd pgnd pgnd sw vcc pvcc ilim fb nc nc nc vddq en freq ss agnd boot sw vin pvin 1 9 10 27 26 18 17 34 2 3 8 7 4 5 6 28 29 30 31 32 33 19 20 21 22 23 24 25 11 16 15 14 13 12 figure 4. bottom view figure 5. top view pin definitions name pad / pin description pvin p2 ; 5 -11 power i nput for the power stage . vin 1 power input to the linear regulator; u sed in the modulator for input voltage feed - forward . pvcc 25 power output of the linear regulator; d irect ly supplies power for the low - side gate d river and b oot d iode . can be connected to vin and pvin for operation from 5 v rail. vcc 26 power s upply input for the controller . pgnd 18-21 power g round for the low - side p ower mosfet and for the low - side gate driver . agnd p1 ; 4, 23 analog g round for the analog portions of the ic and for substrate . sw p3 ; 2, 12 - 17, 22 switching node; junction between high - and low - side mosfets . boot 3 supply for high - side mosfet gate driver. a capacitor from boot to sw supplies the charge to t urn on the n - channel high- side mosfet. during the freewheel ing interval (low - side mosfet on), the high- side capacitor is recharged by an internal diode connected to pvcc . ilim 24 current limit . a resistor between ilim and sw set s the current - limit threshold. fb 27 output v oltage feedback to the modulator . en 29 enable input to the ic . pin must be driven logic high to enable, or logic low to disable. ss 30 soft -s tart input to the modulator vddq 31 external ref erence input to the modulator. the modulator regulates to half of the voltage at the vddq pin. freq 32 on - time and f requency programming pin. connect a resistor between freq and agnd to program on - time and switching frequency. nc 28 , 33 - 34 leave pin open or connect to agnd.
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 5 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, e xtended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter condition min . max . unit v pvin power input referenced to pgnd - 0.3 25.0 v v in modulator input referenced to agnd - 0.3 25.0 v v boot boot voltage referenced to pv cc - 0.3 26.0 v referenced to pv cc , <20 ns - 0.3 30.0 v v sw sw voltage to gnd referenced to pgnd, agnd -1 25 v referenced to pgnd, agnd < 20 ns -5 25 v v boot boot to sw voltage referenced to sw - 0.3 6 .0 v boot to pgnd referenced to pgnd - 0.3 30 v v pvcc gate drive supply input referenced to pgnd, agnd - 0.3 6 .0 v v vcc controller supply input referenced to pgnd, agnd - 0.3 6.0 v v ilim current limit input referenced to agnd - 0.3 6 .0 v v fb output voltage feedback referenced to agnd - 0.3 6 .0 v v en enable input referenced to agnd - 0.3 6 .0 v v ss soft start input referenced to agnd - 0.3 6 .0 v v freq frequency input referenced to agnd - 0.3 6 .0 v v ddq vddq in put referenced to agnd - 0.3 6 .0 v esd electrostatic discharge human body model, jesd22 - a114 2000 v charged device model, jesd22 - c101 2500 v t j junction temperature +150 c t stg storage temperature -55 +150 c recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or desi gning to absolute maximum ratings. symbol parameter condition min. max. unit v pvin power input referenced to pgnd 7 15 v v in modulator input referenced to agnd 7 15 v t j junction temperature -40 +125 c i load load current t a =25c, no airflow 6 a v pvin , v in , v pvcc pv in , v in , and gate drive supply input v pvin , v in , v pvcc connected for 5 v rail operation and referenced to pgnd, agnd 4.5 5.5 v thermal characteristics the thermal characteristics were evaluated on a 4 - layer pcb structure (1 oz/1 oz/1 oz/1 oz) measuring 7 cm x 7 cm) . symbol parameter typ. unit ja thermal resistance, junction - to - ambient 35 c/w jc thermal characterization parameter, junction -to - top of case 2.7 c/w jp c b thermal characterization parameter, junction -to - pcb 2.3 c/w
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 6 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination electrical characteristics unless otherwise noted; v in = 12 v, v out = 0.6 v, t a = t j = - 40 to + 125c . symbol parameter condition min. typ. max. unit supply current i vin,sd shutdown current e n = 0 v 16 a i vin,q quiescent current e n = 5 v, not s witching 1 . 8 ma i vin,gatecharge gate charge current e n =5 v, f sw = 500 khz 10 ma linear regulator v reg regulator output voltage 4. 75 5 . 00 5. 2 5 v i reg regulator current limit 60 ma reference, feedback comparator v fb fb voltage threshold 590 5 96 602 mv v ddq v ddq pin voltage range 0 3 v i fb fb pin bias current -100 0 100 na modulator t on on - time accuracy r freq =56 k, v in =10 v, t on =250 ns, no load -20 20 % t off,min minimum sw off - time 320 374 ns d min minimum duty cycle f b=1 v 0 % soft - start i ss soft - start current ss=0 v 7 10 13 a current limit i lim valley current limit accuracy t a =t j = 25c, i valley =4 a -10 10 % k ilim i lim set - point scale factor 233 i limtc temperature coefficient 4000 ppm/c enable v th+ rising threshold 1.11 1.26 1.43 v v hyst hysteresis 122 m v v th - falling threshold 1.00 1.14 1.28 v v enclamp enable voltage clamp i en =20 a 4. 3 4.5 v i enclamp c lamp current e n =5 v 24 a i enlk enable pin leakage e n =1.2 v 100 na i enlk enable pin leakage v en = 5 v 76 a uvlo v on v cc good threshold rising 4.4 v v hys hysteresis voltage 160 mv thermal shutdown t off thermal shutdown trip point ( 1 ) 155 c t hys hysteresis ( 1 ) 15 c internal bootstrap diode v fboot forward voltage i f =10 ma 0. 6 v i r reverse leakage v r =5 v 1000 a mosfets r ds,on,hs drain to source on resistance ( 2 ) v gs =5 v, i d =30 a, t a =25 c 9.67 m r ds,on.ls drain to source on resistance ( 2 ) v gs =5 v, i d =30 a, t a =25 c 5.46 m note : 1. guaranteed by design; not production tested. 2. typical r ds , on value i s provided for reference only, and is derived from discrete mosfet data .
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 7 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination typical performance characteristics tested using evaluation board circuit shown in figure 1 with v in =12 v, v out = 0.6 v, f sw =500 khz, t a =25 c, and no airflow; unless otherwise specified. figure 6. e f ficiency vs . load current v in =12 v and f sw =500 khz figure 7. efficiency vs . load current v in =12 v and f sw =500 khz figure 8. efficiency vs . load current with v in =12 v and v out =0.6 v figure 9. case temperature rise vs. load current figure 10. load regulation figure 11. startup waveforms using soft - start with 2.4 a resistive load 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 efficiency (%) load current (a) vo=1.05v, l=1.2h vo=0.9v, l=1.2h vo=0.75v, l=0.72h vo=0.6v, l=0.72h 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 efficiency (%) load current (a) vo=5v, l=3.3h vo=3.3v, l=2.4h vo=1.2v, l=1.2h 40 45 50 55 60 65 70 75 80 85 90 0 2 4 6 efficiency (%) load current (a) fsw=500khz, l=0.72h fsw=1mhz, l=0.4h fsw=1.5mhz, l=0.4h 0 5 10 15 20 25 0 2 4 6 case temperature rise ( c) load current (a) 12vi/0.6vo/1.5mhz 12vi/0.6vo/1mhz 12vi/0.6vo/500khz 0.585 0.590 0.595 0.600 0.605 0.610 0.615 0.620 0.625 0 1 2 3 4 5 6 output voltage (v) load current (a) r load =0.25 v in =12v v out (0.5v/div) v ddq (1v/div) en (5v/div) v ss (0.5v/div)
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 8 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination typical performance characteristics (continued) figure 12. startup waveforms tracking v ddq with 2.4 a resistive load figure 13. shutdown waveforms tracking v ddq with 2.4 a resistive load figure 14. tracking operation with variable v ddq reference input figure 15. static output ripple with no load figure 16. static output ripple with 4 a load current figure 17. operation as load changes from 0 a to 4 a r load =0.25 v in =12v v out (0.5v/div) v ddq (1v/div) en (5v/div) v ss (0.5v/div) v sw (5v/div) v in =12v v out =1.2v v out (20mv/div) v out (20mv/div) v sw (5v/div) v in =12v v out =1.2v v in =12v v out =1.2v v out (20mv/div) i out (1a/div) r load =0.25 v in =12v v out (0.5v/div) v ddq (0.5v/div) en (5v/div)
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 9 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination typical performance characteristics (continued) figure 18. operation as load changes from 4 a to 0 a figure 19. load transient from 0% to 50% load current figure 20. load transient from 50% to 100% load current figure 21. over - current protection with heavy load v out (20mv/div) i l (1a/div) v in =12v, v out =1.2v i out from 0a to 2a, 2.5a/s v out (20mv/div) i l (1a/div) v in =12v, v out =1.2v i out from 2a to 4a, 2.5a/s v out (1v/div) v ss (1v/div) i o (5a/div) i out =0a then short output i out (1a/div) v in =12v v out =1.2v v out (20mv/div)
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 10 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination circuit opera tion the fan23sv 04t uses a constant -on- time modulation architecture with a v in feed - forward input to accommodate a wide v in range . this method provides fixed switching frequency (f sw ) operation when the inductor operates in continuous conduction mode (ccm) . a dditional benefits include e xcellent line and load transient response, cycle -by - cycle current limiting, and elimination of loop compensatio n require ments . at the beginning of each cyc le, fan23sv04t turns on the high - side mos fet (hs) for a fixed duration (t on ) . at the end of t on , hs turn s off for a duration (t off ) determined by the operating conditions . once the fb voltage (v fb ) fall s below the reference voltage (v ref ), a new switching cycle begin s . the modulator provides a minimum off - time (t off - min ) of 250 ns to provide a guaranteed interval for low - side mosfet (ls) current sensing and pfm operation. t off - min provide s stability against multiple pulsing and limits maximum switching frequency during transient events. enable the enable pin can be driven with an external logic signal, connected to a resistive divider from pvin/vin to ground to create an under - voltage locko ut (uvlo) based on the pvin/vin supply, or connected to pvin/vin through a single resistor to auto - enable while operating within the en pin internal clamp current sink capability. the en pin can be directly driven by logic voltages of 5 v, 3.3 v, 2.5 v, e tc. if the en pin is driven by 5 v logic, a small current flows into the pin when the en pin voltage exceeds the internal clamp voltage of 4.3 v. to eliminate clamp current flowing into the en pin use a voltage divider to limit the en pin voltage to < 4 v. to implement the uvlo function based on pvin/vin voltage level, select values for r7 and r8 in figure 1 such that the tap point reaches 1. 26 v when v in reaches the desired startup level using the following equation: ? 7 = ? 8 ? ? ?? , ?? ? ?? , ?? ? 1 ? (1 ) where v in, on is the input voltage for startup and v en,on is the en pin rising threshold of 1. 26 v. with r8 selected as 10 k, and v in,on =9 v the value of r7 is 61.9 k. the en pin can be pulled high with a single resistor connected from vin to the en pin. with vin > 5.5v a series resistor is required to limit the current flow into the en pin clamp to less than 24 a to keep the internal clamp within normal operating range. the resistor value can be calculated from the following equation: ? ?? > ? ?? , ??? ? ? ?? , ????? , ??? 22 ? (2 ) constant on - t ime modulation the fan23sv04t uses a constant on - time modulation technique, in which the hs mosfet is turned on for a fixed time , set by the modulator , in response to the input voltage and the frequency - setting resi stor. this on - time is proportional to the desired output voltage , divi ded by the input voltage. with this proportionality, the frequency is essentially constant over the load range where inductor current is continuous. for a buck converter in continuous - conduction mode (ccm) , the switching frequency f sw is expressed as : ? ?? = ? ??? ? ?? ? ? ?? (3 ) the on - time generator sets the on- time (t on ) for the high - side mosfet, which results in the switching frequency of the regulator during steady - state operation. t o maintain a relati vely constant switching frequency over a wide range of input conditions, the input voltage information is fed into the on - time generator. t on is determined by: ? ?? = ? ??? ? ??? ? 2 ? (4 ) where i ton is: ? ??? = 1 10 ? ? ?? ? ???? (5 ) w here r freq is the frequency - setting resistor described in the setting switching frequency s ection ; c t on is the internal 2. 2 pf capacitor ; and i t on is the v in feed - forward current that generates the on- time . the fan23sv04t implements open - circuit detection on the freq pin to protect the output from an infinitely long on- time. in the event the freq pin is left floating, switching of the regulator is disabled. the fan23sv04t is designed for a v in input range 7 to 15 v and f sw from 200 k hz to 1 .5 mhz, resulting in an i t on ratio of 1 to 1 6 . as the ratio of v out to v in increases, t off,min introduces a limit on the maximum switching frequency as calculated in the following equation, where the factor 1.2 is included in the denominator to provide some headroom for transient operation: ? ?? < ? 1 ? ? ??? ? ?? , ??? ? 1 . 2 ? ? ??? , ??? (6 ) vddq th is pin is connected to the v ddq supply , which the fan23sv04t must track during startup and produce an output (v tt ) equal to half of v ddq in steady - state conditions . to accomplish this, the v ddq pin has an internal resistor divider to agnd that provides a reference voltage equal to v ddq /2 at the positive input of the fb comparator. soft - start (ss) a conventional soft - start ramp is implemented to provide a controlled startup sequence of the output voltage. a current is generated on the ss pin to charge an external capacitor. the lesser of the voltage on the ss pin and the reference voltage is used fo r output regulation.
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 11 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination during normal operation, the ss voltage is clamped to 400 mv above the fb voltage. the clamp voltage drops to 40 mv during an overload condition (when v fb is 400 mv) to allow the converter to recover using the so ft- start ramp once the overload condition is removed. there is no on - time modulation during normal normal soft - start or when recovering from an overload condition. the nominal startup time is programmable through an internal current source charging the ext ernal soft - start capacitor c ss : ? ?? = ? ?? ? ? ?? ? ??? (7 ) where: c ss = external soft - start programming capacitor ; i ss = internal soft - start charging current source , 10 a; t s s = soft - start time ; and v ref = vddq/2 . for example; for 1ms start up time, c ss =15 nf. the soft - start option can be used for ratiometric tracking. when en is low , the soft - start capacitor is discharged. internal linear regulator the fan23sv04t includes a linear regulator to facilitate single - supply operation for self - biased applications. pvcc is the linear regulator ou tput and supplies power to the internal gate drivers. the pvcc pin should be bypassed with a 2.2 f ceramic capacitor. the devic e can operate from a 5 v rail if the v in , p vin , and p vcc pins are connected together to bypass the internal linear regulator. v cc bias supply and uvlo the v cc rail su pplies power to the controller. it is generally connected to the pvcc rail through a low - p ass filter of a 10 ? resistor and 0.1 f capacitor to minimize any noise sources from the driver supply. an under - voltage lockout (uvlo) circuit monitors the v cc volt age to ensure proper operation. once the v cc voltage is above th e uvlo threshold, the part begin s operation after an i nitialization routine of 50 s. there is no uvlo circuitry on either the pvcc or v in rails. over - current protection (ocp) the fan23sv04t uses current informat ion through the ls to implement valley - curre nt limiting. while an oc event is detected, the hs is prevented from turning on and the ls is kept on until the current falls bel ow the user - defined set point. once the current is below the set point, the hs is allowed to turn on. the ilim pin has an open detection circuit to provide protection against operation without a current limit. over - temperature protection (otp) fan23sv04t incorporates an over - temp erature protection circuit that disables the converter when the die temperature reaches 155c. the ic restarts when the die temperature falls below 140 c . application information stability constant on - time stability consists of two parameters: stability criterion and sufficient signal at v fb . stability criterion is given by: ? ??? ? ? ??? ? ? ?? 2 (8 ) sufficient signal requirement is given by: ? ? ??? ? ? ??? > ? ? ?? (9 ) w here ? i ind i s the inductor current ripple and ? v fb is the ripple voltage on v fb , w hich should be 12 mv. i n certain applications, especially designs utilizing only ceramic output capacitors, there may not be sufficient ripple magnitude available on the feedback pin for stable operat ion . in this case, an external circuit , such as r2 -c4 - c5 sho wn in figure 1 , can be added to inject ripple voltage into the fb pin. there are some specific considerations when selecting the rcc ripple injector circuit. for typical applications, the value of c4 can be selected as 0.1 f and approximate values for r2 and c5 can be determined using the following equations. r2 must be small enough to develop 12 mv of ripple: ? 2 < ( ? ?? ? ? ??? ) ? ? ??? ? ?? ? 0 . 012 ? ? ? 4 ? ? ?? (10) r2 must also be selected such that the r2c4 time constant enables stable operation: ? 2 < 0 . 33 ? 2 ? ? ? ?? ? ? ??? ? ? ??? ? 4 (11) the minimum value of c5 can be selected to minimize the capacitive component of ripple appearing on the feedback pin : c 5 min = l out ? c out r 2 ? r 3 ? c 4 (12) using the minimum value of c5 generally offers the best transient response, and 100 pf is a good initial value in many applications. however, under some operating conditions excessive pulse jitter may be observed. to reduce jitter and improve stability, the value of c5 can be increased : ? 5 2 ? c 5 min (13) 5 v pv cc the pv cc is the output of the internal regulator that supplies power to the drivers and v cc . it is crucial to keep this pin decoupled to pgnd with a 1 f x5r or x7r ceramic capacitor. because v cc powers the internal analog circuit, it is filtered from pv cc with a 10 resistor and 0. 1 f x7r decoupling ceramic capacitor to agnd.
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 12 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination setting the output voltage (v out ) the output voltage, v out , is regulated by initiating a high - side mosfet on - time interval when the valley of the divided outpu t voltage appearing at the fb pin reaches v ref . since this method regulates at the valley of the output ripple voltage, the actual dc output voltage on v out is offset from the programmed output voltage by the average value of the output ripple voltage. the output v out setting of the regulator can be determined using the following equation : ? ??? = ? ??? 2 (14) w here v ddq is the voltage applied to pin 31 . for example ; if v ddq = 1.2 v then v out = 600 mv . v fb is trimmed to a value of 596 mv when v ddq = v ref =600 mv . t he final output voltage , including the effect of the output ripple voltage , can be approximate d by : ? ??? = ? ?? ? ? ? ??? 2 ? (15) setting the switching frequency ( f sw ) f sw is programmed through external r freq as follows: ? ???? = ? ??? 20 ? ? ??? ? ? ?? (16) w here c t on = 2. 2 pf ) . for example ; for f sw = 500 khz and v out = 0.6 v, then select a standard resistor value for r freq = 2 7.4 k ? . inductor selection t he inductor is typically selected based on the ripple current ( ? i l ), which is approximately 25% to 45% of the maximum dc load . the inductor current rating should be selected such that the saturation and heating current ratings exceed the intended currents encountered in the application over the expected temperature range of operation. regulators that require fast transient response use smaller inductance and higher current ripple ; while regulators that require higher efficiency keep ripple current on the low side. the inductor value is given by : ? = ( ? ?? ? ? ??? ) ? ? ? ? ? ?? ? ? ??? ? ?? (17 ) for example: for 12 v v in , 0.6 v v out , 4 a load, 25% il, and 5 0 0 khz f sw ; l is calculated to be 1.1 h and a standard value of 1 h is selected. input capacitor selection input c apacitor c in is selected based on voltage rating, rms current i cin( rms ) rating , and capacitance . for capacitors with dc v oltage bias derating , such as ceramic capacitors, hig her rating is strongly recommended. rms current rating is given by: ? ??? ( ??? ) = ? ???? ? ??? ? ? ? ? ( 1 ? ? ) (18) w here i load - max is the maximum load current and d is the duty cycle v out /v in . the maximum i cin (rms) occurs at 50% duty cycle. the capacitance is given by: ? ?? = ? ???? ? ??? ? ? ? ( 1 ? ? ) ? ?? ? ? ? ?? (19) w here ? v in is input voltage ripple, normally 1% of v in . for example : f or v in =12 v, ? v in =120 mv, v out = 0.6 v, 4 a load, and f sw = 950 khz ; then c in is calculated as 1.7 f , select a single 10 f, 25 v- rated ceramic capacitor with x7r or similar dielectric, recognizing that the capacitor dc bias characteristic indicates that the capacitance value fall s approximately 40% at v in =12 v. output capacitor selection output c apacitor c out is also selected based on voltage rating, rms current i cin (rms) rating , and capacitance. for capacitors with dc v oltage bias derating , such as ceramic capacitors, higher rating is recommended. when calculating c out , usually the dominant requirement is the current load step transient. if the unloading transient requirement (i out transitioning from high to low ) , is satisfied, the load tran sient (i out transitioning low to high ) , is also usually satisfied. the unloading c out calculation, assuming c out has negligible parasitic resistance and inductance in the circuit path, is given by : ? ??? = ? ? ? ????? 1 2 ? ? ????? 2 2 ( ? ??? + ? ? ?? ? ) 2 ? ? ??? 2 (20) w here i level1 and i level2 are current levels before and after load steps, and ? v out is the voltage overshoot, usually specified at 5%. for example: for v i =12 v, v out = 0.6 v, i level1 =3 a, i level2 =2 a, f sw = 5 0 0 khz , l out = 1 h , and 4 .0 % ? v out overshoot of 24 mv ; the c out value is calculated to be 170 f , and four 47 f, 6.3 v- rated x5r ceramic capacitors may be used. this equation assumes that the load current rises instantaneously : with reduced current slew rate , the value for c out can be reduced. setting the current limit current limit is implemented by sensing the inductor valley current across the ls r ds(on) during the ls on - time. the current - limit comparator prevents a new on - time from start ing until the valley current is less than the current limit. the set point is configured by connecting a resistor fr om the ilim pin to the sw pin. a trimmed current of approximately 20 a is output onto the ilim pin , which creates a volt age across the resistor. when the voltage on ilim goes negative, an over - current condition is detected.
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 13 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination the current flowing out of the ilim pin through r ilim is trimmed to compensate for both the r ds(on) of the ls mosfet and the offset v oltage of the current limit comparator. r ilim is calculated by : ? ???? = 1 . 02 ? ? ???? ? ? ?????? (21) where k ilim is the current source scale factor equal to the average r ds,on of the ls mosfet divided by the average ilim pin current of 20 a , and i valley is the inductor valley current when the current limit threshold is reached. the factor 1.01 accounts for the temperature offset of the ls mosfet compared to control circuit (ap proximately 5 c), and the approximate increase in the r ds,on of the ls mosfet of 4000 ppm/c . with the c onstant on-t ime architecture, hs is always turned on for a fixed on - time . t his determines the peak - to - peak inductor current. current ripple ? i is given by: ? ? ? = ( ? ?? ? ? ??? ) ? ? ?? ? (22) fro m the equation above, the worst - case ripple occurs during an output short circuit (where v out is 0 v). this should be taken into account when selecting the current limit set point. t he fan23sv04t uses valley - current sensing. t he current limit (i ilim ) set point is the valley (i valley ). the v alley current level for calculating r ilim is given by : ? ?????? = ? ???? ( ?? ) ? ? ? ? 2 (23) w here i load ( cl ) is the dc load current when the current limit threshold is reached . for example : i n a converter designed for 4 a steady - state operation and 1 a current ripple , the current - limit threshold could be selected at 1 20 % of i load,( ss) to accommodate transient operation and inductor value decrease under loading. as a resul t ; i load,( ss) is 4.8 a, i valley = 4 .3 a, and r ilim is selected as the standard value of 1. 0 2 k ? . boot resistor in some applications, especially with higher input voltage, the v sw ring voltage may exceed the derating guidelines of 80% to 90% of absolute rating for v sw . in this situation , a resistor can be connected in series with the boot capacitor (c3 in figure 1 ) to reduc e the turn - on speed of the high - side mosfet to reduce the amplitude of the v sw ring voltage. pcb (printed circuit board) layout guidelines the following should be considered before beginning a pcb layout using the fan23sv0 4t . a sample pcb layout from the tinybuck ? evaluation board following the layout guidelines is shown in figure 22 - figure 25 . power components consisting of the input capacitors, output capacitors, inductor, and tinybuck device should be on a common side of the pcb in close proximity to each other and connected usin g surface copper. sensitive analog components ; including ss, fb, ilim, freq, and en ; should be placed away from the high - voltage switching circuits , such as sw and boot, and connected to their respective pins with short traces. the inner pcb layer closest to the tinybuck device should have power ground (pgnd) under the power - processing portion of the device (pvin, sw, and pgnd). this inner pcb layer should have a separate analog ground (agnd) under the p1 pad and the associated analog components. agnd and p gnd should be connected together near the ic between pgnd pins 18 - 21 and agnd pin 23, which connects to p1 thermal pad. the agnd thermal pad (p1) should be connected to agnd plane on the inner layer using four 0.25 mm vias spread under the pad. no vias are included under pvin (p2) and sw (p3) to maintain the pgnd plane under the power circuitry intact. power circuit loops that carry high currents should be arranged to minimize the loop area. primary focus should be directed to minimize the loop for current flow from the input capacitor to pvin, through the internal mosfets, and returning to the input capacitor. the input capacitor should be placed as close to the pvin terminals as possible. the current return path from pgnd at the low - side mosfet source to t he negative terminal of the input capacitor can be routed under the inductor and also through vias that connect the input capacitor and low - side mosfet source to the pgnd region under the power portion of the ic. the sw node trace that connects the source of the high - side mosfet and the drain of the low - side mosfet to the indu ctor should be short and wide. to control the voltage across the output capacitor, the output voltage divider should be located close to the fb pin, with the upper fb voltage divider r esistor connected to the positive side of the output capacitor, and the bottom resistor should be connected to the agnd portion of the tinybuck device. when using ceramic capacitor solutions with external ramp injection circuitry (r2, c4, c5 in figure 1 ), r2 and c4 should be connected near the inductor and coupling capacitor c5 should be placed near the fb pin to minimize fb pin trace length. decoupling capacitors for pvcc and vcc should be located close to their respective device pins. sw node connections to boot, ilim, and ripple injection resistor r2 should be through separate traces.
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 14 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination figure 22. evaluation b oard t op l ayer c opper figure 23. e valuation b oard i nner l ayer 1 c opper
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 15 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination figure 24. evaluation board inner l ayer 2 c opper figure 25. evaluation board b ottom l ayer c opper
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 16 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination physical dimensions figure 26. 34- lead , pqfn , 5.5 mm x 5.0 mm package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and /or date on the drawing and contact a fairchild semiconductor representative to verify or obtain the most recent revision. package specifications do not expand the terms of fairc hild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . bottom view land pattern recommendation notes: unless otherwise specified a) does not fully conform to jedec registration mo-220, dated may/2005. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. mold flash or burrs does not exceed 0.10mm. d) dimensioning and tolerancing per asme y14.5m-1994. e) drawing file name: mkt-pqfn34arev1 see detail 'a' detail 'a' scale: 2:1 seating plane top view front view c 0.30 0.20 0.05 0.00 1.10 0.90 0.10 c 0.08 c 0.33 2.28 2.08 1.68 1.48 (0.43) 0.50 0.30 (30x) 5.60 5.40 5.10 4.90 0.10 c 2x b a 0.10 c 2x 0.30 0.20 (30x) 2.28 2.08 0.10 c a b 0.05 c 0.50 9 1 34 27 26 18 17 10 pin#1 indicator 3.60 3.40 2.68 2.48 0.78 0.58 0.30 (30x) 9 1 34 27 26 18 17 10 9 1 34 27 26 18 17 10 (0.20) (0.30) 0.55 (4x) (1.75) 3.50 0.30 (3x) 0.20 (2x) (0.08) (0.35) 1.58 2.18 4.10 5.70 2.58 0.50 0.68 4.10 3.60 5.20 1.80 0.55 0.75 1.75 0.35 0.35 0.75
? 20 11 f airchild semiconductor corporation www.fairchildsemi.com fan23sv04t ? rev. 1.0. 1 17 fan23sv04t ? tinybuck ? 4 a integrated synchronous buck regulator for ddr termination

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