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data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 2048 mb ddr3 C sdram ultra low profile ecc dimm 240 pin unbuffered ecc dimm sgu02g72h1b g 2sa - xx r t 2gbyte in fbga techn ology rohs compliant environmental requirements: ? operating temperature (ambient) standard grade 0c to 70c ? operating humidity 10% to 90% relative humidity, noncondensing ? operating pressure 105 to 69 kpa (up to 10000 ft.) ? storage temperature - 55c to 1 00c ? storage humidity 5% to 95% relative humidity, noncondensing ? storage pressure 1682 psi (up to 5000 ft.) at 50c options: ? data rate / latency marking ddr3 1066 mt/s cl7 - bb ddr3 1333 mt/s cl9 - cc ? module density 2048mb with 18 dies and 2 ranks ? standard grade (t a ) 0c to 70c (t c 0c to 85c figure: mechanical dimensions 1 features: ? 240 - pin 72 - bit unbuffered dual - in - line double data rate s ynchronous dram module with ecc ? module organization: dual rank 256 x 72 ? v dd = 1.5v 0.075v, v ddq 1.5 v 0.075v ? 1.5v i/o ( sstl_15 compatible) ? fly - by - bus with termination for c/a & clk bus ? supports ecc, error detection and correction ? ultra low profile (ulp) ? on - board i2c temperature sensor with integrated serial presence - detect (spd) eeprom (according to j edec jesd21c) ? gold - contact pad ? this module family is fully pin and functional compatible to jedec pc3 - 12800 spec and mo - 269. (see www.jedec.org ) ? the pcb and all components are manufactured according to th e rohs complian ce specification [eu directive 2002/95/ec restriction of hazardous substances (rohs)] ? ddr 3 - sdram component samsung k4b1g0846g ? 128 mx8 ddr3 sdram in pg - tfbga - 78 package ? 8 - bit pre fetch architecture ? programmable cas latency, cas write latency, additive late ncy, burst length and burst type. ? on - die - termination (odt) and dynamic odt for improved signal integrity. ? refresh. self refresh and power down modes. ? zq calibration for output driver and odt. ? system level timing calibration support via write leveling and m ulti purpose register (mpr) read pattern. 1 if no tolerances specified 0.15mm 1 7 . 7 5 m m 1 6 . 5 0 m m 1 0 . 3 0 m m 8 . 7 0 m m 2 . 20 mm 2 . 3 0 m m 54 . 67 mm 133 . 35 mm r 0 . 75 mm 3 . 0 5 m m r 0 . 70 mm 3 . 0 0 m m r 0 . 70 mm r 0 . 7 0 m m
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 this swissbit module is an industry standard 240 - pin 8 - byte ddr3 sdram dual - in - line memory module ( u dimm) which is organized as x 72 high speed cmos memory arrays. the module uses internally configured oct al - bank ddr3 sdram devices. the module uses double data rate architecture to achieve high - speed operation. ddr3 sdram modules operate from a differential clock (ck and ck#). read and write accesses to a ddr3 sdram module is burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. the burst leng th is either four or eight locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr3 sdram devices have a multibank architecture which allows a concurrent operation t hat is providing a high effective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_15 compatible. the ddr3 sdram module uses the serial presence detect (spd) function i mplemented via serial eeprom using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the dimm manufacturer (swissbit) to identify the module type, the modules organization and several timing parameters. the second 128 bytes are available to the end user. module configuration organization ddr3 sdrams used row addr. device bank addr. col umn addr. refresh module bank select 256 m x 72 bit 1 8 x 128m x 8bit (1 024m bit) 1 4 ba0, ba1, ba2 10 8k s0#, s 1# module dimensions in mm 133.35 (long) x 17.75 (high) x 4.00 [max] (thickness) timing parameters part number module density transfer rate clock cycle /data bit rate latency sgu02g72h1b g 2sa - bbr t 2048 mb 8.5 gb/s 1.87ns/1066mt/s 7 - 7 - 7 sgu02g72h1b g 2 sa - ccr t 2048 mb 10.6 gb/s 1.5ns/1333mt/s 9 - 9 - 9 pin name a0 C a 9, a11, a13 address inputs a10/ap address input / autoprecharge bit a12/bc # address input / burst chop ba0 C ba2 bank address inputs dq0 C dq63 data input / output cb0 C cb7 ecc check bi ts dm0 C dm8 input data mask dqs0 C dqs8 data strobe, positive line dqs0# - dqs8# data strobe, negative line (only used when differential data strobe mode is enabled) ras# row address strobe cas# column address strobe we# write enable cke0 C cke1 cl ock enable s0#, s1# chip select ck0 C ck1 clock inputs, positive line figure 1: mechanical dimensions
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 ck0# - ck1# clock inputs, negative line event# temperature event: the event# pin is asserted by the temperature sensor when critical v dd supply voltage (1.5v 0.075v) v ref dq refere nce voltage: dq, dm (vdd/2) v ref ca reference voltage: control, command, and address (vdd/2) v ss ground v tt termination voltage: used for control, command, and address (vdd/2). v ddspd serial eeprom positive power supply scl serial clock for presence de tect sda serial data out for presence detect sa0 C sa2 presence detect address inputs odt0, odt1 on - die termination nc no connection pin configuration frontside pin symbol pin symbol pin symbol pin symbol pin symbol 1 v refdq 27 dq18 49 nc 75 v dd 1 01 v ss 2 v ss 28 dq19 50 cke0 76 s1# 102 dqs6# 3 dq0 29 v ss 51 v dd 77 odt1 103 dqs6 4 dq1 30 dq24 52 ba2 78 v dd 104 v ss 5 v ss 31 dq25 53 nc( err_out# ) 79 nc( s2# ) 105 dq50 6 dqs0# 32 v ss 54 v dd 80 v ss 106 dq51 7 dqs0 33 dqs3# 55 a11 81 dq32 107 v ss 8 v ss 34 dqs3 56 a7 82 dq33 108 dq56 9 dq2 35 v ss 57 v dd 83 v ss 109 dq57 10 dq3 36 dq26 58 a5 84 dqs4# 110 v ss 11 v ss 37 dq27 59 a4 85 dqs4 111 dqs7# 12 dq8 38 v ss 60 v dd 86 v ss 112 dqs7 13 dq9 39 cb0 61 a2 87 dq34 113 v ss 14 v ss 40 cb1 62 v dd 88 dq35 1 14 dq58 15 dqs1# 41 v ss 63 ck1 89 v ss 115 dq59 16 dqs1 42 dqs8# 64 ck1# 90 dq40 116 v ss 17 v ss 43 dqs8 65 v dd 91 dq41 117 sa0 18 dq10 44 v ss 66 v dd 92 v ss 118 scl 19 dq11 45 cb2 67 v refca 93 dqs5# 119 sa2 20 v ss 46 cb3 68 nc( par_in ) 94 dqs5 120 v tt 21 dq16 47 v ss 69 v dd 95 v ss 22 dq17 48 nc 70 a10/ ap 96 dq42 23 v ss 71 ba0 97 dq43 24 dqs2# 72 v dd 98 v ss 25 dqs2 73 we# 99 dq48 26 v ss 74 cas# 100 dq49 signals in brackets () may be connected at the dimm socket, but are not us ed on the dimm
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 backside pin symbol pin symbol pin symbol pin symbol pin symbol 121 v ss 147 dq23 169 cke1 195 odt0 221 dm6( dqs15 ) 122 dq4 148 v ss 170 v dd 196 a13 222 nc( dqs15# ) 123 dq5 149 dq28 171 nc( a15 ) 197 v dd 223 v ss 124 v ss 150 dq29 172 nc(a14) 198 nc( s3# ) 224 dq54 125 dm0( dqs9 ) 151 v ss 173 v dd 199 v ss 225 dq55 126 nc( dqs9# ) 152 dm3( dqs12 ) 174 a12, bc # 200 dq36 226 v ss 127 v ss 153 nc( dqs12# ) 175 a9 201 dq37 227 dq60 128 dq6 154 v ss 176 v dd 202 v ss 228 dq61 129 dq7 155 dq30 177 a8 203 dm4 ( dq s13 ) 229 v ss 130 v ss 156 dq31 178 a6 204 nc( dqs13# ) 230 dm7( dqs16 ) 131 dq12 157 v ss 179 v dd 205 v ss 231 nc( dqs16# ) 132 dq13 158 cb4 180 a3 206 dq38 232 v ss 133 v ss 159 cb5 181 a1 207 dq39 233 dq62 134 dm1( dqs10 ) 160 v ss 182 v dd 208 v ss 234 dq63 135 n c( dqs10# ) 161 dm8( dqs17 ) 183 v dd 209 dq44 235 v ss 136 v ss 162 nc( dqs17# ) 184 ck0 210 dq45 236 v ddspd 137 dq14 163 v ss 185 ck0# 211 v ss 237 sa1 138 dq15 164 cb6 186 v dd 212 dm5( dqs14 ) 238 sda 139 v ss 165 cb7 187 nc( event# ) 213 nc( dqs14# ) 239 v ss 140 dq 20 166 v ss 188 a0 214 v ss 240 v tt 141 dq21 167 nc(test) 189 v dd 215 dq46 142 v ss 168 reset# 190 ba1 216 dq47 143 dm2( dqs11 ) 191 v dd 217 v ss 144 nc( dqs11# ) 192 ras# 218 dq52 145 v ss 193 s0# 219 dq53 146 dq22 194 v dd 220 v ss signa ls in brackets () may be connected at the dimm socket, but are not used on the dimm
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 functional block diagramm 2048 mb ddr3 sdram dimm, 2 ranks and 1 8 components dq 0 dq 1 dq 2 dq 3 dq 5 dq 4 dq 6 dq 7 s 0 dqs 0 dqs 0 dm 0 dqs 1 dqs 1 dm 1 dq 8 dq 9 dq 10 dq 11 dq 13 dq 12 dq 14 dq 15 dqs 2 dqs 2 dm 2 dq 16 dq 17 dq 18 dq 19 dq 21 dq 20 dq 22 dq 23 dqs 3 dqs 3 dm 3 dq 24 dq 25 dq 26 dq 27 dq 29 dq 28 dq 30 dq 31 dq 32 dq 33 dq 34 dq 35 dq 37 dq 36 dq 38 dq 39 dqs 4 dqs 4 dm 4 dqs 5 dqs 5 dm 5 dq 40 dq 41 dq 42 dq 43 dq 45 dq 44 dq 46 dq 47 dqs 6 dqs 6 dm 6 dq 48 dq 49 dq 50 dq 51 dq 53 dq 52 dq 54 dq 55 dqs 7 dqs 7 dm 7 dq 56 dq 57 dq 58 dq 59 dq 61 dq 60 dq 62 dq 63 v ddspd spd v dd / v ddq d 0 - d 17 v refdq v refca d 0 - d 17 d 0 - d 17 d 0 - d 17 v ss ck 0 , ck 1 notes : 1 . dq - to - i / o wiring is shown as recommended but may be changed . 2 . dq / dqs / dqs / odt / dm / cke / s relationship must be maintained as shown . 3 . dq , dm , dqs / dqs resistors : refer to associated topology diagram . 4 . refer to the appropriate clock wiring topology under the dimm wiring details section of the jeded document . 5 . for each dram , a unique zq resistor is connected to gnd . the zq resistor is 240 o 1 %. 6 . refer to associated figure for spd details . i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 0 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 9 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 1 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 10 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 2 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 11 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 3 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 12 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 4 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 13 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 5 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 14 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 6 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 15 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 7 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 16 dqs cs s 1 cb 0 cb 1 cb 2 cb 3 cb 5 cb 4 cb 6 cb 7 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 8 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 17 dqs cs ba 0 - ba 2 ba 0 - ba 2 : sdram d 0 - d 17 a 0 - a 13 a 0 - a 13 : sdram d 0 - d 17 ras ras : sdram d 0 - d 17 cas cas : sdram d 0 - d 17 we we : sdram d 0 - d 17 odt 0 odt : sdram d 0 - d 8 cke 1 cke : sdram d 9 - d 17 ck : sdram d 0 - d 17 ck 0 , ck 1 ck : sdram d 0 - d 17 reset reset : sdram d 0 - d 17 cke 0 cke : sdram d 0 - d 8 odt 1 odt : sdram d 9 - d 17 dqs 8 dm 8 dqs 8
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 maximum electrical dc characteristics parameter/ condition symbol min max units supply v oltage v dd - 0.4 1.975 v i/o supply voltage v dd q - 0.4 1.975 v v dd l supply voltage v dd l - 0.4 1.975 v voltage on any pin relative to v ss v in , v out - 0.4 1.975 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 16 16 ck, ck# - 16 16 dm - 2 2 output leakage current (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 8 8 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.425 1.5 1.575 v i/o supply voltage v dd q 1.425 1.5 1.575 v v dd l suppl y voltage v dd l 1.425 1.5 1.575 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt 0.49 x v dd q - 20mv 0.50 x v dd q 0.51x v dd q +20mv v input high (logic 1) voltage v ih (dc) v ref + 0.1 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.175 - v input low (logic 0) voltage v il (ac) - v ref - 0.175 v capacitance at ddr3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gr oss estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets.
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 i dd specifications and conditions (0c t case + 85c; v dd q = +1.5v 0. 075v, v dd = +1.5v 0.075v) parameter & test condition symbol max. unit 10600 - 999 8500 - 777 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid commands; dq inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 405 405 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 468 450 ma precharge power - down current: all device banks idle; power - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast exit i dd2p 216 216 ma slow exit 180 180 precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 270 270 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once ever y two clock cycles; dq inputs changing once per clock cycle i dd2n 270 270 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref (always fast exit) i dd3p 270 270 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles ; dq inputs changing once per clock cycle i dd3n 360 360 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 720 630 ma
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 parameter & test condition symbol max. unit 10600 - 999 8500 - 777 operating write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are chang ing once every two clock cycles; dq inputs changing once per clock cycle i dd4w 720 630 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 1620 1530 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are floating at v ref ; dqs are floating at v ref i dd6 180 180 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i d d ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1260 1035 ma *) value calculated as one module r ank in this operating condition, and all other module ranks in idd2p (cke low) mode. timing values used for i dd measurement i dd measurement conditions symbol 10600 - 999 8500 - 777 unit cl (i dd ) 9 7 t ck t rcd (i dd ) 13.5 13.125 ns t rc (i dd ) 49.5 50.625 ns t rrd (i dd ) 6 7.5 ns t ck (i dd ) 1.5 1. 87 ns t ras min (i dd ) 36 37.5 ns t ras max (i dd ) 70 200 70 200 ns t rp (i dd ) 13.5 13.125 ns t rfc (i dd ) 110 110 ns
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 ddr3 sdram component electrical characteristics and recommended ac operating conditions (0c t cas e + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 10600 - 999 8500 - 777 parameter symbol min max min max unit clock cycle time cl = 10 t ck (10) 1.5 <1.875 - - ns cl = 9 t ck (9) 1.5 <1.875 - - ns cl = 8 t ck (8) 1.875 <2. 5 - - ns cl = 7 t ck (7) 1.875 <2.5 1.875 <2.5 ns cl = 6 t ck (6) 2.5 3.3 2.5 3.3 ns ck high - level width t ch (avg) 0.47 0.53 0.47 0.53 t ck ck low - level width t cl (avg) 0.47 0.53 0.47 0.53 t ck data - out high - impedance window from ck/ck# t hz 250 300 ps data - out low - impedance window from ck/ck# t lz - 500 250 - 600 300 ps dq and dm input setup time relative to dqs t ds(base) 30 25 ps dq and dm input hold time relative to dqs t dh(base) 65 100 ps dq and dm input setup time relative to dqs v ref =1v/ns t d s1v 180 200 ps dq and dm input hold time relative to dqs v ref =1v/ns t dh1v 165 200 ps dq and dm input pulse width ( for each input ) t dipw 400 490 ps dqs, dqs# to dq skew, per access t dqsq 125 150 ps dq - dqs hold, dqs to first dq to go non - valid, per access t qh 0.38 0.38 t ck (avg) dqs input high pulse width t dqsh 0.45 0.55 0.45 0.55 t ck dqs input low pulse width t dqsl 0.45 0.55 0.45 0.55 t ck dqs, dqs# rising to/from ck, ck# t dqsck - 255 255 - 300 300 ps dqs, dqs# rising to/from ck, ck# when d ll disabled t dqsck dll_dis 1 10 1 10 ns dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 t ck dqs read preamble t rpre 0.9 note1 0.9 note1 t ck dqs read postamble t rpst 0.3 note2 0.3 note2 t ck dqs write preamble t wpre 0.9 0.9 t ck dqs write postamble t wpst 0.3 0.3 t ck positive dqs latching edge to associated clock edge t dqss - 0.25 + 0.25 - 0.25 + 0.25 t ck address and control input pulse width ( for each input ) t ipw 620 780 ps ctrl, cmd, addr setup to ck, ck# t is(base) 65 125 ps ctrl, cmd, addr setup to ck, ck# v ref @ 1v/ns t is(1v) 240 300 ps 1 the maximum preamble is bound by t lzdqs (max) 2 the maximum postamble is bound by t hzdqs (max)
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 ddr3 sdram component electrical c haracteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 10600 - 999 8500 - 777 parameter symbol min max min max unit ctrl, cmd, addr hold to ck, ck# t ih(base) 140 200 ps ctrl, cmd, addr hold to ck, ck# v ref @ 1v/ns t ih( 1v) 240 300 ps cas# to cas# command delay t ccd 4 4 t ck active to active (same bank) command period t rc 49.5 50.625 ns active bank a to active bank b command t rrd max 4nck,10ns max 4nck,7.5ns ns active to read or write delay t rcd 13.5 13.125 n s four bank activate period 1k page size t faw 30 37.5 ns 2k page size 45 50 active to precharge command t ras 36 70 t rtp max 4nck,7.5ns max 4nck,7.5ns ns write recovery time t wr 15 15 ns auto precharge write recovery + precharge time t dal t wr + t rp /t ck t wr + t rp /t ck ns internal write to read command delay t wtr max 4nck,7.5ns max 4nck,7.5ns ns precharge command period t rp 13.5 13.125 ns load mode command cycle time t mrd 4 4 t ck refresh to active or refresh to refresh command interval t rfc 110 70 0 c t case 85 c t refi 7.8 7.8 s 85 c < t case 95 c t refi (it) 3.9 3.9 rtt turn - on from odtl on reference t aon - 250 250 - 300 300 ps rtt turn - on from odtl off reference t aof 0.3 0.7 0.3 0.7 t ck asynchronous rtt turn - on delay (power down with dll o ff) t aonpd 2 8,5 2 8,5 ns asynchronous rtt turn - off delay (power down with dll off) t aofpd 2 8,5 2 8,5 ns rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 t ck exit self refresh to commands not requiring a locked dll t xs max 5nck,tr fc + 10ns max 5nck,tr fc + 10ns ns write levelling setup from rising ck, ck# crossing to rising dqs, dqs# crossing t wls 195 245 ps write levelling setup from rising dqs, dqs# crossing to rising ck, ck# crossing t wlh 195 245 ps first dqs, dqs# rising edge t wlmrd 40 40 t c k dqs, dqs# delay t wldqsen 25 25 t ck
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 ddr3 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 10600 - 999 8500 - 777 pa rameter symbol min max min max unit exit reset from cke high to a valid command t xpr max 5nck, t rfc + 10ns max 5nck, t rfc + 10ns t ck begin power supply ramp to power supplies stable t v ddpr 200 200 ms reset# low to power supplies stable t rps 200 200 ms reset# low to i/o and rtt high - z t ioz 20 20 ns exit precharge power - down to any non - read command t xp max 3nck,6ns max 3nck,7.5ns t ck cke minimum high/low time t cke max 3nck, 5.625ns max 3nck, 5.625ns t ck temperature sensor with serial p resence - detect eeprom temperature sensor with serial presence - detect eeprom operating conditions parameter / condition symbol min max unit supply voltage v ddspd +3 +3.6 v supply current: v dd = 3.3v i dd +2.0 ma input high voltage: logic 1; scl, sda v ih +1.45 v ddspd +1 v input low voltage: logic 0; scl, sda v il - 550 mv output low voltage: i out = 2.1ma v ol - 400 mv input current i in - 5.0 5.0 a temperature sensing range tbd tbd c temperature sensor accuracy tbd tbd c s c l s d a e v e n t s a 2 s a 2 s a 1 s a 1 s a 0 s a 0 e v e n t w p / r 1 0
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 a.c. characteristics of temperature sensor v cc = 3.3 v 10%, t a = ?40c to +125c symbol parameter / condition min max unit f scl scl clock frequency 10 400 khz t buf bus free time between stop and start 1300 ns t f sda fall time 300 ns t r sda r ise time 300 ns t hd:dat data hold time (accepted for input data) 0 ns data hold time (guaranteed for output data) 300 900 ns t h:sta start condition hold time 600 ns t high high period of scl 600 ns t low low period of scl 1300 ns t su:dat data set up time 100 ns t su:sta start condition setup time 600 ns t su:sto stop condition setup time 600 ns t timeout smbus scl clock low timeout 25 35 ms t i noise pulse filtered at scl and sda inputs 100 ns t wr write cycle time 5 ms t pu power - up delay to valid temperature recording 100 ms temperature characteristics of temperature sensor v cc = 3.3 v 10%, t a = ?40c to +125c parameter test conditions/comments max unit temperature reading error class b, jc42.4 compliant +75c t a +95c, active ran +40c t a +125c, monitor range 40c t a +125c, sensing range 1 ja junction - to - ambient (still air) 92 c/w 1 po wer dissipation is defined as p j = (t j ? t a )/ ja , where tj is the junction temperature and ta is the ambient temperature. the thermal resistance value refers to the case of a package being used on a standard 2 - layer pcb. slave address bits of temperature sensor device device type identifier select address signals r/w# b7 1 b6 b5 b4 b3 b2 b1 b0 eeprom 1 0 1 0 a 2 a 1 a 0 r/w# temp. sensor 0 0 1 1 a 2 a 1 a 0 r/w# 1 the most significant bit, b7, is sent first.
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 serial presence - detect matrix byte byte descrip tion 10600 - 999 8500 - 777 0 crc range, eeprom bytes, bytes used 0x 92 1 spd revison 0x 10 2 dram device type 0x 0b 3 module type (form factor) 0x 02 4 sdram device density & banks 0x 02 5 sdram device row & column count 0x 11 6 byte 6 reserved 0x 00 7 modul e ranks & device dq count 0x 09 8 ecc tag & module memory bus width 0x 0b 9 fine timebase dividend/divisor 0x 52 10 medium timebase dividend 0x 01 11 medium timebase divisor 0x 08 12 min sdram cycle time ( t ck min ) 0x0c 0x 0f 13 byte 13 reserved 0x 00 14 ca s latencies supported (cl4 => cl11) 0x3c 0x 1c 15 cas latencies supported (cl12 => cl18) 0x 00 16 min cas latency time ( t aa min ) 0x69 17 min write recovery time ( t wr min ) 0x 78 18 min ras# to cas# delay ( t rcd min ) 0x69 19 min row active to row active del ay ( t rrd min ) 0x30 0x 3c 20 min row precharge delay ( t rp min ) 0x69 21 upper nibble for t ras & t rc 0x 11 22 min active to precharge delay ( t ras min ) 0x 20 0x 2c 23 min active to active/refresh delay ( t rc min ) 0x89 0x 95 24 min refresh recovery delay ( t rfc m in ) lsb 0x 70 25 min refresh recovery delay ( t rfc min ) msb 0x 03 26 min internal write to read cmd delay ( t wtr min ) 0x 3c 27 min internal read to precharge cmd delay ( t rtp min ) 0x 3c 28 min four active window delay ( t faw min ) msb 0x 00 0x 01 29 min four act ive window delay ( t faw min ) lsb 0x f0 0x 2c 30 sdram device output drivers supported 0x 83 31 sdram device thermal & refresh options 0x 01
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 byte byte description 10600 - 999 8500 - 777 32 module thermal sensor 0x 80 33 sdram device type 0x 00 bytes 32 - 59 re served 0x 00 60 module height (nominal) 0x 03 61 module thickness (max) 0x 11 62 reference raw card id 0x 04 63 address mapping edge conector to dram 0x 0 1 64 - 116 bytes 64 - 116 reseved 0x 00 117 module mfr id (lsb) 0x 83 118 module mfr id (msb) 0x da 119 mo dule mfr location id 0x01 (swi t zerland) 0x02 (germany) 0x03 (usa) 120 module mfr year x 121 module mfr week x 122 - 125 module serial number x 126 - 127 crc 0x346a 0x 76c3 128 - 145 module part number " sgu02g72h1b g 2sa - xx " 146 module die rev 0x 52 147 module pcb rev 0x 54 148 dram device mfr id (lsb) 0x 80 149 dram device mfr (msb) 0x ce 150 - 175 mfr reserved bytes 150 - 175 0xff 176 - 255 customer reserved bytes 176 - 255 0xff part number code s g u 02g 72 h1 b g 2 sa - cc * r ** 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ** t = termal sensor on module *rohs compl. swissbit ag ddr3 - 1333 mt/s sdram d dr 3 24 0 pin unb. dimm 1.5v chip vendor ( samsung ) depth ( 2 gb) 2 module ranks width chip rev. g pcb - type ( s3 c1e100 ) chip organisation x8 * optional / additional information
data sheet rev.1.0 04.02.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 15 ch - 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 15 locations swissbit ag industriestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 ___________________ __________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 14 willett avenue, suite 301a port chester, ny 10573 usa phone: +1 914 935 1400 fax: +1 914 935 9865 _____________________________ swissbit na, inc. 3913 todd lane, suite C 307 austin, tx 78744 usa phone: +1 512 302 9001 fax: +1 512 302 4808 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 k oenji - kita, suginami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512

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