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| 1 SI4020-ds rev 1.9r 0308 www.silabs.com/integration SI4020 pin assignment microcontroller mode eeprom mode this document refers to SI4020-ic rev i1 . see www.silabs.com/integration for any applicable errata. see back page for ordering information. SI4020 universal ism band fsk transmitter description silicon labs? SI4020 is a single chip, low power, multi-channel fsk t ransmitter designed for use in applications requiring fcc or etsi conformance for unlicensed use in the 315, 433, 868, and 915 mhz bands. used in conjunction with ia4320, si licon labs? fsk receiver, the SI4020 transmitter feature ezradio tm technology, which produces a flexible, low cost, and highly integrated solution that does not require production alignments. all required rf functions are integrated. only an external crystal and bypass filtering are needed for operation. the SI4020 features a completely integrat ed pll for easy rf design, and its rapid settling time allows for fast frequency hopping, bypassing multipath fading and interference to achieve robust wireless links. in addition, highly stable and accurate fsk modulation is accomplished by direct closed-loop modulation with bit rates up to 256 kb ps. the pll?s high resolution allows the use of multiple channels in any of the bands. the integrated power amplifier of the transmitter has an open-collector differential output that directly drive a loop antenna with programmable output level. no additional matching network is required. an automatic antenna tuning circuit is built in to avoid costly trimming procedures and de- tuning due to the ?hand effect?. for low-power applications, the device supports automatic activation from sleep mode. active mode can be initiated by several wake-up events (on-chip timer timeout, low supply voltage detection, or activation of any of the four push-button inputs). the SI4020?s on-chip digita l interface suppo rts both a microc ontroller mode and an eeprom mode. the latter allows complete data transmitter operation without a microcontroller (both control commands and data are read from the eeprom). any wake-up ev ent can start a transmission of the corresponding data stored in the eeprom. functional block diagram crystal oscillator synthesizer low battery detect wake-up timer controller reference load cap low bat treshold timeout period clock frequency level rfp rfn nirq/nlbd clk/sdo sdi sck nsel fsk pb4 pb3 pb2 pb1 vss vdd mod xtl ook features ? fully integrated (low bom, easy design-in) ? no alignment required in production ? fast settling, programmable, high-resolution pll ? fast frequency hopping capability ? stable and accurate fsk modu lation with programmable deviation ? high bit rate (up to 256 kbps) ? direct loop antenna drive ? automatic antenna tuning circuit ? programmable output power level ? alternative ook support ? eeprom mode supported ? spi bus for applications with microcontroller ? clock output for microcontroller ? integrated programmable crystal load capacitor ? power-saving sleep mode ? multiple event handling opti ons for wake-up activation ? push-button event handling with switch de-bounce ? wake-up timer ? low battery detection ? 2.2 to 5.4 v supply voltage ? low power consumption ? low standby current (0.3 a) ? compact 16-pin tssop package typical applications ? remote control ? home security and alarm ? wireless keyboard/mouse and other pc peripherals ? toy control ? remote keyless entry ? tire pressure monitoring ? telemetry ? personal/patient data logging ? remote automatic meter reading
SI4020 2 detailed description the SI4020 fsk transmitter is desi gned to cover the unlicensed frequency bands at 315, 433, 868, and 915 mhz. the device facilitates compliance with fcc and etsi requirements. pll the programmable pll synthesizer determines the operating frequency, while preserving accuracy based on the on-chip crystal-controlled reference oscillator. the pll?s high resolution allows the usage of multiple channels in any of the bands. the fsk deviation is selectable (from 30 to 240 khz with 30 khz increments) to accommodate various bandwidth, data rate and crystal tolerance requirements, and it is also highly accurate due to the direct closed-loop modulation of the pll. the transmitted digital data can be sent asynchronously through the fsk pin or over the control interface us ing the appropriate command. the rf vco in the pll performs automatic calibration, which requires only a few microseconds. to ensure proper operation in the programmed frequency band, the rf vco is automatically calibrated upon activation of the synthesizer. if temperature or supply voltage change signific antly or operational band has changed, vco recalibration is recommended.. recalibration can be initiated at any time by switching the synthesizer off and back on again. rf power amplifier (pa) the power amplifier has an open-collector differential output and can directly drive a loop antenna with a programmable output power level. an automatic antenna tuning circuit is built in to avoid costly trimming procedures and the so-called ?hand effect.? the transmitters can operate in on-off keying (ook) mode by switching the power amplifier on and off. when the appropriate control bit is set using the power setting command, the fsk pin becomes an enable input (active high) for the power amplifier. crystal oscillator the chip has a single-pin crystal oscillator circuit, which provides a 10 mhz reference signal for the pll. to reduce external parts and simplify design, the crystal load capacitor is internal and programmable. guidelines for selecting the appropriate crystal can be found later in this datasheet. the transmitters can supply the clock signal for the microcontroller, so accurate timing is possible without the need for a second crystal. when the chip receives a sleep command from the microcontroller and turns itself off, it provides several further clock pulses (?clock tail?) for the microcontroller to be able to go to idle or sleep mode. the length of the clock tail is programmable. low battery voltage detector the low battery voltage detector circuit monitors the supply voltage and generates an interrupt if it falls below a programmable threshold level. the detector circuit has 50 mv hysteresis. wake-up timer the wake-up timer has very low current consumption (1.5 ua typical) and can be programmed from 1 ms to several days with an accuracy of 5%. it calibrates itself to the crystal oscillator at every startup. when the oscillator is switched off, the calibration circuit switches on the crystal oscillator only long enough for a quick calibration (a few milliseconds) to facilitate accurate wake-up timing. event handling in order to minimize current consumption, the device supports sleep mode. active mode can be initiated by several wake-up events: timeout of wake-up timer, detection of low supply voltage, pressing any of the four push-button inputs, or through the serial interface. the push-button inputs can be driven by a logic signal from a microcontroll er or controlled directly by normally open switches. pull-up resistors are integrated. if any wake-up event occurs, the wake-up logic generates an interrupt, which can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. the cause of the interrupt can be read out from the transmitters by the microcontroller through the nirq pin. interface an spi compatible serial interface lets the user select the operating frequency band and center frequency of the synthesizer, polarity and deviatio n of fsk modulation, and output power level. division ratio for the microcontroller clock, wake-up timer period, and low battery detector threshold are also programmable. any of these auxiliary functions can be disabled when not needed. all parameters are set to default after power- on; the programmed values are retained during sleep mode. eeprom mode in simple applications, the on-chip digital controller provides the transmitters with direct interface to a serial (spi) eeprom. in this case, no external microcontroller is necessary. wake-up events initiate automatic readout of the assigned command sequence from eeprom memory. for every event, there is a dedicated starting address available in the eeprom. programming the eeprom is very simple. any control command can be programmed in the eeprom sequentially (same as in microcontroller mode). the internal power-on reset (por) is a dedicated event, which can be used to program the basic settings of the transmitters. in this case the chip starts to read out the preprogrammed data from the 00h address in eeprom. data can be transmitted with the help of the data transmit command, which tells the transmitters how many bytes must be transmitted. the whole process finishes with a sleep command. SI4020 3 package pin definitions, microcontroller mode pin type key: d=digital, a=analog, s=su pply, i=input, o=output, io=input/output microcontroller mode pin assignment pin name type function 1 sdi di data input of serial control interface 2 sck di clock input of serial control interface 3 nsel di chip select input of serial control interface (active low) 4 pb1 di push-button input #1 (active low with internal pull-up resistor) 5 pb2 di push-button input #2 (active low with internal pull-up resistor) 6 pb3 di push-button input #3 (active low with internal pull-up resistor) 7 pb4 di push-button input #4 (active low with internal pull-up resistor) 8 clk do microcontroller clock (1 mhz-10 mhz) 9 xtl aio crystal connection (other terminal of crystal to vss) 10 vss s ground reference 11 mod di connect to logic high (microcontroller mode) 12 rfn ao power amplifier output (open collector) 13 rfp ao power amplifier output (open collector) 14 nirq do interrupt request output for microcontroller (active low) and status read output 15 vdd s positive supply voltage 16 fsk di serial data input for fsk modulation SI4020 4 typical application, microcontroller mode vdd xtl vss mod rfn rfp nirq vdd fsk x1 10mhz gnd gnd gnd 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 ia4220 gnd c3 c2 10nf c1 2.2f r1 470 d1 led red gp4 gp3 gp2 gp1 micro controller gp0 clkin (ec osc. mode) sdi sck nsel pb1 pb2 pb3 pb4 clk gp5 optional s1 s2 s3 s4 optional gnd gp6 gp7 gp8 gp9 to other circuits antenna note: for detailed information about the supply decoupling capacitors see page 6. SI4020 5 package pin definitions, eeprom mode pin type key: d=digital, a=analog, s=su pply, i=input, o=output, io=input/output eeprom mode pin assignment pin name type function 1 sdi di data input of serial control interface 2 sck do clock output of serial control interface 3 nsel do chip select output of serial control interface (active low) 4 pb1 di push-button input #1 (active low with internal pull-up resistor) 5 pb2 di push-button input #2 (active low with internal pull-up resistor) 6 pb3 di push-button input #3 (active low with internal pull-up resistor) 7 pb4 di push-button input #4 (active low with internal pull-up resistor) 8 sdo do data output of serial control interface 9 xtl aio crystal connection (other terminal of crystal to vss) 10 vss s ground reference 11 mod di connect to logic low (eeprom mode) 12 rfn ao power amplifier output (open collector) 13 rfp ao power amplifier output (open collector) 14 nlbd do low battery voltage detector output (active low) 15 vdd s positive supply voltage 16 fsk di not used, connect to vdd or vss SI4020 6 typical application, eeprom mode vdd 1 8 3 7 2 6 4 5 eeprom 25aa080 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 ia4220 sd i sck nsel pb1 pb2 pb3 pb4 sd0 xtl vss mod rfn rfp nlbd vdd fsk ncs so nwp gnd si sck hold vcc r1 470 d1 led red x1 10mhz gnd gnd gnd gnd gnd s1 s2 s3 s4 c3 c2 10nf c1 2.2f x antenna optional recommended supply decoupling capacitor values c2 and c3 should be 0603 size ceramic capacitors to achieve th e best supply decoupling. the capa citor values are valid for both stand-alone and microcontroller mode. band [mhz] c1 c2 c3 315 2.2f 10nf 390pf 433 2.2f 10nf 220pf 868 2.2f 10nf 47pf 915 2.2f 10nf 33pf SI4020 7 general device specifications all voltages are referenced to v ss , the potential on the ground reference pin vss. absolute maximum ratings (non-operating) symbol parameter min max units v dd positive supply voltage -0.5 6.0 v v in voltage on any pin except open collector outputs -0.5 v dd +0.5 v v oc voltage on open collector outputs -0.5 6.0 v i in input current into any pin except vdd and vss -25 25 ma esd electrostatic discharge with human body model 1000 v t st storage temperature -55 125 o c t ld lead temperature (soldering, max 10 s) 260 o c recommended operating range symbol parameter min max units v dd positive supply voltage 2.2 5.4 v v oc voltage on open collector outputs (max 6.0 v) v dd - 1 v dd + 1 v t op ambient operating temperature -40 85 oc electrical specification (min/max values are valid over the whole reco mmended operating range, typical conditions: t op = 27 o c; v dd = v oc = 2.7 v) dc characteristics symbol parameter conditions/notes min typ max units 315 mhz band 9 433 mhz band 10 868 mhz band 12 i dd_tx_0 supply current (tx mode, p out = 0 dbm) 915 mhz band 13 ma 315 mhz band 11 433 mhz band 12 868 mhz band 14 i dd_tx_pmax supply current (tx mode, p out = p max ) 915 mhz band 15 ma i pd standby current in sleep mode all blocks disabled (note 1) 0.3 a i w t wake-up timer current consumption 1.5 a i lb low battery detector current consumption 0.5 a i x idle current only crystal oscillator is on 1.5 ma v lba low battery detection accuracy 75 mv v lb low battery detector threshold programmable in 0.1 v steps 2.2 5.3 v v il digital input low level 0.3*v dd v v ih digital input high level 0.7*v dd v i il digital input current v il = 0 v -1 1 a i ih digital input current v ih = v dd , v dd = 5.4 v -1 1 a v ol digital output low level i ol = 2 ma 0.4 v v oh digital output high level i oh = -2 ma v dd -0.4 v note for table above is on page 7. SI4020 8 ac characteristics symbol parameter conditions/notes min typ max units f ref pll reference frequency crystal operation mode is parallel (note 2) 8 10 12 mhz 315 mhz band, 2.5 khz resolution 310.24 319.75 433 mhz band, 2.5 khz resolution 430.24 439.75 868 mhz band, 5.0 khz resolution 860.48 879.51 f o output frequency (programmable) 915 mhz band, 7.5 khz resolution 900.72 929.27 mhz t lock pll lock time frequency error < 10 khz after 10 mhz step 20 s t sp pll startup time after turning on from idle mode, with crystal oscillator already stable 250 s i out open collector output current (note 3) at all bands 0.1 2.5 ma p maxl available output power (315 and 433 mhz band) with optimal antenna impedance (note 4) 3 dbm p maxh available output power (868 and 915 mhz band) with optimal antenna impedance (note 4) 1 dbm p out typical output power selectable in 3 db steps (note3) p max -21 p max dbm p sp spurious emission at max power with loop antenna (note 5) -50 dbc at low bands 1.5 2.3 3.1 c o output capacitance (set by the automatic antenna tuning circuit) at high bands 1.6 2.2 2.8 pf q o quality factor of the output capacitance 16 18 22 100 khz from carrier -75 l out output phase noise 1 mhz from carrier -85 dbc/hz br fsk fsk bit rate 256 kbps br ook ook bit rate 512 kbps df fsk fsk frequency deviation programmable in 30 khz steps 30 240 khz c xl crystal load capacitance see crystal selection guidelines programmable in 0.5 pf steps, tolerance +/- 10% 8.5 16 pf t por internal por timeout (note 6) after v dd has reached 90% of final value 100 ms t sx crystal oscillator startup time crys tal esr < 100 ohms (note 7) 1 5 ms t pbt wake-up timer clock accuracy crystal oscillator must be enabled to ensure proper calibration at startup (note 7) +/-10% ms t wake-up programmable wake-up time 1 2 10 9 ms c in, d digital input capacitance 2 pf t r, f digital output rise/fall time 15 pf pure capacitive load 10 ns all notes for table above are on page 7. SI4020 9 note 1: using a cr2032 battery (225 mah capacity), the expected battery li fe is greater than 2 years usin g a 60-second wake-up period for sending 100 byte packets in length at 19.2 kbps with +3 dbm output power in the 915 mhz band. note 2: using anything but a 10 mhz crystal is allowed but not recommended because all crystal-referred timing and frequency parameters will change accordingly. note 3: adjustable in 8 steps. note 4: optimal antenna admittance/ impedance for the SI4020: yantenna [s] zantenna [ohm] lantenna [nh] 315 mhz 9.4e-4 - j4.5e-3 43 + j214 112.00 434 mhz 8.4e-4 - j6.25e-3 21 + j157 59.00 868 mhz 1.15e-3 - j1.2e-2 7.9 + j83 15.30 915 mhz 1.2e-3 - j1.25e-2 7.6 + j79 13.90 note 5: with selective resonant antennas (see: application notes available from http://www.silabs.c om/integration). note 6: during this period, no commands are accepted by the chip. for detailed information see the reset modes section. note 7: the crystal oscillator start- up time strongly depends on the capacitance seen by the oscillator. using low capacitance and lo w esr crystal is recommended. when designing the pcb layout keep the trace connecting to the crystal short to minimize stray capacitance. SI4020 10 typical performance data unmodulated rf spectrum the output spectrum is measured at different frequencies. the output is loaded with 50 ohms through a matching network. 15:18:59 oct 29, 2003 ref -10 dbm #atten 5 db mkr1 434.0630 mhz -23.41 dbm samp log 10 db/ vavg 100 w1 s2 s3 fc aa center 434.1 mhz z h k 0 1 w b v z h k 0 1 w b s e r span 2 mhz sweep 40.74 ms (2001 pts) 1 15:20:49 oct 29, 2003 ref -10 dbm #atten 5 db mkr1 868 .0680 mhz -23.23 dbm samp log 10 db/ vavg 10 0 w1 s2 s3 fc aa center 868.1 mhz z h k 0 1 w b v z h k 0 1 w b s e r span 2 mhz swee p 40.74 ms (2001 pts) 1 15:37:47 dec 15, 2003 ref -10 dbm atten 5 db mkr1 315.0010 mhz -22.7 dbm samp log 10 db/ vavg 100 w1 s2 s3 fc aa center 315 mhz z h k 0 1 w b v z h k 0 1 w b s e r span 2 mhz sweep 40.74 ms (2001 pts) 1 15:28:02 dec 15, 2003 ref -10 dbm atten 5 db mkr1 915.0000 mhz -24.63 dbm samp log 10 db/ vavg 100 w1 s2 s3 fc aa center 915 mhz z h k 0 1 w b v z h k 0 1 w b s e r span 2 mhz sweep 40.74 ms (2001 pts) 1 a t 315 mhz a t 433 mhz a t 868 mhz a t 915 mhz SI4020 11 modulated rf spectrum at 433 mhz with 180 khz deviation at 64 kbps at 868 mhz with 180 khz deviation at 64 kbps 15:46:09 oct 29, 2003 ref -10 dbm atten 5 db #peak log 10 db/ vavg 100 w1s2 s3 fc aa center 434 mhz res bw 10 khz vbw 100 khz span 2 mhz sweep 20.07 ms (2001 pts) 15:43:45 oct 29, 2003 ref -10 dbm atten 5 db #peak log 10 db/ vavg 100 w1s2 s3 fc aa center 868 mhz res bw 10 khz vbw 100 khz span 2 mhz sweep 20.07 ms (2001 pts) spurious rf spectrum with 10 mhz clk output enabled at 433 mhz antenna tuning characteristics 750?970 mhz p 16:29:03 jun 17, 2003 ref 0 dbm atten 10 db mkr1 ? 20.0 mhz -55.11 db #peak log 10 db/ w1s2 s3 fc aa center 434.8 mhz #res bw 3 khz #vbw 300 hz span 50 mhz sweep 45.47 s (401 pts) 1 1r marker ? 20.000000 mhz -55.11 db 16:54:54 mar 11, 2003 ref -36 dbm #atten 0 db mkr1 915.0 mhz -37.62 dbm peak log 1 db/ v1 m2 s3 fc aa start 700 mhz #res bw 1 mhz vbw 1 mhz stop 1.05 ghz sweep 50 ms (401 pts) 1 * marker 915.000000 mhz -37.62 dbm the antenna tuning characteristics was recorded in ?max-hold? state of the spectrum analyzer. during the measurement, the transmitters were forced to change frequencies by forcing an external reference signal to the xtl pin. while the carrier was ch anging the antenna tuning circuit switched trough all the available stat es of the tuning circuit. the graph clearly demonstrates that while the complete output circuit had about a 40 mhz bandwidth, the tuning allows operating in a 220 mhz band. in other words the tuning circuit can compensate for 25% variation in the resonant frequency due to any proce ss or manufacturing spread. SI4020 12 control interface commands to the transmitters are sent serially. data bits on pin sdi are shifted into the device upon the rising edge of the cl ock on pin sck whenever the chip select pin nsel is low. when the nsel signal is high, it initializes the serial interface. the number of bits sent is an integer multiple of 8. all commands consist of a command code, followed by a varying number of parameter or data bit s. all data are sent msb first (e.g . bit 15 for a 16-bit command). bits having no in fluence (don?t care) are indicated with x. the power on reset (por) circuit sets default values in all control and command registers. timing specification timing diagram sck sdi nirq nsel t ds t dh t ch t cl bit15 bit14 bit13 t ss por bit8 bit7 t od wk-up nirq bit1 bit0 t sh t shi symbol parameter minimum value [ns] t ch clock high time 25 t cl clock low time 25 t ss select setup time (nsel falling edge to sck rising edge) 10 t sh select hold time (sck falling edge to nsel rising edge) 10 t shi select high time 25 t ds data setup time (sdi transition to sck rising edge) 5 t dh data hold time (sck rising edge to sdi transition) 5 t od data delay time 10 t bl push-button input low time 25 SI4020 13 control commands control command related parameters/functions 1 configuration setting command frequency band, microcontroller clock output, crystal load capacitance, frequency deviation 2 power management command crystal oscillator, synthesizer, power amplifier, low battery detector, wake-up timer, clock output buffer 3 frequency setting command carrier frequency 4 data rate command bit rate (at eeprom mode only) 5 power setting command nominal output power, ook mode 6 low battery detector command low battery threshold limit 7 sleep command length of the clock tail after power down 8 push-button command push-button related functions 9 wake-up timer command wake-up time period 10 data transmit command data transmission 11 status register command transmitter status read note: in the following tables the por column shows the default values of the command registers after power-on. 1. configuration setting command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 0 0 b1 b0 d2 d1 d0 x3 x2 x1 x0 ms m2 m1 m0 8080h b1 b0 frequency band [mhz] 0 0 315 0 1 433 1 0 868 1 1 915 d2 d1 d0 clock output frequency [mhz] 0 0 0 1 0 0 1 1.25 0 1 0 1.66 0 1 1 2 1 0 0 2.5 1 0 1 3.33 1 1 0 5 1 1 1 10 x3 x2 x1 x0 crystal load capacitance [pf] 0 0 0 0 8.5 0 0 0 1 9.0 0 0 1 0 9.5 0 0 1 1 10.0 ? 1 1 1 0 15.5 1 1 1 1 16.0 the resulting output frequency can be calculated as: f out = f 0 ? (-1) sign * (m + 1) * (30 khz) where: f 0 is the channel center frequency (see the next command) m is the three bit binary number < m2 : m0> sign = ( ms ) xor (fsk input) SI4020 14 2. power management command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 0 0 0 0 a1 a0 ex es ea eb et dc c000h bits 5-0, enable the corresponding block of the transmitters, i.e. the crystal oscillator is enabled by the ex bit, the synthesizer by es , the power amplifier by ea and the low battery detector by eb , while the wake-up timer by et. the bit dc disables the clock output buffer. when receiving the data transmit command , the chip supports automatic on/off control over the crystal oscillator, the pll and the pa. if bit a1 is set, the crystal oscillator and the synthesizer are controlled automatically. data transmit command starts up the crystal oscillator and as soon as a stable reference frequency is available the sy nthesizer starts. after a subsequent delay to allow locking of t he pll, if a0 is set the power amplifier is turned on as well. note : ? to enable the automatic internal control of the crystal oscillator, the synthesizer and the power amplifier, the corresponding bits ( ex, es, ea ) must be zero in the power management command . ? in microcontroller mode, the ex bit should be set in the power management command for the correct control of es and ea . the oscillator can be switched off by clearing the ex bit after the transmission. ? in eeprom operation mode after an identified data transmit command the internal logic switches on the synthesizer and pa. at the end of data transmit command header if necessary the current clock cycle is automatically extended to ensure the pll stabilization and rf power ramp-up. ? in eeprom operation mode the internal logic switches off the pa when the given number of bytes is transmitted. (see: data transmit command in eeprom operation.) ? when the chip is controlled by a microcontroller, the sleep command can be used to indicate the end of the data transmission process, because in microcontroller mode the data transmit command does not contain the length of the tx data. ? for processing the events caused by the pe ripheral blocks (por, lbd, wake-up timer, push-buttons) the chip requires operation o f the crystal oscillator. this operation is fully contro lled internally, independently from the status of the ex bit, but if the dc bit is zero, the oscillator remains active until sleep command is issued. (this command can be consid ered as an event controller reset.) oscillator control logic SI4020 15 3. frequency setting command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 0 1 0 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 a7d0h the 12-bit parameter of the frequency setting command SI4020 16 6. low battery detector command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 0 0 1 0 0 0 0 t4 t3 t2 t1 t0 c200h the 5-bit value t of < t4 : t0> determines the threshold voltage v lb of the detector: v lb = 2.25 v + t * 0.1 v 7. sleep command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 0 1 0 0 s7 s6 s5 s4 s3 s2 s1 s0 c400h the effect of this command depends on the power management command . it immediately disables the power amplifier (if a0 =1 and ea =0) and the synthesizer (if a1 =1 and es =0). stops the crystal oscillator after s periods of the microcontroller clock (if a1 =1 and ex =0) to enable the microcontroller to execute all necessary comma nds before entering sleep mode itself. the 8-bit value s is determined by bits < s7 : s0> . 8. push-button command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 1 0 1 0 p4 d1 d0 b4 b3 b2 b1 bc ca00h if the corresponding bit was set ( b1-b4 ) the event remains active while the button is pressed. in eeprom mode, the chip is continuously performing the routine assigned to the push-button while it is pressed. in microcontroller mode, the chip continuously generate s interrupts on nirq until the push-button is released. weak pull-up currents are switched off when bc is high. the d0, d1 bits set the de-bouncing time period: d1 d0 de-bouncing time [ms] 0 0 160 0 1 40 1 0 10 1 1 0 (bypassed) note : ? until the de-bouncing time has expired, the crystal oscillat or remains switched on, independent of the status of the ex bit in the power management command . (because the circuit uses the crys tal oscillator signal for timing.) if the p4 bit is set, the controller performs the routine assigned to the fourth button when pb1 and pb2 are pressed down simultaneously. with the addition of this feature, there is a way to build a device that uses 3 buttons, but performs 4 functio ns. it is possible to detect multiple pressed push-buttons in both modes. in eeprom mode the controll er executes sequentially all t he routines belonging to the pressed buttons. SI4020 17 simultaneously pressed push-bu tton detect by microcontroller vdd microcontroller mode spi nirq por (internal) push button input 2 push button input 1 por pb1 pb1 pb2 pb1 pb2 pb1 status rd status rd status rd status rd status rd status rd status rd pb_nirqdly* note: *pb_nirqdly is equal with the debounce time simplified block diagram of push-button 1?4 inputs to digital glitch filter for push-button4 push-button1,2,3 d q clr event flag sleep command * stat. reg. read command ** count/single vdd note: * in eeprom mode ** in uc controlled mode push-button1 push-button2 push-button4 internal blocker signal to push-button1 and push-button2 p4 weak pull-up enable/disable vdd with internal weak pull-up por, lbd, wake up timer, p. buttons event flags notice: only one event is serviced simultaneously the others are pending. digital glitch filter clk clr for p.b1,2 b1, b2, b3 bc SI4020 18 9. wake-up timer command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 1 r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 e000h the wake-up time period can be calculated as: t wake-up = m * 2 r [ms] , where m is defined by the < m7 : m0> digital value and r is defined by the < r4 : r0> digital value. the value of r should be in the range of 0 and 23. the maximum achievable wake-up time period can be up to 24 days. note: ? f or continual operation the et bit should be cleared and se t at the end of every cycle. software reset: sending ff00h command to the chip triggers software reset. for more details see the reset modes section. 10. data transmit command this command is not needed if the transmitters? power management bits ( ex, es, ea ) are fully controlled by the microcontroller and tx data comes through the fsk pin. in eeprom operation mode: bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 0 1 1 0 n7 n6 n5 n4 n3 n2 n1 n0 - - in microcontroller slave mode: bit 7 6 5 4 3 2 1 0 por 1 1 0 0 0 1 1 0 - - this command indicates that the following bitstream coming in vi a the serial interface is to be transmitted. in eeprom mode, th e 8- bit value n of bits < n7 : n0> contains the number of data bytes to follow. note : ? if the crystal oscillator was formerly switched off ( ex =0), the internal oscillator needs t sx time, to switch on. the actual value depends on the type of quartz crystal used. ? if the synthesizer was formerly switched off ( es =0), the internal pll needs t sp startup time. valid data ca n be transmitted only when the internal locking process is finished. ? in eeprom mode, before issuing the data transmit command , the power amplifier must be enabled, with the ea or a0 bit in the power management command . ? in eeprom mode, when n bytes have been read and transmitted the controller continues reading the eeprom and processing the data as control commands. this process stops after sleep command has been read from the eeprom. SI4020 19 data transmit sequence through the fsk pin nsel sck sdi instruction internal operations a0, a1 = 0 ex, es, ea = 1 xtal osc. stable xtal osc staus fsk t x d a t a synthesizer on, pll locked, pa ready to transmit synthesizer / pll / pa status t sx * t sp * c 0 h 3 8 h d o n ' t c a r e p o w e r m a n a g e m e n t c o m m a n d note: * see page 6 for the timing values data transmit sequence through the sdi pin note : ? do not send clk pulses with the tx data bits; otherwise they will be interpreted as commands. ? this mode is not spi compatible, therefore it is not recommended in microcontroller mode. ? if the crystal oscillator and the pll are running, the t sx +t sp delay is not needed. SI4020 20 11. status register read command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 - - with this command, it is possible to read the chip?s status register through the nirq pin. this command clears the last service d interrupt and processing the next pend ing one will start (if there is any). status register read sequence nsel sck sdi nirq 0 instruction 123456 7 8 9 10 11 12 13 14 15 por pb1 pb2 pb3 pb4 lbd wk-up nirq status out SI4020 21 eeprom mode in this mode, the transmitters can operate with a standard at least 1 kbyte serial eeprom with an spi interface, and no microcontroller is necessary. the following events cause wake-up of the device: event number n eeprom entry point description 0 0000h power-on 1 0080h low level on input pb1 2 0100h low level on input pb2 3 0180h low level on input pb3 4 0200h low level on input pb4 5 0280h low supply voltage level 6 0300h wake-up timer timeout after any of these events, the crystal oscillator turns on and th e device starts to read bytes from the eeprom continuously (bl ock read) starting from address n * 128 (dec imal) and executes them as commands as described in the previous section. note : zero bytes can be put in the eeprom for timing purposes. never put more than 31 consecutive zero bytes into the eeprom?s active region (between the actual entr y point and the closing sleep command). example eeprom hex content power-on reset: 00000000 c0 c4 ca 1e c8 23 c4 00 00 00 00 00 00 00 00 00 00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 short explanation: data in address, command, and parame ter fields are hexadecimal values. for the detailed description of the cont rol command bits, see previous section. address command parameter related control command remarks 00?01 c0 c4 power management crystal ? synthesizer ? power amplifier auto on/off mode enable 02?03 ca 1e push button continuous execution for all push buttons 04?05 c8 23 bit rate br = 10m / 29 / ( 35+1 ) ~ 9600 bps 06-07 c4 00 sleep power down SI4020 22 push-button 1: 00000080 88 72 a6 10 c6 60 55 55 55 55 55 55 55 55 55 55 00000090 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000a0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000b0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000c0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000d0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000e0 55 55 55 55 55 55 c4 00 00 00 00 00 00 00 00 00 000000f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 short explanation: address command parameter related control command remarks 80?81 8 872 configuration control 433mhz band, xtal c l =12pf f dev =90khz 82?83 a 610 frequency f c =(43+1552/4000)*10mhz 84?85 c6 60 data transmit transmit the next 96 bytes 86?e5 60x55 data e6?e7 c4 00 sleep power down, go to address 80 (see note) note: ? this routine is repeatedly executed while pb1 is pressed, becaus e continuous execution was selected at por (ca1e code issued in the power-on reset section before). rx-tx alignment procedures rx-tx frequency offset can be caused only by the differences in the actual reference frequency. to minimize these errors it is suggested to use the same crystal type and the same pcb layout for the crys tal placement on the rx and tx pcbs. to verify the possible rx-tx offset it is suggested to measure the clk output of both chips with a high level of accuracy. do n ot measure the output at the xtl pin since the measurement process itself will change the reference frequency. since the carrier frequencies are derived from the reference frequency, having id entical reference frequencies and nominal frequency settings at the tx and rx side there should be no offset if the clk signals have identical frequencies. it is possible to monitor the actual rx-tx offset using the afc st atus report included in the status byte of the receiver. by r eading out the status byte from the receiver, the actual measured offset fr equency will be reported. in order to get accurate values the a fc has to be disabled during the read by clearing the "en" bit in the afc control command (bit 0). SI4020 23 crystal selection guidelines the crystal oscillator of the SI4020 requires a 10 mhz parallel mode crystal. the circuit contains an integrated load capacitor in order to minimize the external component co unt. the internal load capacitance value is programmable from 8.5 pf to 16 pf in 0.5 pf steps. with appropriate pcb layout, the to tal load capacitance value can be 10 pf to 20 pf so a variety of crystal types can be used. when the total load capacitance is not more than 20 pf and a worst case 7 pf shunt capacitance (c 0 ) value is expected for the crystal, the oscillator is able to start up with any crystal having less than 300 oh ms esr (equivalent series loss resistance). however, lower c 0 and esr values guarantee faster oscillator startup. the crystal frequency is used as the reference of the pll, which generates the rf carrier frequency (f c ). therefore, f c is directly proportional to the crystal frequency. the accuracy requirements for production tole rance, temperature drift and aging can thus be determined from the maximum allowable carrier frequency error. maximum xtal tolerances including temperature and aging [ppm] bit rate: 2.4kbps 30 60 90 120 150 180 210 315 mhz 30 75 100 100 100 100 100 433 mhz 20 50 75 100 100 100 100 868 mhz 10 25 40 60 75 100 100 915 mhz 10 25 40 50 75 75 100 bit rate: 9.6kbps 30 60 90 120 150 180 210 315 mhz 25 70 100 100 100 100 100 433 mhz 15 50 75 100 100 100 100 868 mhz 8 2540607575100 915 mhz 8 2540507075100 bit rate: 38.3kbps 30 60 90 120 150 180 210 315 mhz don?t use 30 75 100 100 100 100 433 mhz don't use 20 50 75 100 100 100 868 mhz don't use 10 30 40 60 75 100 915 mhz don't use102540607575 transmitter deviation [+/- khz] transmitter deviation [+/- khz] transmitter deviation [+/- khz] whenever a low frequency error is essential for the application, it is possible to ?pu ll? the crystal to the accurate frequency by changing the load capacitor value. the wide st pulling range can be achieved if the no minal required load capacitance of the cry stal is in the ?midrange?, for example 16 pf. the ?pull-ability? of the crystal is defined by its motional capacitance and c 0 . note: there may be other requirements for the tx carrier accuracy wi th regards to the requirements as defined by standards and/or c hannel separations. SI4020 24 reset modes the chip will enter into reset mode if an y of the following conditions are met: ? power-on reset: during a power up sequence until the v dd has reached the correct level and stabilized ? power glitch reset: transients present on the v dd line ? software reset: special control command received by the chip power-on reset after power up the supply voltage starts to rise from 0v. the re set block has an internal ramping voltage reference (reset-ramp signal), which is rising at 100mv/ms (typ ical) rate. the chip remains in reset stat e while the voltage difference between the a ctual v dd and the internal reset-ramp signal is higher than the reset threshold voltage, which is 600 mv (typical). as long as the v dd voltage is less than 1.6v (typical) the chip stays in reset mode regardless the voltage difference between the v dd and the internal ramp signal. the reset event can last up to 150ms supposing that the v dd reaches 90% its final value within 1ms. during this period the chip does not accept control commands via the serial control interface. power-on reset example: power glitch reset the internal reset block has two basic mode of operation: normal and sensitive reset. the default mode is sensitive, which can be changed by the appropriate control command (see related control commands at the end of this section). in normal mode the power glitch detection circuit is disabled. there can be spikes or glitches on the v dd line if the supply filtering is not satisfactory or the internal resistance of the power supply is too high. in such cases if the sensitive reset is enabled an (unw anted) reset will be generated if the positive going edge of t he v dd has a rising rate greater than 100mv/ms and the voltage di fference between the internal ramp signal and the v dd reaches the reset threshold voltage (600 mv). typical case when the battery is weak and due to its increased intern al resistance a sudden decreas e of the current consumption (for example turning off the power amplifier) might lead to an increase in supply voltage. if for some reason the sensitive reset cannot be disabled step -by-step decrease of the current consumpti on (by turning off the different stages on e by one) can help to avoid this problem. any negative change in the supply voltage will not cause reset event unless the v dd level reaches the reset threshold voltage (250mv in normal mode, 1.6v in sensitive reset mode). if the sensitive mode is disabled and the power supply turned off the v dd must drop below 250mv in order to trigger a power-on reset event when the supply voltage is turned back on. if the decoupling capacitors keep their charges for a long time it could happe n that no reset will be generated upon power-up because the power glitch detector circuit is disabled. note that the reset event reinitializes the internal re gisters, so the sensitive mode will be enabled again. SI4020 25 sensitive reset enabled, ripple on v dd : time v dd reset threshold voltage (600mv) nres output h l 1.6v reset ramp line (100mv/ms) sensitive reset disabled: time v dd reset threshold voltage (600mv) nres output h l 250mv reset ramp line (100mv/ms) software reset software reset can be issued by sending the appropriate control command (described at the end of the section) to the chip. the result of the command is the same as if power-on reset was occurred. v dd line filtering during the reset event (caused by power-on, fast positive spike on the supply line or software reset command) it is very import ant to keep the v dd line as smooth as possible. noise or periodic disturbing signal superimposed the supply voltage may prevent the part getting out from reset state. to avoid this phenomenon use adequa te filtering on the power supply line to keep the level of the disturbing signal below 10mv p-p in the dc ? 50khz range for 200ms from v dd ramp start.. typical example when a switch-mode regulator is used to supply the radio, switching noise may be present on the v dd line. follow the manufacturer?s recommendations how to decrease the ripple of the regulator ic and/or how to shift the switching frequency. related control commands ?low battery detector command? setting bit<6> to high will change the reset mo de to normal from the default sensitive. ?sw reset command? issuing ff00h command will trigger software reset. see the wake-up timer command . SI4020 26 simplified internal control and timing the internal controller uses the clock gene rated by the crystal oscillator to sequenti ally process the various events and to de -bounce the push-button (pb) inputs. if the oscillat or is not running, internal logic automati cally turns it on te mporarily and then of f again. such events are: any wake-up event (por, pb press, wake-up timer timeout, and low supply voltage detection), pb release and status read request by the microcontroller. if two wake-up events occur in succession, th e crystal oscillator stays on until the ne xt status read (acknowledgment of the fi rst event). simplified internal control and timing diagrams note: * tsx : crystal oscillator st artup t im e ** length of tclk_tail is determined by the parameter in the sleep comm a nd vdd push-button inpu t x microcontroller mode (ec=0, ex=0) spi osc_on (in te rna l) por (inte rna l) debouncing time + t s x* status rd cmd status rd cmd (pb x) stat. b its vdd spi osc_on (in te rna l) por (inte rna l) nirq status rd cmd (po r ) stat. b its status rd cmd (pb x) stat. b its microcontroller modewith multiple event read (ec=0, ex=0) nirq push-button inpu t x 1us tsx* (po r ) stat. b its tsx* tsx* vdd microcontroller mode (ec=1, ex=0) spi osc_on (in te rna l) por (inte rna l) slee p cmd slee p cmd push-button inpu t x tclk_tail** status rd status rd tclk_tail** SI4020 27 matching network for a 50 ohm single ended output matching network schematic SI4020 l1 [nh] l2 [nh] l3 [nh] c1 [pf] c2 [pf] c3 [pf] 315 mhz 72 110 390 3.9 2.2 56..100 433 mhz 43 82 390 2.7 1.5 56..100 868 mhz 10 27 100 1.8 1 27..56 915 mhz 10 27 100 1.8 1 27..56 SI4020 28 example applications for microcontroller mode schematic pcb layout of keyboard transmitter demo circuit using microcontroller mode (operating in the 915 mhz band) top layer bottom layer SI4020 29 for eeprom mode schematic pcb layout of push-button transmitter demo circui t using eeprom mode (operating in the 434 mhz band) top layer bottom layer SI4020 30 package information 16-pin tssop detail ?a? gauge plane 0. 2 5 section b-b see detail ?a? min. nom. max. min. nom. max. 7 4 0 , 0 0 2 , 1 a 6 0 0 , 0 2 0 0 , 0 5 1 , 0 5 0 , 0 1 a a2 0,80 0,90 1,05 0,031 0,035 0,041 2 1 0 , 0 7 0 0 , 0 0 3 , 0 9 1 , 0 b b1 0,19 0,22 0,25 0,007 0,009 0,010 8 0 0 , 0 4 0 0 , 0 0 2 , 0 9 0 , 0 c 6 0 0 , 0 4 0 0 , 0 6 1 , 0 9 0 , 0 1 c d 4,90 5,00 5,10 0,193 0,197 0,201 e e e1 4,30 4,40 4,50 0,169 0,173 0,177 l 0,50 0,60 0,75 0,020 0,024 0,030 l1 4 0 0 , 0 9 0 , 0 r 4 0 0 , 0 9 0 , 0 1 r 8 0 8 0 1 2 3 symbol dimensions in mm dimensions in inches . c s b 6 2 0 . 0 . c s b 5 6 . 0 6.40 bsc. 12 ref. 12 ref. 12 ref. 12 ref. 1.00 ref. 0.252 bsc. 0.39 ref. SI4020 31 this page has been inten tionally left blank. SI4020 32 related products and documents SI4020 universal ism band fsk transmitter description ordering number SI4020 16-pin tssop SI4020-ic cc16 rev i1 die see silicon labs demo boards and development kits description ordering number development kit ia ism ? dk remote temperature monitoring station ia ism ? datd related resources description ordering number antenna selection guide ia ism ? an1 antenna development guide ia ism ? an2 ia4320 universal ism band fsk receiver see www.silabs.com/integration for details note: volume orders must include chip revision to be accepted. silicon labs, inc. 400 west cesar chavez austin, texas 78701 tel: 512.416.8500 fax: 512.416.9669 toll free: 877.444.3032 www.silabs.com/integration wireless@silabs.com the specifications and descriptions in this document are based on information available at the time of publication and are subject to change without notice. silicon laboratories assumes no responsibility for errors or omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes to the product and its documentation at any time. silicon laboratories makes no representations, warranties, or guarant ees regarding the suitability of its products for any particular purpose and does not assume any liability arising out of the application or use of an y product or circuit, and specifically disclaims any and all liability for c onsequential or incidental damages arising out of use or failure of the product. nothing in this document shall operate as an express or implied license or i ndemnity under the intellectual property rights of silicon laboratories or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. no warranties of any kind, including but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document. ?2008 silicon laboratories, inc. all rights reserved. silicon laboratories is a trademark of silicon laboratories, inc. all other trademarks belong to their respective owners. |
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