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9FGP205 idt ? frequency timing generator for peripherals 1664?05/14/10 frequency timing generator for peripherals 1 datasheet advance information pin configuration recommended application: peripheral clock for intel servers with wake-on-lan support output features: ? 1 - 0.7v current-mode differential cpu output ? 6 - 50mhz rmii outputs ? 2 - 125mhz rgmii outputs ? 1 - 0.7v current-mode differential dot 96mhz output ? 1 - 33.33mhz output ? 1 - 32.768khz output ? 2 - 25mhz ref outputs key specifications: ? exact synthesis on cpu, rgmii, rmii & 33.33mhz clocks ? +/- 100ppm frequency accuracy on other clocks features/benefits: ? selectable smbus address - d0/d1 or c0/c1 ? spread spectrum capability on cpu and dot 96mhz clocks ? smbus control: - m/n and spread programming on cpu and dot 96mhz clocks via smbus - differential outputs can be disabled via pins or smbus cpu fs2 cpu fs1 cpu fs0 b y te0 bit2 b y te0 bit1 b y te0 bit0 0 0 0 266.67 96.00 33.33 50.00 125.00 25.00 32.768 0 0 1 133.33 96.00 33.33 50.00 125.00 25.00 32.768 0 1 0 200.00 96.00 33.33 50.00 125.00 25.00 32.768 0 1 1 166.67 96.00 33.33 50.00 125.00 25.00 32.768 1 0 0 333.33 96.00 33.33 50.00 125.00 25.00 32.768 1 0 1 100.00 96.00 33.33 50.00 125.00 25.00 32.768 1 1 0 400.00 96.00 33.33 50.00 125.00 25.00 32.768 1 1 1 reserved 96.00 33.33 50.00 125.00 25.00 32.768 power up default is highlighted. 25 mhz 32.768 khz rmii mhz functionality cpuclk mhz dot96ss mhz 33.33 mhz rgmii mhz vtt_pwrgd/wol_stop# smbdat smbclk rgmii0 rgmii1 gndrgmii vddrgmii rmii0 rmii1 vddrmii 40 39 38 37 36 35 34 33 32 31 gnd 130 gndrmii vdd96 229 rmii2 dot96sst 328 rmii3 dot96ssc 427 gndrmii oe_96 526 vddrmii oe_cpu 625 rmii4 cpuclkt0 724 rmii5 cpuclkc0 823 vdd33 vddcpu 922 33.33mhz/**smbadr gndcpu 10 21 gnd33 11 12 13 14 15 16 17 18 19 20 iref vdd32k 32.768khz gnd32k vddref 25mhz_0 25mhz_1 gndref x1_25 x2_25 9FGP205 40-mlf * internal pull-up resistor ** internal pull-dow n resistor smbus address selection smbadr = 0 smbadr = 1 d0/d1 c0/c1 smbadr
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 2 advance information pin description pin # pin name pin type description 1 gnd pwr ground pin. 2 vdd96 pwr power pin for the dot96 clocks, nominal 3.3v 3 dot96sst out true clock of differential pair for 96.00mhz spread spectrum capable dot clock. these are current mode outputs. external resistors are required for voltage bias. 4 dot96ssc out complementary clock of differential pair for 96.00mhz spread spectrum capable dot clock. these are current mode outputs. external resistors are required for voltage bias. 5 oe_96 in active high input for enabling 96hz outputs. 1 = enable output(s), 0 = tri-state output(s) 6oe_cpu in active high input for enabling cpu diff pairs. 1 = enable output(s), 0 = tri-state output(s) 7cpuclkt0 out true clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 8cpuclkc0 out complementary clock of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 9 vddcpu pwr supply for cpu clocks, 3.3v nominal 10 gndcpu pwr ground pin for the cpu outputs 11 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 12 vdd32k pwr power pin for the 32.768khz outputs, nominal 3.3v 13 32.768khz out 32.768khz clock output 14 gnd32k pwr ground pin for the 32.768khz outputs 15 vddref pwr ref, xtal power supply, nominal 3.3v 16 25mhz_0 out 25mhz clock output, 3.3v 17 25mhz_1 out 25mhz clock output, 3.3v 18 gndref pwr ground pin for the ref outputs. 19 x1_25 in crystal input, nominally 25.00mhz. 20 x2_25 out crystal output, nominally 25.00mhz. 21 gnd33 pwr ground pin for the 33.33mhz outputs 22 33.33mhz/**smbadr i/o 33.33mhz clock output / smbus address select bit. 23 vdd33 pwr power pin for the 33.33mhz outputs, nominal 3.3v 24 rmii5 out 3.3v 50mhz rmii clock output 25 rmii4 out 3.3v 50mhz rmii clock output 26 vddrmii pwr 3.3v power pin for the rmii clocks. 27 gndrmii pwr ground pin for the rmii outputs 28 rmii3 out 3.3v 50mhz rmii clock output 29 rmii2 out 3.3v 50mhz rmii clock output 30 gndrmii pwr ground pin for the rmii outputs 31 vddrmii pwr 3.3v power pin for the rmii clocks. 32 rmii1 out 3.3v 50mhz rmii clock output 33 rmii0 out 3.3v 50mhz rmii clock output 34 vddrgmii pwr 3.3v power pin for the rgmii clocks and pll 35 gndrgmii pwr ground pin for the rgmii outputs 36 rgmii1 out 3.3v 125mhz rgmii clock output 37 rgmii0 out 3.3v 125mhz rgmii clock output 38 smbclk in clock pin of smbus circuitry, 5v tolerant 39 smbdat i/o data pin of smbus circuitry, 5v tolerant 40 ckpwrgd_wol_stop# in notifies clock to sample latched inputs on first low to high transition. after first power up, a low stops all outputs except those designated to run in power down mode (wol_stop# mode)
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 3 advance information general description block diagram the 9FGP205 is a peripheral clock for intel servers. it is driven with a 25mhz crystal and generates a variety of clocks, including 125mhz rgmii. an smbus interface allows full control of the device. power supply pins vdd gnd 9 10 cpuclk output and pll 2 1 dot96ss output and pll 34 35 125 mhz rgmii outputs and pll 26,31 27,30 50 mhz rmii outputs 23 21 33.33mhz output 12 14 32.768khz output 15 18 xtal, ref outputs description pin number note: all vdd should be connected to a common power rail with proper filtering and decoupling. pins 2, 9 and 34 should be treated as analog pins for decoupling purposes. x1_25 x2_25 cpuclk control logic smbdat smbclk smbadr cpu pll (spread capable) oe_cpu dot96ss dot pll (spread capable) fixed pll xtal dividers oe_96 6 ckpwrgd_ wol_stop# 33.33mhz rmii(5:0) 32.768khz 25mhz(1:0) dividers rgmii(1:0) 2
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 4 advance information drive strength for all the single-ended outputs can be controlled by the smbus bytes 4 and 5 as shown in the default drive stre ngth table. test load cl=5pf rs zo ics9fgp202a sepp output buffer (single ended push pull) rs zo rs zo sepp output buffer (single ended push pull) cl=5pf cl=5pf l1 l2 note: l1 must equal l2 +/- 25 mils ics9FGP205 default drive strength table default drive optional drive rgmii 1 load na rmii 1 load 2 loads 33.33mhz 2 loads 1 load 25mhz 2 loads 1 load 32.768khz 2 loads 1 load series termination resistor values except rgmii output drive strength series resistor (rs) for driving 1 load series resistor (rs) for driving 2 loads 1 load 22 ohms n/a 2 loads 33 ohms 8.2 ohms note: all values are for zo = 50 ? series termination resistor values - rgmii output drive stren g th series resistor (rs) for driving 1 load series resistor (rs) for driving 2 loads 1 load 27 ohms n/a note: all values are for zo = 50 ?
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 5 advance information truth table1: ckpwrgd_wol_stop#, oe_96 and oe_cpu ckpwrgd_wol_stop# oe_96 dot96ssc oe_cpu cpuclk 0 0 1 0 disabled 0 disabled 1 1 enabled 1 enabled *assuming dot96 output enable from smbus byte2 bit0 sets to enable (default) *assuming cpuclk output enable from smbus byte2 bit1 sets to enable (default) xx xx truth table 2: ckpwrgd_wol_stop# single-ended outputs ckpwrgd_wol_stop# pin 16, 29, 32, 33 pin 22 other outputs 0 running hi-z low 1 running running running *assuming smbus at default value. table: cpu spread and frequency selection cpu ss_en cpu fs2 cpu fs1 cpu fs0 byte 0 bit 3 byte 0 bit 2 byte 0 bit 1 byte 0 bit 0 0 0 0 0 266.67 0% 0 0 0 1 133.33 0% 0 0 1 0 200.00 0% 0 0 1 1 166.67 0% 0 1 0 0 333.33 0% 0 1 0 1 100.00 0% 0 1 1 0 400.00 0% 0 1 1 1 200.00 0% 1 0 0 0 266.67 0.5% 1 0 0 1 133.33 0.5% 1 0 1 0 200.00 0.5% 1 0 1 1 166.67 0.5% 1 1 0 0 333.33 0.5% 1 1 0 1 100.00 0.5% 1 1 1 0 400.00 0.5% 1 1 1 1 200.00 0.5% cpu mhz down spread %
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 6 advance information table: dot96 spread and frequency selection table dot96 ss_en fs3 fs2 fs1 fs0 byte 0 bit 4 byte 3 bit 3 byte 3 bit 2 byte 3 bit 1 byte 3 bit 0 0000096.00 0000196.00 0001096.00 0001196.00 0010096.00 0010196.00 0011096.00 0011196.00 0100096.00 0100196.00 0101096.00 0101196.00 0110096.00 0110196.00 0111096.00 0111196.00 1000096.00+/-0.25center 1000196.00+/-0.5center 1001096.00+/-0.75center 1001196.00+/-1.0center 1010096.00-0.25down 1010196.00-0.50down 1011096.00 -0.75 down 1011196.00-1.0down 1100096.00-1.25down 1100196.00 -1.50 down 1101096.00-1.75down 1101196.00-2.0down 1110096.00 -2.25 down 1110196.00-2.5down 1111096.00-2.75down 1111196.00-3.00down 0 0 0 0 0 0 0 0 0 0 0 0 dot96ss mhz spread % 0 0 0 0
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 7 advance information absolute maximum ratings parameter symbol conditions min typ max units notes 3.3v supply voltage vddxxx - gnd - 0.5 3.3v gnd + 4.5 v 1 maximum difference across all vdd pins vdddelta - 0.5 v 1 storage temperature ts - -65 150 c 1 ambient operating temp tambient - 070c 1 junction temperature tj - 125 c 1 input esd protection hbm esd prot - 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. electrical characteristics - input/supply/common output parameters parameter symbol conditions* min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 v dd + 0.3 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 operating current i dd3.3op all outputs driven, cpu@100m 225 ma 1 wol_stop mode (default) 75 ma 1 all diff pairs driven 30 ma 1 all differential pairs tri-s tated 8 ma 1 input frequency f i v dd = 3.3 v 25.00000 mhz 2 pin inductance l p in 7nh1 c in logic inputs 4 pf 1 c out output pin capacitance 5 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabiliz ation t stab from vdd power-up or de- assertion of pd to 1st clock 0.5 2.5 ms 1 modulation frequency triangular modulation 30 33 khz 1 tdrive_pd cpu output enable after pd de-assertion 260 300 us 1 tfall_pd pd fall time of 5 ns 1 trise_pd pd rise time of 5 ns 1 smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup 45 ma1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5% 1 guaranteed by design and characterization, not 100% tested in production. input low current input capacitance powerdown current i dd3.3pd 2 input frequency should be measured at the ref pin and tuned to ideal 25.00mhz to meet ppm frequency accuracy on pll outputs.
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 8 advance information electrical characteristics - cpu 0.7v current mode differential pair parameter symbol conditions* min typ max units notes current source output impedance zo v o = v x 3000 ? 1 voltage high vhigh 660 731 850 mv 1,3 voltage low vlow -150 70 150 mv 1,3 max voltage vovs 800 1150 mv 1 min voltage vuds -300 8 mv 1 crossing voltage (abs) vx(abs) 250 366 550 mv 1 crossing voltage (var) d-vx variation of crossing over all edges 16 140 mv 1 long accuracy ppm see tperiod min-max values -100 0 100 ppm 1,2 100.00mhz nominal 9.9990 10.0000 10.0001 ns 2 100.00mhz spread 10.0240 10.0250 10.0251 ns 2 absolute min/max period t absmin/max 100.00mhz nominal/spread 9.9490 10.1011 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 376 700 ps 1,4 fall time t f v oh = 0.525v v ol = 0.175v 175 335 700 ps 1,4 rise time variation d-t r v ol = 0.175v, v oh = 0.525v 104 125 ps 1 fall time variation d-t f v oh = 0.525v v ol = 0.175v 92 125 ps 1 rise/fall matching t rfm single-ended measurement, averaging on 12.7 20 % 1 slew rate t slew differential measurment 1 2 4 v/ns 1,5 duty cycle d t3 measurement from differential wavefrom 45 49.8 55 % 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom, cpuclk 45 50 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? , i re f = 475 ? 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that 25mhz_x is tuned to exactly 25.000mhz 3 i re f = v dd /(3xr r ). for r r = 475 ? (1%), i re f = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . 4 rise/fall time measured on single-ended waveform per ck410 specification. 5 slew rate measured on differential waveform per ck505 specification. average period t period statistical measurement on single ended signal measurement on single ended signal using absolute value.
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 9 advance information electrical characteristics - dot96ss 0.7v current mode differential pair parameter symbol conditions* min typ max units notes current source output impedance zo v o = v x 3000 ? 1 voltage high vhigh 660 725 850 mv 1,3 voltage low vlow -150 51 150 mv 1,3 max voltage vovs 764 1150 mv 1 min voltage vuds -300 5 mv 1 crossing voltage (abs) vx(abs) 250 372 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all edges 140 mv 1 long accuracy ppm see tperiod min-max values -100 -41 100 ppm 1,2 96.00mhz nominal 10.4156 10.4166 10.4176 ns 2 96.00mhz -0.5% spread 10.4417 10.4427 10.4437 ns 2 absolute min period tabsmin 96.00mhz nominal/-0.5% spread 10.1917 10.6937 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 361 700 ps 1,4 fall time t f v oh = 0.525v v ol = 0.175v 175 375 700 ps 1,4 rise time variation d-t r v ol = 0.175v, v oh = 0.525v 107 125 ps 1 fall time variation d-t f v oh = 0.525v v ol = 0.175v 107 125 ps 1 rise/fall matching t rfm single-ended measurement, averaging on 15 20 % 1 slew rate t slew differential measurment 1 2 4 v/ns 1,5 duty cycle d t3 measurement from differential wavefrom 45 51.3 55 % 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 54 250 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? , i re f = 475 ? 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that 25mhz_x is tuned to exactly 25.000mhz 3 i re f = v dd /(3xr r ). for r r = 475 ? (1%), i re f = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . 4 rise/fall time measured on single-ended waveform per ck410 specification. 5 slew rate measured on differential waveform per ck505 specification. measurement on single ended signal using absolute value. statistical measurement on single ended signal average period tperiod electrical characteristics - ref - 25mhz parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -50 0 50 ppm 1,2 clock period t p eriod 25.00mhz output nominal 39.998 40.000 40.002 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 1.14 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 1.32 2 ns 1 skew t sk1 v t = 1.5 v 16 500 ps 1 duty cycle d t1 v t = 1.5 v 45 53.2 55 % 1 jitter, cycle-cycle t j c y c-c y c v t = 1.5 v 75 200 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs as shown in the termination table (unless otherwise specif ied) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that 25mhz_x is tuned to exactly 25.000mhz i ol output low current i oh output high current
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 10 advance information electrical characteristics - rgmii - 125mhz parameter symbol conditions* min typ max units notes long accuracy ppm see tperiod min-max values -50 0 50 ppm 1,2 clock period tperiod 125.00mhz output nominal 7.9996 8.000 8.0004 ns 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rise time t r v ol =20%xvdd, v oh =80%xvdd 0.66 0.75 ns 1 fall time t f v ol =20%xvdd, v oh =80%xvdd 0.70 0.75 ns 1 duty cycle d t1 v t = 1.5 v 45 52.9 55 % 1 group skew t skew rgmii v t = 1.5 v, 15 100 ps 1 jitter, long term t j abs v t = 1.5 v, 10 : sec interval 141 500 ps 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 75 250 ps 1 jitter, peak t jp eak v t = 1.5 v 68 100 ps 1,3 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs as shown in the termination table (unless otherwise specif ied) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that 25mhz_x is tuned to exactly 25.000mhz 3 1/2 of the peak-to-peak jitter. (lg+ + |lg-|)/2 i oh output low current i ol output high current electrical characteristics - rmii - 50mhz parameter symbol conditions* min typ max units notes long accuracy ppm see tperiod min-max values -50 0 50 ppm 1,2 clock period tperiod 50.00mhz output nominal 19.9990 20.0000 20.001 ns 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rise time t r v ol = 0.4 v, v oh = 2.4 v 1 1.1 3 ns 1 fall time t f v oh = 2.4 v, v ol = 0.4 v 1 1.1 3 ns 1 duty cycle d t1 v t = 1.5 v 35 51.5 65 % 1 group skew t skew_rmii(5:0) v t = 1.5 v, across all 6 outputs 60 200 ps 1 jitter, long term t j abs v t = 1.5 v, 10 8 sec interval 127 500 ps 1 jitter, peak t jp eak v t = 1.5 v 88 100 ps 1,3 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs as shown in the termination table (unless otherwise specif ied) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that 25mhz_x is tuned to exactly 25.000mhz 3 1/2 of the peak-to-peak jitter. (lg+ + |lg-|)/2 output high current i oh output low current i ol
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 11 advance information electrical characteristics - 33.33mhz parameter symbol conditions* min typ max units notes long accuracy ppm see tperiod min-max values -100 0 100 ppm 1 clock period tperiod 33.33mhz output non-spread 29.9970 30.0000 30.0030 ns 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rise time t r v ol = 0.4 v, v oh = 2.4 v 0.5 0.87 2 ns 1 fall time t f v oh = 2.4 v, v ol = 0.4 v 0.5 1.35 2 ns 1 duty cycle d t1 v t = 1.5 v 45 50.7 55 % 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 104 350 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs as shown in the termination table (unless otherwise specif ied) 1 guaranteed by design and characterization, not 100% tested in production. output high current i oh output low current i ol electrical characteristics - 32.768khz parameter symbol conditions* min typ max units notes long accuracy ppm see tperiod min-max values -100 -79 100 ppm 1 clock period tperiod 32.768khz output nominal 30.5149 30.5180 30.5211 us 1 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rise time t r v ol = 0.4 v, v oh = 2.4 v 1 1.39 4 ns 1 fall time t f v oh = 2.4 v, v ol = 0.4 v 1 1.6 4 ns 1 duty cycle d t1 v t = 1.5 v 45 49.5 55 % 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 220 500 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs as shown in the termination table (unless otherwise specif ied) 1 guaranteed by design and characterization, not 100% tested in production. output low current i ol output high current i oh
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 12 advance information general smbus serial interface information for the 9FGP205 how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the beginning byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address *d0 (h) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address *d1 (h) index block read operation slave address *d0 (h) beginning byte = n ack ack * by default, smbadr = 0, therefore, smbus write/read address is d0/d1. please see smbus address selection table on page 1.
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 13 advance information smbus table: cpu frequency select and spread spectrum control register b y te 0 name control function t yp e0 1 pwd bit 7 wol_stop_en enables 25m in power down rw disable enabled 1 bit 6 reserved reserved rw 0 bit 5 reserved reserved rw 0 bit 4 dot96 ss_en dot96 spread spectrum enable rw disable enable 0 bit 3 cpu ss_en cpu spread spectrum enable rw 0 bit 2 cpu fs2 cpu freq select bit 2 rw 1 bit 1 cpu fs1 cpu freq select bit 1 rw 0 bit 0 cpu fs0 cpu freq select bit 0 rw 1 smbus table: rmii output control register b y te 1 name control function t yp e0 1 pwd bit 7 rmii_5 enable rmii_7 output control rw disable enable 1 bit 6 rmii_4 enable rmii_6 output control rw disable enable 1 bit 5 rmii_3 enable rmii_5 output control rw disable enable 1 bit 4 rmii_2 enable rmii_4 output control rw disable enable 1 bit 3 rmii_1 enable rmii_3 output control rw disable enable 1 bit 2 rmii_0 enable rmii_2 output control rw disable enable 1 bit 1 rgmii_1 enable rgmii_1 output control rw disable enable 1 bit 0 rgmii_0 enable rgmii_0 output control rw disable enable 1 smbus table: dot, cpu, 32.768khz, 25mhz and 33.33mhz outputs control register b y te 2 name control function t yp e0 1 pwd bit 7 cpuclk pd drive mode driven in power down rw driven hi-z 1 bit 6 dot96ss pd drive mode driven in power down rw driven hi-z 1 bit 5 33.33mhz enable 33.33mhz output control rw disable enable 1 bit 4 25mhz_1 enable 25mhz_1 output control rw disable enable 1 bit 3 25mhz_0 enable 25mhz_0 output control rw disable enable 1 bit 2 32.768khz enable 32.768khz output control rw disable enable 1 bit 1 cpuclk enable cpuclk output control rw disable enable 1 bit 0 dot96ss enable dot96ss output control rw disable enable 1 smbus table: dot96 frequency select and spread spectrum control register b y te 3 name control function t yp e0 1 pwd bit 7 rmii_5 wol_stop rmii_5 runs in power down rw off runs 0 bit 6 rmii_4 wol_stop rmii_4 runs in power down rw off runs 0 bit 5 rmii_3 wol_stop rmii_3 runs in power down rw off runs 0 bit 4 rmii_2 wol_stop rmii_2 runs in power down rw off runs 1 bit 3 dot96ss fs3 dot96 freq select bit 3 rw 0 bit 2 dot96ss fs2 dot96 freq select bit 2 rw 0 bit 1 dot96ss fs1 dot96 freq select bit 1 rw 0 bit 0 dot96ss fs0 dot96 freq select bit 0 rw 0 smbus table: rmii strength control register b y te 4 name control function t yp e0 1 pwd bit 7 rmii_5 str rmii_5 strength control rw 1-load (1x) 2-loads (2x) 0 bit 6 rmii_4 str rmii_4 strength control rw 1-load (1x) 2-loads (2x) 0 bit 5 rmii_3 str rmii_3 strength control rw 1-load (1x) 2-loads (2x) 0 bit 4 rmii_2 str rmii_2 strength control rw 1-load (1x) 2-loads (2x) 0 bit 3 rmii_1 str rmii_1 strength control rw 1-load (1x) 2-loads (2x) 0 bit 2 rmii_0 str rmii_0 strength control rw 1-load (1x) 2-loads (2x) 0 bit 1 rmii_1 wol_stop rmii_1 runs in power down rw off runs 1 bit 0 rmii_0 wol stop rmii_0 runs in power down rw off runs 1 17 pin # 25 - - 37 7,8 24 3,4 22 32 33 - - - 16 - reserved - - - 24 36 28 29 - 28 29 13 25 6 5 - - 32 29 28 25 see table 2: dot frequency selection table 24 pin # reserved see table 1: cpu frequency selection table pin # pin # pin # 33 32 33
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 14 advance information smbus table: 32.768khz, 25mhz and 33.33mhz strength control register b y te 5 name control function t yp e0 1 pwd bit 7 reserved reserved rw reserved 0 bit 6 reserved reserved rw reserved 0 bit 5 33.33mhz str 33.33mhz strength control rw 1-load (1x) 2-loads (2x) 1 bit 4 25mhz_1 str 25mhz_1 strength control rw 1-load (1x) 2-loads (2x) 1 bit 3 25mhz_0 str 25mhz_1 strength control rw 1-load (1x) 2-loads (2x) 1 bit 2 32.768khz str 32.768khz strength control rw 1-load (1x) 2-loads (2x) 1 bit 1 25mhz_1_wol_stop 25mhz_1 runs in power down rw off runs 0 bit 0 25mhz_0_wol_stop 25mhz_0 runs in power down rw off runs 1 smbus table: vendor & revision id register b y te 6 name control function t yp e0 1 pwd bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device id b y te 7 name control function t yp e0 1 pwd bit 7 device id 7 (msb) r 0 bit 6 device id 6 r 0 bit 5 device id 5 r 1 bit 4 device id 4 r 0 bit 3 device id 3 r 0 bit 2 device id 2 r 1 bit 1 device id 1 r 0 bit 0 device id 0 (lsb) r 1 smbus table: byte count register b y te 8 name control function t yp e0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 1 bit 2 bc2 rw - - 0 bit 1 bc1 rw - - 0 bit 0 bc0 rw - - 1 smbus table: reserved b y te 9 name control function t yp e0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 ics/idt = 0001 a rev = 0000 b rev = 0001 reserved reserved pin # reserved reserved reserved reserved reserved reserved - - - - - vendor id - - - - - pin # pin # - - - - - reserved - writing to this register configures how many bytes will be read back. - - - - - - - device id reserved reserved reserved reserved reserved reserved reserved - - 22 17 16 13 pin # 17 16 pin # revision id -
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 15 advance information smbus table: plls m/n programming enable register b y te 10 name control function t yp e0 1 pwd bit 7 m/n_en plls m/n programming enable rw disable enable 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: cpu pll vco frequency control register b y te 11 name control function t yp e0 1 pwd bit 7 n div8 n divider prog bit 8 rw x bit 6 n div 9 n divider prog bit 9 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x smbus table: cpu pll vco frequency control register b y te 12 name control function t yp e0 1 pwd bit 7 n div7 rw x bit 6 n div6 rw x bit 5 n div5 rw x bit 4 n div4 rw x bit 3 n div3 rw x bit 2 n div2 rw x bit 1 n div1 rw x bit 0 n div0 rw x smbus table: cpu pll spread spectrum control register b y te 13 name control function t yp e0 1 pwd bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x smbus table: cpu pll spread spectrum control register b y te 14 name control function t yp e0 1 pwd bit 7 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x these spread spectrum bits in byte 13 and 14 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. reserved - - - m divider programming bits - - - pin # - pin # - - - spread spectrum programming b(7:0) - spread spectrum programming b(14:8) - pin # - - - - - these spread spectrum bits in byte 13 and 14 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. - - - - - pin # reserved reserved reserved reserved reserved - - - - - the decimal representation of m and n divier in byte 11 and 12 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 25 x [ndiv(9:0)+8] / [mdiv(5:0)+2] n divider programming b(7:0) the decimal representation of m and n divier in byte 11 and 12 will configure the vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = 25 x [ndiv(9:0)+8] / [mdiv(5:0)+2] reserved reserved pin # - - - - -
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 16 advance information smbus table: dot pll vco frequency control register b y te 15 name control function t yp e0 1 pwd bit 7 n div8 n divider prog bit 8 rw x bit 6 n div9 n divider prog bit 9 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x smbus table: dot pll vco frequency control register b y te 16 name control function t yp e0 1 pwd bit 7 n div7 rw x bit 6 n div6 rw x bit 5 n div5 rw x bit 4 n div4 rw x bit 3 n div3 rw x bit 2 n div2 rw x bit 1 n div1 rw x bit 0 n div0 rw x smbus table: dot pll spread spectrum control register b y te 17 name control function t yp e0 1 pwd bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x smbus table: dot pll spread spectrum control register b y te 18 name control function t yp e0 1 pwd bit 7 0 bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x bytes 19:21 are reserved. - spread spectrum programming b(14:8) these spread spectrum bits in byte 19 and 20 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. - - - - pin # reserved - - m divider programming bits - pin # - - - - - - pin # - - spread spectrum programming b(7:0) these spread spectrum bits in byte 19 and 20 will program the spread pecentage. it is recommended to use ics spread % table for spread programming. - - - - - - - - pin # - - - - - - - the decimal representation of m and n divier in byte 17 and 18 will configure the vco frequency. default at power up = byte 0 rom table. vco frequency = 25 x [ndiv(9:0)+8] / [mdiv(5:0)+2] n divider programming b(7:0) the decimal representation of m and n divier in byte 17 and 18 will configure the vco frequency. default at power up = byte 0 rom table. vco frequency = 25 x [ndiv(9:0)+8] / [mdiv(5:0)+2]
idt ? frequency timing generator for peripherals 1664?05/14/10 9FGP205 frequency timing generator for peripherals 17 advance information top view index area 1 e d sawn singulation anvil singulation o r a 0.08 c c a3 a1 seating plane e2 e2 2 l (n -1)x e (ref.) d (ref.) n&n even d e n e d2 2 d2 d e (ref.) n&n odd 1 2 e 2 (typ.) if n & n are even (n -1)x e (ref.) e e d b thermal base 2 n thermally enhanced, very thin, fine pitch quad flat / no lead plastic package dimensions symbol min. max. 40l a 0.8 1.0 symbol tolerance a1 0 0.05 n 40 40 a3 n d 1 0 1 0 b 0.1 8 0.3 n e 1 0 1 0 e d x e basic 6.00 x 6.00 6.00 x 6.00 d2 min. / max. 1.75 / 4.80 2.75 / 3.0 e2 min. / max. 1.75 / 4.80 2.75 / 3.0 l min. / max. 0.30 / 0.50 0.3 / 0.5 vjjd-2 / -5 dimensions 0.25 reference 0.50 basic (jedec reference only) (idt package) ordering information part / order number shipping packaging package temperature 9FGP205aklf trays 40-pin mlf 0 to +70 c 9FGP205aklft tape and reel 40-pin mlf 0 to +70 c ?lf? to the suffix are the pb-free configuration and are rohs compliant. ?a? is the device revision designator (will not correlate with the datasheet revision).
9FGP205 frequency timing generator for peripherals 18 advance information innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. issue date who description page # 0.1 4/13/2009 rdw initial release - 0.2 4/30/2010 rdw 1. changed name of pin 40 to ckpwrgd_wol_stop# to update description. no change in functionality. 2. added control bits to byte 3, 4, and 5 to select wol_stop# functionality for the 25m ref outputs and the 50m rmii outputs. note default settings. 3. updated table 1 (combined with table 2) 4. changed table 2 to reflect wol_stop function for pins 16, 29, 32, 33. 5. added wol_stop entry for power down current. 6. updated/corrected block dia g ram b y removin g oe_rmii pins. 0.3 5/3/2010 rdw 1. corrected error in truth table 2, added separate column for pin 22. 5 0.4 5/14/2010 rdw 1. cpu and dot 96 default power down mode changed from driven to hi-z to support wol_stop# mode. termination circuit will give low/low on those outputs in power down. byte 2, but 7 and 6 default changed to 1. 2. corrected byte 7 to be read only. 13, 14

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