View MT5HTF3272KY-40EC2_7493963.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

products and specifications discussed herein ar e subject to change by micron without notice. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm features pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_1.fm - rev. a 7/05 en 1 ?2004, 2005 micron technology, inc. all rights reserved. ddr2 sdram registered minidimm mt5htf1672(p)k ? 128mb mt5htf3272(p)k ? 256mb mt5htf6472(p)k ? 512mb for the latest data sheet, please refer to the micron ? web site: www.micron.com/products/modules features ? 244-pin, mini dual in-line memory module (minidimm) ? fast data transfer rates: pc2-3200, pc2-4200, or pc2-5300 ? supports ecc error detection and correction ? 128mb (16 meg x 72), 256mb (32 meg x 72) 512mb (64 meg x 72) ?v dd = v dd q = +1.8v ?v ddspd = +1.7v to +3.6v ? jedec standard 1.8v i/o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ? four-bit prefetch architecture ? dll to align dq and dqs transitions with ck ? multiple internal device banks for concurrent operation ? supports duplicate output strobe (rdqs/rdqs#) ? programmable cas# latency (cl) ? posted cas# additive latency (al) ? write latency = read latency - 1 t ck ? programmable burst lengths: 4 or 8 ? adjustable data-output drive strength ? 64ms, 8,192-cycle refresh ? on-die termination (odt) ? serial presence detect (spd) with eeprom ? gold edge contacts ? single rank figure 1: 244-pin dimm (mo-244 r/c ?a?) notes: 1. cl = cas (read) latency; registered mode will add one clock cycle to cl. 2. contact micron for product availability. options marking ?parity p ?package 244-pin dimm (lead-free) y ? frequency/cas latency 1 3ns @ cl = 4 (ddr2-667) 2 -667 3.75ns @ cl = 4 (ddr2-533) -53e 5.0ns @ cl = 3 (ddr2-400) -40e ?pcb height 1.18in. (29.97mm) hei g ht 1.18in. (29.97mm)
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_1.fm - rev. a 7/05 en 2 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm features notes: 1. all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: MT5HTF3272KY-40EC2 . table 1: address table 128mb 256mb 512mb refresh count 8k 8k 8k row addressing 8k (a0?a12) 16k (a0?a12) 16k (a0?a12) device bank addressing 4 (ba0, ba1) 4 (ba0, ba1) 8 (ba0, ba1, ba2) device page size per bank 1kb 1kb 1kb device configuration 256mb (16 meg x 16) 512mb (32 meg x 16) 1gb (64 meg x 16) column addressing 1k (a0?a8) 1k (a0?a9) 1k (a0?a9) module rank addressing 1 (s0#) 1 (s0#) 1 (s0#) table 2: key timing parameters speed grade data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 3 cl = 4 cl = 5 -667 ? 533 667 15 15 55 -53e 400 533 ? 15 15 55 -40e 400 400 ? 15 15 55 table 3: part numbers and timing parameters part number 1 module density configuration module bandwidth memory clock/ data rate latency (cl - t rcd - t rp) mt5htf1672(p)ky-667__ 128mb 16 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 mt5htf1672(p)ky-53e__ 128mb 16 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt5htf1672(p)ky-40e__ 128mb 16 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt5htf3272(p)ky-667__ 256mb 32 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 mt5htf3272(p)ky-53e__ 256mb 32 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt5htf3272(p)ky-40e__ 256mb 32 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt5htf6472(p)ky-667__ 512mb 64 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 mt5htf6472(p)ky-53e__ 512mb 64 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt5htf6472(p)ky-40e__ 512mb 64 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72ktoc.fm - rev. a 7/05 en 3 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 pin assignments and descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 pll and register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 serial presence-detect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 mode register (mr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 dll reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 write recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 cas latency (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 extended mode register (emr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 dll enable/disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 output drive strength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 dqs# enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 rdqs enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 output enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 on die termination (odt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 off-chip driver (ocd) impedance calibratio n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 posted cas additive latency (al) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 extended mode register 2 (emr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 extended mode register 3 (emr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 command truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 input electrical characteristics and operat ing conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 i dd 7 conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 ac operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 pll and register specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 serial presence-detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 spd clock and data conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 spd start condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 spd stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 spd acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 module dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 data sheet designation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72klof.fm - rev. a 7/05 en 4 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm list of figures list of figures figure 2: pin locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 4: ddr2 power-up and initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6: cas latency (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 8: read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 9: write latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 14: acknowledge response from receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 15: spd eeprom timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 16: 244-pin dimm ddr2 module dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72klot.fm - rev. a 7/05 en 5 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm list of tables list of tables table 1: address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: part numbers and timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 4: pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 5: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 6: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 7: commands truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 8: absolute maximum dc ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 9: recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 10: input dc logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 11: input ac logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 12: general i dd parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 13: i dd 7 timing patterns ? 128mb and 256mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 14: i dd 7 timing patterns ? 512mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 15: i dd specifications and conditions ? 128mb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 16: i dd specifications and conditions ? 256mb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 17: i dd specifications and conditions ? 512mb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 18: ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 19: register timing requir ements and switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 20: register electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 21: pll clock driver electrical charac teristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 22: pll clock driver timing requirements and switchin g characteristics . . . . . . . . . . . . . . . . . . .41 table 23: eeprom device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 24: eeprom operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 25: serial presence-detect eeprom dc operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 26: serial presence-detect eeprom ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 27: serial presence-detect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 6 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm pin assignments and descriptions pin assignments and descriptions note: pin 55 is nc for 128mb and 256mb or ba2 for 512mb. figure 2: pin locations table 4: pin assignments 244-pin minidimm front 244-pin mindimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ref 32 v ss 63 v dd q 94 dqs5# 123 v ss 154 dq28 185 a3 216 nc 2v ss 33 dq24 64 a2 95 dqs5 124 dq4 155 dq29 186 a1 217 v ss 3 dq0 34 dq25 65 v dd 96 v ss 125 dq5 156 v ss 187 v dd 218 dq46 4dq1 35 v ss 66 v ss 97 dq42 126 v ss 157 dm3 188 ck0 219 dq47 5v ss 36 dqs3# 67 v ss 98 dq43 127 dm0 158 nc 189 ck0# 220 v ss 6 dqs0# 37 dqs3 68 p ar _i n 99 v ss 128 nc 159 v ss 190 v dd 221 dq52 7dqs038 v ss 69 v dd 100 dq48 129 v ss 160 dq30 191 a0 222 dq53 8v ss 39 dq26 70 a10 /ap 101 dq49 130 dq6 161 dq31 192 ba1 223 v ss 9 dq2 40 dq27 71 ba0 102 v ss 131 dq7 162 v ss 193 v dd 224 rfu 10 dq3 41 v ss 72 v dd 103 sa2 132 v ss 163 cb4 194 ras# 225 rfu 11 v ss 42 cb0 73 we# 104 nc (test) 133 dq12 164 cb5 195 v dd q226 v ss 12 dq8 43 cb1 74 v dd q105 v ss 134 dq13 165 v ss 196 s0# 227 dm6 13 dq9 44 v ss 75 cas# 106 dqs6# 135 v ss 166 dm8 197 v dd q228 nc 14 v ss 45 dqs8# 76 v dd q 107 dqs6 136 dm1 167 nc 198 odt0 229 v ss 15 dqs1# 46 dqs8 77 nc 108 v ss 137 nc 168 v ss 199 nc/ a13 230 dq54 16 dqs1 47 v ss 78 nc 109 dq50 138 v ss 169 cb6 200 v dd 231 dq55 17 vss 48 cb2 79 v dd q 110 dq51 139 rfu 170 cb7 201 nc 232 v ss 18 reset# 49 cb3 80 nc 111 v ss 140 rfu 171 v ss 202 v ss 233 dq60 19 nc 50 v ss 81 v ss 112 dq56 141 v ss 172 nc 203 dq36 234 dq61 20 v ss 51 nc 82 dq32 113 dq57 142 dq14 173 v dd q 204 dq37 235 v ss 21 dq10 52 v dd q 83 dq33 114 v ss 143 dq15 174 nc, cke1 205 v ss 236 dm7 22 dq11 53 cke0 84 v ss 115 dqs7# 144 v ss 175 v dd 206 dm4 237 nc 23 v ss 54 v dd 85 dqs4# 116 dqs7 145 dq20 176 nc 207 nc 238 v ss 24 dq16 55 nc 86 dqs4 117 v ss 146 dq21 177 nc 208 v ss 239 dq62 25 dq17 56 e rr _o ut 87 v ss 118 dq58 147 v ss 178 v dd q 209 dq38 240 dq63 26 v ss 57 v dd q 88 dq34 119 dq59 148 dm2 179 a12 210 dq39 241 v ss 27 dqs2# 58 a11 89 dq35 120 v ss 149 nc 180 a9 211 v ss 242 sda 28 dqs2 59 a7 90 v ss 121 sa0 150 v ss 181 v dd 212 dq44 243 scl 29 v ss 60 v dd 91 dq40 122 sa1 151 dq22 182 a8 213 dq45 244 v ddspd 30 dq18 61 a5 92 dq41 152 dq23 183 a6 214 v ss 31 dq19 62 a4 93 v ss 153 v ss 184 v dd q 215 dm5 pin 123 pin 187 pin 188 pin 244 pin 1 pin 65 pin 66 pin 122 indicates a v dd or v ddq pin indicates a v ss pin front view back view u1 u2 u3 u4 u6 u7 u8 u5 no dram devices this side of module
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 7 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm pin assignments and descriptions table 5: pin descriptions pin numbers may not correlat e with symbols; refer to pin assignmen t tables on page 6 for more information pin numbers symbol type description 198 odt0 input on-die termination: odt (regis tered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is only applied to each of the following pins: dq, dqs, dqs#, rdqs, rdqs#, cb, and dm. the odt input will be ignored if disabled via the load mode command. 188, 189 ck0, ck0# input clock: ck and ck# are differenti al clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dqs and dqs/dqs#) is referenced to the crossings of ck and ck#. 53 cke0 input clock enable: cke (registered high) activates and cke (registered low) deactivates cl ocking circuitry on the ddr2 sdram. the specific circuitry that is enabled/disabled is dependent on the ddr2 sdram configuration and operating mode. cke low provides prec harge power-down and self refresh operations (all device banks idle), or active power- down (row active in any device bank). cke is synchronous for power-down entry, power-down exit, output disable, and for self refresh entry. cke is asynchronous fo r self refresh exit. input buffers (excluding ck, ck#, cke, and odt) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_18 input but will detect a lvcmos low level once v dd is applied during first power-up. after vref has become stable during the power on and initialization sequence, it mu st be maintained for proper operation of the cke receiver. for proper self-refresh operation v ref must be maintained to this input. 196 s0# input chip select: s# enables (registere d low) and disables (registered high) the command decoder. al l commands are masked when s# is registered high. s# provides for external ra nk selection on systems with multiple ranks. s# is considered part of the command code. 73, 75, 194 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 55 (512mb) , 71, 192 ba0, ba1, ba2 (512mb) input bank address inputs: ba0?ba1/ba2 define to which device bank an active, read, write, or precharge command is being applied. ba0?ba1 define which mode register including mr, emr, emr(2), and emr(3) is loaded during the load mode command. 58, 59, 61, 62, 64, 70, 179, 179, 180, 182, 183, 191 a0?a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/ write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether th e precharge applies to one device bank (a10 low, device bank selected by ba0?ba1/ba2) or all device banks (a10 high). the address inpu ts also provide the op-code during a load mode command.
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 8 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm pin assignments and descriptions 3, 4, 9, 10, 12, 13, 21, 22, 24, 25, 30, 31, 33, 34, 39, 40, 82, 83, 88, 89, 91, 92, 97, 98, 100, 101, 109, 110, 112, 113, 118, 119, 124, 125, 130, 131, 133, 134, 142, 143, 145, 146, 151, 152, 154, 155, 160, 161, 203, 204, 209, 210, 212, 213, 218, 219, 221, 222, 230, 231, 233, 234, 239, 240 dq0?dq63 i/o data input/output: bidirectional data bus. 6, 7, 15, 16, 27, 28, 36, 37, 45, 46, 85, 86, 94, 95, 106, 107, 115, 116 dqs0?dqs8 i/o data strobe: output with read data, input with write data for source synchronous operation. edge-aligned with read data, center aligned with write data . dqs# is only used when differential data strobe mode is enabled via the load mode command. 127, 136, 148, 157, 166, 206, 215, 227, 236 dm0?dm8 i/o input data mask: dm is an input mask signal for write data. input data is masked when dm is samp led high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading is designed to match that of dq and dqs pins. if rdqs is disabled, dqs0?dqs17 become dm0?dm8 and dqs9#?dqs17# are not used. 42, 43, 48, 49, 163, 164, 169, 170 cb0?cb7 i/o check bits. 68 p ar _i n input parity bit for the address and control bus. 56 e rr _o ut output parity error found on th e address and control bus. 243 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfe r to and from the module. 103, 121, 122 sa0?sa2 input presence-detect address inputs: th ese pins are used to configure the presence-detect device. 242 sda i/o serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. 18 reset# input asynchronously forces all regi stered outputs low when reset# is low. this signal can be used during power up to ensure that cke is low and dqs are high-z. 54, 60, 65, 69, 72, 175, 181, 187, 190, 193, 200 v dd supply power supply: 1.8v 0.1v. 52, 57, 63, 74, 76, 79, 173, 178, 184, 195, 197 v dd q supply dq power supply: 1.8v 0.1v. 1v ref supply sstl_18 refere nce voltage. 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 66, 67, 81, 84, 87, 90, 93, 96, 99, 102, 105, 108, 111, 114, 117, 120, 123, 126, 129, 132, 135, 138, 141, 144, 147, 150, 153, 156, 159, 162, 165, 168, 171, 202, 205, 208, 211, 214, 217, 220, 223, 226, 229, 232, 235, 238, 241 v ss supply ground. table 5: pin descriptions pin numbers may not correlat e with symbols; refer to pin assignmen t tables on page 6 for more information pin numbers symbol type description
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 9 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm pin assignments and descriptions 244 v ddspd supply serial eeprom positive po wer supply: +1.7v to +3.6v. 51, 55 (128mb, 256mb), 77, 78, 80, 104, 128, 137, 149, 158, 167, 172, 174, 176, 177, 199, 201, 207, 216, 228, 237128mb nc ? no connect: these pins should be left unconnected. 139, 140, 224, 225 rfu ? reserved for future use. table 5: pin descriptions pin numbers may not correlat e with symbols; refer to pin assignmen t tables on page 6 for more information pin numbers symbol type description
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 10 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm functional block diagram functional block diagram unless otherwise noted, resistor values are 22 . micron module part numbers are explained in the module part numbering guide at www.micron.com/support/number- ing.html . modules use the following ddr2 sd ram devices: mt47h16m16bt (256mb); mt47h32m16bt (512mb); mt47h64m16bt (1gb). figure 3: functional block diagram a0 s erial pd a1 a2 s a0 s a1 s a2 s da sc l wp r e g i s t e r pll u5 par_in s 0# ba0-ba1/ba2 a0-a12 ra s # c a s # we# c ke0 odt0 re s et# c k c k# err_out r s 0#: ddr2 s drams rba0-rba1/rba2: ddr2 s drams ra0-ra12: ddr2 s drams rra s #: ddr2 s drams r c a s #: ddr2 s drams rwe#: ddr2 s drams r c ke0: ddr2 s drams rodt0: ddr2 s drams c k0 c k0# 120 ddr2 s dram ddr2 s dram ddr2 s dram ddr2 s dram ddr2 s dram re g i s ter re s et# u 6 u4 v ref v ss ddr2 s dram s ddr2 s dram s v dd ddr2 s dram s v dd s pd s erial pd v ddq ddr2 s dram s dq0 dq1 dq2 dq3 dq4 dq5 dq 6 dq7 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq3 6 dq37 dq38 dq39 r s 0# dq s 0 dq s 0# dm0/dq s 9 dq s 4 dq s 4# dm4/dq s 13 dq s 1 dq s 1# dm1/dq s 10 dq s 5 dq s 5# dm5/dq s 14 dq s 2 dq s 2# dm2/dq s 11 dq s6 dq s6 # dm 6 /dq s 15 dq s 3 dq s 3# dm3/dq s 12 dq s 7 dq s 7# dm7/dq s 1 6 dq s 8 dq s 8# dm8/dq s 17 dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq4 6 dq47 dq dq dq dq dq dq dq dq dq1 6 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq dq dq dq dq dq dq dq dq24 dq25 dq2 6 dq27 dq28 dq29 dq30 dq31 dq dq dq dq dq dq dq dq dq5 6 dq57 dq58 dq59 dq 6 0 dq 6 1 dq 6 2 dq 6 3 dq dq dq dq dq dq dq dq c b0 c b1 c b2 c b3 c b4 c b5 c b 6 c b7 dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq cs # cs # cs # cs # cs # ldq s ldq s # ldm udq s udq s # udm ldq s ldq s # ldm ldq s ldq s # ldm ldq s ldq s # ldm ldq s ldq s # ldm udq s udq s # udm udq s udq s # udm udq s udq s # udm udq s udq s # udm v dd u1 u2 u7 u8 u3
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 11 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm general description general description the mt5htf1672(p)k, mt5htf3272(p)k, and mt5htf6472(p)k ddr2 sdram mod- ules are high-speed, cmos, dynamic rand om-access 128mb, 256mb, and 512mb mem- ory modules organized in x72 configuratio n. ddr2 sdram modules use internally configured quad-bank (128mb, 256mb) or eight-bank (512mb) ddr2 sdram devices. ddr2 sdram modules use double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially a 4 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr2 sdram module effectively consists of a single 4 n -bit- wide, one-clock-cycle data transfer at the internal dram core and four corresponding n -bit-wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram device during reads and by the memory controller during writes. dqs is edge- aligned with data for reads and center-aligned with data for writes. ddr2 sdram modules operate fr om a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. com- mands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to ddr2 sdram module s are burst-oriented; accesses start at a selected location and continue for a prog rammed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the de vice bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the device bank and the starting column location for the burst access. ddr2 sdram modules provide for programmable read or write burst lengths of four or eight locations. ddr2 sdram devices support interrupting a burst read of eight with another read, or a burst write of eight with another write. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. the pipelined, multibank architecture of ddr2 sdram devices al lows for concurrent operation, thereby providing high, effectiv e bandwidth by hiding row precharge and activation time. a self refresh mode is provided, along with a power-saving power-down mode. all inputs are compatible with the jedec st andard for sstl_18. all full drive-strength outputs are sstl_ 18-compatible. pll and register operation ddr2 sdram modules operate in registered mode, where the command/address input signals are latched in the registers on the ri sing clock edge and sent to the ddr2 sdram devices on the following rising clock edge (data access is delayed by one clock cycle). a phase-lock loop (pll) on the module receives and redrives the differential clock signals (ck, ck#) to the ddr2 sdram devices. the registers and pll minimize system and clock loading. registered mode will add one clock cycle to cl.
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 12 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm serial presence-detect operation serial presence-detect operation ddr2 sdram modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage de vice contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of stor- age are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signal s, together with sa (2:0), which provide eight unique dimm/eeprom addresses. write protect (wp) is tied to ground on the module, permanently disabling hardware write protect. initialization the following sequence is required for power-up and initialization and is shown in figure 4, ddr2 power-up and initialization, on page 13. 1. apply power; if cke is maintained below 20 percent of v dd q, outputs remain dis- abled. to guarantee r tt (odt resistance) is off, v ref must be valid and low must be applied to the odt pin (all other inputs may be undefined). the time from when v dd first starts to power up to the completion of v dd q must be equal to or less than 20ms. at least one of the following two sets of conditions (a or b) must be met: a. v dd , v dd l and v dd q are driven from a single power converter output ?v tt is limited to 0.95v max ?v ref tracks v dd q/2 b. apply v dd before or at the same time as v dd l. ? apply v dd l before or at the same time as v dd q ? apply v dd q before or at the same time as v tt and v ref 3. the voltage difference between any v dd supply can not exceed 0.3v. for a minimum of 200 s after stable power and clock (ck, ck#), apply nop or deselect commands and take cke high 4. wait a minimum of 400ns, then issue a precharge all command. 5. issue a load mode command to the emr(2) register. (to issue an emr(2) com- mand, provide low to ba0 and ba2, provide high to ba1.) 6. issue a load mode command to the emr(3) register. (to issue an emr(3) com- mand, provide high to ba0 and ba1, provide low to ba2.) 7. issue a load mode command to the emr register to enable dll. to issue a dll enable command, provide low to ba1, ba2, and a0, provide high to ba0. bits e7, e8, and e9 must all be set to 0. 8. issue a load mode command for dll reset. 200 cycles of clock input is required to lock the dll. (to issue a dll reset, provid e high to a8 and provide low to ba2, ba1 and ba0.) cke must be high the entire time. 9. issue precharge all command. 10. issue two or more refresh commands. 11. issue a load mode command with low to a8 to initialize device operation (i.e., to program operating parameters without resetting the dll). 12. issue a load mode command to the emr to enable ocd default by setting bits e7, e8, and e9 to 1 and set all other desired parameters. 13. issue a load mode command to the emr to enable ocd exit by setting bits e7, e8, and e9 to 0 and set all other desired parameters. the ddr2 sdram device is now intialized and ready for normal operation 200 clocks after dll reset in step 8.
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 13 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm initialization figure 4: ddr2 power-up and initialization notes: 1. v tt is not applied directly to the device; however, t vtd should be greater than or equal to zero to avoid device latch-up. the time from when v dd first starts to power-up to the completion of v dd q must be equal to or less than 20ms. one of the following two conditions (a or b) must be met: a. v dd , v dd l, and v dd q are driven from a single power converter output. v tt may be 0.95v maximum during power up. v ref tracks v dd q/2. b. apply v dd before or at the same time as v dd l. apply v dd l before or at the same time as v dd q. apply v dd q before or at the same time as v tt and v ref . the voltage difference between any v dd supply can not exceed 0.3v. 2. either a nop or deselect command may be applied. 3. 200 cycles of clock (ck, ck#) are requir ed before a read command can be issued. cke must be high the entire time. 4. two or more refresh commands are required. 5. bits e7, e8, and e9 must all be set to 0 with all other operating parameters of emrs set as required. 6. pre = precharge command, lm = load mode command, re f = refresh command, act = active command, ra = row address, ba = bank address. 7. dm represents all dm. dqs represents all dqs, dqs#, rdqs,and rdqs# (rdqs/rdqs# only functional on rdimms using x8 co mponents). dq represents all dq. 8. cke pin uses lvcmos input levels prior to state t0. after state t0, cke pin uses sstl_18 input levels. 9. a10 should be high at states tb0 and tg0 to ensure a precha rge (all banks) command is issued. 10. bits e7, e8, and e9 must be set to 1 to set ocd default. 11. bits e7, e8, and e9 must be set to 0 to set ocd exit and all other operating parameters of emrs set as required. t vtd 1 c ke rtt power-up: v dd an d sta b le c lo c k ( c k, c k#) t = 200s (min) hi g h-z dm 7 dq s 7 hi g h-z addre ss 9 c k c k# t c l v tt 1 v ref v ddl v dd q c ommand nop 2 pre t0 ta0 don?t c are t c l t c k v dd odt dq 7 hi g h-z t = 400ns (min) t b 0 200 c y c les of c k 3 emr with dll ena b le 5 mr with dll reset t mrd t mrd tt rf c t rf c lm pre lm ref ref lm t g 0 th0 ti0 tj0 mr w/o dll reset emr with o c d default 10 t mrd t mrd t mrd tk0 tl0 tm0 te0 tf0 emr(2) emr(3) t mrd t mrd lm lm a10 = 1 t rpa t c 0t d 0 lv c mo s low level 8 ss tl_18 low level 8 valid 3 valid in d i c ates a b reak in time s c ale rpa lm emr with o c d exit 11 lm normal operation see note 4 see note 3 c ode c ode a10 = 1 c ode c ode c ode c ode c ode
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 14 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm mode register (mr) mode register (mr) the mode register is used to define the specific mode of operation of the ddr2 sdram device. this definition includes the selection of a burst length, bu rst type, cas latency, operating mode, dll reset, write recovery, and power-down mode as shown in figure 5, mode register (mr) definition. contents of the mode register can be altered by re-exe- cuting the load mode (lm) command. if the user chooses to modify only a subset of the mr variables, all variables (m0?m14) must be programmed when the load mode command is issued. the mode register is programmed via the lm command (bits ba0?ba1/ba2 all = 0) and other bits (m0?m13 or will retain the stored information until it is programmed again or the device loses power (except for bit m8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. the load mode command can only be issued (or reissued) when all banks are in the precharged state. the controller must wait the specified time t mrd before initiating any subsequent operations such as an active command. violating either of these require- ments will result in unspecified operation. burst length burst length is defined by bits m0?m2 as sh own in figure 5, mode register (mr) defini- tion. read and write accesses to the ddr2 sdram device are burst-oriented, with the burst length being programmable to either fo ur or eight. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses fo r that burst take place within this block, meaning that the burst will wrap within the bl ock if a boundary is reached. the block is uniquely selected by a2?a i when the burst length is set to four and by a3?a i when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least si gnificant) address bit(s) is (are) used to select the starting location within the bl ock. the programmed burs t length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved. the burst type is selected via bit m3 as shown in figure 5, mode register (mr) defini- tion. the ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address as shown in table 6, burst definition, on page 16. ddr2 sdram devices support 4-bit burst and 8-bit burst modes only. for 8-bit burst mode, full interleave address ordering is supported; however, sequential address order- ing is nibble-based.
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 15 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm mode register (mr) figure 5: mode register (mr) definition note: a13 is not used in x16-configured compon ents, so is not applic able for this module. burst length cas# latency bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 14 dll tm wr mr burst length cas# latency bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 15 dll tm wr a13 mr 128mb address bus 256mb address bus burst length cas# latency bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 burst length reserved reserved 4 8 reserved reserved reserved reserved m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 0 1 burst type sequential interleaved m3 cas latency reserved reserved reserved 3 4 5 reserved reserved m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 0 1 mode normal test m7 15 dll tm 0 1 dll reset no yes m8 write recovery reserved 2 3 4 5 6 reserved reserved m9 0 1 0 1 0 1 0 1 m10 0 0 1 1 0 0 1 1 m11 0 0 0 0 1 1 1 1 wr a13 mr 0 1 0 1 mode register definition mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) m15 0 0 1 1 0 1 pd mode fast exit (normal) slow exit (low power) m12 m14 ba2 16 0* 512mb address bus
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 16 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm mode register (mr) operating mode the normal operating mode is selected by issuing a load mode command with bit m7 set to zero, and all other bits set to the desired values as shown in figure 5, mode register (mr) definition, on page 15. when bit m7 is ?1 ,? no other bits of the mode register are programmed. programming bit m7 to ?1? pl aces the ddr2 sdram device into a test mode that is only used by the manufacturer and should not be used. no operation or functionality is guaranteed if m7 bit is ?1.? dll reset dll reset is defined by bit m8 as shown in figure 5, mode register (mr) definition, on page 15. programming bit m8 to ?1? will activate the dll reset function. bit m8 is self- clearing, meaning it returns back to a value of ?0? after the dll reset function has been issued. anytime the dll reset function is used, 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchroniz ation to occur may result in a violation of the t ac or t dqsck parameters. write recovery write recovery (wr) time is defined by bits m9?m11 as shown in figure 5, mode register (mr) definition, on page 15. the wr register is used by the ddr2 sdram device during write with auto precharge operation. during write with auto precharge operation, the ddr2 sdram device delays the internal auto precharge operation by wr clocks (programmed in bits m9?m11) from the last data burst. write recovery (wr) values of 2, 3, 4, 5, or 6 clocks may be used for programming bits m9?m11. the user is required to program the value of write recovery, which is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up a noninteger value to the next integer; wr [cycles] = t wr [ns] / t ck [ns]. reserved states should not be used as unknown operation or incompatibility with future versions may result. table 6: burst definition burst length starting column address (a2, a1, a0) order of accesses within a burst burst type = sequential burst type = interleaved 4 0 0 0 0,1,2,3 0,1,2,3 0 0 1 1,2,3,0 1,0,3,2 0 1 0 2,3,0,1 2,3,0,1 0 1 1 3,0,1,2 3,2,1,0 8 0 0 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 0 0 1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6 0 1 0 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5 0 1 1 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 1 0 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 1 0 1 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2 1 1 0 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1 1 1 1 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 17 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm mode register (mr) power-down mode active power-down (pd) mode is defined by bit m12 as shown in figure 5, mode register (mr) definition, on page 15. pd mode allows the user to determine the active power- down mode, which determines performance vs. power savings. pd mode bit m12 does not apply to precharge power-down mode. when bit m12 = 0, standard active power-down mode or ?fast-exit? active power-down mode is enabled. the t xard parameter is used for ?fast-exit? active power-down exit timing. the dll is expected to be enabled and running during this mode. when bit m12 = 1, a lower power active power-down mode or ?slow-exit? active power- down mode is enabled. the t xards parameter is used for ?slow-exit? active power-down exit timing. the dll can be enabled, but ?frozen? during active power-down mode since the exit-to-read command timing is relaxed. the power difference expected between pd ?normal? and pd ?low-power? mode is defined in the i dd table. cas latency (cl) the cas latency (cl) is defined by bits m4?m6 as shown in figure 5, mode register (mr) definition, on page 15. cas latency is the delay, in clock cycles, between the registration of a read command and the availability of th e first bit of output data. the cas latency can be set to 3, 4, or 5 clocks. cas latency of 6 clocks is a jedec optional features and may be enabled in future speed grades. ddr2 sdram devices do not support any half clock latencies. reserved states should not be used as unknown operation or incompat- ibility with future versions may result. ddr2 sdram devices also support a feature called posted cas additive latency (al). this feature allows the read command to be issued prior to t rcd(min) by delaying the internal command to the ddr2 sdram device by al clocks. the al feature is described in more detail in the extended mode register (emr) and operational sections. examples of cl = 3 and cl = 4 are shown in figure 6, cas latency (cl); both assume al = 0. if a read command is registered at clock edge n , and the cas latency is m clocks, the data will be available nominally coincident with clock edge n + m (this assumes al = 0).
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 18 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm mode register (mr) figure 6: cas latency (cl) d out n + 3 d out n + 2 d out n + 1 ck ck# command dq dqs, dqs# cl = 3 (al = 0) read burst length = 4 posted cas# additive latency (al) = 0 shown with nominal t ac, t dqsck, and t dqsq t0 t1 t2 don?t care transitioning data nop nop nop d out n t3 t4 t5 nop nop t6 nop d out n + 3 d out n + 2 d out n + 1 ck ck# command dq dqs, dqs# cl = 4 (al = 0) read t0 t1 t2 nop nop nop d out n t3 t4 t5 nop nop t6 nop
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 19 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm extended mode register (emr) extended mode register (emr) the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable, output drive strength, odt (r tt ), posted cas additive latency (al), off- chip driver impedance calibration (ocd), dqs# enable/disable, rdqs/rdqs# enable/disable, and output disable/enable. these functions are controlled via the bits shown in figure 7, extended mode register definition. the extended mode register is programmed via the load mode (lm) com- mand and will retain the stored information until it is programmed again or the device loses power. reprogramming the extended mode register will not alter the contents of the memory array, provided it is performed correctly. the extended mode register must be loaded wh en all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any sub- sequent operation. violating either of these requirements could result in unspecified operation. dll enable/disable the dll may be enabled or disabled by programming bit e0 during the load mode command as shown in figure 7, extended mode register definition. the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation afte r having disabled the dll for the purpose of debugging or evaluation. enabling the dll should always be followed by resetting the dll using a load mode command. the dll is automatically disabled when enteri ng self refresh operation and is automati- cally re-enabled and reset upon exit of self refresh operation. any time the dll is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to al low time for the internal clock to be syn- chronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t ac or t dqsck parameters. output drive strength the output drive strength is defined by bit e1 as shown in figure 7, extended mode reg- ister definition. the normal drive strength fo r all outputs are specified to be sstl_18. programming bit e1 = 0 selects normal (100 percent) drive strength for all outputs. selecting a reduced drive strength option (bit e1 = 1) will reduce all outputs to approxi- mately 60 percent of the sstl_18 drive strength. this option is intended for the support of the lighter load and/or point-to-point environments.
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 20 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm output drive strength figure 7: extended mode register definition note: a13 is not used in x16-configured compon ents, so is not applic able for this module. dll posted cas# r tt out a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 14 ocd program ods r tt dqs# rdqs emr dll posted cas# rtt out a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 15 ocd program a13 ods rtt dqs# rdqs emr 128mb address bus 256mb address bus dll posted cas# rtt out a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 0 1 output drive strength standard low power e1 posted cas# additive latency (al) 0 1 2 3 4 reserved reserved reserved e3 0 1 0 1 0 1 0 1 e4 0 0 1 1 0 0 1 1 e5 0 0 0 0 1 1 1 1 0 1 dll enable enable (normal) disable (test/debug) e0 15 0 1 rdqs enable disable reserved e11 ocd program a13 ods rtt dqs# 0 1 dqs# enable enable disable e10 rdqs rtt (nominal) rtt disabled 75 150 50 e2 0 1 0 1 e6 0 0 1 1 0 1 outputs enabled disabled e12 0 1 0 1 mode register set mode register set (mrs) extended mode register (emrs) extended mode register (emrs2) extended mode register (emrs3) e15 0 0 1 1 e14 mrs ba2 16 0* ocd operation ocd not supported reserved reserved reserved reserved e7 0 1 0 0 1 e8 0 0 1 0 1 e9 0 0 0 1 1 512mb address bus
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 21 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm dqs# enable/disable dqs# enable/disable the dqs# enable function is defined by bit e10. when enabled (bit e10 = 0), dqs# is the complement of the differential data strobe pa ir dqs/dqs#. when disabled (bit e10 = 1), dqs is used in a single-ended mode and the dqs# pin is disabled. this function is also used to enable/disable rdqs#. if rdqs is enabled (e11 = 1) and dqs# is enabled (e10 = 0), then both dqs# and rdqs# will be en abled. rdqs/rdqs# is supported only on rdimms using x8 ddr2 sdram devices. rdqs enable/disable rdqs/rdqs# is supported only on rdimms using x8 ddr2 sdram devices. the rdqs enable function is defined by bit e11 as sh own in figure 7, extended mode register defi- nition, on page 20. when enabled (e11 = 1), rd qs is identical in function and timing to data strobe dqs during a read. during a write operation, rdqs is ignored by the ddr2 sdram device. output enable/disable the output enable function is defined by bi t e12 as shown in figure 7, extended mode register definition, on page 20. when enable d (e12 = 0), all outputs (dqs, dqs, dqs#, rdqs, rdqs#) function normally. when di sabled (e12 = 1), all ddr2 sdram device outputs (dqs, dqs, dqs#, rdqs, rdqs#) are di sabled removing output buffer current. the output disable feature is intended to be used during i dd characterization of read current. on die termination (odt) odt effective resistance r tt ( eff ) is defined by bits e2 and e6 of the emr as shown in figure 7, extended mode register definition , on page 20. the odt feature is designed to improve signal integrity of the memory ch annel by allowing the ddr2 sdram device controller to independently turn on/off odt for any or all devices. r tt effective resis- tance values of 75 and 150 are selectable and apply to each dq, dqs/dqs#, rdqs/ rdqs#, and dm signals. additionally, the -667 speed modules offer a third option of 50 . reserved states should not be used, as unknown operation or incompatibility with future versions may result. the odt control pin is used to determine when r tt ( eff ) is turned on and off, assuming odt has been enabled via bits e2 and e6 of the emr. the odt feature and odt input pin are only used during active, active powe r-down (both fast-exit and slow-exit modes), and precharge power-down modes of operation. if self refresh operation is used, r tt ( eff ) should always be disabled and the odt input pin is disabled by the ddr2 sdram device. during power-up and initialization of the ddr2 sdram device, odt should be disabled until the emr command is issued to enable the odt feature, at which point the odt pin will determine the r tt ( eff ) value. refer to the 256mb, 512mb, or 1gb ddr2 sdram discrete data sheet for odt timing diagrams.
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 22 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm off-chip driver (ocd) impedance calibration off-chip driver (ocd) impedance calibration the ocd function is not supported and must be set to the default state. see ?initializa- tion? on page 12, to properly set ocd defaults. posted cas additi ve latency (al) posted cas additive latency (al) is supported to make the command and data bus effi- cient for sustainable bandwidths in ddr2 sdra m device. bits e3?e5 define the value of al as shown in figure 7, extended mode register definition, on page 20. bits e3?e5 allow the user to program the ddr2 sdram device with a cas# additive latency of 0, 1, 2, 3, or 4 clocks. reserved states should not be used as unknown operation or incompat- ibility with future versions may result. in this operation, the ddr2 sdram device allows a read or write command to be issued prior to t rcd (min) with the requirement that al t rcd(min). a typical appli- cation using this feature would set al = t rcd (min) - 1 x t ck. the read or write com- mand is held for the time of the additive latenc y (al) before it is issued internally to the ddr2 sdram device. read latency (rl) is controlled by the sum of the posted cas additive latency (al) and cas latency (cl); rl = al + cl. write latency (wl) is equal to read latency minus one clock; wl = al + cl - 1 x t ck. an example of a read latency is shown in figure 8, read latency. an example of a write latency is shown in figure 9, write latency. figure 8: read latency figure 9: write latency d out n + 3 d out n + 2 d out n + 1 c k c k# c ommand dq dq s , dq s # al = 2 a c tive n burst len g th = 4 s hown with nominal t a c , t dq sc k, an d t dq s q t0 t1 t2 don?t c are tran s itionin g data read n nop nop d out n t3 t4 t5 nop t 6 nop t7 t8 nop nop c l = 3 rl = 5 c a s # laten c y ( c l) = 3 a dd itive laten c y (al) = 2 read laten c y (rl) = al + c l = 5 t r c d (min) nop ck ck# command dq dqs, dqs# active n burst length = 4 t0 t1 t2 don ? t care transitioning data nop nop t3 t4 t5 nop write n t6 nop d in n + 3 d in n + 2 d in n + 1 wl = al + cl - 1 = 4 t7 nop d in n cas# latency (cl) = 3 additive latency (al) = 2 write latency = al + cl -1 = 4 t rcd (min) nop al = 2 cl - 1 = 2
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 23 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm extended mode register 2 (emr2) extended mode register 2 (emr2) the extended mode register 2 (emr2) contro ls functions beyond those controlled by the mode register. currently all bits in emr2 are reserved as shown in figure 10, extended mode register 2 (e mr2) definition. the emr2 is programmed via the load mode command and will retain the stored information until it is programmed again or the device loses power. reprogramming the extended mode regist er will not alter the contents of the memory array, provided it is performed correctly. the extended mode register must be loaded wh en all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any sub- sequent operation. violating either of thes e requirements could result in unspecified operation. figure 10: extended mode register 2 (emr2) definition note: a13 is not used in x16-configured compon ents, so is not applic able for this module. a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 * e12 (a12)?e0 (a0) are reserved for future use and must all be programmed to '0.' 14 emr(2) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 15 a13 emr2 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 128mb address bus 256mb address bus a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 15 a13 0 1 0 1 mode register set mode register set (mrs) extended mode register (emrs) extended mode register (emrs2) extended mode register (emrs3) m15 0 0 1 1 m14 mrs 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* ba2 16 0* 512mb address bus * e13 (a13)?e0 (a0) are reserved for future use and must all be programmed to '0.' * e16 (ba2) and e13 (a13) - e0 (a0) are reserved for future use and must all be programmed to '0.'
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 24 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm extended mode register 3 (emr3) extended mode register 3 (emr3) the extended mode register 3 (emr3) contro ls functions beyond those controlled by the mode register. currently all bits in emr3 are reserved as shown in figure 11, extended mode register 3 (e mr3) definition. the emr3 is programmed via the load mode command and will retain the stored information until it is programmed again or the device loses power. reprogramming the extended mode regist er will not alter the contents of the memory array, provided it is performed correctly. the extended mode register must be loaded wh en all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any sub- sequent operation. violating either of these requirements could result in unspecified operation. figure 11: extended mode register 3 (emr3) definition note: a13 is not used in x16-configured compon ents, so is not applic able for this module. a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 * e12 (a12)?e0 (a0) are reserved for future use and must all be programmed to '0.' 14 emr(3) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 15 a13 emr3 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 128mb address bus 256mb address bus a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 15 a13 0 1 0 1 mode register set mode register set (mrs) extended mode register (emrs) extended mode register (emrs2) extended mode register (emrs3) m15 0 0 1 1 m14 mrs 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* ba2 16 0* * e13 (a13)?e0 (a0) are reserved for future use and must all be programmed to '0.' 512mb address bus * e16 (ba2) and e13 (a13) - e0 (a0) are reserved for future use and must all be programmed to '0.'
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 25 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm command truth tables command truth tables table 7, commands truth table provides a quick reference of ddr2 sdram device available commands. refer to the 256mb, 512mb, or 1gb ddr2 sdram component data sheet for more truth table definitions, including cke power-down modes and device bank-to-bank commands. notes: 1. all ddr2 sdram device commands are defi ned by states of s#, ras#, cas#, we#, and cke at the rising ed ge of the clock. 2. device bank addresses (ba) ba0?ba1/ba2 determine which device bank is to be operated upon. for emr, ba selects an extended mode register. 3. burst reads or writes at bl = 4 cannot be te rminated or interrupted. refer to the 256mb, 512mb, or 1gb ddr2 sdram discrete data sh eet for other restrictions or details. 4. the power down mode does not perform an y refresh operations. the duration of power- down is therefore limited by the refresh re quirements outlined in the ac parametric sec- tion. 5. the state of odt does not affect the states de scribed in this table. the odt function is not available during self refresh. refer to the 256mb, 512mb, or 1g b ddr2 sdram discrete data sheet for other restrictions or details. 6. ?x? means ?h or l? (but a defined logic level). 7. self refresh exit is asynchronous. 8. ba2 valid for 512mb only. table 7: commands truth table notes: 1, 5, 6 function cke s# ras# cas# we# ba2 8 , ba1, ba0 a12? a11 a10 a9?a0 notes previous cycle current cycle mode register set h h l l l l ba op code 2 refresh h hlllhxxxx self refresh entry h l lllhxxxx self refresh exit l h xxxx x x x x 7 lhhhxxxx single device bank precharge hhllhlbaxlx2 all device banks precharge hhllhlxxhx device bank activate h h l l h h ba row address 2 write h h l h l l ba column address l column address 2, 3 write with auto precharge h h l h l l ba column address h column address 2, 3 read h h lhlhbacolumn address l column address 2, 3 read with auto precharge h h lhlhbacolumn address h column address 2, 3 no operation h xlhhhxxxx device deselect h xhxxxxxxx power-down entry h lhxxxxxxx4 lhhhxxxx power-down exit l hhxxxxxxx4 lhhhxxxx
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 26 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm absolute maximum ratings absolute maximum ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. dc operating conditions notes: 1. v dd and v dd q must track each other. v dd q must be less than or equal to v dd . 2. v ref is expected to equal v dd q/2 of the transmitting device and to track variations in the dc level of the same. peak-to-pe ak noise (non-common mode) on v ref may not exceed 1percent of the dc value. peak-to-peak ac noise on v ref may not exceed 2 percent of v ref (dc). this measurement is to be taken at the nearest v ref bypass capacitor. 3. v tt is not applied directly to the device. v tt is a system supply for signal termination resis- tors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 4. v dd q tracks with v dd ; v dd l tracks with v dd . table 8: absolute maximum dc ratings symbol parameter min max units v dd v dd supply voltage relative to v ss -1.0 2.3 v v dd q v dd q supply voltage relative to v ss -0.5 2.3 v v dd l v dd l supply voltage relative to vss -0.5 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature -55 100 c t case ddr2 sdram device operating temperature (ambient) 085c t opr operating temperature (ambient) 055c i i input leakage current; any input 0v v in v dd ; v ref input 0v v in 0.95v; (all other pins not under test = 0v) command/address, ras#, cas#, we# s#, cke, ck, ck#, dm -5 5 a i oz output leakage current; 0v v out v dd q; dqs and odt are disabled dq, dqs, dqs# -5 5 a i v ref v ref leakage current; v ref = valid v ref level -10 10 a table 9: recommended dc operating conditions all voltages referenced to v ss parameter symbol min nom max units notes supply voltage v dd 1.7 1.8 1.9 v 1 v dd l supply voltage v dd l1.7 1.8 1.9 v 4 i/o supply voltage v dd q1.7 1.8 1.9 v 4 i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51 x v dd qv 2 i/o termination voltage (system) v tt v ref - 40 v ref v ref + 40 mv 3
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 27 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm input electrical characteristics and operating conditions input electrical characterist ics and operating conditions i dd specifications and conditions i dd specifications are tested after the device is properly initialized. 0c t case +85c. v dd = v dd q = v dd l = +1.8v 0.1v; v ref =v dd q/2. input slew rate is specified by ac parametric test conditions. i dd parameters are speci- fied with odt disabled. data bus consists of dq, dm, dqs, dqs#. i dd values must be met with all combinations of emr bits 10 and 11. definitions for i dd conditions: ? low is defined as v in v il (ac) (max) ?high is defined as v in v ih (ac) (min) ? stable is defined as inputs stable at a high or low level ? floating is defined as inputs at v ref = v dd q/2 ? switching is defined as inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals ? switching is defined as in puts changing between high and low every other data transfer (once per clock) for dq signals not including masks or strobes table 10: input dc logic levels all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage v ih ( dc )v ref + 125 v dd q + 300 mv input low (logic 0) voltage v il ( dc )-300v ref - 125 mv table 11: input ac logic levels all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage v ih ( ac )v ref + 250 - mv input low (logic 0) voltage (-40e/-53e) v il ( ac )? v ref - 250 mv input low (logic 0) voltage (-667) v il ( ac )? v ref - 200 mv table 12: general i dd parameters i dd parameter -667 -53e -40e units cl (i dd ) 54 3 t ck t rcd (i dd ) 15 15 15 ns t rc (i dd ) 55 55 55 ns t rrd (i dd ) 7.5 7.5 7.5 ns t ck (i dd ) 33.75 5 ns t ras min (i dd ) 45 45 40 ns t ras max (i dd ) 70,000 70,000 70,000 ns t rp (i dd ) 15 15 15 ns t rfc (i dd )128mb 75 75 75 ns 256mb 105 105 105 ns 512mb 127.5 127.5 127.5 ns
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 28 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm i dd specifications and conditions i dd 7 conditions table 13, idd7 timing patterns ? 128mb and 256mb, and table 14, idd7 timing patterns ? 512mb, specify detailed timing requirements for i dd 7. changes will be required if tim- ing parameter changes are made to the specification. legend: a = active; ra = read auto precharge; d = deselect. all banks are being inter- leaved at minimum t rc (i dd ) without violating t rrd (i dd ) using a bl = 4. control and address bus inputs are stable during deselects. i out = 0ma. capacitance at ddr2 data rates, micron encourages designers to simulate the performance of the module to achieve optimum values. when in ductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and real- istic than a gross esti mation of module capacitance. simulations can then render a con- siderably more accurate result. jedec modules are now designed by using simulations to close timing budgets. table 13: i dd 7 timing patterns ? 128mb and 256mb all bank interleave read operation speed grade idd7 timing patterns -40e a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d -53e a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d -667 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d table 14: i dd 7 timing patterns ? 512mb all bank interleave read operation speed grade idd7 timing patterns -40e a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d -53e a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d a4 ra4 d a5 ra5 d a6 ra6 d a7 ra7 d d d -667 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 29 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm i dd specifications and conditions table 15: i dd specifications and conditions ? 128mb values shown for ddr2 sdram components only parameter/condition symbol -667 -53e -40e units operating one bank active-precharge current; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 0 450 400 385 ma operating one bank active-read-precharge current; i out = 0ma; bl = 4, cl = cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; ad dress bus inputs are switching; data pattern is same as i dd 4w. i dd 1 500 450 425 ma precharge power-down current ; all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus in puts are stable; data bus inputs are floating. i dd 2p 25 25 25 ma precharge quiet standby current ; all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other co ntrol and address bus inpu ts are stable; data bus inputs are floating. i dd 2q 250 175 125 ma precharge standby current ; all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and addres s bus inputs are switching; data bus inputs are switching. i dd 2n 200 175 150 ma active power-down current ; all device banks open; t ck = t ck (i dd ); cke is low; other contro l and address bus inputs are stable; data bus inputs are floating. fast pdn exit mr[12] = 0 i dd 3p 150 125 100 ma slow pdn exit mr[12] = 1 30 30 30 ma active standby current ; all device banks open; t ck = t ck(i dd ), t ras = tras max (i dd ), t rp = t rp(i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. i dd 3n 275 200 150 ma operating burst write current ; all device banks open, continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high betwee n valid commands; address bus inputs are switching; data bu s inputs are switching. i dd 4w 1,075 900 700 ma operating burst read current ; all device banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 4r 950 800 600 ma burst refresh current ; t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. i dd 5 900 850 825 ma self refresh current ; ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. i dd 6252525ma operating bank interleave read current ; all device banks interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd )-1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc(i dd ), t rrd = t rrd(i dd ), t rcd = t rcd(i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during dese lects; data bus inputs are switching; see i dd 7 conditions for detail. i dd 7 1,250 1,200 1,150 ma
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 30 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm i dd specifications and conditions table 16: i dd specifications and conditions ? 256mb values shown for ddr2 sdram components only parameter/condition symbol -667 -53e -40e units operating one bank active-precharge current; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 0 600 550 550 ma operating one bank active-read-precharge current; i out = 0ma; bl = 4, cl = cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd 4w. i dd 1 725 650 625 ma precharge power-down current ; all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus in puts are stable; data bus inputs are floating. i dd 2p 25 25 25 ma precharge quiet standby current ; all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other co ntrol and address bus inpu ts are stable; data bus inputs are floating. i dd 2q 275 225 200 ma precharge standby current ; all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and addres s bus inputs are switching; data bus inputs are switching. i dd 2n 300 250 225 ma active power-down current ; all device banks open; t ck = t ck (i dd ); cke is low; other contro l and address bus inputs are stable; data bus inputs are floating. fast pdn exit mr[12] = 0 i dd 3p 175 150 125 ma slow pdn exit mr[12] = 1 50 50 50 ma active standby current ; all device banks open; t ck = t ck(i dd ), t ras = t ras max (i dd ), t rp = t rp(i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. i dd 3n 350 300 250 ma operating burst write current ; all device banks open, continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high betwee n valid commands; address bus inputs are switching; data bu s inputs are switching. i dd 4w 1,150 950 750 ma operating burst read current ; all device banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 4r 1,175 975 775 ma burst refresh current ; t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. i dd 5 1,100 1,050 1,000 ma self refresh current ; ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. i dd 6252525ma operating bank interleave read current ; all device banks interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd )-1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc(i dd ), t rrd = t rrd(i dd ), t rcd = t rcd(i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during dese lects; data bus inputs are switching; see i dd 7 conditions for detail. i dd 7 1,650 1,625 1,600 ma
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 31 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm i dd specifications and conditions table 17: i dd specifications and conditions ? 512mb values shown for ddr2 sdram components only parameter/condition symbol -667 -53e -40e units operating one bank active-precharge current; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 0 675 550 550 ma operating one bank active-read-precharge current; i out = 0ma; bl = 4, cl = cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd 4w. i dd 1 800 650 625 ma precharge power-down current ; all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus in puts are stable; data bus inputs are floating. i dd 2p 35 25 25 ma precharge quiet standby current ; all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other co ntrol and address bus inpu ts are stable; data bus inputs are floating. i dd 2q 325 225 200 ma precharge standby current ; all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and addres s bus inputs are switching; data bus inputs are switching. i dd 2n 350 250 200 ma active power-down current ; all device banks open; t ck = t ck (i dd ); cke is low; other contro l and address bus inputs are stable; data bus inputs are floating. fast pdn exit mr[12] = 0 i dd 3p 200 150 125 ma slow pdn exit mr[12] = 1 25 25 25 ma active standby current ; all device banks open; t ck = t ck(i dd ), t ras = t ras max (i dd ), t rp = t rp(i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. i dd 3n 375 275 250 ma operating burst write current ; all device banks open, continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high betwee n valid commands; address bus inputs are switching; data bu s inputs are switching. i dd 4w 1,350 950 800 ma operating burst read current ; all device banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 4r 1,375 975 900 ma burst refresh current ; t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. i dd 5 1,350 1,250 1,200 ma self refresh current ; ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. i dd 6352525ma operating bank interleave read current ; all device banks in terleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd )-1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc(i dd ), t rrd = t rrd(i dd ), t rcd = t rcd(i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during dese lects; data bus inputs are switching; see i dd 7 conditions for detail. i dd 7 2,025 1,775 1,775 ma
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 32 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm ac operating specifications ac operating specifications table 18: ac operating conditions (sheet 1 of 4) notes: 1?5; notes ap pear on page 36; 0c t case +85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -667 -53e -40e units notes parameter symbol min max min max min max clock clock cycle time cl = 5 t ck (5) 3,000 8,000 ? ? ? ? ps 16, 25 cl = 4 t ck (4) 3,750 8,000 3,750 8,000 5,000 8,000 ps 16, 25 cl = 3 t ck (3) 5,000 8,000 5,000 8,000 5,000 8,000 ps 16, 25 ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck 19 ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 19 half clock period t hp min ( t ch, t cl) min ( t ch, t cl) min ( t ch, t cl) ps 20 clock jitter t jit tbd tbd tbd tbd tbd tbd ps 18 data dq output access time from ck/ck# t ac -450 +450 -500 +500 -600 +600 ps data-out high-impedance window from ck/ck# t hz t ac (max) t ac max t ac max ps 8, 9 data-out low-impedance window from ck/ck# t lz t ac (min) t ac (max) t ac min t ac max t ac min t ac max ps 8, 10 dq and dm input setup time relative to dqs t ds a 300 350 400 ps 7, 15, 22 dq and dm input hold time relative to dqs t dh a 300 350 400 ps 7, 15, 22 dq and dm input setup time relative to dqs t ds b 100 100 150 ps 7, 15, 22 dq and dm input hold time relative to dqs t dh b 175 225 275 ps 7, 15, 22 dq and dm input pulse width (for each input) t dipw 0.35 0.35 0.35 t ck data hold skew factor t qhs 340 400 450 ps dq?dqs hold, dqs to first dq to go nonvalid, per access t qh t hp - t qhs t hp - t qhs t hp - t qhs ps 15, 17 data valid output window (dvw) t dvw t qh - t dqsq t qh - t dqsq t qh - t dqsq ns 15, 17
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 33 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm ac operating specifications data strobe dqs input high pulse width t dqsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck -400 +400 -450 +450 -500 +500 ps dqs falling edge to ck rising ? setup time t dss 0.2 0.2 0.2 t ck dqs falling edge from ck rising ? hold time t dsh 0.2 0.2 0.2 t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq 240 300 350 ps 15, 17 dqs read preamble t rpre 0.91.10.91.10.91.1 t ck 36 dqs read postamble t rpst 0.40.60.40.60.40.6 t ck 36 dqs write preamble setup time t wpres 0 0 0 ps 12, 13, 37 dqs write preamble t wpre 0.35 0.25 0.25 t ck dqs write postamble t wpst 0.40.60.40.60.40.6 t ck 11 write command to first dqs latching transition t dqss wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 t ck table 18: ac operating conditions (sheet 2 of 4) notes: 1?5; notes ap pear on page 36; 0c t case +85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -667 -53e -40e units notes parameter symbol min max min max min max
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 34 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm ac operating specifications command and address address and control input pulse width for each input t ipw 0.6 0.6 0.6 t ck address and control input setup time t is a 400 500 600 ps 6, 22 address and control input hold time t ih a 400 500 600 ps 6, 22 address and control input setup time t is b 200 250 350 ps 6, 22 address and control input hold time t ih b 275 375 475 ps 6, 22 cas# to cas# command delay t ccd 2 2 2 t ck active to active (same bank) command t rc 55 55 55 ns 34 active bank a to active bank b command t rrd 10 10 10 ns 28 active to read or write delay t rcd 15 15 15 ns four bank activate period t faw 50 50 50 ns 31 active to precharge command t ras 40 70,000 40 70,000 40 70,000 ns 21, 34 internal read to precharge command delay t rtp 7.5 7.5 7.5 ns 24, 28 write recovery time t wr 15 15 15 ns 28 auto precharge write recovery + precharge time t dal t wr + t rp t wr + t rp t wr + t rp ns 23 internal write to read command delay t wtr 10 7.5 10 ns 28 precharge command period t rp 15 15 15 ns 32 precharge all command period t rpa t rp + t ck t rp + t ck t rp + t ck ns 32 load mode command cycle time t mrd 2 2 2 t ck cke low to ck,ck# uncertainty t delay t is + t ck + t ih t is + t ck + t ih t is + t ck + t ih ns 29 table 18: ac operating conditions (sheet 3 of 4) notes: 1?5; notes ap pear on page 36; 0c t case +85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -667 -53e -40e units notes parameter symbol min max min max min max
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 35 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm ac operating specifications self refresh refresh to active or refresh to refresh command interval t rfc (128mb) 75 70,000 75 70,000 75 70,000 ns 14 t rfc (256mb) 105 70,000 105 70,000 105 70,000 ns 14 t rfc (512mb) 127.5 70,000 127.5 70,000 127.5 70,000 ns 14 average periodic refresh interval t refi 200 7.8 7.8 7.8 s 14 exit self refresh to non-read command t xsnr t rfc (min) + 10 t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd 200 200 200 t ck exit self refresh timing reference t isxr t is t is t is ps 6, 30 odt odt turn-on delay t aond222222 t ck odt turn-on t aon t ac (min) t ac (max) + 700 t ac (min) t ac (max) + 1,000 t ac (min) t ac (max) + 1000 ps 26 odt turn-off delay t aofd 2.52.52.52.52.52.5 t ck odt turn-off t aof t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps 27 odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1000 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power-down entry latency t anpd 3 3 3 t ck odt power-down exit latency t axpd 8 8 8 t ck power-down exit active power-down to read command, mr[bit12=0] t xard 2 2 2 tck exit active power-down to read command, mr[bit12=1] t xards 7 - al 6 - al 6 - al t ck exit precharge power-down to any non-read command. t xp 2 2 2 t ck cke minimum high/low time t cke 3 3 3 t ck 35 table 18: ac operating conditions (sheet 4 of 4) notes: 1?5; notes ap pear on page 36; 0c t case +85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -667 -53e -40e units notes parameter symbol min max min max min max
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 36 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm notes notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.0v in the test environ- ment and parameter specifications are guar anteed for the specif ied ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1.0v/ns for signals in the range between v il (ac) and v ih (ac). slew rates less than 1.0v/ns require the timing parameters to be derated as specified. 5. the ac and dc input level specifications are as defined in the sstl_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as th e signal does not ring back above [below] the dc input low [high] level). 6. command/address minimum input slew rate is at 1.0v/ns. command/address input timing must be derated if th e slew rate is not 1.0v/ns. this is easily accommodated using t is b and the setup and hold time derating values table. t is timing ( t is b ) is refer- enced from v ih ( ac ) for a rising signal and v il ( ac ) for a falling signal. t ih timing ( t ih b ) is referenced from v ih ( ac ) for a rising signal and v il ( dc ) for a falling signal. the timing table also lists the t is b and t ih b values for a 1.0v/ns slew rate; these are the ?base? val- ues. 7. data minimum input slew rate is at 1.0v/ns. data input timing must be derated if the slew rate is not 1.0v/ns. this is easily ac commodated if the timing is referenced from the logic trip points. t ds timing ( t ds b ) is referenced from v ih (ac) for a rising signal and v il (ac) for a falling signal. t ih timing ( t ih b ) is referenced from v ih (dc) for a ris- ing signal and v il ( dc ) for a falling signal. the timing table lists the t ds b and t dh b val- ues for a 1.0v/ns slew rate. if the dqs/dqs# differential strobe feature is not enabled, timing is no longer referenced to the cros spoint of dqs/dqs#. data timing is now ref- erenced to v ref , provided the dqs slew rate is not less than 1.0v/ns. if the dqs slew rate is less than 1.0v/ns, then da ta timing is now referenced to v ih ( ac ) for a rising dqs and v il ( dc ) for a falling dqs. 8. t hz and t lz transitions occur in the same access time windows as valid data transi- tions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving ( t hz) or begins driving ( t lz). 9. this maximum value is derived from the referenced test load. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 10. t lz (min) will prevail over a t dqsck (min) + t rpre (max) condition. 11. the intent of the don?t care state after completion of the postamble is the dqs-driven signal should either be high, low or high-z and that any signal transition within the input switching region must follow valid input requirements. that is if dqs transi- tions high (above v ih dc(min) then it must not transition low (below v ih (dc) prior to t dqsh(min). 12. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. output (v out ) reference point 25 v tt = v dd q/2
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 37 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm notes 13. it is recommended that dqs be valid (high or low) on or before the write com- mand. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 14. the refresh period is 64ms. this equates to an average refresh rate of 7.8125s. how- ever, a refresh command must be asse rted at least once every 70.3s or t rfc (max). to ensure all rows of all banks are properly refreshed, 8192 refresh com- mands must be issued every 64ms. 15. each byte lane has a corresponding dqs. 16. ck and ck# input slew rate must be 1v/ns ( 2 v/ns if measured differentially). 17. the data valid window is derived by achieving other specifications - t hp. ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates in direct propor- tion to the clock duty cycle and a practical data valid window can be derived. 18. t jit specification is currently tbd. 19. min( t cl, t ch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch). for example, t cl and t ch are = 50 percent of the period, less the half period jitter [ t jit(hp)] of the clock source, and less the half period jitter due to cross talk [ t jit(cross talk)] into the clock traces. 20. t hp (min) is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs. 21. reads and writes with auto precharge are allowed to be issued before t ras (min) is satisfied since t ras lockout feature is supported in ddr2 sdram devices. 22. v il /v ih ddr2 overshoot/undershoot. r efer to the 256mb, 512mb, or 1gb ddr2 sdram data sheet for more detail. 23. t dal = (nwr) + ( t rp/ t ck): for each of the terms above, if not already an integer, round to the next highest integer. t ck refers to the application clock period; nwr refers to the t wr parameter stored in the mr[11,10,9]. example: for -53e at t ck = 3.75 ns with t wr programmed to four clocks. t dal = 4 + (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks. 24. the minimum read to internal precharge time. this parameter is only applicable when t rtp/(2* t ck) > 1. if t rtp/(2* t ck) 1, then equation al + bl/2 applies. notwith- standing, t ras (min) has to be satisfied as well. the ddr2 sdram device will auto- matically delay the internal precharge command until t ras (min) has been satisfied. 25. operating frequency is only allowed to change during self refresh mode, precharge power-down mode, and system reset condition. 26. odt turn-on time t aon (min) is when the device leaves high impedance and odt resistance begins to turn on. odt turn-on time t aon (max) is when the odt resis- tance is fully on. both are measured from t aond. 27. odt turn-off time t aof (min) is when the device starts to turn off odt resistance. odt turn off time t aof (max) is when the bus is in high impedance. both are mea- sured from t aofd. 28. this parameter has a two cloc k minimum requirement at any t ck. 29. t delay is calculated from t is + t ck + t ih so that cke registration low is guaranteed prior to ck, ck# being removed in a system reset condition. 30. t isxr is equal to t is and is used for cke setup time during self refresh exit. 31. no more than 4 bank active commands may be issued in a given t faw(min) period. t rrd(min) restriction still applies. the t faw(min) parameter applies to all 8 bank ddr2 devices, regardless of the number of banks already open or closed.
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 38 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm notes 32. t rpa timing applies when the precharge(all) command is issued, regardless of the number of banks already open or closed. if a single-bank precharge command is issued, t rp timing applies. t rpa(min) applies to all 8-bank ddr2 devices. 33. value is minimum pulse width, no t the number of clock registrations. 34. applicable to read cycles only. write cycles generally require additional time due to write recovery time ( t wr) during auto precharge. 35. t cke (min) of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not tran- sition from its valid level during the time period of t is + 2 x t ck + t ih. 36. this parameter is not referenced to a specific voltage level, but specified when the device output is no longer driving ( t rpst) or beginning to drive ( t rpre). 37. when dqs is used single-ended, th e minimum limit is reduced by 100ps.
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 39 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm pll and register specifications pll and register specifications notes: 1. timing and switch ing specifications for th e register listed above are critical for proper operation of the ddr2 sdram registered dimms. these are meant to be a subset of the parameters for the specific device used on th e module. detailed info rmation for this regis- ter is available in jedec standard jesd82. 2. this parameter is not necessarily production tested. 3. data inputs must be low a minimum time of t act (max), after reset# is taken high. 4. data and clock inputs must be held at valid levels (not floating) a minimum time of t inact (max), after reset# is taken low. table 19: register timing requirements and switching characteristics symbol parameter condition 0c t opr +55c v dd = +1.8v 0.1v units min max v oh i oh = -6 ma 1.2 ? v v ol i ol = 6 ma ? .05 v i i all inputs v i = v dd or gnd ? 5 a i dd static standby reset# = gnd ? 100 a static operating reset# = v dd , v i = v ih (ac) or v il (ac), i 0 = 0 ? 40 ma i ddd dynamic operating ? clock only reset# = v dd , v i = v ih (ac) or v il (ac), i 0 = 0; ck and ck# switching 50% duty cycle varies by mfr varies by mfr a dynamic operating ? per each data input, 1:1 mode r eset# = v dd , v i = v ih (ac) or v il (ac), i 0 = 0; ck and ck# switching 50% duty cycle; one data input switching at t ck/2, 50% duty cycle varies by mfr varies by mfr dynamic operating ? per each data input, 1:2 mode reset# = v dd , v i = v ih (ac) or v il (ac), i 0 = 0; ck and ck# switching 50% duty cycle; one data input switching at t ck/2, 50% duty cycle varies by mfr varies by mfr c i data inputs v i = v ref 250mv 2.5 3.5 pf ck and ck# v icr = 0.9v, v id = 600mv 2 3 reset v i = v dd or gnd varies varies table 20: register elec trical characteristics note: 1 register symbol parameter condition 0c t opr +55c v dd = +1.8v 0.1v units notes min max sstl (bit pattern by jesd82) f clock clock frequency ? 270 mhz t w pulse duration 1 ? ns t act differential inputs active time ?10ns2, 3 t inact differential inputs inactive time ?15ns2, 4 t su setup time data before ck high, ck# low 0.7 ? ns data before ck high, ck# low 0.5 ? ns odt, cke, and data before ck high, ck# low 0.5 ? t h hold time oke, cke, and data after ck high, ck# low 0.50 ? ns
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 40 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm pll and register specifications notes: 1. total i dd = i dd q = i add = f ck x c pd x v dd q, solving for c pd = (i dd q + i add )/(f ck x v dd q) where f ck is the input frequency, v dd q is the power supply and cpd is the power dissipa- tion capacitance. table 21: pll clock driver electrical characteristics symbol parameter test condition 0c t opr +55c v dd = +1.8v 0.1v units notes min nominal max v ik all inputs i i = -18 m a? ? -1.2v v oh high output voltage i oh = -100a v dd q/2 - 0.2 ? ? v i oh = -9ma 1.1 ? ? v v ol low output voltage i ol = 100a ? 0.1 a i ol = 9ma 0.6 v i odl output disabled low current oe = l, v odl = 100mv 100 ? ? a v od output differential voltage, the magnitude of the difference between the true and complimentary outputs 0.6 ? ? v i i ck, ck# v i = v dd q or gnd ??250a i ddld static supply current: i dd q + i add ck and ck# = l ? ? 500 a i dd dynamic supply current: i dd q + i add ck and ck# = 270 mhz, all outputs are open (not connected to a pcb) ??300ma1 c i ci and ck# v i = v dd q or gnd 2?3pf c i ( ) ci and ck# v i = v dd q or gnd v dd q/2 - 0.2 ? 0.25 pf
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 41 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm pll and register specifications notes: 1. timing and switch ing specifications for th e pll listed above are critical for proper opera- tion of the ddr2 sdram registered dimms. these are mean t to be a subset of the param- eters for the specific device used on the mo dule. detailed information for this pll is available in jedec standard jesd82. 2. static phase offset do es not include jitter. 3. period jitter and half-period ji tter specifications are separate specifications that must be met independently of each other. 4. design target is 60ps, unless it is unachievable. 5. v ox specified at the dram cloc k input, or the test load. 6. the output slew rate is dete rmined from th e ibis model: table 22: pll clock driver timing requirements and switching characteristics note: 1 parameter symbol 0c t opr +55c v dd = +1.8v 0.1v units notes min nominal max output enable to any y/y# t en ? ? 8 ns output enable to any y/y# t dis ? ? 8 ns cycle to cycle jitter t jit cc -40 ? 40 ps static phase offset t ? -50 0 50 ps 2 dynamc phase offset t ? dyn -50 0 50 ps 2 output clock skew t sk o ??40ps period jitter t jit per -40 ? 40 ps 3, 4 half-period jitter t jit hper -75 ? 75 ps 3 input clock slew rate t ls i 1.0 2.5 4 v/ns output clock slew rate t ls o 1.5 2.5 3 v/ns 6 output differential-pair cross-voltage v ox v dd q/2 - 0.1 ? v dd q/2 + 0.1 v 5 ssc modulation frequency 30 ? 33 khz ssc clock input frequency deviation 0.0 ? -0.50 % pll loop bandwidth (-3db from unity gain) 2.0 ? ? mhz v dd g nd v dd c u878 r= 6 0 r= 6 0 v c k v c k 2
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 42 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm serial presence-detect serial presence-detect spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (figure 12, data validity, and figure 13, definition of start and stop). spd start condition all commands are preceded by the start cond ition, which is a hi gh-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not re spond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condition, which is a low-to-high tran- sition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 14, acknowledge response from receiver). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both th e device and a write operation have been selected, the spd device will respond with an acknowledge after the receipt of each sub- sequent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop conditio n is generated by the master, the slave will continue to transmit data. if an acknowledge is not dete cted, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. figure 12: data validity scl sda data stable data stable data change
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 43 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm serial presence-detect figure 13: definition of start and stop figure 14: acknowledge response from receiver scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 44 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm serial presence-detect figure 15: spd eeprom timing diagram table 23: eeprom device select code the most significant bit (b7) is sent first select code device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1010sa2sa1sa0rw protection register select code 0110sa2sa1sa0rw table 24: eeprom operating modes mode rw bit wc bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = ?1 ? random address read 0v ih or v il 1 start, device select, rw = ?0 ? , address 1v ih or v il 1 restart, device select, rw = ?1 ? sequential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = ?0 ? page write 0v il 16 start, device select, rw = ?0 ? scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 45 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm serial presence-detect notes: 1. to avoid spurious start and stop condit ions, a minimum delay is placed between scl = 1 and the falling or ri sing edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a vali d stop condition of a write sequence to the end of the eeprom internal erase/program cycle. du ring the write cycle, the eeprom bus interface circui t is disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address. table 25: serial presence-detec t eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +1.7v to +3.6v parameter/condition symbol min max units supply voltage v ddspd 1.7 3.6 v input high voltage: logic 1; all inputs v ih v ddspd x 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il -0.6 v ddspd x 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li 0.10 3 a output leakage current: v out = gnd to v dd i lo 0.05 3 a standby current: i sb 1.6 4 a power supply current, read: sc l clock frequency = 100 khz i cc r 0.4 1 ma powr supply current, write: scl clock frequency = 100 khz i cc w 23ma table 26: serial presence-detec t eeprom ac operating conditions all voltages referenced to v ss ; v ddspd = +1.7v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 s data-out hold time t dh 200 ns sda and scl fall time t f 300 ns 2 data-in hold time t hd:dat 0 s start condition hold time t hd:sta 0.6 s clock high period t high 0.6 s noise suppression time con stant at scl, sda inputs t i50ns clock low period t low 1.3 s sda and scl rise time t r0.3s2 scl clock frequency f scl 400 khz data-in setup time t su:dat 100 ns start condition setup time t su:sta 0.6 s 3 stop condition setup time t su:sto 0.6 s write cycle time t wrc 10 ms 4
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 46 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm serial presence-detect table 27: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driv en to low?; table notes located on page 47 byte description entry (version) mt5htf1672k/ mt5htf1672pd mt5htf3272k/ mt5htf3272pd mt5htf6472k/ mt5htf6472pd 0 number of spd bytes used by micron 128 808080 1 total number of bytes in spd device 256 080808 2 fundamental memory type ddr2 sdram080808 3 number of row addresses on assembly 13 0d 0d 0d 4 number of column addresses on assembly 09, 10 09 0a 0a 5 dimm height and module ranks 1.18in., single rank 60 60 60 6 module data width 72 48 48 48 7 module data width (continued) 0 000000 8 module voltage interface levels sstl 1.8v 05 05 05 9 sdram cycle time, t ck (cl = maximum value, see byte 18) -667 -53e -40e 30 3d 50 30 3d 50 30 3d 50 10 sdram access from clock, t ac (cl = maximum value, see byte 18) -667 -53e -40e 45 50 60 45 50 60 45 50 60 11 module configuration type 02/06 02/06 02/06 12 refresh rate/type 7.81s/self 82 82 82 13 sdram device widt h (primary sdram) 16 10 10 10 14 error-checking sdram data width 16 10 10 10 15 minimum clock delay, back-to-back random column access 1 clock000000 16 burst lengths supported 4, 8 0c0c0c 17 number of banks on sdram device 4 or 8040408 18 cas latencies supported -667 (5, 4, 3) -53e/-40e (4, 3) 38 18 38 18 38 18 19 module thickness 01 01 01 20 ddr2 dimm type registered dimm 10 10 10 21 sdram module attributes 04 04 04 22 sdram device attri butes: weak driver (01) and 50 odt (03) -667 -53e/-40e 03 01 03 01 03 01 23 sdram cycle time, t ck, max. cl - 1 -667 -53e/-40e 3d 50 3d 50 3d 50 24 sdram access from ck, t ac, max. cl - 1 -667 -53e -40e 45 50 60 45 50 60 45 50 60 25 sdram cycle time, t ck, max. cl - 2 -667 -53e/-40e(n/a) 50 00 50 00 50 00 26 sdram access from ck, t ac, max. cl - 2 -667 -53e/-40e(n/a) 45 00 45 00 45 00 27 minimum row precharge time, t rp 3c 3c 3c 28 minimum row active to row active, t rrd 28 28 28 29 minimum ras# to cas# delay, t rcd 3c 3c 3c 30 minimum ras# pulse width, t ras (see note 1) -667/-53e -40e 2d 28 2d 28 2d 28 31 module rank density 128mb, 256mb, 512mb 20 40 80
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 47 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm serial presence-detect notes: 1. the t ras spd value shown is based on the jedec st andard value of 45 ns; the actual device specification is t ras = 40ns. 32 address and command setup time, t is b -667 -53e -40e 20 25 35 20 25 35 20 25 35 33 address and command hold time, t ih b -667 -53e -40e 27 37 47 27 37 47 27 37 47 34 data/ data mask input setup time, t ds b -667/-53e -40e 10 15 10 15 10 15 35 data/ data mask input hold time, t dh b -667 -53e -40e 17 22 27 17 22 27 17 22 27 36 write recovery time, t wr 3c 3c 3c 37 write to read cmd delay, t wtr -667/-53e -40e 1e 28 1e 28 1e 28 38 read to precharge cmd delay, t rtp 1e 1e 1e 39 mem analysis probe 00 00 00 40 extension for bytes 41 and 42 00 00 06 41 min active auto refresh time, t rc -667/-53e -40e 3c 37 3c 37 3c 37 42 minimum auto refresh to active/ auto refresh command period, t rfc 4b 69 7f 43 sdram device max cycle time, t ck max 80 80 80 44 sdram device max dqs-dq skew time, t dqsq -667 -53e -40e 18 1e 23 18 1e 23 18 1e 23 45 sdram device max read data hold skew factor, t qhs -667 -53e -40e 22 28 2d 22 28 2d 22 28 2d 46 pll relock time 0f 0f 0f 47?61 optional features , not supported 00 00 00 62 spd revision release 1.2 12 12 12 63 checksum for bytes ?62 -667 -53e -40e 18/1c c3/c7 2a/2e 57/5b 02/06 69/6d b7/bb 62/66 c9/cd 64 manufacturer ? s jedec id code micron 2c 2c 2c 65?71 manufacturer ? s jedec id code (continued) ff ff ff 72 manufacturing location 01?12 01?0c 01?0c 01?0c 73?90 module part number (ascii) variable data variable data variable data 91 pcb identification code 1?9 01?09 01?09 01?09 92 identification code (continued) 0 000000 93 year of manufacture in bcd variable data variable data variable data 94 week of manufacture in bcd variable data variable data variable data 95?98 module serial number variable data variable data variable data 99?127 manufacturer-specific data (rsvd) ??? table 27: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driv en to low?; table notes located on page 47 byte description entry (version) mt5htf1672k/ mt5htf1672pd mt5htf3272k/ mt5htf3272pd mt5htf6472k/ mt5htf6472pd
pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 48 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm module dimensions module dimensions all dimensions are in inches (millimeters); or typical where noted. the dimensional diagram is fo r reference only. refer to the mo document for complete design dimensions. figure 16: 244-pin dimm ddr2 module dimensions max min 3.233 (82.127) 3.223 (81.873) front view 1.187 (30.152) 1.175 (29.848) 0.787 (20.0) typ 0.394 (10.0) typ 0.039 (1.0) typ 0.079 (2.00) r x2 0.039 (1.00) r x2 0.02 (0.50) r 0.071 (1.80) d x2 0.236 (6.0) typ 0.079 (2.0) typ 3.071 (78.0) typ 0.024 (0.60) typ 0.018 (0.45) typ pin 1 pin 122 1.689 (42.9) typ back view 0.130 (3.3) typ 0.142 (3.6) typ 0.130 (3.3) typ 1.323 (33.6) typ 1.512 (38.4) typ 0.126 (3.2) typ 0 .150 (3.80) max 0.043 (1.10) 0.035 (0.90) pin 244 pin 123 u1 u2 u3 u4 u6 u7 u8 u5 no dram devices this side of module
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trad emarks of micron technology, inc. all other trademarks are the prope rty of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 128mb, 256mb, 512mb (x72, sr) 244-pin ddr2 reg. minidimm data sheet designation pdf: 09005aef80e2b112, source: 09005aef80a43d77 micron technology, inc., reserves the right to change products or specifications without notice. htf5c32_64_128x72k_2.fm - rev. a 7/05 en 49 ?2004, 2005 micron technology, inc. all rights reserved. data sheet designation released (no mark): this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. the released designation applies to mt5htf1672 and mt5htf6472 only.

▲Up To Search▲

Price & Availability of MT5HTF3272KY-40EC2

	To Download MT5HTF3272KY-40EC2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .