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mp28258 high efficiency, fast transient, 3a, 4.2v-20v input synchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 1 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. the future of analog ic technology description the mp28258 is a fully-integrated, high- efficiency, synchronous, step-down, switch mode converter. it offers a very compact solution that can achieve a 3a continuous output current over a wide input supply range with excellent load and line regulation, and can operate at high efficiency over a wide output- current load range. constant-on-time (cot) control mode provides fast transient response and eases loop stabilization. full protection features include scp, ocp, ovp, uvp and, thermal shut down. the mp28258 requires a minimal number of readily-available standard external components. this device is available in a space saving 2mmx3mm 12-pin qfn package. features ? wide 4.2v to 20v operating input range ? 3a output current ? low r ds (on) internal power mosfets ? proprietary switching loss reduction technique ? power-good indicator in qfn package ? soft startup/shutdown ? programmable switching frequency ? scp, ocp, uvp protection and thermal shutdown ? optional ocp protection: latch-off mode and hiccup mode. ? output adjustable from 0.815v to 13v ? available in a qfn12 (2x3mm) package applications ? networking systems ? distributed power systems all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithi c power systems, inc. typical application mp28258 in freq vcc en pg gnd fb sw bst c5 c1 c3 c2 vout 1.2v l1 r4 r1 r2 c4 r7 vin 4.2v - 20v 9 8 2, 10 3 7 1, 11, 12 4 5 6 en off on
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 2 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ordering information part number ocp protection package top marking free air temperature (t a ) mp28258dd* latch-off mode qfn12 (2x3mm) aaa -40 c to 85 c mp28258dd-a hiccup mode qfn12 (2x3mm) acf -40 c to 85 c * for tape & reel, add suffix ?z (e.g. mp28258dd?z). for rohs compliant packaging, add suffix ?lf (e.g. mp28258dd?lf?z) package reference gnd sw bst vcc en gnd sw in freq fb top view pg gnd 1 2 12 3 4 8 7 6 5 11 10 9 sw qfn12 (2x3mm) absolute maxi mum ratings (1) supply voltage v in ....................................... 22v v sw ..................................... -0.3v to (v in + 0.3v) v bst ...................................................... v sw + 6v i vin (rms) ........................................................ 3.5a all other pins ..................................-0.3v to +6v continuous power dissipation (t a = 25c) (2) qfn12 (2x3mm)........................................ 1.8w junction temperature ..............................150 c lead temperature ....................................260 c storage temperature............... -65 c to +150 c recommended operating conditions (3) supply voltage v in ...........................4.2v to 20v output voltage v out .....................0.815v to 13v operating junction temp. (t j ). -40c to +125c thermal resistance (4) ja jc qfn12 (2mmx3mm) ............... 70 ...... 15... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 3 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. electrical characteristics v in = 12v, t a = 25 c, unless otherwise noted. parameters symbol condition min typ max units supply current (shutdown) i in v en = 0v 0 a supply current (quiescent) i in v en = 2v, v fb = 0.9v 360 a hs switch-on resistance hs rds-on 120 m ? ls switch-on resistance ls rds-on 50 m ? switch leakage sw lkg v en = 0v, v sw = 0v or 12v 0 10 a current limit (5) i limit after soft-start time-out 4 5 a one-shot on time t on r 7 = 300k ? ,v out = 1.2v 250 ns minimum off time t off 130 150 ns fold-back off time t fb ilim = 1 4.5 s ocp hold-off time t oc ilim = 1 50 s t a = 25c 807 815 823 mv feedback voltage v fb t a = -40c to 85c 803 827 mv feedback current i fb v fb = 800mv 10 50 na soft start rime t ss 1 ms en rising threshold en vth-hi 1.05 1.35 1.6 v en threshold hysteresis en vth-hys 500 mv v en = 2v 2 a en input current i en v en = 0v 0 power-good rising rhreshold pg vth-hi 0.9 v fb power-good falling rhreshold pg vth-lo 0.85 v fb power-good delay pgtd 0.5 ms power-good sink current capability vpg sink 4ma 0.4 v power-good leakage current ipg_leak vpg = 3.3v 10 na vin under-voltage lockout threshold rising inuv vth 3.1 v vin under-voltage lockout threshold hysteresis inuv hys 300 mv thermal shutdown t sd 150 c thermal shutdown hysteresis t sd-hys 25 c note: 5) guaranteed by design and characterization.
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 4 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. pin functions qfn12 (2x3mm) pin # name description 1, 11, 12 gnd system ground. these pins are the refere nce ground for the regulated output voltage, and require special consideration during pcb layout. 2, 10, exposed pad sw switch output. connect using wide pcb traces. 3 bst bootstrap. requires a capacitor connec ted between sw and bst pins to form a floating supply across the high-side switch driver. 4 vcc internal bias supply. decouple with a 4.7f ceramic capacitor as close to the pin as possible. 5 en en = 1 to enable the mp28258. for automatic start-up, connect en pin to vin with a pull-up resistor. 6 pg power-good output. the output of this pin is an open drain that goes high if the output voltage is higher than 90% of the nominal voltage. there is a 0.5ms delay between when fb 90% to when the pg pin goes high. 7 fb feedback. sets the output voltage when connec ted to the tap of an external resistor divider that is connected between output and gnd. 8 freq frequency. set during ccm operation. connect a resistor r 7 to in to set the switching frequency. decouple with a 1nf capacitor. 9 in supply voltage. the mp28258 operates from a +4.2v to +20v input rail. c1 is needed to decouple the input rail. use wide pcb traces and multiple vias to make the connection.
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 5 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics v in = 12v, v out = 1.2v, l = 2h, t a = 25c, unless otherwise noted. efficiency v out =5v, f s efficiency v out =1.2v, f s line regulation thermal test v out =1.2v load regulation frequency vs. temperature 55 60 65 70 75 80 85 90 95 0.01 0.1 1 10 i out (a) i out (a) i out (a) i out (a) i out (a) effi. 60 65 70 75 80 85 90 95 100 0.01 0.1 1 10 effi v in (v) normalized re -1.00 -0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 0 0.5 1 1.5 2 2.5 3 regulatio 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 t_case_rise thermal test v in =12v, v out =5v, t a 0 5 10 15 20 25 30 35 40 45 50 55 012345 t_case_rise 400 405 410 415 420 425 430 435 440 445 450 -40 -20 0 20 40 60 80 100 120140 tem f w s ( h) z v in =12v v in =5v v in =16v v in =8v v in =12v v in =12v v in =21v v in =12v no air flow no air flow frequency vs. input voltage i out =1a 500 600 700 800 900 0 5 10 15 20 v in (v) f w s (khz) v out =1.8v v out =3.3v -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 5 7 9111315171921 i out =3a v out vs . i out v out =1.2v, freq=500khz i out (a) v out (v) 1.1 1.12 1.14 1.16 1.18 1.2 1.22 1.24 0.01 0.1 1 10 v in =16v v in =12v v in =5v v in =8v
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 6 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in = 12v, v out = 1.2v, l = 2h, t a = 25c, unless otherwise noted. v in /ac 100mv/div. v out /ac 50mv/div. v out 500mv/div. v sw 5v/div. i l 2a/div. v in 2v/div. v sw 2v/div. i l 500ma/div. v out 500mv/div. v in 2v/div. v sw 2v/div. i l 2a/div. v out 500mv/div. v in 1v/div. v sw 1v/div. i l 200ma/div. v out 500mv/div. v in 2v/div. v sw 2v/div. i l 2a/div. v out 500mv/div. v en 2v/div. v sw 5v/div. i l 2a/div. v out 500mv/div. v en 2v/div. v sw 5v/div. i l 2a/div. v out 500mv/div. v en 2v/div. v sw 5v/div. i l 1a/div. v out 500mv/div. v en 2v/div. v sw 5v/div. i l 2a/div.
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 7 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in = 12v, v out = 1.2v, l = 2h, t a = 25c, unless otherwise noted. v out /ac 50mv/div. i l 2a/div. i l 2a/div. v out /ac 50mv/div. v sw 5v/div. i l 2a/div. v out /ac 50mv/div. v sw 5v/div.
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 8 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. block diagram start - + + - + - + - + soft start/stop freq vcc 5v ldo ilim oc q vcc sw gnd 0 vcc in bst rsen ls driver hs driver ls _ fet hs _ fet pwm logic xs xr over-current timer current sense amplifer current modulator uv ov uv detect comparator ov detect comparator off timer on timer hs iiimit comparator loop comparator en 1.0v 0.8v 1meg 0.4v 0 0 fb pgood comparator reference pg + - - + figure 1?function block diagram
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 9 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. operation pwm operation the mp28258 is a fully-integrated, synchronous, rectified, step-down switch converter. the device uses constant-on-time (cot) control to provide fast transient response and easy loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) turns on whenever the feedback voltage (v fb ) is lower than the reference voltage (v ref )?a low v fb indicates insufficient output voltage. the input voltage and the frequency-set resistor determine the on period as follows: =+ ? 7 on in 9.3 r (k ) t(ns) 40ns v(v) 0.4 (1) after the on period elapses, the hs-fet enters the off state. by cycling hs-fet between the on and off states, the converter regulates the output voltage. the integrated low-side mosfet (ls-fet) turns on when the hs-fet is in its off state to minimize the conduction loss. shoot-through occurs when there is both hs-fet and ls-fet are turned on at the same time, causing a dead short between input and gnd. shoot-through dramatically reduces efficiency, and the mp28258 avoids this by internally generating a dead-time (dt) between when hs- fet is off and ls-fet is on, ls-fet is off and hs-fet is on. the device enters either heavy- load operation or light-load operation depending on the amplitude of the output current. heavy-load operation figure 2?heavy load operation during heavy-load operation?when the output current is high?the mp28258 enters continuous- conduction mode (ccm) where the hs-fet and ls-fet repeat the on/off operation described for pwm operation, the inductor current never goes to zero, and the switching frequency (f sw ) is fairly constant. figure 2 shows the timing diagram during this operation. light-load operation during light-load operation?when the output current is low?the mp28258 automatically reduces the switching frequency to maintain high efficiency, and the inductor current drops near zero.. when the inductor current reaches zero, the ls-fet driver goes into tri-state (high z). the current modulator controls the ls-fet and limits the inductor current to around -1ma as shown in figure 3. hence, the output capacitors discharge slowly to gnd through ls-fet, r1, and r2. this operation greatly improv es device efficiency when the output current is low. figure 3?light load operation light-load operation is also called skip mode because the hs-fet does not turn on as frequently as during heavy-load conditions. the frequency at which the hs-fet turns on is a function of the output current?as the output current increases, the time period that the current modulator regulates becomes shorter, and the hs-fet turns on more frequently. the switching frequency increases in turn. the output current reaches the critical level when the current modulator time is zero, and can be determined using the following equation: in out out out sw in (v v ) v i 2lf v ? = (2) the device reverts to pwm mode once the output current exceeds the critical level. after that, the switching frequency stays fairly constant over the output current range.
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 10 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. bs t n 1 lsg vc c c 3 s w l c o u t c 5 figure 4? floating driver and bootstrap charging the floating power mosfet driver is powered by an external bootstrap capacitor. this floating driver has its own uvlo protection with a rising threshold of 2.2v and a hysteresis of 150mv. the bootstrap capacitor is charges from vcc through n1 (fig. 4). n1 turns on when the ls- fet turns on and turns off when the ls-fet turns off. switching frequency mp28258 uses constant-on-time (cot) control because there is no dedicated oscillator in the ic. the input voltage is feed-forwarded to the on- time one-shot timer through the resistor r7. the duty ratio is kept as v out /v in , and the switching frequency is fairly constant over the input voltage range. the switching frequency can be determined with the following equation: 6 sw 7in delay in out 10 f(khz) 9.3 r (k ) v (v) t(ns) v(v) 0.4 v (v) = + ? (3) where t delay is the comparator delay, and equals approximately 40ns. mp28258 is optimized to operate at high switching frequency with high efficiency. high switching frequency makes it possible to use small-sized lc filter components to save system pcb space. jitter and fb ramp slope jitter occurs in both pwm and skip modes when noise in the v fb ripple propagates a delay to the hs-fet driver, as shown in figures 5 and 6. jitter can affect system stability, with noise immunity proportional to the steepness of v fb ?s downward slope. however, v fb ripple does not directly affect noise immunity. v re f v fb hs dr i ver v noise jitter v slo pe1 figure 5?jitter in pwm mode v fb hs dr i ver jitter v ref v slo pe2 v noise figure 6?jitter in skip mode ramp with large esr cap in the case of poscap or other types of capacitor with larger esr is applied as output capacitor. the esr ripple dominates the output ripple, and the slope on the fb is quite esr related. figure 7 shows an equivalent circuit in pwm mode with the hs-fet off and without an external ramp circuit. turn to application information section for design steps with large esr caps. figure 7?simplified circuit in pwm mode without external ramp compensation
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 11 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. to realize the stability when no external ramp is used, usually the esr value should be chosen as follow: sw on esr out tt 0.7 2 r c + (4) t sw is the switching period. ramp with small esr cap when the output capacitors are ceramic ones, the esr ripple is not high enough to stabilize the system, and external ramp compensation is needed. skip to application information section for design steps with small esr caps . figure 8?simplified circuit in pwm mode with external ramp compensation figure 8 shows a simplified external ramp compensation (r4 and c4) for pwm mode, with hs-fet off. chose r1, r2, r9 and c4 of the external ramp to meet the following condition: 12 9 sw 4 1 2 rr 11 r 2f c 5 rr ?? < + ?? + ?? (5) where: r4 c4 fb c4 iiii =+ (6) and the vramp on the v fb can then be estimated as: in out 12 ramp on 44 12 9 vv r//r vt rc r//rr ? = + (7) the downward slope of the v fb ripple then follows ? ? == out ramp slope1 off 4 4 v v v trc (8) as can be seen from equation 8, if there is instability in pwm mode, we can reduce either r4 or c4. if c4 can not be reduced further due to limitation from equation 5, then we can only reduce r4. for a stable pwm operation, the v slope1 should be design follow equation 9. sw on -3 esr out slope1 out out sw on tt +-rc io 10 0.7 2 -v v + 2lc t -t (9) io is the load current. in skip mode, the downward slope of the v fb ripple is the same whether the external ramp is used or not. figure9 shows the simplified circuit of the skip mode when both the hs-fet and ls- fet are off. figure 9?simplified circuit in skip mode the downward slope of the v fb ripple in skip mode can be determined as follow: () ref slope2 12 out v v (r r //ro) c ? = + (10) where ro is the equivalent load resistor. as described in figure 6, v slope2 in the skip mode is lower than that is in the pwm mode, so it is reasonable that the jitter in the skip mode is larger. if one wants a system with less jitter during light load condition, the values of the v fb resistors should not be too big, however, that will decrease the light load efficiency. when using a large-esr capacitor on, the output, add a ceramic capacitor with a value of 10uf or less to in parallel to minimize the effect of esl. soft start/stop mp28258 employs a soft start/stop (ss) mechanism to ensure smooth output during power up and power shut-down. when the en pin goes high, the internal ss voltage slowly ramps up. the output voltage smoothly ramps up
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 12 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. with the ss voltage. once ss voltage rises above the v ref , it continues to ramp up while the pwm comparator only compares the v ref and the fb voltage. at this point, the soft start finishes and it enters steady state operation. the ss time is set about 1ms internally. when the en pin goes low, an internal current source discharges the internal ss voltage. once the ss voltage falls below the v ref , the pwm comparator will only compare the v ref to the ss voltage. the output voltage will decrease smoothly with the ss voltage until the voltage level zeros out. power-good (pg) the pg pin is the open drain of a mosfet that connects to v cc or some other voltage source through a resistor (ex. 100k). the mosfet turns on with the application of an input voltage so that the pg pin is pulled to gnd before ss is ready. after fb voltage reaches 90% of v ref , the pg pin is pulled high after a 0.5ms delay. when the fb voltage drops to 85% of v ref , the pg pin will be pulled low. over-current protection (ocp) and short- circuit protection (scp) mp28258 has cycle-by cycle over-current limit control. the inductor current is monitored during the on state. and it has two optional ocp/scp protection modes: latch-off mode and hiccup mode. for mp28258dd, the hs-fet turns off when the inductor current exceeds the current limit and the ocp timer?set at 50 s?starts. the ocp triggers if the inductor current reaches or exceeds the current limit every cycle in those 50 s. the mp28258dd short-circuit protection (scp) occurs when dead shorts occur?when the inductor current exceeds the current limit and the fb voltage is lower than 50% of the v ref ?and will trigger the ocp.. for mp28258dd-a, it enters hiccup mode, that periodically restarts the part when the inductor current peak value exceeds the current limit and v fb drops below the under-voltage (uv) threshold. typically, the uv threshold is 50% below the ref voltage. in ocp/scp, mp28258dd-a will disable the output voltage power, discharge internal soft-start cap, and then automatically try to soft-start again. if the over-current circuit condition still holds after soft-start ends, it repeats this operation cycle until the over-current circuit condition disappears, and output rises back to regulation level. over/under-voltage protection (ovp/uvp) mp28258 monitors the output voltage through a resistor-divided feedback (fb) voltage to detect over and under voltage on the output. when the fb voltage is higher than 125% of the v ref , it will trigger the ovp. once it triggers the ovp, the ls-fet is always on while the hs-fet is off. it needs to power cycle to turn on again. conversely, the uvp triggers when the fb voltage falls below 50% of the v ref (0.815v) usually uvp accompanies a drop in the current limit and this results in scp. uvlo protection mp28258 has under-voltage lock-out protection (uvlo). when the input voltage is higher than the uvlo rising threshold voltage, the mp28258 powers up. it shuts off when the input voltage is lower than the uvlo falling threshold voltage. this is non-latch protection. thermal shutdown the mp28258 employs thermal shutdown by internally monitoring the junction temperature of the ic. if the junction temperature exceeds the threshold value (typically 150oc), the converter shuts off. this is non-latch protection. there is about 25oc hysteresis. once the junction temperature drops around 125oc, it initiates a soft start.
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 13 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. application information setting the output voltage-large esr caps for applications that electrolytic capacitor or pos capacitor with a controlled output of esr is set as output capacitors. the output voltage is set by feedback resistors r1 and r2. as figure 10 shows. figure10?simplified circuit of pos capacitor first, choose a value for r2. r2 should be chosen reasonably, a small r2 will lead to considerable quiescent current loss while too large r2 makes the fb noise sensitive. it is recommended to choose a value within 5k ? - 50k ? for r2, using a comparatively larger r2 when vo is low, etc.,1.05v, and a smaller r2 when vo is high. then r1 is determined as follow with the output ripple considered: out out ref 12 ref 1 vvv 2 rr v ? ? =? (11) out v is the output ripple determined by equation 20. setting the output voltage-small esr caps figure11?simplified circuit of ceramic capacitor when low esr ceramic capacitor is used in the output, an external voltage ramp should be added to fb through resistor r4 and capacitor c4.the output voltage is influenced by ramp voltage v ramp besides r divider as shown in figure 11. the v ramp can be calculated as shown in equation 7. r2 should be chosen reasonably, a small r2 will lead to considerable quiescent current loss while too large r2 makes the fb noise sensitive. it is recommended to choose a value within 5k ? -50k ? for r2, using a comparatively larger r2 when vo is low, etc.,1.05v, and a smaller r2 when vo is high. and the value of r1 then is determined as follow: 2 1 fb(avg) 2 out fb(avg) 4 9 r r= v r - (v -v ) r +r (12) the v fb(avg) is the average value on the fb, v fb(avg) varies with the vin, vo, and load condition, etc., its value on the skip mode would be lower than that of the pwm mode, which means the load regulation is strictly related to the v fb(avg) . also the line regulation is related to the v fb(avg) ,if one wants to gets a better load or line regulation, a lower vramp is suggested once it meets equation 9. for pwm operation, v fb(avg) value can be deduced from equation 13. 12 fb( avg) ref ramp 12 9 r//r 1 vvv 2r//rr =+ + (13) usually, r9 is set to 0 ? , and it can also be set following equation 14 for a better noise immunity. it should also set to be 5 timers smaller than r1//r2 to minimize its influence on vramp. 9 4sw 1 r 2c2f = (14) using equation 12 to calculate the output voltage can be complicated. to simplify the calculation of r1 in equation 12, a dc-blocking capacitor cdc can be added to filter the dc influence from r4 and r9. figure 12 shows a simplified circuit with external ramp compensation and a dc-blocking capacitor. with this capacitor, r1 can easily be obtained by using equation 15 for pwm mode operation. ?? = + out ref ramp 12 ref ramp 1 (v v v ) 2 rr 1 vv 2 (15) cdc is suggested to be at least 10 times larger than c4 for better dc blocking performance, and should also not larger than 0.47 f considering
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 14 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. start up performance. in case one wants to use larger cdc for a better fb noise immunity, combined with reduced r1 and r2 to limit the cdc in a reasonable value without affecting the system start up. be noted that even when the cdc is applied, the load and line regulation are still vramp related. figure12?simplified circuit of ceramic capacitor with dc blocking capacitor input capacitor the input current to the step-down converter is discontinuous and therefore requires a capacitor to supply the ac current to the step-down converter while maintaining the dc input voltage. ceramic capacitors are recommended for best performance and should be placed as close to the v in pin as possible. capacitors with x5r and x7r ceramic dielectrics are recommended because they are fairly stable with temperature fluctuations. the capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated as follows: out out cin out in in vv ii (1 ) vv = ? (16) the worst-case condition occurs at v in = 2v out , where: out cin i i 2 = (17) for simplification, choose the input capacitor with an rms current rating greater than half of the maximum load current. the input capacitance value determines the input voltage ripple of the converter. if there is an input voltage ripple requirement in the system, choose the input capacitor that meets the specification. the input voltage ripple can be estimated as follows:: out out out in sw in in in iv v v(1) fc v v = ? (18) under worst-case conditions where v in = 2v out : out in sw in i 1 v 4f c = (19) output capacitor the output capacitor is required to maintain the dc output voltage. ceramic or poscap capacitors are recommended. the output voltage ripple can be estimated as: out out out esr sw in sw out vv 1 v(1)(r ) fl v 8fc = ? + (20) in the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. the output voltage ripple is mainly caused by the capacitance. for simplification, the output voltage ripple can be estimated as: out out out 2 sw out in vv v(1) 8f lc v = ? (21) the output voltage ripple caused by esr is very small. therefore, an external ramp is needed to stabilize the system. the external ramp can be generated through resistor r4 and capacitor c4 following equation 5, 8 and 9. in the case of poscap capacitors, the esr dominates the impedance at the switching frequency. the ramp voltage generated from the esr is high enough to stabilize the system. therefore, an external ramp is not needed. a minimum esr value around 12m ? is required to ensure stable operation of the converter. for simplification, the output ripple can be approximated as: out out out esr sw in vv v(1)r fl v = ? (22) maximum output capacitor limitation should be also considered in design application. mp28258 has an around 1ms soft-start time period. if the output capacitor value is too high, the output voltage can?t reach the design value during the
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 15 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. soft-start time, and then it will fail to regulate. the maximum output capacitor value c o_max can be limited approximately by: o_max lim_avg out ss out c(i i)t/v =? (23) where, i lim_avg is the average start-up current during soft-start period. t ss is the soft-start time. inductor the inductor is necessary to supply constant current to the output load while being driven by the switched input voltage. a larger-value inductor will result in less ripple current that will result in lower output ripple voltage. however, a larger-value inductor will have a larger physical footprint, higher series resistance, and/or lower saturation current. a good rule for determining the inductance value is to design the peak-to- peak ripple current in the inductor to be in the range of 30% to 40% of the maximum output current, and that the peak inductor current is below the maximum switch current limit. the inductance value can be calculated by: out out sw l in vv l(1) fi v =? (24) where i l is the peak-to-peak inductor ripple current. the inductor should not saturate under the maximum inductor peak current, where the peak inductor current can be calculated by: out out lp out sw in vv ii (1 ) 2f l v =+ ? (25) recommend design example some design examples and recommended maximum output capacitor value with typical outputs are provided below when the ceramic capacitors is applied: table 1?1.2v v out (l = 2 h) v in (v) v out (v) c1 r7 ( ? ) r4 ( ? ) c4 (f) r1 ( ? ) r2 ( ? ) f sw (hz) 12 1.2 10 f*1 300k 499k 220p 12.1k 24.3k 450k 5 1.2 10 f*1 300k 390k 220p 12.1k 24.3k 440k table 2?1.8v v out (l = 2 h) v in (v) v out (v) c1 r7 ( ? ) r4 ( ? ) c4 (f) r1 ( ? ) r2 ( ? ) f sw (hz) 12 1.8 10 f*1 402k 499k 220p 30k 24.3k 480k 51.810 f*1 402k 390k 220p 30k 24.3k 460k table 3?2.5v v out (l = 4.2 h) v in (v) v out (v) c1 r7 ( ? ) r4 ( ? ) c4 (f) r1 ( ? ) r2 ( ? ) f sw (hz) 12 2.5 10 f*1 500k 453k 390p 21.5k 10k 500k 52.510 f*1 500k 453k 390p 21.5k 10k 500k table 4?3.3v v out (l = 6.5 h) v in (v) v out (v) c1 r7 ( ? ) r4 ( ? ) c4 (f) r1 ( ? ) r2 ( ? ) f sw (hz) 12 3.3 10 f*1 680k 470k 330p 31.6k 10k 500k 53.310 f*1 680k 470k 330p 31.6k 10k 500k table 5?5v v out (l = 8.8 h) v in (v) v out (v) c1 r7 ( ? ) r4 ( ? ) c4 (f) r1 ( ? ) r2 ( ? ) f sw (hz) 12 5 10 f*1 1m 750k 330p 53.6k 10k 500k table 6?recommended maximum output capacitor value (f sw =500 khz) recommended conditions: v in =12v, i out =3a v out (v) 1.2 1.8 2.5 3.3 5 c o_max ( f) 680 570 390 330 220 the detailed application schematic is shown in figure 13 when large esr caps are used, and figure14 and figure 15 when low esr caps are applied. the typical performance and circuit waveforms have been shown in the typical performance characteristics section. for more possible applications of this device, please refer to related evaluation board data sheets.
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 16 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical application schematic vin c1a tbd 25v l1 tbd c7 1nf r10 100k r5 499k r7 tbd 9 r3 0 r1 tbd r2 tbd en pg gnd vout in freq vcc en pg gnd gnd gnd fb sw sw bst mp28258 8 4 11 1 6 5 2 10 7 12 3 figure 13?typical application schematic with no external ramp vin c1a tbd 25v l1 tbd c4 tbd c7 1nf r10 100k r5 499k r7 tbd 9 r3 0 r1 tbd r9 0 r2 tbd c2e ns r4 tbd en pg gnd vout in freq vcc en pg gnd gnd gnd fb sw sw bst mp28258 8 4 11 1 6 5 2 10 7 12 3 figure 14?typical application schematic with low esr ceramic capacitor vin c1a tbd 25v l1 tbd c4 tbd c7 1nf r10 100k r5 499k r7 tbd 9 r3 0 cdc tbd r1 tbd r2 tbd c2e ns r4 tbd en pg gnd vout in freq vcc en pg gnd gnd gnd fb sw sw bst mp28258 8 4 11 1 6 5 2 10 7 12 3 figure 15?typical application schematic with low esr ceramic capacitor\ and dc blocking capacitor
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) mp28258 rev 1.14 www.monolithicpower.com 17 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. layout recommendation 1) the high current paths (gnd, in, and sw) should be placed very close to the device with short, wide, and direct traces. 2) put the input capacitors as close to the in and gnd pins as possible. 3) put the decoupling capacitor as close to the v cc and gnd pins as possible. 4) keep the switching node sw short and away from the feedback network. 5) the external feedback resistors should be placed next to the fb pin. make sure that there is no via on the fb trace. 6) keep the bst voltage path (bst, c3, and sw) as short as possible. 7) four-layer layout is recommended to achieve better thermal performance.
mp28258 ? 3a, 4.2v-20v input, fast transient sy nchronous step-down converter in qfn12 (2x3mm) notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp28258 rev 1.14 www.monolithicpower.com 18 9/25/2012 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. package information qfn12 (2x3mm) side view top view bottom view 1.90 2.10 2.90 3.10 0.00 0.05 pin 1 id marking recommended land pattern note: 1) all dimensions are in millimeters . 2) exposed paddle size does not include mold flash . 3) lead coplanarity shall be 0.10 millimeter max. 4) jedec reference drawing is jedec mo -220 5) drawing is not to scale . pin 1 id index area 1 11 7 5 0.45 0.55 0.50 bsc 0.20 0.30 0.35 0.45 0.80 1.00 0.20 ref 6 12 0.35 0.45 0.60 0.50 0.25 1.90 0.70 0.00 1.10 0.35 0.45 0.40 0.35 0.45 0.00 1.30 0.20 0.20 0.30 1.45 0.90 0.25 1.80 0.70 0.25 0.60

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