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preliminary specifications ?2006 silicon storage technology, inc. s71297-01-000 7/06 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mpf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. 16 mbit (x16) multi-purpose flash plus sst39wf1601 / SST39WF1602 features: ? organized as 1m x16 ? single voltage read and write operations ? 1.65-1.95v ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption (typical values at 5 mhz) ? active current: 5 ma (typical) ? standby current: 5 a (typical) ? auto low power mode: 5 a (typical) ? hardware block-protection/wp# input pin ? top block-protection (top 32 kword) for SST39WF1602 ? bottom block-protection (bottom 32 kword) for sst39wf1601 ? sector-erase capability ? uniform 2 kword sectors ? block-erase capability ? uniform 32 kword blocks ? chip-erase capability ? erase-suspend/erase-resume capabilities ? hardware reset pin (rst#) ? security-id feature ? sst: 128 bits; user: 128 bits ? fast read access time: ? 90 ns ? latched address and data ? fast erase and word-program: ? sector-erase time: 36 ms (typical) ? block-erase time: 36 ms (typical) ? chip-erase time: 140 ms (typical) ? word-program time: 28 s (typical) ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bits ? data# polling ? cmos i/o compatibility ? jedec standard ? flash eeprom pin assignments and command sets ? packages available ? 48-ball tfbga (6mm x 8mm) ? 48-ball wfbga (5mm x 6mm) ? all non-pb (lead-free) devices are rohs compliant product description the sst39wf1601/1602 devices are 1m x16 cmos multi-purpose flash plus (mpf+) manufactured with sst?s proprietary, high-performance cmos superflash technology. the split-gate cell design and thick-oxide tun- neling injector atta in better reliability and manufacturability compared with alternate approaches. the sst39wf1601/ 1602 write (program or erase) with a 1.65-1.95v power supply. these devices conf orm to jedec standard pin assignments for x16 memories. featuring high performance word-program, the sst39wf1601/1602 devices provide a typical word-pro- gram time of 28 sec. t hese devices use toggle bit or data# polling to indicate the completion of program opera- tion. to protect against inadvertent write, they have on-chip hardware and software data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. data retention is rated at greater than 100 years. the sst39wf1601/1602 devices are suited for applica- tions that require convenient and economical updating of program, configuration, or data memory. for all system applications, they significantly improve performance and reliability, while lowering powe r consumption. they inher- ently use less energy during erase and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the super- flash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. these devices also improve flexibility while lowering the cost for program, data, and configuration stor- age applications. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/program cycles. sst39wf160x2.7v 16mb (x16) mpf+ memories
2 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 to meet high density, surface mount requirements, the sst39wf1601/1602 are offered in both 48-ball tfbga and 48-ball wfbga packages. see figures 2 and 3 for pin assignments. device operation commands are used to initiate the memory operation func- tions of the device. commands are written to the device using standard microprocessor write sequences. a com- mand is written by asserting we# low while keeping ce# low. the address bus is latc hed on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. the sst39wf1601/1602 also have the auto low power mode which puts the device in a near standby mode after data has been accessed with a valid read operation. this reduces the i dd active read current from typically 9 ma to typically 5 a. the auto low power mode reduces the typi- cal i dd active read current to the range of 2 ma/mhz of read cycle time. the device exits the auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. note that the device does not enter auto-low power mode after power-up with ce# held steadily low, until the first address transition or ce# is driven high. read the read operation of the sst39wf1601/1602 is con- trolled by ce# and oe#, both have to be low for the sys- tem to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is dese- lected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 4). word-program operation the sst39wf1601/1602 are programmed on a word-by- word basis. before programming, the sector where the word exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the pro- gram operation, once initiated, will be completed within 40 s. see figures 5 and 6 for we# and ce# controlled pro- gram operation timing diagrams and figure 20 for flow- charts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal pro- gram operation, the host is free to perform additional tasks. any commands issued during the internal program opera- tion are ignored. during the command sequence, wp# should be statically held high or low. sector/block-e rase operation the sector- (or block-) erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. the sst39wf1601/1602 offer both sector- erase and block-erase modes. the sector architecture is based on uniform sector size of 2 kword. the block-erase mode is based on uniform block size of 32 kword. the sector-erase operation is initiated by executing a six-byte command sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the block- erase operation is initiated by executing a six-byte com- mand sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of- erase operation can be determined using either data# polling or toggle bit methods. see figures 10 and 11 for timing waveforms and figure 24 for the flowchart. any commands issued during the sector- or block-erase oper- ation are ignored. when wp# is low, any attempt to sector- (block-) erase the protected block will be ignored. during the command sequence, wp# should be statically held high or low.
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 3 ?2006 silicon storage technology, inc. s71297-01-000 7/06 erase-suspend/erase- resume commands the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an erase operation. the operation is executed by issuing one byte command sequence with erase-suspend command (b0h). the device automatically enters read mode typically within 20 s after the erase-suspend command had been issued. valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase-suspended sectors/blocks will output dq 2 toggling and dq 6 at ?1?. while in erase-suspend mode, a word-program operation is allowed except for the sector or block selected for erase-suspend. to resume sector-erase or block-erase operation which has been suspended the system must issue erase resume command. the operation is executed by issuing one byte command sequence with erase resume command (30h) at any address in the last byte sequence. chip-erase operation the sst39wf1601/1602 provide a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 6 for the command sequence, figure 10 for tim- ing diagram, and figure 24 for the flowchart. any com- mands issued during the chip-erase operation are ignored. when wp# is low, an y attempt to chip-erase will be ignored. during the command sequence, wp# should be statically held high or low. write operation status detection the sst39wf1601/1602 provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the soft- ware detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which ini- tiates the internal program or erase operation. the actual completion of the nonvolatile write is asyn- chronous with the system; theref ore, either a data# poll- ing or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to pre- vent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. data# polling (dq 7 ) when the sst39wf1601/1602 are in the internal pro- gram operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase oper- ation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 7 for data# polling timing diagram and figure 21 for a flowchart.
4 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 toggle bits (dq6 and dq2) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. for sector-, block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or ce#) pulse. dq 6 will be set to ?1? if a read operation is attempted on an erase-suspended sector/block. if program operation is ini- tiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector is being actively erased or erase-suspended. table 1 shows detailed status bits information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or ce#) pulse of write operation. see figure 8 for toggle bit timing diagram and figure 21 for a flowchart. note: dq 7 and dq 2 require a valid address when reading status information. data protection the sst39wf1601/1602 provide both hardware and soft- ware features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit t he write operation. th is prevents inadvert- ent writes during power-up or power-down. hardware block protection the SST39WF1602 support top hardware block protec- tion, which protects the top 32 kword block of the device. the sst39wf1601 support bottom hardware block pro- tection, which protects the bottom 32 kword block of the device. the boot block address ranges are described in table 2. program and erase operations are prevented on the 32 kword when wp# is low. if wp# is left floating, it is internally held high via a pull-up resistor, and the boot block is unprotected, enabling program and erase opera- tions on that block. hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when the rst# pin is held low for at least t rp, any in-progress operat ion will terminate and return to read mode. when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place (see figure 16). the erase or program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. software data protection (sdp) the sst39wf1601/1602 provide the jedec approved software data protection scheme for all data alteration operations, i.e., program and erase. any program opera- tion requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. these devices are shipped with the software data protection permanently enabled. see table 6 for the specific software command codes. during sdp command sequence, invalid commands will abort the device to read mode within t rc. the contents of dq 15 -dq 8 can be v il or v ih , but no other value, during any sdp com- mand sequence. table 1: write operation status status dq 7 dq 6 dq 2 normal operation standard program dq 7 # toggle no toggle standard erase 0 toggle toggle erase- suspend mode read from erase-suspended sector/block 1 1 toggle read from non- erase-suspended sector/block data data data program dq 7 # toggle n/a t1.0 1297 table 2: boot block address ranges product address range bottom boot block sst39wf1601 000000h-007fffh top boot block SST39WF1602 0f8000h-0fffffh t2.0 1297
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 5 ?2006 silicon storage technology, inc. s71297-01-000 7/06 common flash memory interface (cfi) the sst39wf1601/1602 contain the cfi information to describe the characteristics of the device. the sst39wf1601/1602 support the original sst cfi query mode implementation for co mpatibility with existing sst devices as well as the general cfi query mode. both will be explained in subsequent paragraphs. in order to enter the sst cfi query mode, the system must write the three-byte sequence, same as the product id entry command with 98h (cfi query command) to address 5555h in the last byte sequence. once the device enters cfi query mode, the system can read cfi data at the addresses given in tables 7 through 9. the system must write the cfi exit command to return to read mode from the cfi query mode. in order to enter the general cfi query mode, the system must write a one-byte sequence with entry command with 98h to address 55h. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 7 through 9. the system must write the cfi exit command to return to read mode from the cfi query mode. product identification the product identification mode identifies the devices as the sst39wf1601, SST39WF1602 and manufacturer as sst. this mode may be a ccessed software operations. users may use the software product identification opera- tion to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see table 6 for software operation, figure 12 for the software id entry and read timing diagram and fig- ure 22 for the software id entry command sequence flowchart. product identification mode exit/ cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit/ cfi exit command is ignored during an internal program or erase operation. see table 6 for software command codes, figure 14 for timing waveform, and figures 22 and 23 for flowcharts. security id the sst39wf1601/1602 devices offer a 256-bit security id space. the secure id space is divided into two 128-bit segments - one factory programmed segment and one user programmed segment. the first segment is pro- grammed and locked at sst with a random 128-bit num- ber. the user segment is left un-programmed for the customer to program as desired. to program the user segment of the security id, the user must use the security id word-program command. to detect end-of-write for the sec id, read the toggle bits. do not use data# polling. once this is complete, the sec id should be locked using the user sec id program lock-out. this disables any future corrupt ion of this space. note that regardless of whether or not the sec id is locked, neither sec id segment can be erased. the secure id space can be queried by executing a three- byte command sequence with enter sec id command (88h) at address 5555h in the last byte sequence. to exit this mode, the exit sec id command should be executed. refer to table 6 for more details. table 3: product identification address data manufacturer?s id 0000h bfh device id sst39wf1601 0001h bf274b SST39WF1602 0001h bf274a t3.0 1297
6 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 1: functional block diagram figure 2: pin assignments for 48-ball tfbga y-decoder i/o buffers and data latches 1297 b1.0 address buffer & latches x-decoder dq 15 - dq 0 memory address oe# ce# we# superflash memory control logic wp# reset# a13 a9 we# nc a7 a3 a12 a8 rst# wp# a17 a4 a14 a10 nc a18 a6 a2 a15 a11 a19 nc a5 a1 a16 dq7 dq5 dq2 dq0 a0 nc dq14 dq12 dq10 dq8 ce# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss 1297 48-tfbga b3k p1.1 top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 7 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 3: pin assignments for 48-ball wfbga a2 a1 a0 ce# v ss a4 a3 a5 dq8 oe# dq0 a6 a7 a18 dq10 dq9 dq1 a17 wp# a19 dq2 nc dq3 nc v dd we# dq12 rst nc nc dq13 a9 a10 a8 dq4 dq5 dq14 a11 a13 a12 dq11 dq6 dq15 a14 a15 a16 dq7 v ss top view (balls facing down) a b c d e f g h j k l 6 5 4 3 2 1 1297 48-wfbga mbq p020 sst39wf160x
8 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 table 4: pin description symbol pin name functions a ms 1 -a 0 address inputs to provide memory addresses. during sector-erase a ms -a 11 address lines will select the sector. during block-erase a ms -a 15 address lines will select the block. dq 15 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. wp# write protect to protect the top/bottom boot bl ock from erase/program operation when grounded. rst# reset to reset and return the device to read mode. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 1.65-1.95v v ss ground nc no connection unconnected pins. t4.0 1297 1. a ms = most significant address a ms = a 19 for sst39wf1601/1602 table 5: operation modes selection mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector or block address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 6 t5.0 1297
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 9 ?2006 silicon storage technology, inc. s71297-01-000 7/06 table 6: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h erase-suspend xxxxh b0h erase-resume xxxxh 30h query sec id 5 5555h aah 2aaah 55h 5555h 88h user security id word-program 5555h aah 2aaah 55h 5555h a5h wa 6 data user security id program lock-out 5555h aah 2aaah 55h 5555h 85h xxh 6 0000h software id entry 7,8 5555h aah 2aaah 55h 5555h 90h sst cfi query entry 5555h aah 2aaah 55h 5555h 98h general cfi query mode 55h 98h software id exit 9,10 /cfi exit/sec id exit 5555h aah 2aaah 55h 5555h f0h software id exit 9,10 /cfi exit/sec id exit xxh f0h t6.0 1297 1. address format a 14 -a 0 (hex). addresses a 15 -a 19 can be v il or v ih , but no other value, for command sequence for sst39wf1601/1602. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence 3. wa = program word address 4. sa x for sector-erase; uses a ms -a 11 address lines ba x , for block-erase; uses a ms -a 15 address lines a ms = most significant address a ms = a 19 for sst39wf1601/1602 5. with a ms -a 4 = 0; sec id is read with a 3 -a 0 , sst id is read with a 3 = 0 (address range = 000000h to 000007h), user id is read with a 3 = 1 (address range = 000010h to 000017h). user id lock status is read with a 7 -a 0 = 0000ffh. unlocked: dq 3 = 1 / locked: dq 3 = 0. 6. valid word-addresses for sec id are from 000000h-000007h and 000010h-000017h. 7. the device does not remain in software product id mode if powered down. 8. with a ms -a 1 =0; sst manufacturer id = 00bfh, is read with a 0 = 0, sst39wf1601 device id = bf274bh, is read with a 0 = 1, SST39WF1602 device id = bf274ah, is read with a 0 = 1. a ms = most significant address a ms = a 19 for sst39wf1601/1602 9. both software id exit operations are equivalent 10. if users never lock after programming, sec id can be programm ed over the previously unprogramm ed bits (data=1) using the sec id mode again (the programmed ?0? bits cannot be reversed to ?1?). valid word-addresses for sec id are from 000000h-000007h and 000010h-000017h.
10 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 table 7: cfi query identification string 1 address data data 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0002h primary oem command set 14h 0000h 15h 0000h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t7.0 1297 1. refer to cfi publication 100 for more details. table 8: system interface information address data data 1bh 0016h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0020h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min. (00h = no v pp pin) 1eh 0000h v pp max. (00h = no v pp pin) 1fh 0005h typical time out for word-program 2 n s (2 5 = 32 s) 20h 0000h typical time out for min. size buffer program 2 n s (00h = not supported) 21h 0005h typical time out for individual sector/block-erase 2 n ms (2 5 = 30 ms) 22h 0007h typical time out for chip-erase 2 n ms (2 7 = 128 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x 2 5 = 64 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 5 = 64 ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 7 = 256 ms) t8.0 1297 table 9: device geometry information address data data 27h 0015h device size = 2 n bytes (15h = 21; 2 21 = 2 mbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of byte in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 00ffh sector information (y + 1 = numb er of sectors; z x 256b = sector size) 2eh 0001h y = 511 + 1 = 512 sectors (01ff = 511 2fh 0010h 30h 0000h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) 31h 001fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 31 + 1 = 32 blocks (001f = 31) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t9.0 1297
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 11 ?2006 silicon storage technology, inc. s71297-01-000 7/06 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 13.2v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. operating range range ambient temp v dd commercial industrial 0c to +70c -40c to +85c 1.65-1.95v 1.65-1.95v ac conditions of test input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 18 and 19
12 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 table 10: dc operating characteristics v dd = 1.65-1.95v 1 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht, at f=5 mhz, v dd =v dd max read 10 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 25 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 2 40 a ce#=v ihc , v dd =v dd max i alp auto low power 40 a ce#=v ilc , v dd =v dd max all inputs=v ss or v dd, we#=v ihc i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i liw input leakage current on wp# pin and rst# 10 a wp#=gnd to v dd or rst#=gnd to v dd i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.2v dd vv dd =v dd min v ih input high voltage 0.8v dd vv dd =v dd max v ol output low voltage 0.1 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.1 v i oh =-100 a, v dd =v dd min t10.0 1297 1. typical conditions for the active current shown on t he front page of the data sheet are average values at 25c (room temperature), and v dd = 1.8v. not 100% tested. 2. for all sst39wf160x commercial and industrial devices, i sb typical is under 5 a. table 11: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t11.0 1297 table 12: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t12.0 1297 table 13: reliability characteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. 2. n end endurance rating is qualified as a 10,000 cycl e minimum for the whole device. a sector- or block-level rating would result in a higher minimum specification. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t13.0 1297
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 13 ?2006 silicon storage technology, inc. s71297-01-000 7/06 ac characteristics table 14: read cycle timing parameters v dd = 1.65-1.95v symbol parameter sst39wf1601/1602-90 units min max t rc read cycle time 90 ns t ce chip enable access time 90 ns t aa address access time 90 ns t oe output enable access time 50 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 40 ns t ohz 1 oe# high to high-z output 40 ns t oh 1 output hold from address change 0 ns t rp 1 rst# pulse width 500 ns t rhr 1 rst# high before read 50 ns t ry 1,2 2. this parameter applies to sector-erase, block-erase and program operations. this parameter does not apply to chip-erase operations. rst# pin low to read mode 20 3 3. this parameter is 100 s if reset after an erase operation. s t14.0 1297 table 15: program/erase cycle timing parameters symbol parameter min max units t bp word-program time 40 s t as address setup time 0 ns t ah address hold time 50 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 50 ns t wp we# pulse width 50 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 50 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 50 ms t be block-erase 50 ms t sce chip-erase 200 ms t15.0 1297
14 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 4: read cycle timing diagram figure 5: we# controlled program cycle timing diagram 1297 f03.1 address a 19-0 dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 1297 f04.1 address a 19-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1s after the command sequence. x can be v il or v ih, but no other value.
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 15 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 6: ce# controlled prog ram cycle timing diagram figure 7: data# polling timing diagram 1297 f05.1 address a 19-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# ce# t bp note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1s after the command sequence. x can be v il or v ih, but no other value. 1297 f06.1 address a 19-0 dq 7 data data# data# data we# oe# ce# t oeh t oe t ce t oes
16 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 8: toggle bits timing diagram figure 9: we# controlled chip-erase timing diagram 1297 f07.1 address a 19-0 dq 6 and dq 2 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs 1297 f08.1 address a 19-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchangeable as l ong as minimum timings are met. (see table 15.) wp# must be held in proper logic state (v ih ) 1 s prior to and 1s after the command sequence. x can be v il or v ih, but no other value.
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 17 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 10: we# controlled block-erase timing diagram figure 11: we# controlled sector-erase timing diagram 1297 f09.1 address a 19-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# ce# six-byte code for block-erase t be t wp note: this device also supports ce# contro lled block-erase operation. the we# and ce# signals are interchangeable as l ong as minimum timings are met. (see table 15.) ba x = block address wp# must be held in proper logic state (v ih ) 1 s prior to and 1s after the command sequence. 1297 f10.1 address a 19-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled sector-erase operation. the we# and ce# signals are interchangeable as l ong as minimum timings are met. (see table 15.) sa x = sector address wp# must be held in proper logic state (v ih ) 1 s prior to and 1s after the command sequence.
18 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 12: software id entry and read figure 13: cfi query entry and read 1297 f11.1 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1s after the command sequence. device id - see table 3 x can be v il or v ih, but no other value. 1297 f12.1 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1s after the command sequence. x can be v il or v ih, but no other value.
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 19 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 14: software id exit/cfi exit figure 15: sec id entry 1297 f13.1 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1s after the command sequence. x can be v il or v ih, but no other value. 1297 f20.1 address a 19-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx88 note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1s after the command sequence. x can be v il or v ih, but no other value.
20 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 16: rst# timing diagram (when no internal operation is in progress) figure 17: rst# timing diagram (during program or erase operation) 1297 f22.0 rst# ce#/oe# t rp t rhr 1297 f23.1 rst# ce#/oe# t rp t ry end-of-write detection (toggle-bit)
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 21 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 18: ac input/output reference waveforms figure 19: a test load example 1297 f14.1 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1297 f15.1 to tester to dut c l v dd 25k 25k
22 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 20: word-program algorithm 1297 f16.0 start load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxa0h address: 5555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed x can be v il or v ih, but no other value
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 23 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 21: wait options 1297 f17.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
24 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 22: software id/cfi entry command flowcharts 1297 f21.0 load data: xxaah address: 5555h software product id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h cfi query entry command sequence load data: xx55h address: 2aaah load data: xx98h address: 5555h wait t ida read cfi data load data: xxaah address: 5555h sec id query entry command sequence load data: xx55h address: 2aaah load data: xx88h address: 5555h wait t ida read sec id x can be v il or v ih , but no other value load data: xx98h address: 55h general cfi query entry command sequence wait t ida read cfi data
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 25 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 23: software id/cfi exit command flowcharts 1297 f18.0 load data: xxaah address: 5555h software id exit/cfi exit/sec id exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation x can be v il or v ih, but no other value
26 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 24: erase command sequence 1297 f19.0 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait t se sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait t be block erased to ffffh x can be v il or v ih, but no other value
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 27 ?2006 silicon storage technology, inc. s71297-01-000 7/06 product ordering information valid combinations for sst39wf1601 sst39wf1601-90-4c-b3k sst39wf1601-90-4c-b3ke sst39wf1601-90-4c-mbqe sst39wf1601-90-4i-b3k sst39wf1601-90-4i-b3ke sst39wf1601-90-4i-mbqe valid combinations for SST39WF1602 SST39WF1602-90-4c-b3k SST39WF1602-90-4c-b3ke SST39WF1602-90-4c-mbqe SST39WF1602-90-4i-b3k SST39WF1602-90-4i-b3ke SST39WF1602-90-4i-mbqe note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. environmental attribute e 1 = non-pb package modifier k = 48 balls q = 48 balls (66 possible positions) package type b3 = tfbga (6mm x 8mm) mb = wfbga (5mm x 6mm) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 90 = 90 ns hardware block protection 1 = bottom boot-block 2 = top boot-block device density 160 = 16 mbit voltag e w = 1.65-1.95v product series 39 = multi-purpose flash 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. sst 39 wf 1602 - 90 - 4c - b3k e xx x xxxx x - xxx -x x -xx x x
28 preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 ?2006 silicon storage technology, inc. s71297-01-000 7/06 packaging diagrams figure 25: 48-ball thin-profile, fine-pitch ball grid array (tfbga) 6mm x 8mm sst package code: b3k a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.20 0.45 0.05 (48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-4 note: 1. complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm
preliminary specifications 16 mbit multi-purpose flash plus sst39wf1601 / SST39WF1602 29 ?2006 silicon storage technology, inc. s71297-01-000 7/06 figure 26: 48-ball very-very-thin-profile, fine -pitch ball grid array (wfbga) 5mm x 6mm sst package code mbq table 16: revision history number description date 00 ? initial release oct 2005 01 ? added mbq package information including product numbers. ? migrated document to preliminary specifications ? updated table 10 on page 12 jul 2006 l k j h g f e d c b a abcdefghjkl 6 5 4 3 2 1 6 5 4 3 2 1 0.50 0.50 bottom view 5.00 0.08 0.32 0.05 (48x) 6.00 0.08 2.50 5.00 a1 corner top view 48-wfbga-mbq-5x6-32mic-0 1mm detail side view seating plane 0.20 0.06 0.73 max. 0.636 nom. 0.08 a1 indicator note: 1. although many dimensions are similar to those of jedec publication 95, mo-225, this specific package is not registered. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.08 mm 4. ball opening size is 0.29 mm ( 0.05 mm) silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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