S7600A datasheet 1999/ o c t o b er seiko instruments inc. 1 tcp/ip protocol stack lsi S7600A sii - de s igned ichip s - 7600a, by u s ing lo w po w e r cm o s de s ign, c ontains t c p/ip p r oto c ol sta c k s that a c t a s a n a c c e le r a to r bet w een mpu and inte r net or network w hi ch uses tcp/ip protocol. ichip S7600A -- de s igned to p r ovide inte r net c onne c tivit y to devi c e s u s ing popular microcontrollers -- provides the functionality necessary for remote m anage m ent and m onito r i ng appli c ation s , po r table e m ail, inte r net do w nload s , network access, and much more. ichip S7600A is a completely self-contained, drop-in solution for any device r equi r i ng net w o r k ing c onne c tivit y and w ill p r ovide a high c onne c t s peed w i th low power consumption -- integrating full tcp/ip, ppp, and udp protocols, and 10k of on-chip sram for those protocol supports. the chip is based upon iready's internet tuner? technology. features tcp/ip ver.4 / udp/ ppp 2 general sockets low clock rat e bit-rate x 4 low power consumptio n less than 3 mw at 256 khz operating speed 68/80(moto/intel) mpu bus interface uart interface wide operating voltage rang e 2.4 ~ 3.6v stand-by mode pin assignment figure 1 txd rtsx dtrx dcd rxd ri dsrx ctsx vss clk test resetx 12 ti4 ti5 ti6 ti7 vdd to1 to2 to3 to4 to5 to6 to7 1 48 37 36 25 24 13 ti3 rs cs c86 readx vss psx writex intctrl int1 int2x busyx sd7 nc ti2 sd6 ti1 vdd sd5 sd4 sd3 sd2 sd1 sd0
tcp/ip network protocol stack lsi s-7600a S7600A datasheet 1999/ o c t o b e r 2 seiko instruments inc. block diagram figure 2 dimensions figure 3 unit : mm 48 lqfp 7x7 1.4t mpu interface ctsx network stack physical layer interface sram 10kbytes sd(7:0) cs psx c86 rs readx writex busyx intctl int1 int2x dsrx ri rxd dcd dtrx rtsx txd resetx clk ppp ip udp tcp sram interface
tcp/ip network protocol stack lsi S7600A datasheet 1999/ o c t o b e r s-7600a seiko instruments inc. 3 function of each pin table 1 function of each pin name i/o description vdd1,vdd2 - positive power supply vss1,vss2 - gnd potential resetx i reset input test, ti1 to ti7 i test input (built in pull-down resistor) to1 to to7 o test output clk i clock input ctsx i clear to send input dsrx i data set ready input ri i ring indicator input rxd i serial received data input dcd i data carrier detect input dtrx o data terminal ready output rtsx o request to send output txd o serial transmit data output rs i register selection input cs i chip selection input c86 i mpu interface mode selection input( 1: 68k mode, 0: x80 mode) readx i x80 mode : read requirement input , 68k mode : enable input psx i parallel/serial interface selection input writex i x80 mode: write requirement input 68k mode: read/write selection input intctrl i int1/int2x drive type(cmos/od) selection input int1 *ot interrupt output(active high) from s-7600a chip to mpu int2x *ot interrupt output(active low) from s-7600a chip to mpu busyx o busy indicator output sd7 b x80/68k mode : data bus serial mode: serial data input sd6 b x80/68k mode : data bus serial mode: serial clock input sd5 b x80/68k mode : data bus serial mode: serial data output sd0 to sd4 b data bus *ot: three-state output
tcp/ip network protocol stack lsi s-7600a S7600A datasheet 1999/ o c t o b e r 4 seiko instruments inc. absolute maximum ratings table 2 absolute maximum ratings parameter symbol condition rating unit storage temperature t sta -40 to +125 c operating temperature t opr -10 to +70 c operating voltage v dd ta=25 c -0.3 to 4.0 v input voltage v in ta=25 c vss-0.3 to vdd+0.3 v output voltage v out ta=25 c vss to vdd v recommended operating conditions table 3 recommended operating conditions parameter symbol conditions min. typ. max. unit note operating frequency range f opr ta=-10 to +70 c - 0.256 5 mhz 1 operating voltage range v dd ta=-10 to +70 c 2.4 - 3.6 v input voltage v in ta=-10 to +70 c 0 - vdd v note1: the clock is inputted by clk pin and needs integer times of the baud rate. (integer tolerance <2%) mpu interface overview the s-7600a supports two mpu interfaces: parallel and serial. in parallel interface mode, s-7600a can interface with x80 family mpu or 68k family mpu. table 4 interface selection psx cs rs readx writex busyx c86 sd7 sd6 sd5 sd4 to sd0 h: parallel x80 cs rs readx writex busyx l d7 d6 d5 d4 to d0 h: parallel 68k cs rs e r/wx busyx h d7 d6 d5 d4 to d0 l: serial cs rs h or l r/wx busyx h or l si scl so hi-z parallel interface setting psx to h select the parallel interface. in parallel interface mode the s-7600a can interface with either x80 family mpu and 68k family mpu. the desired mpu mode can be selected by setting the c86 pin to h or l. table 5connection relationship between mpu and pins rs 68 family mpu writex(r/wx) 80 family mpu function readx writex 1 1 0 1 read register 1 0 1 0 write register 0 1 0 1 read index register 0 0 1 0 write index register
tcp/ip network protocol stack lsi S7600A datasheet 1999/ o c t o b er s-7600a seiko instruments inc. 5 68k family mpu mode this mode can be selected by pulling the c86 input pin h and the psx input pin h. in this mode, the address and data are muxed into a single 8-bit bus. all cycles start by placing an address on the bus and setting the rs pin to l. in this mode writex signal works as read/write(r/wx) signal and readx is the enable (e) signal for 68k family mpu interface. after the address cycle, the mpu generates a read or writes strobe by setting the readx and writex pins. the s-7600a mpu interface logic assert a busyx signal low during data write and read phases. the mpu samples the busyx bit before starting a new cycle. the can initiate a new cycle if the bit is h. x80 family mpu mode this mode is selected by pulling the c86 input pin l and the psx input pin h. in this mode, the address and data are muxed onto a single 8-bit bus. all cycles start with the address placed on the bus. this address is then latched internally on the rising edge of writex . the rs pin l indicates that the writex strobe is for the address phase. in the next phase, data is either written or read by generating writex or readx strobe. the mpu interface logic will assert the busyx signal after readx or writex strobes are de-asserted. the busyx signal is de-asserted after the s-7600a complete a read or writes operation. the mpu samples the busyx bit before starting a new cycle. the mpu can initiate a new cycle after the busyx signal gets de-asserted. serial interface this mode is selected by pulling the psx input pin l. in this mode bit 6 of the data bus is used as the serial clock and bit 5 and 7 are used as data input and data output. bit 0 to 4 are high impedance. by pulling writex signal to h or l, the mpu performs a read or write operation. interrupt the interrupt signal outputs an active level while the interrupt flag is set in the interrupt register in the s-7600as interru pt register. the interrupt signal returns to an inactive level if the flag clears. the int1 and int2x can be open drain or cmos output depending on the setting of intctl . the int1 and int2x outputs are cmos if intctl is h otherwise outputs are open drain. table 7 defines the interrupt selection. table 7 interrupt selection interrupt flag intctl int1 int2x set h h l set l h l reset h l h reset l hi-z hi-z
tcp/ip network protocol stack lsi s-7600a S7600A datasheet 1999/ o c to b er 6 seiko instruments inc. s-7600a register definitions overview this section covers the s-7600a's api registers. the registers are divided into three types: global, direct and indexed. global registers occupy the address space from 0x00 to 0x1d and 0x60 to 0x6f. direct and indexed registers occupy the configuration space from 0x20 to 0x3f. indexed registers require the socket index to be set prior to accessing the register. iapi register map table 8 and table 9 shows the complete iapi register map for the s-7600a chip. all registers not listed are reserved, and shou ld not be accessed. table 8 iapi register map add register bit definitions 0x00 revision major revision number minor revision number 0x01 general_control - - - - - - - sw_ rst 0 x 0 2 genera l _ s o c k e t _ lo c a t i o n s1 s0 0 0 0 0 0 0 1 1 0 x 0 4 m a s t er_ i n t errup t - - - - - p t_ int link _int sock_i nt 0 x 0 8 s e r i a l _ p or t _ con f i g s _ d a v loop back mode dc d dsr/ hwfc cts r i d tr rts sctl 0x09 serial_port_int pint dsint - - - - - - 0x0a serial_port_int_ mask pint _en dsint_ en ------ 0x0b serial_port_data serial data register 0x0c - 0x0d baud_rate_div baud rate divider registers 0x10 - 0x13 our_ip_address our ip address 0x1c clock_div_low low byte for 1 khz clock divider 0x1d clock_div_high high byte for 1 khz clock divider 0x20 index socket index 0x21 tos* type of service field 0x22 socket_ config_status_low* to buff_ empty buff_ full data_ avail/ rst -protocol_type 0x23 socket_status_mid* urg rst term conu tcp state 0x24 socekt_activate - - - --- s1 s0 0x26 socket_interrupt - - - --- i1 i0 0x28 socket_data_avail - - - - - - dav1 dav0 note: 1) reserved bits are signified by a dash (-). all reserved bits should be written as 0. 2) indexed registers are signified by an asterisk (*).
tcp/ip network protocol stack lsi S7600A datasheet 1999/ o c to b e r s-7600a seiko instruments inc. 7 table 9 iapi register map (continued) add register bit definitions 0x2a socket_interrupt_ mask_low* to_ en buff_ emp_ en buff_f ull data_ avail_ en ---- 0x2b socket_interrupt_ mask_high* urg_en rst_ en term_ en conu en ---- 0x2c socket_interrupt_low* to buff_ empty buff_ full data_ avail ---- 0x2d socket_interrupt_high* urg rst te r m conu - - - - 0x2e socket_data* socket 8-bit data 0x30 tcp_data_send (wo)* any write causes data to be sent 0x30 - 0x31 buffer_out (ro)* buffer out length 0x32 - 0x33 buffer_in (ro)* buffer in length 0x34 - 0x35 urgent_data_pointer* urgent data offset pointer, udp datagram size 0x36 - 0x37 their_port* target port address 0x38 - 0x39 our_port* our port address 0x3a socket_status_high* - - - - - - - snd_ bsy 0x3c - 0x3f their_ip_address* target ip address 0x60 ppp_control_status ppp_int con_ val use_ pap to_ dis ppp_ int_en kick ppp_ en ppp_ up / srset 0x61 ppp_interrupt_code interrupt code 0x62 ppp_max_retry - ppp maximum retry 0x64 ppp_string pap user name and password 0x6f ppp test control - - - - test bypass - loop back note: 1) reserved bits are signified by a dash (-). all reserved bits should be written as 0. 2) indexed registers are signified by an asterisk (*).
tcp/ip network protocol stack lsi s-7600a S7600A datasheet 1999/ o c to b er 8 seiko instruments inc. application example in case of 80 family mpu with lcd controller figure 4 80 family mpu example lcd controller (s-4592,etc.) s-7600a 80 family mpu -personal computer -modem -pdc -piafs driver/ receiver decoder ps writex readx cs sd0 to sd7 rs res wr wr rd rd d0 to d7 iorq a1 to a7 a0 reset c86 c86 psx cs rs d0 to d7 res seiko instruments inc. 1-8, nakase, mihama-ku, chiba-shi, chiba 261, japan components sales div. telephone : +81-43-211-1196 facsimile : +81-43-211-8032 e-mail : component@sii.co.jp seiko instruments usa inc. electronic components div. 2990 w. lomita blvd, torrance, ca 90505, usa telephone : +1-909-934-9334 facsimile : +1-909-975-5699 e-mail : seiko-ecd@salessupport.com h t t p://www.seiko-usa-ecd.com notice if the products, systems, or assemblies, incorporating seiko instruments inc. tcp/ip network protocol stack lsi infringe upon any patent, copyright, or other intellectual property right, seiko instruments inc. shall not be responsible for any matters or damages arising out of or in connection with such patent copyright or other intellectual property right infringement.
s-7600a reliability test data (october, 1999) test condition duration result high temp operation* t a = 125 0 c, v dd = v opr max 1,000 hr 0/22 high temp bias* t a = 125 0 c, v dd = 0.9*v abs max 1,000 hr 0/22 high humidity & t a = 85 0 c, rh == 85%, v dd = 0.9*v abs max 1,000 hr 0/22 high temp bias* unsaturated pressure t a = 85 0 c, rh == 85%, v dd = 0.9*v abs max 1,000 hr 0/22 cooker bias* p = p a *2*10 8 high temp storage* t a = 150 0 c 1,000 hr 0/22 low temp storage* t a = -65 0 c 1,000 hr 0/22 temp cycle* t a = -65 0 c to +150 0 c, 30 min each 200 cycles 0/22 thermal shock* t a = -65 0 c to +150 0 c, 5 min each 100 cycles 0/22 (liquid to liquid) solderability t = 230 0 c 5 seconds 0/11 lead strength pull force = 1.0 newton 30 seconds 0/11 lead strength force = 0.5 newton, 2 x 0/11 (bending test) 45 degree bend a lead esd v = 2,000 v, c = 100 pf, r = 1,500 ohms 5 pulses 0/20 referenced to v dd /v ss latch up +/- 100 ma (v clamp = v abs max) 1 pulse 0/5 10 ms pulse, v dd = v opr max notes: result = number of failures / sample quantity v abs max = absolute maximum voltage v opr max = maximum operating voltage ?*? indicates that this test is performed after ?pre-treatment?: 1. high temp storage (+125 0 c) for 24 hours, plus 2. high humidity (65%) with high temp storage (+85 0 c) for 168 hours, plus 3. soldering heat (245 0 c) for 10 seconds.
|
