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march, 1999 data sheet general description features lxt980/980a dual-speed, 5-port fast ethernet repeater with integrated management support the lxt980 is a 5-port 10/100 class ii repeater that is fully compliant with ieee 802.3 standards. four ports directly support either 100base-tx/10base-t copper media or 100base-fx fiber media via pseudo-ecl (pecl) interfaces. the fifth port, a 10 or 100 mbps media independent interface (mii), connects to media access controllers (macs) for bridge/switch applications. at 100 mbps, the mii can also be configured to interface to another phy device, such as the lxt970. this data sheet applies to all lxt980 products (lxt980, lxt980a, and any subsequent variants), except as specifically noted. the lxt980 provides auto-negotiation with parallel detection for the four phy ports. these ports can also be manually configured, either by hardware or software. the lxt980 provides two internal repeater state machines one operating at 10 mbps and one at 100 mbps. once configured, the lxt980 automatically connects each port to the appropriate repeater. the lxt980 also provides two inter-repeater backplanes (irbs) for expansion one operating at 10 mbps and one at 100 mbps. up to 240 ports can logically be combined into one repeater using these buses. the lxt980 supports snmp and rmon management via on-chip 32- and 64-bit counters. the counters and control information are accessible via a high-speed serial management interface (smi). the device supports two source address tracking registers per port and a source address matching function. ? four 10/100 ports with complete twisted-pair phys including integrated filters and 100base-fx pecl interfaces. ? 10/100 mii port connection to either mac or phy. ? independent segments for 10 and 100 mbps operation. ? cascadable inter-repeater backplanes (irbs). ? hardware assist for rmon and the repeater mib. ? high-speed serial management interface (smi). ? two address-tracking registers per port. ? source address matching function. ? integrated led drivers with user-selectable modes. ? available in 208-pin qfp package. ? case temperature range: 0-115 c. revision 1.4 10base-t repeater 100base-x repeater mii led drivers 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy rmon & snmp counters 10 mbps backplane 100 mbps backplane serial port device management port switching logic 10m irb 100m irb mode control serial mgmt reversible mii port & mgmt status indicators twisted pair_i/o fiber_i/o twisted pair_i/o fiber_i/o twisted pair_i/o fiber_i/o twisted pair_i/o fiber_i/o lxt980/980a block dia g ram refer to www.level1.com for most current information. )
lxt980/980a dual-speed, 5-port fast ethernet repeater 2 table of contents pin assignments and signal descriptions ........................................................................................ ............. 4 functional description ......................................................................................................... ..........................15 introduction................................................................................................................... ..............................15 tp/fx port configuration ....................................................................................................... ................................18 forced operation ............................................................................................................... .............................18 auto-negotiation ............................................................................................................... ..............................18 link establishment and tp port connection...................................................................................... .............18 changing port speed on the fly ................................................................................................. ...................18 mii port configuration ......................................................................................................... ...................................18 interface descriptions......................................................................................................... ....................................19 twisted-pair interface ......................................................................................................... ............................19 fiber interface ................................................................................................................ .................................20 media independent interface (mii) .............................................................................................. ....................20 serial management interface .................................................................................................... ......................20 repeater operation ............................................................................................................. ...................................21 100 mbps repeater operation..................................................................................................... ...................21 10 mbps repeater operation ...................................................................................................... ....................21 management support ............................................................................................................. ................................22 configuration and status....................................................................................................... ..........................22 snmp and rmon support .......................................................................................................... ...................22 source address management...................................................................................................... ...................22 led drivers .................................................................................................................... ........................................22 requirements ................................................................................................................... ..........................23 power .......................................................................................................................... ...........................................23 clock .......................................................................................................................... ............................................23 bias current ................................................................................................................... ........................................23 reset .......................................................................................................................... ............................................23 prom........................................................................................................................... ..........................................23 chipid ......................................................................................................................... ...........................................23 management master i/o link ..................................................................................................... ............................23 irb bus pull-ups............................................................................................................... .....................................23 led operation.................................................................................................................. ..........................24 blink rates .................................................................................................................... .........................................24 power-up and reset conditions .................................................................................................. ..........................24 port leds ...................................................................................................................... .........................................24 segment leds ................................................................................................................... ....................................24 global leds .................................................................................................................... .......................................24 irb operation.................................................................................................................. ...........................28 mac irb access................................................................................................................. .................................. 28 irb isolation .................................................................................................................. ........................................ 28 mmstrin, mmstrout .............................................................................................................. ......................... 28 mii port operation ............................................................................................................. .........................29 phy mode operation ............................................................................................................. ................................30 mac mode operation............................................................................................................. ................................30 mii port timing considerations ................................................................................................. .............................31
3 lxt980/980a table of contents serial management interface .................................................................................................... ................. 32 serial clock ................................................................................................................... ........................................ 32 serial data i/o................................................................................................................ ........................................32 read and write operations...................................................................................................... ..............................32 management frame format ........................................................................................................ ...................32 auto-clearing registers ........................................................................................................ ..........................32 interrupt functions ............................................................................................................ .....................................34 address arbitration............................................................................................................ .....................................35 serial eeprom interface ........................................................................................................ ................. 37 application information ........................................................................................................ ......................... 38 general design guidelines ...................................................................................................... .................. 38 power supply filtering......................................................................................................... ................ 38 power and ground plane layout considerations ............................................................................... 37 mii terminations ............................................................................................................... ................... 39 the rbias pin .................................................................................................................. .................. 40 the twisted-pair interface..................................................................................................... .............. 39 the fiber interface ............................................................................................................ .................. 39 magnetics information .......................................................................................................... ............... 40 typical application circuitry .................................................................................................. ..................... 41 test specifications ............................................................................................................ ............................. 48 absolute maximum ratings ....................................................................................................... ................ 48 recommended operating conditions ............................................................................................... ......... 48 input clock requirements....................................................................................................... ................... 49 i/o electrical characteristics ................................................................................................. ..................... 49 100 mbps irb electrical characteristics ......................................................................................... ........... 50 10 mbps irb electrical characteristics .......................................................................................... ............ 51 100base-tx transceiver electrical characteristics.............................................................................. .... 51 100base-fx transceiver electrical characteristics.............................................................................. .... 52 10base-t transceiver electrical characteristics ................................................................................ ...... 52 100 mbps port-to-port delay timing ............................................................................................. ............. 53 100base-tx timing .............................................................................................................. .................... 54 100base-fx timing .............................................................................................................. .................... 58 10base-t timing ................................................................................................................ ...................... 62 100 mbps irb timing............................................................................................................. .................... 64 10 mbps irb timing.............................................................................................................. ..................... 65 serial management timing ....................................................................................................... ................. 67 prom interface timing.......................................................................................................... .................... 68 register definitions........................................................................................................... ............................. 69 counter registers .............................................................................................................. ........................ 69 ethernet address registers ..................................................................................................... .................. 73 control and status registers ................................................................................................... .................. 75 configuration registers........................................................................................................ ...................... 81 auto-negotiation registers ..................................................................................................... ................... 86 mechanical specifications...................................................................................................... ....................... 90 revision history ............................................................................................................... .............................. 91
lxt980/980a dual-speed, 5-port fast ethernet repeater 4 pin assignments and signal descriptions figure 1: pin assignments reset ..... 53 clk25 ..... 54 ir10iso ..... 55 ir100iso ..... 56 vcc ..... 57 reconfig ..... 58 srx ..... 59 stx ..... 60 serclk ..... 61 ser_match ..... 62 mmstrout ..... 63 arbout ..... 64 arbselect ..... 65 mgr_pres ..... 66 prom_clk ..... 67 prom_cs ..... 68 prom_dtout ..... 69 prom_dtin ..... 70 chipid0 ..... 71 chipid1 ..... 72 chipid2 ..... 73 auto_blink/gnd .. 74 gnd ..... 75 vcc ..... 76 rps_fault ..... 77 rps_pres ..... 78 macactive ..... 79 holdcol ..... 80 irq ..... 81 gnd ..... 82 gnd ..... 83 vcc ..... 84 col10_led ..... 85 col100_led ..... 86 mgr_led ..... 87 gnd ..... 88 vcc ..... 89 act10_led ..... 90 act100_led ..... 91 fault_led ..... 92 gnd ..... 93 vccv ..... 94 gndv ..... 95 vcc ..... 96 n/c ..... 97 rps_led ..... 98 port5_sel ..... 99 port5_spd ..... 100 n/c ..... 101 n/c ..... 102 n/c ..... 103 gndr ..... 104 208 .......ledsel0 207 .......ledsel1 206 .......vcc 205 .......vcc 204 .......vcc 203 .......vcc 202 .......gnd 201 .......vcc 200 .......gnd 199 .......mmstrin 198 .......arbin 197 .......config0 196 .......config1 195 .......config2 194 .......config3 193 .......config4 192 .......config5 191 .......config6 190 .......config7 189 .......port1_spd0 188 .......port1_spd1 187 .......port2_spd0 186 .......port2_spd1 185 .......port3_spd0 184 .......port3_spd1 183 .......port4_spd0 182 .......port4_spd1 181 .......port1_led1 180 .......port1_led2 179 .......port1_led3 178 .......gnd 177 .......port2_led1 176 .......port2_led2 175 .......port2_led3 174 .......gnd 173 .......port3_led1 172 .......port3_led2 171 .......port3_led3 170 .......vcc 169 .......vccv 168 .......gndv 167 .......gnd 166 .......port4_led1 165 .......port4_led2 164 .......port4_led3 163 .......gnd 162 .......port5_led1 161 .......port5_led2 160 .......port5_led3 159 .......gnd 158 .......gnd 157 .......fibip1 52 ......... ir100clk 51 ......... vcc 50 ......... gnd 49 ......... ir100dat4 48 ......... n/c 47 ......... n/c 46 ......... ir100dat3 45 ......... ir100dat2 44 ......... ir100dat1 43 ......... ir100dat0 42 ......... ir100dv 41 ......... ir100den 40 ......... ir100col 39 ......... n/c 38 ......... ir100sngl 37 ......... ir100cfsbp 36 ......... ir100cfs 35 ......... vcc 34 ......... gnd 33 ......... mii_rxd3 32 ........ mii_rxd2 31 ......... n/c 30 ......... mii_rxd1 29 ......... mii_rxd0 28 ......... vcc 27 ......... gnda 26 ......... mii_rxdv 25 ......... mii_rxclk 24 ......... mii_rxer 23 ......... n/c 22 .........mii_txer 21 ......... mii_txclk 20 .........mii_txen 19 ......... mii_txd0 18 ......... mii_txd1 17 ......... mii_txd2 16 ......... mii_txd3 15 ......... n/c 14 ......... mii_col 13 ......... mii_crs 12 ......... vcc 11 ......... gnd 10 ......... ir10clk 9 ........... ir10dat 8 ........... ir10ena 7 ........... n/c 6 ........... ir10den 5 ........... ir10cfsbp 4 ........... ir10colbp 3 ........... ir10col 2 ........... gnd 1 ........... ir10cfs tpip4......105 tpin4......106 vccr......107 tpop4......108 gndt......109 tpon4......110 vcct......111 fibop4......112 fibon4......113 sigdet4......114 fibin4......115 fibip4......116 gndr......117 tpip3......118 tpin3......119 vccr......120 tpop3......121 gndt......122 tpon3......123 vcct......124 fibop3......125 fibon3......126 sigdet3......127 fibin3......128 fibip3......129 gnda......130 rbias......131 gndr......132 tpip2......133 tpin2......134 vccr......135 tpop2......136 gndt......137 tpon2......138 vcct......139 fibop2......140 fibon2......141 sigdet2......142 fibin2......143 fibip2......144 gndr......145 tpip1......146 tpin1......147 vccr......148 tpop1......149 gndt......150 tpon1......151 vcct......152 fibop1......153 fibon1......154 sigdet1......155 fibin1......156 note: for pin 74 si g nal description, see table 9 on pa g e13 ( lxt980 ) and table 11 on pa g e14 ( lxt980a ) . xxxx xxxx LXT980AHC/ lxt980qc xxxxxx (date code) (part#) (trace code) (lot#)
5 lxt980/980a pin assignments and signal descriptions table 1: mode control signal descriptions pin symbol type 1 description 189 188 port1_spd0 port1_spd1 ttl input, pu, latched on reset speed select - ports 1 through 4. these pins set the default value of the port speed control register for the associated port as follows: 187 186 port2_spd0 port2_spd1 spd1 0 0 1 1 spd0 0 1 0 1 mode allow 10/100 auto-negotiation/parallel detection. force 10base-t. force 100base-fx. force 100base-tx. 185 184 port3_spd0 port3_spd1 183 182 port4_spd0 port4_spd1 100 port5_spd ttl input, pu speed select - port 5. selects operating speed of the mii (mac) interface. also selects the segment on which statistics are kept. high = 100 mbps. low = 10 mbps. (port 5 speed of 10 mbps is available when phy mode is selected.) 99 port5_sel ttl input, pu mode select - port 5. selects operating mode of the mii interface. pin is monitored at power-up and reset. subsequent changes have no effect. high = phy mode (lxt980 acts as phy side of the mii.) low = mac mode (lxt980 acts as mac side of the mii.) 197 196 195 194 193 192 191 190 config0 config1 config2 config3 config4 config5 config6 config7 ttl input, pd configuration register inputs. these inputs allow the user to store system-specific information (board type, plug-in cards, status, etc.) in the serial configuration register (address ac). this register may be read remotely through the serial management interface (smi). 1. nc = no clamp. pad will not clamp input in the absence of power. pu = input contains pull-up. pd = input contains pull-down. ttl = transistor-transistor logic. table 2: phy mode mii interface signal descriptions pin symbol type 1 description 29 30 32 33 mii_rxd0 mii_rxd1 mii_rxd2 mii_rxd3 output ttl receive data. the lxt980 transmits received data to the controller on these out- puts. data is driven on the falling edge of mii_rxclk. 26 mii_rxdv output ttl receive data valid. active high signal, synchronous to mii_rxclk, indicates valid data on mii_rxd<3:0>. 1. mii interface pins reverse direction based on phy/mac mode. direction listed is for phy mode.
lxt980/980a dual-speed, 5-port fast ethernet repeater 6 25 mii_rxclk output ttl receive clock. mii receive clock for expansion port. this is a 2.5 or 25 mhz clock derived from the clk25 input (refer to table 11). 24 mii_rxer output ttl receive error. active high signal, synchronous to mii_rxclk, indicates invalid data on mii_rxd<3:0>. 22 mii_txer input ttl transmit error. mii_txer is a 100m-only signal. the mac asserts this input when an error has occurred in the transmit data stream. the lxt980 responds by sending invalid code symbols on the line. 21 mii_txclk output ttl transmit clock. 2.5 or 25 mhz continuous output derived from the 25 mhz input clock. 20 mii_txen input ttl transmit enable. external controllers drive this input high to indicate that data is being transmitted on the mii_txd<3:0> pins. tie this input low if it is unused. 19 18 17 16 mii_txd0 mii_txd1 mii_txd2 mii_txd3 input ttl transmit data. external controllers use these inputs to transmit data to the lxt980. the lxt980 samples mii_txd<3:0> on the rising edge of mii_txclk, when mii_txen is high. 14 mii_col output ttl collision. the lxt980 drives this signal high to indicate that a collision has occurred. 13 mii_crs output ttl carrier sense. active high signal indicates lxt980 is transmitting or receiving. table 3: mac mode mii interface signal descriptions pin symbol type 1 description 29 30 32 33 mii_rxd0 mii_rxd1 mii_rxd2 mii_rxd3 input ttl receive data. the lxt980 receives data from the phy on these pins. data is sam- pled on the rising edge of mii_rxclk. 26 mii_rxdv input ttl receive data valid. the phy asserts this active high signal, synchronous to mii_rxclk, to indicate valid data on mii_rxd<3:0>. 25 mii_rxclk input ttl receive clock. mii receive clock for expansion port. this is a 25 mhz clock. 24 mii_rxer input ttl receive error. the phy asserts this active high signal, synchronous to mii_rxclk, to indicate invalid data on mii_rxd<3:0>. 22 mii_txer output ttl transmit error. the lxt980 asserts this signal when an error has occurred in the transmit data stream. 21 mii_txclk input ttl transmit clock. 25 mhz continuous input clock. must be supplied from same source as clk25 system clock. 1. mii interface pins reverse direction based on phy/mac mode. direction listed is for mac mode. table 2: phy mode mii interface signal descriptions C continued pin symbol type 1 description 1. mii interface pins reverse direction based on phy/mac mode. direction listed is for phy mode.
7 lxt980/980a pin assignments and signal descriptions 20 mii_txen output ttl transmit enable. the lxt980 drives this output high to indicate that data is being transmitted on the mii_txd<3:0> pins. 19 18 17 16 mii_txd0 mii_txd1 mii_txd2 mii_txd3 output ttl transmit data. the lxt980 drives these outputs to transmit data to the phy. the device drives mii_txd<3:0> on the rising edge of mii_txclk, when mii_txen is high. 14 mii_col input ttl collision. the phy asserts this active high signal to notify the lxt980 that a col- lision has occurred. 13 mii_crs input ttl carrier sense. the phy asserts this active high signal to notify the lxt980 that the phy is transmitting or receiving. table 4: inter-repeater backplane signal descriptions pin symbol type 1 description common irb signals 199 mmstrin ttl input pd, nc management master input. the management master (mm) daisy chain ensures that collisions are counted correctly in multi-board applications. attach the mmstrin input of each device to the mmstrout output of the previous device. ground mmstrin of the first or only device. 63 mmstrout ttl output management master output. mm daisy chain output. in hot-swap applications, a 1 k w - 3 k w resistor can be used as a by-pass between mmstrin and mmstrout. 100 mbps irb signals (refer to figure 21) 36 ir100cfs analog i/o 100 mbps irb collision force sense. a three-level signal that determines num- ber of active ports on the logical repeater. high level (5v) indicates no ports active; mid level (approx. 2.8v) indicates one port active; low level (0v) indi- cates more than one port active, resulting in a collision. this signal requires a 2 40w pull-up resistor, and connects between chips on the same board. 1. nc = no clamp. pad will not clamp input in the absence of power. pu = input contains pull-up. pd = input contains pull-down. i/o = input / output. od = open drain ttl = transistor-transistor logic even if the irb is not used, required pull-up resistors must be installed as listed above. table 3: mac mode mii interface signal descriptions C continued pin symbol type 1 description 1. mii interface pins reverse direction based on phy/mac mode. direction listed is for mac mode.
lxt980/980a dual-speed, 5-port fast ethernet repeater 8 37 ir100cfsbp analog i/o nc 100 mbps irb collision force sense - backplane. this three-level signal func- tions the same as ircfs; however, it connects between chips with chipid=0, on different boards. ir100cfsbp requires a single 91w pull-up resistor on each stack. 38 ir100sngl schmitt cmos i/o pu 100 mbps single driver state. this active low signal is asserted by the device with chipid = 000 when a packet is being received from one or more ports. this signal should not be connected between boards. 40 ir100col schmitt cmos i/o pu 100 mbps multiple driver state. this active low signal is asserted by the device with chipid = 000 when a packet is being received from more than one port (collision). it should not be connected between boards. 41 ir100den ttl output od 100 mbps irb driver enable. this output provides directional control for an external bidirectional transceiver (245) used to buffer the 100 mbps irb in multi-board applications. it must be pulled up by a 330 w resistor. when there are multiple devices on one board, tie all ir100den outputs together. if ir100den is tied directly to the dir pin on a 245, attach the on-board ir100dat, ir100clk, and ir100dv signals to the b side of the 245, and connect the off-board signals to the a side of the 245. 42 ir100dv schmitt cmos i/o od, pu 100 mbps irb data valid. this active low signal indicates port activity on the repeater. ir100dv frames the clock and data of the packet on the backplane. this signal requires a 120 w pull-up resistor. 43 44 45 46 49 ir100dat0 ir100dat1 ir100dat2 ir100dat3 ir100dat4 tri-state schmitt cmos i/o pu 100 mbps irb data. these bidirectional signals carry data on the 100 mbps irb. data is driven on the falling edge and sampled on the rising edge of ir100clk. these signals can be buffered between boards. 52 ir100clk tri-state schmitt cmos i/o pd 100 mbps irb clock. this bidirectional, non-continuous, 25 mhz clock is recovered from received network traffic. schmitt triggering is used to increase noise immunity. this signal must be pulled to vcc when idle. one 1 k w pull-up resistor on both side of a 245 buffer is recommended. 56 ir100iso ttl output 100 mbps stack backplane isolate. this output allows one lxt980 per board the ability to enable or disable an external bidirectional transceiver (245). attach the output to the enable input of the 245. the output is driven high (disable) to isolate the 100 mbps irb. table 4: inter-repeater backplane signal descriptions C continued pin symbol type 1 description 1. nc = no clamp. pad will not clamp input in the absence of power. pu = input contains pull-up. pd = input contains pull-down. i/o = input / output. od = open drain ttl = transistor-transistor logic even if the irb is not used, required pull-up resistors must be installed as listed above.
9 lxt980/980a pin assignments and signal descriptions 10 mbps irb signals (refer to figure 22) 9 ir10dat cmos i/o od, pd 10 mbps irb data. carries data on the 10 mbps irb. data is driven and sam- pled on the rising edge of the corresponding irclk. this signal must be pulled up by a 330 w resistor. between boards, this signal can be buffered. 10 ir10clk tri-state schmitt cmos i/o pd 10 mbps irb clock. this bidirectional, non-continuous, 10 mhz clock is recov- ered from received network traffic. during idle periods, the output is high-imped- anced. schmitt triggering is used to increase noise immunity. 6 ir10den ttl output od 10 mbps irb driver enable. this output provides directional control for an external bidirectional transceiver (245) used to buffer the irbs in multi-board applications. it must be pulled up by a 330 w resistor. when there are multiple devices on one board, tie all ir10den outputs together. if ir10den is tied directly to the dir pin on a 245, attach the on-board ir10dat, ir10clk and ir10ena signals to the b side of the 245, and connect the off-board signals to the a side of the 245. 8 ir10ena cmos i/o od, pu 10 mbps irb enable. this active low output indicates carrier presence on the irb. a 330 w pull-up resistor is required to pull the ir10ena output high when the irb is idle. when there are multiple devices, tie all ir10ena outputs together. this signal may be buffered between boards. 3 ir10col cmos i/o od, pu 10 mbps irb collision. this output is driven low to indicate that a collision has occurred on the 10 mbps segment. a 330 w resistor is required in each box to pull this signal high when there is no collision. this signal should not be connected between boards and it may not be buffered. 4 ir10colbp cmos i/o od, nc 10 mbps irb collision - backplane. this active low output has the same function as ir10col , but is used between boards. attach this signal only from the device with chipid = 0 to the backplane or connector, without buffering . the output must be pulled up by one 330 w resistor per system. 1 ir10cfs analog i/o od 10 mbps irb collision force sense. this three-state analog signal indicates transmit collision when driven low. ir10cfs requires a 680 w , 1% pull-up resistor. do not connect this signal between boards and do not buffer. 5 ir10cfsbp analog i/o od, nc 10 mbps irb collision force sense - backplane. functions the same as ir10cfs , but connects between boards. attach this signal only from the device with chipid = 0 to the backplane or connector, without buffering . this signal requires one 330 w , 1% pull-up resistor per system. 79 macactive ttl input pd mac active. a ttl-level signal. active high input allows external asics to participate in 10 mbps irb. driving data onto the irb requires that the external asic assert macactive high for one clock cycle, then assert i r10ena low. asic monitors ir10col (active low) for collision. by using macactive, the repeaternot the macdrives the three-level ir10cfs pin. table 4: inter-repeater backplane signal descriptions C continued pin symbol type 1 description 1. nc = no clamp. pad will not clamp input in the absence of power. pu = input contains pull-up. pd = input contains pull-down. i/o = input / output. od = open drain ttl = transistor-transistor logic even if the irb is not used, required pull-up resistors must be installed as listed above.
lxt980/980a dual-speed, 5-port fast ethernet repeater 10 55 ir10 iso ttl output 10 mbps irb isolate. by using ir10 is, one lxt980 per board can enable or disable an external bidirectional transceiver (245). attach the output to the enable input of the 245. driven high (disable) to isolate the 10 mbps irb. 80 holdcol ttl i/o pd hold collision for 10 mbps mode. this active high signal is driven by the device with chipid = 0 to extend a non-local transmit collision to other devices on the same board. the holdcol signals from different boards should not be attached together. table 5: twisted-pair port signal descriptions pin symbol type description 149, 151 136, 138 121, 123 108, 110 tpop1, tpon1 tpop2, tpon2 tpop3, tpon3 tpop4, tpon4 analog output twisted-pair outputs - ports 1 through 4. these pins are the positive and negative outputs from the respective ports twisted-pair line drivers. these pins can be left open when not used. 146, 147 133, 134 118, 119 105, 106 tpip1, tpin1 tpip2, tpin2 tpip3, tpin3 tpip4, tpin4 analog input twisted-pair inputs - ports 1 through 4. these pins are the positive and negative inputs to the respective ports twisted-pair receivers. these pins can be left open when not used. table 6: fiber port signal descriptions pin symbol type description 153, 154 140, 141 125, 126 112, 113 fibop1, fibon1 fibop2, fibon2 fibop3, fibon3 fibop4, fibon4 pecl output fiber outputs - ports 1 through 4. these pins are the positive and negative outputs from the respective ports pecl drivers. these pins can be left open when not used. 157, 156 144, 143 129, 128 116, 115 fibip1, fibin1 fibip2, fibin2 fibip3, fibin3 fibip4, fibin4 pecl input fiber inputs - ports 1 through 4. these pins are the positive and negative inputs to the respective ports pecl receivers. these pins can be left open when not used. 155 142 127 114 sigdet1 sigdet2 sigdet3 sigdet4 pecl input signal detect - ports 1 through 4. signal detect for the fiber ports. these pins can be left open when not used. table 4: inter-repeater backplane signal descriptions C continued pin symbol type 1 description 1. nc = no clamp. pad will not clamp input in the absence of power. pu = input contains pull-up. pd = input contains pull-down. i/o = input / output. od = open drain ttl = transistor-transistor logic even if the irb is not used, required pull-up resistors must be installed as listed above.
11 lxt980/980a pin assignments and signal descriptions table 7: serial management interface signal descriptions pin symbol type 1 description 58 reconfig ttl input pd, nc reconfigure . this input controls the driving of the clock signal on the high- speed serial management interface (serclk). when this input is high, the lxt980 drives serclk with a 625 khz output. when this input is low, serclk is an input to the lxt980. in addition, a low-to-high transition on reconfig causes the lxt980 to drive 13 continuous 0s on the smi, caus- ing a re-arbitration to occur. 62 ser_match ttl output serial match. the lxt980 device with chipid = 0 asserts this active high output whenever it detects a message on the smi that matches the local hub id. refer to figure 10 on page 34. 59 srx ttl input, pd serial receive. receive data input for high-speed serial management inter- face. must be tied to stx externally. srx is sampled on the rising edge of serclk. 60 stx ttl output od serial transmit. transmit data output for high-speed serial management interface. must be tied to srx externally. data transmitted on stx is com- pared with data received on srx. in the event of a mismatch, stx is put in the high impedance state. stx is driven on the falling edge of serclk. 61 serclk tri-state ttl i/o, pd serial clock. clock for serial management interface. depending on reconfig, this pin is either a 625 khz output or a 0 to 2 mhz input. 198 arbin ttl input, pd, nc arbitration in/out . used with chain arbitration. if used, tie arbin to arbout of the previous device. arbin at the top of the daisy chain can be connected to ground or to arbout of the scc. if unused, tie arbin high. 64 arbout ttl output nc 65 arbselect ttl input pu arbitration mode select. 0 = eeprom based, 1 = chain based. 66 mgr_pres ttl input nc, pu manager present. this signal is sensed at power up and hardware reset. if the signal is high, it indicates that no local manager is present, and the lxt980 enables all ports and sets all leds to operate in hardware mode. if it is low, indicating that a manager is present, the lxt980 disables all ports, pending control of network manager. 1. nc = no clamp. pad will not clamp input in the absence of power. pu = input contains pull-up. pd = input contains pull-down od = open drain ttl = transistor-transistor logic.
lxt980/980a dual-speed, 5-port fast ethernet repeater 12 table 8: led signal descriptions pin symbol type 1 description 208 207 ledsel0 ledsel1 ttl input pd led mode select . must be static. 00 = mode 1, 01 = mode 2, 10 = mode 3 181 177 173 166 162 port1_led1 port2_led1 port3_led1 port4_led1 port5_led1 ttl output led driver 1 - ports 1 through 5. programmable led driver. active low. refer to port leds on page 24. 180 176 172 165 161 port1_led2 port2_led2 port3_led2 port4_led2 port5_led2 ttl output led driver 2 - ports 1 through 5. programmable led driver. active low. refer to port leds on page 24. 179 175 171 164 160 port1_led3 port2_led3 port3_led3 port4_led3 port5_led3 ttl output led driver 3 - ports 1 through 5. programmable led driver. active low. refer to port leds on page 24. 85 col10_led ttl output 10 mbps collision led driver. active low indicates collision on 10mbps segment. 86 col100_led ttl output 100 mbps collision led driver. active low indicates collision on 100 mbps segment. 87 mgr_led ttl output manager present led driver. active low indicates manager present. 90 act10_led ttl output 10 mbps activity led driver. active low indicates activity on 10 mbps segment. 91 act100_led ttl output 100 mbps activity led driver. active low indicates activity on 100 mbps segment. 92 fault_led ttl output fault led driver. active low indicates global fault. 98 rps_led ttl output redundant power supply led driver. active low indicates rps fault. 1. pd = input contains pull-down. ttl = transistor-transistor logic
13 lxt980/980a pin assignments and signal descriptions table 9: power supply and indication signal descriptions pin symbol type 1 description 12, 28, 35, 51, 57, 76, 84, 89, 96, 170, 201, 203-206 vcc digital power supply inputs. each of these pins must be connected to a common +5 vdc power supply. a de-coupling capacitor to digital ground should be supplied for every one of these pins. 2, 11, 34, 50, 75, 82, 83, 88, 93, 158, 159, 163, 167, 174, 178, 200, 202 gnd digital ground. connect each of these pins to digital ground. 74 gnd ( lxt980 only ) digital ground. connect this pin to digital ground. note: for lxt980a, refer to table 11 on page 14. 94, 169 vccv analog vco supply inputs. each of these pins must be connected to a common +5 vdc power supply. a de-coupling capacitor to gndv should be supplied for every one of these pins. 95, 168 gndv analog vco ground . 111, 124, 139, 152 vcct analog transmitter supply inputs. each of these pins must be connected to a common +5 vdc power supply. a de-coupling capacitor to gndt should be supplied for every one of these pins. 109, 122, 137, 150 gndt analog transmitter ground. 107, 120, 135, 148 vccr analog receiver supply inputs. each of these pins must be connected to a common +5 vdc power supply. a de-coupling capacitor to gndr should be supplied for every one of these pins 104, 117, 132, 145, gndr analog receiver ground. 131 rbias analog rbias. used to provide bias current for internal circuitry. the 100 m a bias current is provided through an external 22.1 k w, 1% resistor to gnda. 27, 130 gnda analog analog ground. 78 rps_pres ttl input pd redundant power supply present. active high input indicates presence of redundant power supply. tie low if not used. 77 rps_fault ttl input pu redundant power supply fault. active low input indicates redundant power supply fault. the state of this input is reflected in the rps_led output (refer to table 8). tie high if not used. 1. pu = input contains pull-up. pd = input contains pull-down. ttl = transistor-transistor logic.
lxt980/980a dual-speed, 5-port fast ethernet repeater 14 table 10: prom interface signal descriptions pin symbol type 1 description 67 prom_clk tri-state ttl i/ o, pd prom clock. 1 mhz clock for reading prom data (chipid=0). if a prom is not used, this pin must be tied low. 68 prom_cs tri-state ttl output prom chip select. selects eprom. active high signal driven by chip with id of 0. 69 prom_dtou t tri-state ttl output prom data output. selects read instruction for eprom. active high signal driven only by chip with id of 0. 70 prom_dtin ttl input, pd prom data input. if prom not used, input tied low or high. 1. pd = input contains pull-down. ttl = transistor-transistor logic. table 11: miscellaneous signal descriptions pin symbol type 1 description 53 reset schmitt cmos input nc reset. this active low input causes internal circuits, state machines, and counters to reset (address tracking registers do not reset). on power-up, devices should not be brought out of reset until the power supply has stabilized and reached 4.5v. when there are multiple devices, it is recommended that all be supplied by a common reset that is driven by an ls14 or similar device. 54 clk25 schmitt cmos input 25 mhz system clock. drive with mos levels. 71 72 73 chipid0 chipid1 chipid2 ttl input, pd chip id. these pins assign unique chipids to as many as eight devices on a single board. one device on each board must be assigned chipid = 0. 74 auto_blink ( lxt980a only ) ttl input, pd auto_blink. setting this pin high disables the blink indication that shows a no link condition for port n led3. note: for lxt980, refer to table 9 on page 13. 81 irq ttl output od interrupt request. active low interrupt. refer to tables 65 and 71 for criteria and clearing options. 7, 15, 23, 31, 39, 47, 48, 97, 101, 102, 103, nc - no connects. leave these pins unconnected. 1. nc = no clamp. pad will not clamp input in the absence of power. pd = input contains pull-down. ttl = transistor-transistor logic.
lxt980/980a functional description 15 functional description introduction as a fully integrated ieee 802.3 repeater capable of 10 mbps and 100 mbps functionality, the lxt980 is a very versatile device allowing great flexibility in ethernet design solutions. figures 2, 3, and 4 show some typical applications, and figure 5 shows a more complete i/o cir- cuit. refer to application information (page 38) for spe- cific circuit implementations. this multi-port repeater provides four 10base-t/ 100base-tx/100base-fx ports. in addition, there is a bidirectional media independent interface (mii) expansion port that may be connected to either a 10/100 mac, or to a 100 mbps phy. the lxt980 provides two repeater state machines and two inter-repeater backplanes (irb) on a single chipone for 10 mbps operation and one for 100 mbps operation. the 100 mbps repeater fully meets ieee 802.3 class ii requirements. each ports operating speed may be selected independent of the other ports. the auto-negotiation capability of the lxt980 allows it to poll connected nodes and configure itself accordingly. the lxt980 incorporates full rmon support by providing on-chip counters and hardware assistance for a fully managed environment. the segmented backplane simplifies dual-speed operation, and allows multiple devices to be stacked and function as one logical repeater. up to 240 ports (192 tp ports and 48 mii ports) can be supported in a single cascade. figure 2: typical managed repeater architectures 10m backplane lxt980 device management 10base-t repeater 100base-t repeater mii led drivers 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy rmon & snmp counters 10 mbps backplane 100 mbps backplane serial port 100m backplane serial management scc (8530) lxt980 device management 10base-t repeater 100base-t repeater mii led drivers 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy rmon & snmp counters 10 mbps backplane 100 mbps backplane serial port lxt980 device management 10base-t repeater 100base-x repeater mii led drivers 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy rmon & snmp counters 10 mbps backplane 100 mbps backplane serial port mii-to-mii bridge (any 2 lxt980s) buffer 100m backplane buffer 10m backplane chassis backplanes
lxt980/980a dual-speed, 5-port fast ethernet repeater 16 figure 3: typical unmanaged 100 mbps repeater architectures figure 4: typical hybrid switch/repeater application lxt980 device mana g ement 10base-t repeater 100base-t repeater mii led drivers 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy rmon & snmp counters 10 mbps backplane 100 mbps backplane serial port lxt980 device mana g ement 10base-t repeater 100base-t repeater mii led drivers 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy rmon & snmp counters 10 mbps backplane 100 mbps backplane serial port lxt980 device mana g ement 10base-t repeater 100base-x repeater mii led drivers 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy rmon & snmp counters 10 mbps backplane 100 mbps backplane serial port led banks 100m backplane 100m backplane buffer chassis backplane 10m backplane lxt980 device management 10base-t repeater 100base-t repeater mii led drivers 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy rmon & snmp counters 10 mbps backplane 100 mbps backplane serial port 100m backplane serial mana g ement to scc (8530) lxt980 device management 10base-t repeater 100base-x repeater mii led drivers 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy 10/100 e'net phy rmon & snmp counters 10 mbps backplane 100 mbps backplane serial port mii switch connections 1 each for 10 m and 100m
17 lxt980/980a functional description figure 5: typical application block diagram tpop1 tpon1 tpip1 tpin1 tp2 tp3 tp4 xfmrs rj45s resistor packs irena irdat irclk prom_cs prom_dtout prom_clk prom_dtin irden isolate ircfs holdcol ircolbp ircol ircfsbp '245 inter- module irb to stack connector local irb to on- board lxt980 mmstrout mmstrin port leds prom chipid2 chipid1 chipid0 hubid assi g nment to next lxt980 mii_txclk mii_txd<3:0> mii_rxclk mii_rxd<3:0> mii_rxdv mii_rxer mii_col macactive mii (port 5, phy mode) input allows mac to drive irb (10m only) srx stx serclk reconfig mg_prsnt serial m g mt i/f 8530 scc lxt980 chipid assi g nment 4 tp ports independently switchable to either 10 or 100 m backplane irb100 2 independent irbs, 10 & 100 irb10 port1_led1 port1_led2 port1_led3 port2_led1 port2_led2 port2_led3 port3_led1 port3_led2 port3_led3 port4_led1 port4_led2 port4_led3 port5_led1 port5_led2 port5_led3 act10_led col10_led act100_led mgr_led rps_led fault_led col100_led se g ment leds fibop1 fibon1 fibip1 fibin1 fo2 fo3 fo4 fiber module 4 100 m fo ports local irb inter-module irb sigdet1 mii_txen mii_crs mii_txer global leds vcc
lxt980/980a dual-speed, 5-port fast ethernet repeater 18 tp/fx port configuration the lxt980 reads the hardware configuration pins at power-up, hardware reset, or software reset (but not at repeater reset), to determine operating conditions for each of its twisted-pair (tp) or fiber (fx) ports. each port has its own configuration pins so that it can be individually con- figured. software can monitor or change the configuration through the port speed control register (see table 61 on page 77). the four possible configurations for each port are summarized in table 12. forced operation a port can be directly configured to operate in one of three modes: 100fx, 100tx, or 10bt. when a port is configured for forced operation via hardware or software, it immediately begins operating in the selected mode. forced operation is the only way to enable 100fx operation. all links are established as half-duplex only. as a repeater, the lxt980 cannot support full-duplex operation. auto-negotiation any port can be configured to establish its link via auto-negotiation. the port and its link partner establish link conditions by exchanging fast link pulse (flp) bursts. each flp burst contains 16 bits of data that advertise the ports capabilities. the flp bursts sent by the port are maintained in its auto-negotiation advertisement register (table 81 on page 88). the link partners abilities are stored in the auto- negotiation link partner register (table 79 on page 86). status can be observed in the respective auto- negotiation status register (table 80 on page 87). each port has its own advertisement, link partner advertisement, and auto-negotiation status registers. when auto-negotiation is enabled, the capabilities advertised by the lxt980 are predetermined and cannot be changed; the advertisement register is read only, except for bit 13 (remote fault). the lxt980 always advertises 100 half duplex and 10 half duplex. it never advertises 10 or 100 full-duplex. if the link partner does not support auto-negotiation, the lxt980 determines link state by listening for 100 mbps idle symbols or 10 mbps link pulses. if it detects either of these signals, it configures the port and updates the status registers appropriately. link establishment and tp port connection once a port establishes link, the lxt980 automatically connects it to the appropriate repeater state machine. if link loss is detected and auto- negotiation is enabled, the port returns to the auto- negotiation state. changing port speed in order to change port speed while operating, the following sequence is required: ? disable the port(s) to be changed. ? set port speed control register to desired speed. ? perform a repeater reset (lxt980 will not read hardware configuration pins. refer to table 69 on page 81.) ? re-enable the port(s). note the entire repeater must be reset in order to change the port speed on any port. mii port configuration at power-up or reset, the mii is configured via external pins to one of the three modes of operation: ? 100 mbps, phy side of interfacefor interfacing to 100 mbps mac. ? 10 mbps, phy side of interfacefor interfacing to 10 mbps mac. ? 100 mbps, mac side of interfaceto drive fifth 100 mbps port via an lxt970 or other mii- compliant phy. in this mode, the external phy must be configured as either a 100-tx or 100-fx connection. table 12: manual speed selection spd1 spd0 speed selection 0 0 allow 10/100 auto-negotiation/ parallel detection on copper media 0 1 force port to 10base-t mode 1 0 force port to 100base-fx mode 1 1 force port to 100base-tx mode
19 lxt980/980a functional description interface descriptions the lxt980 provides four network interface ports. each port provides both a twisted-pair and a fiber interface. the twisted-pair interface directly supports 100base-tx (100tx) and 10base-t (10t) ethernet applications. a common termination circuit is used for both media types. the fiber interface indirectly supports 100base-fx (100fx) media through a pecl connection to an external fiber-optic transceiver. both interfaces fully comply with ieee 802.3 standards. twisted-pair interface the twisted-pair interface for each port consists of two differential signal pairs one for transmit and one for receive. the transmit signal pair is tpop/tpon, the receive signal pair is tpip/tpin. the twisted-pair interface for a given port is enabled when the port con- figuration is set to auto-negotiate, forced 10t or forced 100tx operation. the twisted-pair interface is dis- abled when 100fx is selected. the transmitter is current driven and requires magnet- ics with 2:1 turns ratio. a 400 w resistive load should be placed across the tpop/n pair, in parallel with the magnetics. the centertap of the primary side of the transmit winding must be tied to a quiet vcc for proper operation. when the twisted-pair interface is disabled, the transmitter outputs are tri-stated. the receiver requires magnetics with a 1:1 turns ratio, and a load of 100 w . when the twisted-pair port is enabled, the receiver actively biases its inputs to approximately 2.8v. when the twisted-pair interface is disabled, no biasing is provided. a 4 k w load is always present across the tpip/tpin pair. when used in 100tx applications, the lxt980 sends and receives a continuous, scrambled 125 mbaud mlt-3 waveform on this interface. in the absence of data, idle symbols are sent and received in order to keep the link up. when used in 10t applications, the lxt980 sends and receives a non-continuous, 10 mbaud manchester- encoded waveform. to maintain link during idle periods, the lxt980 sends link pulses every 16 ms, and expects to receive them every 10 to 20 ms. each 10base-t port automatically detects and sends link pulses, and disables its transmitter if link pulses are not detected. each receiver can also be configured to ignore link pulses, and leave its transmitter enabled all the time (link pulse transmission cannot be disabled). each 10base-t port can detect and automatically correct for polarity reversal on the tpip/n inputs. the 10base-t interface provides integrated filters using level ones patented filter technology. these filters facilitate low-cost system designs which meet emi requirements. in applications where the twisted-pair interface is not used, the inputs and outputs may be left unconnected.
lxt980/980a dual-speed, 5-port fast ethernet repeater 20 fiber interface each fiber interface consists of the fibop/fibon (transmit) and fibip/fibin (receive) signal pair. each interface also provides a signal detect input which can be tied to the corresponding output on the fiber transceiver for determining signal quality. the transmit pair is biased to approximately 1.5v and generally must be ac-coupled to the transceiver. the receive pair will accommodate an input bias in the 2v- 5v range, and can be dc-coupled to the transceiver. refer to figure 18 for a typical interface circuit. the fiber interface for each port is enabled when the speed select is set to 100fx, and is disabled in all other cases. when a fiber port is disabled, its outputs are pulled to ground, and its inputs are tri-stated. the input and output pins on unused fiber ports may be left unconnected. each fiber port transmits and receives a continuous, 1v peak-to-peak, non-scrambled, nrzi waveform. the lxt980 does not support scrambling or auto- negotiation on the fiber interface. remote fault reporting the sd pin detects signal quality and reports a remote fault if the signal quality starts to degrade. loss of signal quality also blocks any further data from being received and causes loss of the link. the remote fault code consists of 84 consecutive 1s followed by a single 0, and is transmitted at least three times. the lxt980 transmits the remote fault code and sets the associated interrupts when both of the following conditions are true: ? fiber mode is selected. ? signal detect indicates no signal, or the receive pll cannot lock. media independent interface the lxt980 supports a standard media independent interface (mii). this interface can be programmed to operate as either the phy or the mac side of the interface. when the mii is operating as the mac side of the interface (mac mode), it always operates at 100 mbps. when the mii is operating as the phy side of the interface (phy mode), it can be programmed to operate either at 10 mbps or at 100 mbps. once the mii is configured, the lxt980 automatically connects it to the corresponding internal repeater. note the mii does not support auto-negotiation, auto- speed, auto-link, or partition functions. on the lxt980, the mii always operates as a nibble- wide (4b) interface. symbol mode (5b interface) is not supported on the lxt980 mii. serial management interface the serial management interface (smi) provides system access to the status, control and statistic gathering abilities of the lxt980. this interface is designed to allow multiple devices to be managed from a single multi-drop (daisy-chain) connection, and to use the minimum number of signals (2) for ease of system design. the interface itself consists of two digital nrz signals clock and data. refer to table 7 on page 11 for serial management i/f pin assignments and signal descriptions. data is framed into hdlc-like packets, with a start/stop flag, header and crc field for error checking. zero-bit insertion/removal is used. the interface can operate at any speed from 0 to 2 mbps. address assignment is provided via one of two arbitration mechanisms which are activated whenever the device is powered up or reset/reconfigured. refer to the section on the smi (page 32).
21 lxt980/980a functional description repeater operation the lxt980 contains two internal repeater state machines one operating at 10 mbps and the other at 100 mbps. the lxt980 automatically switches each port to the correct repeater, once the operational state of that port has been determined. each repeater connects all ports configured to the same speed (including the mii), and the corresponding inter-repeater backplane. both repeaters perform the standard jabber, partition, and isolate functions as required. 100 mbps repeater operation the lxt980 contains a complete 100 mbps repeater state machine (100rsm) that is fully ieee 802.3 class ii compliant. any port configured for 100 mbps operation is automatically connected to the 100 mbps repeater. this includes any of the four media ports if they are configured for 100tx or 100fx operation, and the mii port if it is configured for 100 mbps oper- ation. the 100 mbps rsm has its own inter-repeater back- plane (100irb). multiple lxt980s can be cascaded on the 100irb and operate as one repeater segment. data from any port will be forwarded to any other port in the cascade. the 100irb is a 5-bit symbol-mode interface. it is designed to be stackable. the lxt980 maintains a complete set of statistics for its local repeater segment as long as the mii port is configured for 100 mbps operation. these are accessible through the high-speed management interface. the lxt980 performs the following 100 mbps repeater functions: ? signal amplification, wave-shape restoration, and data-frame forwarding. ? handling of received code violations. the lxt980 will substitute the h symbol for all invalid received codes. ? sop, soj, eop, eoj delay < 46bt; class ii com- pliant (see figure 25). ? collision enforcement. during a 100 mbps colli- sion, the lxt980 drives a 1010 jam signal (encoded as data 5 on tx links) to all ports until the collision ends. there is no minimum enforce- ment time. ? partition. the lxt980 partitions any port participating in excess of 60 consecutive collisions or one long collision approximately 575.2 m s long. once partitioned, the lxt980 continues monitoring and transmitting to the port, but does not repeat data received from the port until it properly un-partitions. ? un-partition. the lxt980 supports two un- partition algorithms. the default algorithm, which complies with the ieee 802.3 specification, un-partitions a port only when data can be transmitted to the port for 450-560 bit times without a collision on that port. ? the alternate un-partition algorithm is available through the management interface. the alternate algorithm will un-partition a port on either transmit or receive of at least 450-560 bits without collision on the partitioned port. ? isolate. the lxt980 isolates any port transmitting more than two successive false carrier events. a false carrier event is defined as a packet not starting with a /j/k symbol pair. note: this is not the same as 100irb isolate, which involves segmenting the backplane. ? un-isolate. the lxt980 will un-isolate a port that remains in the idle state for 33000 +/- 25% bt or that receives a valid frame at least 450- 500 bt in length. ? /t/r generation. the lxt980 can insert a /t/r symbol pair (end of stream delimiter) on any incoming packet that does not include one. this feature is optional, and is enabled through the management interface. ? jabber. the lxt980 ignores any receiver remaining active more than 57,500 bit times. the lxt980 exits this state when all jabbering receivers return to the idle condition. the isolate and symbol error functions do not apply to the mii port. 10 mbps repeater operation the lxt980 contains a complete 10 mbps repeater state machine (10rsm) that is fully ieee 802.3 compliant. any port configured for 10 mbps operation is automatically connected to the 10 mbps repeater. this includes any of the four media ports if they are configured for 10bt operation, and the mii port if it is configured for 10 mbps operation. the 10rsm has its own inter-repeater backplane (10irb). multiple lxt980s can be cascaded on the
lxt980/980a dual-speed, 5-port fast ethernet repeater 22 10irb and operate as one repeater segment. data from any port will be forwarded to any other port in the cascade. the 10irb is 1-bit wide and runs at 10 mhz. it is designed to be stackable. the lxt980 maintains a complete set of statistics on its repeater segment, as long as the mii port is configured for 10 mbps operation. these are accessible through the high-speed management interface. the lxt980 performs the following 10 mbps repeater functions: ? signal amplification, wave-shape restoration, and data-frame forwarding. ? preamble regeneration. all outgoing packets will have a minimum of 56 bits of preamble and 8 bits of sfd. ? sop, soj, eop, eoj delays meet requirements of ieee 802.3 section 9.5.5 and 9.5.6. ? collision enforcement. during a 10 mbps collision, the lxt980 drives a jam signal (1010) to all ports for a minimum of 96 bit times and until the collision ends. ? partition. the lxt980 will partition any port that participates in excess of 32 consecutive collisions. once partitioned, the lxt980 will continue monitoring and transmitting to the port, but will not repeat data received from the port until it properly un-partitions. ? un-partition. the lxt980 supports two un- partition algorithms. the default algorithm, which complies with the ieee 802.3 specification, un-partitions a port when data can be either received or transmitted from the port for 450-560 bit times without a collision on that port. ? the lxt980 also provides an alternate un- partition algorithm, which is available through the management interface. the alternate algorithm will un-partition a port only when data can be transmitted to the port for 450-560 bit times without a collision on that port. ? jabber. the lxt980 will assert a minimum-ifg idle period when any port remains actively transmitting for longer than 40,000 to 75,000 bit times. management support configuration and status the lxt980 provides management control and visibility of the following functions: ? reset and zeroing of counters ? auto-negotiation (control, status, advertise- ment, link partner) ? device and board configuration ? led functions ? source address tracking (per port) ? source address matching (per chip) ? device/revision id snmp and rmon support the lxt980 provides snmp and rmon support through its statistics gathering function. statistics are gathered on all data that flow through the device for each of the ports, including the mii. the lxt980 also maintains statistics for either the entire 10 or 100 mbps repeater, depending on the speed setting of the mii port. (two lxt980s are required to maintain statistics on both repeaters. since cascaded lxt980s operate as a single logical 10/100 repeater, any device in the cascade maintains the same 10 or 100 repeater statistics as any other device). all statistics are stored as 32- or 64-bit quantities. per-port counters include: source address management the lxt980 provides two source address manage- ment functions for all ports: source address tracking and source address matching. these functions allow a network manager to track source addresses at each port, or to identify any port that sourced a particular source address. led drivers the lxt980 provides 23 led drivers: ? 3 mode-selectable port led drivers (15 total) readable frames readable octets fcs errors alignment errors framestoolong shortevents runts collisions lateevents verylongevents dataratemismatch autopartitions broadcast multicast sa changes isolates symbol errors
23 lxt980/980a functional description ? 2 segment led drivers (4 total) ? 4 global led drivers refer to table 8 on page 12 for led interface pin assign- ments and signal descriptions. requirements power the lxt980 has four types of +5v power supply input pins (vcc, vccv, vccr, and vcct). these inputs may be supplied from a single power supply, although ferrites should be used to filter the power going to the analog and digital power planes. as a matter of good practice, these supplies should be as clean as possible. specific operating recommendations are shown in the test specifications sec- tion, table 25 on page 48. each supply input should be decoupled to its respective ground. refer to table 6 for power and ground pin assign- ments, and to design recommendations on page 38. clock a stable, external 25 mhz system clock source (cmos) is required by the lxt980. this is connected to the clk25 pin. refer to test specifications, table 26 on page 49, for clock input requirements. bias resistor the lxt980 requires a 22.1 k w , 1% resistor connecting its rbias input to ground. reset at power-up, the reset input must be held low until vcc reaches at least 4.5v. an ls14 or equivalent should be used to drive reset if there are multiple lxt980 devices (see figure 24 on page 47). prom an external, auto-incrementing 48-bit prom can be used for two purposes: ? to assign a unique id to all lxt980s on a board ? to support the eprom-based address arbitration mechanism on the serial management interface (refer to page 35) multiple devices on the same board can share a single common prom. the lxt980 with chipid = 0 actively reads the prom at power-up; all other lxt980s listen in. if prom arbitration is not used, the prom data input signal must be tied either high or low. refer to table 10 on page 14 for prom interface pin assignments and signal descriptions. chip id each lxt980 on a board requires a unique 3-bit chip id value asserted on these pins in order for the serial management interface (smi) to function correctly. one lxt980 on each board must be assigned chipid = 0. when substituting a lxt983 device the lxt983 can be substituted in lxt980 designs for a 10/100mbps unmanaged solution without changing the lxt980 chip id pin states. the lxt980 chip id 0, chip id 1, and chip id 2 pins are renamed fps , gnd, and gnd respectively for the lxt983. for cas- cading, the first lxt983 device is addressed 000 and all others 001 as indicated by the pin names. the lxt983 requires one chip to have the lxt980-equiv- alent address 000 and all other lxt983s a non-000 address. management master i/o link in multiple device applications, the management master daisy chain (mmstrin/mmstrout) ensures that collisions are counted correctly. connect the mmstrin input to the mmstrout output of the previous device, even across board boundaries. ground the mmstrin input of the first or only device in the system. in hot-swap applications, resistive bypassing can be used with a value between 1 and 3 k w . irb bus pull-ups even when the lxt980 is used in a stand-alone configuration, pull-up resistors are required on the irb signals listed below. see figures 21 and 22 on page 46 for sample circuits. 100 mbps irb 10mbps irb ir100cfs ir10dat ir100cfsbp ir10ena ir100dv ir10col ir100clk ir10cfs ir10colbp ir10cfsbp
lxt980/980a dual-speed, 5-port fast ethernet repeater 24 led operation the lxt980 provides three types of led indicators: port, segment, and global (refer to table 8 on page 12). three user-selectable led modes determine pin conditions and how particular conditions are indicated. the led mode is selected via the ledsel<1:0> pins and reflected in an internal register. the leds generally operate under hard- ware control although some limited software overrides are available. in addition to on and off states, some led driv- ers provide a blink state output. blink rates two programmable blink rates are provided. the default period for the slow blink rate is 1.6s. the default period is 0.4s for the fast blink rate. these rates may be changed via the led timer register. the slow blink rate is defined by the upper 8 bits and the fast blink rate is defined by the lower 8 bits of the led timer register. refer to tables 73-75 on page 84 for details. power-up and reset conditions during reset or power-up, all led drivers turn on steady and remain on for approximately 2 seconds after reset is cleared. after reset, the collision, activity, and redundant power supply leds revert to hardware control. the global fault and port leds revert to hardware control unless a manager is present in the system. port leds port leds provide status for the four twisted-pair ports and the mii port. the lxt980 has 3 led driver pins for each port as described in table 8. these pins drive standard leds. three user-selectable modes are provided for the port leds. port led states are also affected by port speed and auto-negotiation status, see tables 13 through 15. link loss during link loss, the speed led indicates10m, and the partition led indicates no partition, regardless of actual partition status. software overrides of port leds the port led control register allows limited soft- ware overrides of the port leds. two bits per port provide independent control of each port. however, all three leds for the respective port receive the same override (all port n leds will be simultaneously set to on, off, or blink). refer to tables 69 and 74 for cod- ing and bit assignments. segment leds these outputs can directly drive leds to indicate activity and collision status on a per segment basis. no software overrides are provided for these led drivers, and they are not affected by led mode selection. pulse stretchers are used to extend the on-time for these leds. collision leds the collision leds turn on for approximately 120 m s when the lxt980 detects a collision on the respective 10 mbps or 100 mbps segment. during the time that the collision led is on, any additional collisions are ignored by the collision led logic. activity leds the activity leds turn on for approximately 4 ms when the lxt980 detects any activity on the respective 10 mbps or 100 mbps segment. during the time that the activity led is on, any additional activity is ignored by the activity led logic. global leds these led driver outputs indicate global status conditions. manager present led when active, this led indicates the presence of a manager in the system. it is not affected by led mode selection and does not allow software overrides. global fault led the global fault led indicates one or more of the following conditions: any port partitioned, any port isolated or rps fault. how the condition is indicated depends on the led mode as shown in tables 13 through 15. software overrides of the global fault led two bits in the global led control register allow software overrides to control the global fault led. refer to tables 69 and 73 on pages 81 and 84 for coding and bit assignments. redundant power supply led the redundant power supply led is controlled by the rps_flt and rps_pres pins. the led state reflects the states of these two inputs, depending on the led mode selected as listed in tables 13 through 15.
25 lxt980/980a functional description table 13: led mode 1 indications led operating mode hardware control software control on blink off port n led1 10 mbps operation link up, not partitioned n/a any other state off via port led control register, address 0b2 100 mbps operation link up, not partitioned, not isolated n/a any other state port n led2 10 mbps operation link up, partitioned n/a any other state 100 mbps operation link up, partitioned or isolated n/a any other state port n led3 auto-neg enabled 100 mbps link up no link, (fast blink) 1 any other state auto-neg disabled 100 mbps link selected, link may be up or down n/a any other state rps any present, fault n/a any other state n/a global fault any any port partitioned, any port isolated or rps fault n/a any other state off via global led con- trol register, address 0b1 1. setting auto_blink (pin 74) high disables blink ( lxt980a only ).
lxt980/980a dual-speed, 5-port fast ethernet repeater 26 table 14: led mode 2 indications led operating mode hardware control software control on blink off port n led1 any 10m: port enabled, link up, not partitioned 100m: port enabled, link up, not partitioned, and not isolated 10m: port enabled, link up, and partitioned 100m: port enabled, link (partitioned or isolate) (slow blink) any other state on, off or fast blink via port led control register, address 0b2 port n led2 (lxt980) any n/a n/a always off port n led2 ( lxt980a ) 10 or 100 mbps ops receive activity (20 ms pulse) n/a any other state port n led3 auto-neg enabled 100 mbps link up no link (fast blink) 1 10 mbps link up auto-neg disabled 100 mbps selected, link may be up or down n/a 10 mbps selected, link may be up or down rps any present, no fault present, fault not present n/a global fault any n/a any port parti- tioned, any port isolated or rps fault (slow blink) any other state on, off, or slow blink via global led control register, address 0b1 1. setting auto_blink (pin 74) high disables blink ( lxt980a only ).
27 lxt980/980a functional description table 15: led mode 3 indications led operating mode hardware control software control on blink off port n led1 10 mbps operation link up, not parti- tioned n/a any other state off via port led control register, address 0b2 100 mbps operation link up, not parti- tioned, not isolated n/a any other state port n led2 10 or 100 mbps ops receive activity (20 ms pulse) n/a any other state port n led3 auto-neg enabled 100 mbps link up no link (fast blink) 1 10 mbps link up auto-neg disabled 100 mbps link selected, link may be up or down n/a 10 mbps link selected, link may be up or down rps any present, fault n/a any other state n/a global fault any any port partitioned, any port isolated or rps fault n/a any other state off via global led control register, address 0b1 1. setting auto_blink (pin 74) high disables blink ( lxt980a only ).
28 lxt980/980a dual-speed, 5-port fast ethernet repeater irb operation the inter repeater backplane (irb) allows multiple devices to operate as a single logical repeater, exchanging data collision status information. each segment on the lxt980 has its own complete, independent irb. the backplanes use a combination of digital and analog signals as shown in figure 6. irb signals can be characterized by connection type as local (connected between devices on the same board), stack (connected between boards) or full (connected between devices on the same board and between different boards). refer to tables 16 and 17 for details on buffering and pull-up requirements, and to figures 21 and figure 22 on page 46 for application circuitry. mac irb access the macactive ttl-level pin allows an external mac or other digital asic to interface directly to the 10 mbps irb. when the macactive pin is asserted, the lxt980 will drive the ir10cfs and ir10cfsbp signals on behalf of the external device, allowing it to participate in collision detection functions. irb isolation the isolate outputs (ir10iso and ir100iso) are provided to control the enable pins of external bidirectional transceivers. in multi-board applications, they can be used to isolate one board from the rest of the system. only one device can control these signals. the output states of these pins are controlled by the isolate bits in the master configuration register. note inter-board analog signals will be isolated internally by the device. mmstrin, mmstrout this daisy chain is provided for correct gathering of statistics in multiple-device configurations. in multiple- board applications, this daisy chain must be maintained across boards. in stand-alone applications, or for the first device in a chain, the mmstrin input must be pulled low in order for the management counters to work correctly. figure 6: irb block diagram mmstr out mmstr out digital irb signals include irndat, irnena and irnclk. local analog irb signals include irncol and irncfs. inter-board analog irb signals include irncolbp and irncfsbp. this diagram shows a single irb. the lxt980 actually has two independent irbs, one per speed/segment. '245 980 chipid = 0 980 chipid = 1 980 chipid = n hub board 1 digital irb signals analog irb signals mmstr out / in mmstr out / in mmstr out mmstr in isolate irden holdcol '245 980 chipid = 0 980 chipid = 1 980 chipid = n hub board 2 digital irb signals analog irb signals mmstr out / in mmstr out / in mmstr out mmstr in isolate irden holdcol '245 980 chipid = 0 980 chipid = 1 980 chipid = n hub board n digital irb signals analog irb signals mmstr out / in mmstr out / in mmstr out mmstr in isolate irden holdcol mmstr out / in holdcol is used on the 10mbps irb only.
29 lxt980/980a functional description table 16: irb signal types connection type connections between devices (same board) connections between boards full connect all. connect using buffers. local connect all. do not connect. stack for devices with chipid 1 0, pull-up at each device and do not interconnect . connect devices with chipid = 0 between boards. use one pull-up resistor per stack. special (xxiso) for devices with chipid 1 0, leave open. for device with chipid = 0, connect to buffer enable. do not connect. table 17: irb signal details name pad type buffer pull-up connection type 100 mbps irb signals ir100dat<4:0> digital yes no full ir100clk digital yes 1 k w full ir100dv digital, open drain yes 120 w full ir100cfs analog no 240 w , 1% local ir100cfsbp analog no 91 w , 1% 2 stack ir100col digitalnonolocal ir100sngl digitalnonolocal ir100den digital, open drain n/a 1 330 w local ir100iso digital n/a 1 no special 10 mbps irb signals ir10dat digital, open drain yes 330 w full ir10clk digital yes no full ir10ena digital, open drain yes 330 w full ir10cfs analog no 680 w , 1% local ir10cfsbp analog no 330 w , 1% stack ir10col analog no 330 w , 1% local ir10colbp analog no 330 w , 1% stack ir10den digital, open drain n/a 1 330 w local ir10iso digital n/a 1 no special 1. isolate and driver enable signals are provided to control an external bidirectional transceiver. 2. 91 w resistors provide greater noise immunity. systems using 91 w resistors are backwards stackable with systems using 100 w resistors.
30 lxt980/980a dual-speed, 5-port fast ethernet repeater mii port operation the lxt980 mii allows a mac or phy to directly connect into the repeater environment. the mii port (port 5) can operate at either 10 or 100 mbps. the lxt980 maintains the same statistics for this port as it does for the other 10/100 ports (except for illegal symbols). utilizing two lxt980s allows the user to have a mac interface to both the 10 and 100 mbps segments, in addition to providing segment statistics for both. the lxt980 does not provide mdio/mdc capability, as this is provided via the serial controller interface. mode and speed control is provided via port5_spd and port5_sel pins as listed in table 18. phy mode operation phy mode is available at both 10 and 100 mbps. it allows the lxt980 to interface to a 10 or 100 mbps mac. when operating at 100 mbps, the lxt980 passes the full 56 bits of preamble through before sending the sfd. when operating at 10 mbps, the lxt980 sends data across the mii starting with the 8-bit sfd (no preamble bits). mac mode operation mac mode (available at 100 mbps only) allows the user to attach an additional phy to the lxt980. in this mode the phy provides both mii_txclk and mii_rxclk. the mii_txclk must be frequency-locked to the 25 mhz oscillator used by the lxt980. the lxt980 does not provide an elasticity buffer to compensate for frequency differences. when operating in mac mode, the lxt980 generates the full 56 bits of preamble before sending the sfd across the mii. table 18: mii (port 5) mode & speed control port5_spd port5_sel speed & statistics mode high low 100 mbps mac low high 10 mbps phy high high 100 mbps phy figure 7: mii (port 5) operation mii_txd<3:0> mii_txen mii_txer mii_txclk mii_rxclk mii_rxd<3:0> mii_rxdv mii_rxer mii_crs mii_col mii_txclk mii_rxclk mii_rxd<3:0> mii_rxdv mii_rxer mii_txd<3:0> mii_txen mii_txer mii_crs mii_col lxt980 10/100 mac 100 mbps phy the lxt980 mii port is reversible. when phy mode is selected, the lxt980 acts as the phy side of the mii. in this mode an external mac sends tx data to the lxt980 to be repeated to the network. the lxt980 repeats network data to the mac via the rx data lines. when mac mode is selected, the lxt980 acts as the mac side of the mii. in this mode the lxt980 repeats network data to the phy via the tx data lines. the external phy sends data to the lxt980 to be repeated to the network via the rx data lines. port 1 port 2 port 3 port 4 port 5 phy mode tp ports mii port lxt980 port 1 port 2 port 3 port 4 port 5 mac mode tp ports mii port
lxt980/980a functional description 31 mii port timing considerations the ieee 802.3u specification provides propagation delay constraints for standard phy devices in section 24.6, and for repeater devices in section 27. the lxt980 mii port is a hybrid that does not fit either of these categories. the crit- ical consideration that applies to the lxt980 mii port is the overall end-to-end system propagation delay (132 bit times maximum). the lxt980 supports the intent of the class ii repeater application. figure 8 summarizes the propagation delay issues relevant to the lxt980 mii port. the lxt980 architecture treats the mii port as a fifth repeater port. the timing delay (latency) from the mii port to any other port meets the requirements for a class ii repeater ( 46 bt). it does not meet the requirements for a standard mii-phy interface (20 - 24 bt). when operating in mac mode with a phy connected to the lxt980 mii port (figure 8b), the fifth tp port does not have the latency characteristics of a class ii repeater with respect to the other ports. with a mac connected to the lxt980 mii port (figure 8d), the maximum latency to any other mac is 112 bt (not including cable delay). the mac connected to the lxt980 has an advantage relative to other macs because it has one less transceiver delay. figure 8: mii timing issues mii tp phy prop delay 20 bt mac mii tp phy prop delay 20 bt mac class ii rptr prop delay 46 bt tp mii mac class ii rptr prop delay 46 bt mii tp phy prop delay 20 bt mac mii tp phy prop delay 20 bt mac class ii rptr prop delay 46 bt tp mii class ii rptr prop delay 46 bt phy prop delay 20 bt prop delay 112 bt tp tp tp lxt980 port 5 (mii) operating in mac mode, connected to a phy device. lxt980 port 5 (mii) operating in phy mode, connected to a mac device. tp ports phy lxt980 meets class ii rptr prop delay ( 46 bt ) tp port mii port does not meet class ii rptr prop delay p1 p2 p3 p4 p5 mii port mii tp phy prop delay 20 bt mac mii tp phy prop delay 20 bt mac class ii rptr prop delay 46 bt class ii rptr prop delay 46 bt mii-to-mii prop delay 132 bt tp propagation delay requirements per ieee 802.3u: - phy prop delay (mii-tp) must be 20 bt - class ii repeater prop delay (tp-tp) must be 46 bt phy-to-mac prop delay 132 bt ab cd
lxt980/980a dual-speed, 5-port fast ethernet repeater 32 serial management i/f the high-speed serial management interface (smi) provides access to repeater mib variables, rmon statistics attributes and status and control information. a network manager can access the interface through a simple serial communications controller. the interface is designed to be used in a multi-drop configuration, allowing multiple lxt980 devices to be managed from one common line. the interface consists of a data input line (srx), data output line (stx), and a clock (serclk). it can operate at up to 2 mbps. the interface operates on a simple command response model, with the network manager as the master and the lxt980 devices as slaves. figure 9 is a simplified view of typical serial management interface architecture. refer to figure 23 on page 47 for circuit details. figure 9: typical serial bus architecture serial clock serclk is a bidirectional pin; direction control is provided by the reconfig input. if reconfig is high, the lxt980 will drive serclk at 625 khz. if reconfig is low, serclk is an input, between 0 and 2 mhz. there is no lower bound to how slow the interface can operate. the clock can be stopped after each operation, as long as an idle (16 ones in a row) is transmitted first. serial data i/o the serial data pins, srx and stx, should be tied together. the srx input is compared with the stx output. if a mismatch occurs, stx goes to a high impedance. stx is driven on the falling edge of serclk. srx is sampled on the rising edge. refer to test specifications (figure 39 on page 67) for timing information. read and write operations normally the network manager directs read and write operations to a specific lxt980 device using a two-part address consisting of hubid and chipid. the interface allows up to 127 32-bit registers to be read at one time. up to two registers can be written at a time. some registers may be automatically cleared when subsequent write operations are performed on other registers. refer to the auto-clearing registers section, which follows. management frame format the smi uses a simple frame format, which is shown in figure 10. table 19 describes the individual fields. table 20 shows how the bits for the header field would be stored in memory, assuming that they are transmitted lsb to msb, low address to high address. table 21 lists the command set and table 22 provides a variety of typical packets. all frames begin and end with a flag of consisting of 01111110. all fields are transmitted lsb first. zero- bit stuffing is required if more than five 1s in a row appear in the header, data or crc fields. in addition, all operations directed to the device must be followed by an idle (ten 1s in a row), and the first operation must be preceded with an idle. note the lxt980 uses the ccitt method of crc (x16 + x12 + x5 +1). auto-clearing registers two registers, the interrupt status register, see table 64 on page 79 and the search port match register, see table 55 on page 74, exhibit an auto clearing feature. how auto clearing works before executing any write command, the device first reads the most recently accessed register. if the accessed register was an auto-clearing register and set to auto-clear mode, it will be read and cleared. example: a read or write command is performed on the interrupt status register. next, a write command is performed on port status register. the write com- mand to the port status register causes an internal read of the interrupt status register. if the interrupt status register was set to auto-clear mode, it will be lxt918 lxt918 lxt980 rmon & repeater mib support 8530 serial controller network management user definable partitioning
33 lxt980/980a functional description read and clearedas a result of the write command to the port status register. because the read and clear is internal (and automatic), the user may not be aware that all data in register 1 is now lost. note the auto-clear behavior of the interrupt status register and the search port match register is determined by the auto-clear bit in the repeater configuration register (see table 70 on page 83). preserving auto-clearing register data to preserve auto-clearing data in either the interrupt status register or the search port match register, always follow any read or write command to these reg- isters with a read command to a register that does not auto clear. in other words, do not leave the read pointer on an auto-clearing register. example: if you read the interrupt status register (address: 0ae), immediately follow with a dummy read of the port link status register (address: 098). this dummy read moves the pointer, ensuring that the information in the interrupt status register is not inad- vertently lost through auto clearing. after the dummy read, you are now free to go perform any read or write operation without fear of losing data in the auto clearing registers. note: there is nothing inherently special about using one particular register for the dummy read instead of another. using the port link status register (in the preceding example) is only a suggestion; a read command to any other register that is not auto-clearing is also acceptable. table 19: serial management interface message fields message description start or stop flag 01111110. protocol requires zero insertion after any five consecutive 1s in the data stream. hub id identifies board or sub-system. assigned by one of two arbitration mechanisms at power-up. chip id identifies one of eight lxt980 devices on a board or sub-system. assigned by 3 external pins on each device. command identifies the particular operation being performed (see table 21) length specifies number of registers to be transferred (1 to 127). maximum is 2 per write, 127 per read. address specifies address of register or register block to be transferred.
lxt980/980a dual-speed, 5-port fast ethernet repeater 34 figure 10: serial management frame format interrupt functions the lxt980 provides a single open-collector pin for exter- nal interrupt signalling. seven different interrupt condi- tions may be reported. the interrupt status register identifies the specific interrupt condition (refer to table 65 on page 79). the interrupt mask register allows specific interrupts to be masked. interrupts may be cleared in two ways, depending on the status of bit 11 in the repeater configuration register (refer to table 71 on page 83). hub id 5 bits data (0-508 bytes) chip id cmd 5 bits length 7 bits address 12 bits 3 bits start flag header crc (2 bytes) stop flag idle idle header content: table 20: serial management header storage msb lsb increasing address addr 11 addr 10 addr 9 addr 8 addr 7 addr 6 addr 5 addr 4 addr 3 addr 2 addr 1 addr 0 length 6 length 5 length 4 length 3 length 2 length 1 length 0 cmd 4 cmd 3 cmd 2 cmd 1 cmd 0 chipid 2 chipid 1 chipid 0 hubid 4 hubid 3 hubid 2 hubid 1 hubid 0 table 21: serial management interface command set command value name usage normally sent by description 18 (hex) write normal ops network mgr used to write up to 2 registers (8 bytes) at a time. 04 (hex) read normal ops network mgr used to read up to 127 registers at a time. 08 (hex) request id arbitration lxt980 requests hub id. repeated periodically. 00 (hex) configchg arbitration lxt980 notifies system of configuration change (hot swap). requests new arbitration phase. 10 (hex) re-arbitrate arbitration network mgr re-starts arbitration. 14 (hex) assign hubid arbitration mech. 2 network mgr assigns hub id to device with arbin=0 and arbout = 1 (top of chain). 0c (hex) set arbout to 1 arbitration mech. 2 network mgr commands specific device to set arbout to 1. 1c (hex) set arbout to 0 arbitration mech. 2 network mgr commands specific device to set arbout to 0. 02 (hex) devid config network mgr asks device to send contents of device revision register.
35 lxt980/980a functional description address arbitration each device has a two part address, consisting of a hubid and a chipid. the chipid is assigned by the input pins chipid<2:0>. the manager assigns the hubid, and each lxt980 within a particular box will have the same hubid. the hub id is assigned through one of two arbitration mechanisms as shown in figure 11. eeprom arbitration mechanism this mechanism requires one serial eeprom with a unique 48-bit id on each board. this id can consist of serial number, date/week/year of manufacture, etc. the arbselect pin must be pulled low. at power- up, the device with chipid = 0 reads a 48-bit id from the prom. all other devices on the board listen in and record this id. the device with chipid = 0 then trans- mits arbitration request messages on the serial man- agement interface (smi) every 2-3 ms. the request messages from the two boards may collide. if this hap- pens, a resolution scheme ensures that only one mes- sage will be transmitted. table 22: typical serial management packets message contents of fields in serial management packet hub id chip id command length address data write 1, 2 user defined user defined 18 hex 01 or 02 hex user defined user defined read request 1, 3 user defined user defined 04 hex 01 to 7f hex user defined null read response 3 00000 000 04 hex 01 to 7f hex user defined data values assign hub id (arb method 1) 11111 111 18 hex 02 hex 188 hex formatted per table 76 assign hub id (arb method 2) 11111 111 14 hex 01 hex 000 hex hub id (lsb) and 27 0s0s set arbout to 0 user defined user defined 1c hex 00 hex 000 hex null set arbout to 1 user defined user defined 0c hex 00 hex 000 hex null arb request 00000 000 08 hex 02 hex 190 hex prom id resend arbitration 11111 111 10 hex 00 hex 000 hex null resend arbitration response 00000 000 08 hex 02 hex 190 hex eeprom id device type/ revision code user defined user defined 02 hex 01 hex 000 hex null device/revision response 00000 000 02 hex 01 hex 0ad hex device type/ revision 1. other than checking that the top 3 bits of the address equals 000, the lxt980 does not check if the user writes or reads past the highest location in the data sheet. there are no adverse effects for writing or reading locations above the specified range. 2. if the user performs a write operation of length 1 or 2 and does not send a data field, the lxt980 will write junk into the s pecified registers. this constitutes an invalid command. 3. if the user reads past the highest location of the lxt980, all those locations will read back 0s. if a read operation is perf ormed with a length of 0, the lxt980 will not respond.
lxt980/980a functional description 36 the network manager must respond to each request with a message that includes the 48-bit id and the hubid. all devices hear this message, but only those that match the 48-bit id receive the hubid as their own. once a hubid has been assigned to a hub, that hub will cease requesting a hubid. this process continues until all hubs have been assigned an id. should a board power off and back on, the hub will re- request an id, which the manager provides. the command types are assigned so an address arbitration packet will be selected over normal requests. chain arbitration mechanism when constructing the stack, the designer should create a daisy chain by tying the arbout pin of each lxt980 to the arbin pin of the following lxt980. the manager is at the top of the stack and has control of the arbin for the first lxt980. the manager progressively assigns hub ids using the assign address and set arbout to zero commands. the manager will initially set its arbout (first lxt980s arbin) to zero. since the assign address command only works on the lxt980 that has an arbin of 0 and an arbout of 1, the first lxt980 can be assigned an address. after the first lxt980 has been assigned an address, it can uniquely be told to switch its arbout to zero. this creates the (01) condition on the next lxt980 in the line. this lxt980 is then assigned an address and the process continues until all chips have been assigned a unique address. the manager can verify that a hub is still present by performing device id commands. if a change of configuration is detected, the manager can perform a broadcast write to return each hubs arbout to 1, and then re-perform the address assignment process. when using the chain arbitration method, set up the daisy chain so that the device with chipid = 0 is the first device on the board that the chain passes through. tie to arbout of the scc or to previous hub in the daisy chain. the first hub arbin can also be grounded. when assigning ids, the first chain bit, located in the device revision register (refer to table 72 on page 84) can then be used to determine when a new board has been encountered. address re-arbitration two mechanisms for address re-arbitration following a configuration change, such as a hot-swap of a board: ? manual re-arbitration. if the lxt980 detects a low-to-high transition on reconfig, or if reconfig is high at power-up, it sends out a configuration change message (all 0s) on the bus, the network manager can use to detect that re-arbitration is required. this message will be sent regardless of arbitration method; however, with chain arbitration mechanism, it will be sent once. the message can be ignored. ? network manager. the network manager detects or re-starts arbitration by sending the re- arbitrate command. figure 11: address arbitration mechanisms network manager serial i/f to next module srx/stx hub board 1 serial eeprom lxt980 srx/stx promdti/o lxt980 srx/stx promdti/o hub board 2 serial eeprom lxt980 srx/stx promdti/o lxt980 srx/stx promdti/o eprom mechanism for address arbitration 1 lxt980 arbin arbout network manager arbout serial i/f to next module srx/stx lxt980 arbin arbout srx/stx 0 srx/stx hub board 1 1 lxt980 arbin arbout srx/stx 1 lxt980 arbin arbout srx/stx 0 hub board 2 arbi/o chain to next module 0 chain mechanism for address arbitration
37 lxt980/980a functional description serial eeprom interface the serial eeprom interface has been designed to allow the vendor to load in optional information unique to each board. items such as serial number or date of manufacture can be placed in the serial eeprom which is also used in the address arbitration process. each board must contain a unique set of information. additionally, only 1 serial eeprom is required per board, they are not required per chip. the lxt980 reads in the first 48 bits (three 16-bit words) out of the eeprom and stores them in a register. this read occurs only on power-up as this information is static. only the lxt980 with a chipid of 000 will drive the serial eeprom control lines; all other lxt980s will listen in on the data and clock lines. the first bit to be shifted into the lxt980 from this interface would correspond to bit 47, while the last would be 0. the serial eeprom shifts out the most significant bit (15) of the word first (the eeprom must be auto-incrementing). figure 12: serial eeprom interface figure 13: optional r/w serial eeprom interface 93cs46 prom_cs prom_clk prom_dtin prom_dtout prom_dtin prom_clk lxt980 (id=0) lxt980 (id 1 0) clk dtout outgoing data is sent on the falling clock edge. incoming data is sampled on the rising clock edge . cs
lxt980/980a dual-speed, 5-port fast ethernet repeater 38 application information design recommendations the lxt980 has been designed to comply with ieee requirements and to provide outstanding receive ber and long-line-length performance. lab testing has shown that the lxt980 can perform well beyond the required distance of 100m. as with any finely crafted device, reaping the full benefits of the lxt980 requires attention to detail and good design practice. general design guidelines adherence to generally accepted design practices is essential to minimize noise levels on power and ground planes. up to 50 mv of noise is considered acceptable. 50 to 80 mv of noise is considered marginal. high-frequency switching noise can be reduced, and its effects can be eliminated, by following these simple guidelines throughout the design: ? fill in unused areas of the signal planes with solid copper and attach them with vias to a vcc or ground plane that is not located adjacent to the signal layer. ? use ample bulk and decoupling capacitors throughout the design (a value of .01 m f is recommended for decoupling caps). ? provide ample power and ground planes. ? provide termination on all high-speed switching signals and clock lines. ? provide impedance matching on long traces to prevent reflections. ? route high-speed signals next to a continuous, unbroken ground plane. ? filter and shield dc-dc converters, oscillators, etc. ? do not route any digital signals between the lxt980 and the rj45 connectors at the edge of the board. ? do not extend any circuit power or ground plane past the center of the magnetics or to the edge of the board. use this area for chassis ground, or leave it void. power supply filtering power supply ripple and digital switching noise on the vcc plane can cause emi problems and degrade line performance. it is generally difficult to predict in advance the performance of any design, although certain factors greatly increase the risk of having these problems: ? poorly-regulated or over-burdened power supplies. ? wide data busses (>32-bits) running at a high clock rate. ? dc-to-dc converters. many of these issues can be improved just by following good general design guidelines. in addition, level one also recommends filtering between the power supply and the analog vcc pins of the lxt980. filtering has two benefits. first, it keeps digital switching noise out of the analog circuitry inside the lxt980, which helps line performance. second, if the vcc planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing emi problems. the recommended implementation is to divide the vcc plane into two sections. the digital section supplies power to the digital vcc pin, and to the external components. the analog section supplies power to vcch, vcct, and vccr pins of the lxt980. the break between the two planes should run under the device. in designs with more than one lxt980, a single continuous analog vcc plane can be used to supply them all. the digital and analog vcc planes should be joined at one or more points by ferrite beads. the beads should produce at least a 100 w impedance at 100 mhz. the beads should be placed so that current flow is evenly distributed. the maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. each lxt980 draws a maximum of 500 ma from the analog supply so beads rated at 750 ma should be used. a bulk cap (2.2 -10 m f) should be placed on each side of each ferrite bead to stop switching noise from traveling through the ferrite. in addition, a high-frequency bypass cap (.01 m f) should be placed near each analog vcc pin. ground noise the best approach to minimize ground noise is strict use of good general design guidelines and by filtering the vcc plane.
39 lxt980/980a application information power and ground plane layout considerations great care needs to be taken when laying out the power and ground planes. the following guidelines are recommended: ? follow the guidelines in the lxt980 design and lay- out guide for locating the split between the digital and analog vcc planes. ? keep the digital vcc plane away from the tpop/n and tpip/n signals, away from the magnetics, and away from the rj45 connectors. ? place the layers so that the tpop/n and tpip/n signals can be routed near or next to the ground plane. for emi reasons, it is more important to shield tpop and tpip/n. chassis ground for esd reasons, it is a good design practice to create a separate chassis ground that encircles the board and is isolated via moats and keep-out areas from all circuit-ground planes and active signals. chassis ground should extend from the rj45 connectors to the magnetics, and can be used to terminate unused signal pairs (bob smith termination). in single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2kv isolation capacitor. in multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kv isolation to the bob smith termination. mii terminations series termination resistors are recommended on all mii signals driven by the lxt980. the proper value = nominal trace impedance minus 13 w . if the nominal trace impedance is not known, use 55 w . the rbias pin the lxt980 requires a 22.1 k w, 1% resistor directly connected between the rbias pin and ground. place the rbias resistor as close to the rbias pin as possible. run an etch directly from the pin to the resistor, and sink the other side of the resistor to ground. surround the rbias trace with ground; do not run high-speed signals next to rbias. the twisted-pair interface because the lxt980 transmitter uses 2:1 magnetics, system designers must take extra precautions to minimize parasitic shunt capacitance in order to meet return loss specifications. these steps include: ? use compensating inductor in the output stage (see figure 20). ? place magnetics as close as possible to the lxt980. ? keep transmit pair traces short. ? do not route transmit pair adjacent to a ground plane. if possible, eliminate planes under the transmit traces completely. otherwise, keep planes 3-4 layers away. ? some magnetic vendors are producing magnetics with higher than average return loss performance. use of these improved magnetics increases the return loss budget available to the system designer. ? improve emi performance by filtering the output centertap. a single ferrite bead may be used to supply centertap current to all four ports. in addition, follow all the standard guidelines for a twisted- pair interface: ? route the signal pairs differentially, close together. allow nothing to come between them. ? keep distances as short as possible; both traces should have the same length. ? avoid vias and layer changes as much as possible. ? keep the transmit and receive pairs apart to avoid cross-talk. ? if possible, place entire receive termination network on one side and transmit on the other. ? keep termination circuits close together and on the same side of the board. ? always put termination circuits close to the source end of any circuit. ? bypass common-mode noise to ground on the in- board side of the magnetics using 0.01 m f capacitors. the fiber interface the fiber interface consists of a pseudo-ecl (pecl) transmit and receive pair to an external fiber optic transceiver. the transmit pair should be ac coupled to the transceiver, and biased to 3.7v with a 50 w equivalent impedance. the receive pair can be dc-coupled, and should be biased to 3.0v with a 50 w equivalent impedance. figure 19 on page 44 shows the correct bias networks to achieve these requirements.
lxt980/980a dual-speed, 5-port fast ethernet repeater 40 magnetics information the lxt980 requires a 1:1 ratio for the receive transformers and a 2:1 ratio for the transmit transformers. the transformer isolation voltage should be rated at 2 kv to protect the circuitry from static voltages across the connectors and cables. refer to table 23 for transformer specifications and magnetic manufacturers for networking product applications (app. note 73) for a reference list of compatible magnetic components. before committing to a specific component, designers should test and validate the magnetics in the specific application to verify that system requirements are met. table 23: magnetics specifications parameter min nom max units test condition rx turns ratio C 1 : 1 C C tx turns ratio C 2 : 1 C C insertion loss 0.0 C 1.1 db 80 mhz primary inductance 350 C C m h transformer isolation C 2 C kv differential to common mode rejection C C -40 db .1 to 60 mhz C C -35 db 60 to 100 mhz return loss - standard C C -16 db 30 mhz C C -10 db 80 mhz return loss - improved C C -20 db 30 mhz C C -15 db 80 mhz
41 lxt980/980a application information typical application circuitry figures 14 through 17 are simplified block diagrams showing typical applications. figures 18 through 24 show application circuitry details. figure 14: managed 10/100 repeater stack figure 15: hybrid switch/repeater application - for balanced 10/100 performance tp/fiber ports tp/fiber ports tp/fiber ports serial comm controller (8530) 16 10/100 ports serial port 10m irb 100m irb 100m irb 10m irb mii inter-repeater backplanes mii serial port inter-repeater backplanes brid g e 10m mac 100m mac serial port 10m irb 100m irb 100m irb 10m irb mii inter-repeater backplanes mii serial port rmon (optional) 10 or 100m mac tp/fiber ports lxt980 lxt980 lxt980 lxt980 16 10/100 ports 10/100 mac tp/fiber ports mii tp/fiber ports 10m irb 100m irb 100m irb 10m irb mii tp/fiber ports mii tp/fiber ports 10m irb 100m irb 100m irb 10m irb mii inter-repeater backplanes inter-repeater backplanes 10 mbps 100 mbps 10 mbps 100 mbps ethernet switch memory control 10/100 mac 10/100 mac 10/100 mac lxt980 lxt980 lxt980 lxt980
lxt980/980a dual-speed, 5-port fast ethernet repeater 42 figure 16: hybrid switch/repeater application - weighted toward 100 mbps performance figure 17: unmanaged 100-only repeater stack 16 10/100 ports tp/fiber ports mii 10m irb 100m irb pal ethernet switch memory control 10 mbps inter-repeater backplanes tp/fiber ports mii 10m irb 100m irb tp/fiber ports mii 10m irb 100m irb tp/fiber ports mii 10m irb 100m irb 10 mbps 100 mbps 100 mbps 100 mbps 100 mbps 100 mbps mac 10 mbps mac 100 mbps mac 100 mbps mac 100 mbps mac lxt980 lxt980 lxt980 lxt980 tp/fiber ports 16 100m ports tp/fiber ports leds 10m irb 100m irb 100m irb 10m irb mii inter-repeater backplanes mii leds tp/fiber ports tp/fiber ports leds 10m irb 100m irb 100m irb 10m irb mii inter-repeater backplanes mii leds lxt980 lxt980 lxt980 lxt980
43 lxt980/980a application information figure 18: power and ground connections rbias vccv gndv gnda vccr gndr .01 m f 22.1k w 1% gnd vcc 0.1 m f + ferrite beads 10 m f +5v lxt980 vcct gndt 10 m f .01 m f .1 m f .1 m f digital supply plane analog supply plane .01 m f .1 m f to output magnetics centertap
lxt980/980a dual-speed, 5-port fast ethernet repeater 44 figure 19: typical fiber port interface fibon n 191 : fibop n fibin n fibip n 191 : 69 : 69 : fiber txcvr to fiber network 0.1 p f 130 : 130 : 80 : 80 : +5 v 0.1 p f td td rd rd 2 0.01 m f 0.01 m f gnda gnda gnda gnda vccr vcct +5 v 1 sigdet n lxt980 1. if the fiber interface is not used, fibin, fibip, fibon, fibop and sigdet may be left unconnected. 2. refer to fiber transceiver manufacturers recommendations for termination circuitry. suitable fiber transceivers include the hfbr-5103 and hfbr-5105.
45 lxt980/980a application information figure 20: typical twisted-pair port interface and power supply filtering 1. receiver common mode bypass cap may improve ber performance in systems with noisy power supplies. 2. a single ferrite bead may be used to supply centertap current to all 4 ports. tpip tpin rj45 tpop tpon 75 w vcct gndt 75 w 0.1 m f 0.001 m f/2kv .01 m f 1 50 w 1% 50 w 1% 0.1 m f gndr to twisted-pair network 3 6 1 2 1:1 2:1 lxt980 output stage with compensating inductor 200 w 1% 200 w 1% 320 nh 50 w 50 w 50 w 50 w 50 w 50 w 4 5 8 7 2
lxt980/980a dual-speed, 5-port fast ethernet repeater 46 figure 21: typical 100 mbps irb implementation figure 22: typical 10 mbps irb implementation lxt980 chip id 1 lxt980 chip id 2 +5v 240 w 1% 120 w ir100dv\ ir100dat <4:0> ir100cfs\ ir100col\ ir100sngl '245 ir100datbp ir100dvbp\ dir ena ir100clkbp ab lxt980 chip id 0 ir100cfsbp\ ir100den\ isolate 91 w 1%* +5v 330 w ir100clk ir100den\ ir100dv\ ir100dat stack or segment connector ir100cfsbp\ +5v 91 w 91 w 2 1 +5v 1 k w +5v 1 k w 1. in stacked configurations, all devices with chipid = 0 are tied together at ir100cfsbp . the entire stack must be pulled up by only one resistor per signal. pull-up resistor is installed in the base board only. 2. all devices with chipid 1 0 require individual pull-up resistors at ir100cfsbp . 3. 91 w resistors provide greater noise immunity. systems using 91 w resistors are backwards stackable with systems using 100 w resistors lxt980 chip id 1 lxt980 chip id 2 +5v 680 w 1% 330 w ir10ena\ ir10dat ir10cfs\ ir10col\ holdcol ir10clk '245 ir10datbp ir10enabp\ dir ena ir10clkbp ab lxt980 chip id 0 ir10colbp\ ir10cfsbp\ ir10den\ isolate 330 w 1% 330 w 1% +5v 330 w ir10den\ ir10clk ir10ena\ ir10dat ir10colbp\ ir10cfsbp\ ir10colbp\ ir10cfsbp\ +5v 330 w 330 w 330 w 330 w stack or segment connector 2 1 1. in stacked configurations, all devices with chipid = 0 are tied together at ir10colbp and ir10cfsbp . the entire stack must be pulled up by only one resistor per signal. pull-up resistors are installed in the base board only. 2. all devices with chipid 1 0 require individual pull-up resistors at ir10colbp and ir10cfsbp .
47 lxt980/980a application information figure 23: typical serial management interface connections figure 24: typical reset circuit '05 '05 srx serdat 1k w 1k w 1k w* vcc vcc vcc '05 stx '05 1k w 1k w vcc vcc * this resistor installed in base module only. vcc c r1 r2 '14 t(cr1) > power supply ramp up time r2 discharges c when supply goes away '14 needed for multiple lxt980 devices. d
lxt980/980a dual-speed, 5-port fast ethernet repeater 48 test specifications note tables 24 through 48 and figures 25 through 40 represent the performance specifications of the lxt980/980a and are guaranteed by test except, where noted, by design. the minimum and maximum values listed in tables 26 through 48 are guaranteed over the recommended operating conditions specified in table 25. table 24: absolute maximum ratings parameter symbol min max units supply voltage v cc -0.3 6 v operating temperature ambient t opa -15 +80 oc case t opc C+130oc storage temperature t st -65 +150 oc caution exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 25: operating conditions parameter sym min typ 1 max units recommended supply voltage v cc 4.75 5.0 5.25 v v ccv 4.75 5.0 5.25 v v ccr 4.75 5.0 5.25 v v cct 4.75 5.0 5.25 v recommended operating temperature ambient t opa 0C70c case t opc 0C115c power consumption auto-negotiation p c CC3.5w 100base-tx, 4 ports active p c CC3.5w 10base-t, 4 ports active p c CC3.4w 100base-fx, 4 ports active p c CC3.0w 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
49 lxt980/980a test specifications table 26: input clock requirements parameter 1 symbol min typ 2 max units test conditions frequency C C25CmhzC frequency tolerance C C C 100 ppm C duty cycle C 40C60 %C 1. these requirements apply to the external clock supplied to the lxt980, not to lxt980 test specifications. 2. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 27: i/o electrical characteristics parameter sym min typ 1 max units test conditions input low voltage v il C C 0.8 v ttl inputs CC30% v cc cmos inputs 2 C C 1.0 schmitt triggers 3 input high voltage v ih 2.0 C C v ttl inputs 70 C C % v cc cmos inputs 2 v cc - 1.0 C C v schmitt triggers 3 hysteresis voltage C 1.0 C C v schmitt triggers 3 output low voltage v ol CC0.4vi ol = 1.6 ma output low voltage (led) v oll CC1.0vi oll = 10 ma output high voltage v oh 2.4 C C v i oh = 40 m a input low current i il -100 C C m aC input high current i ih CC100 m aC output rise / fall time t rf C310nsc l = 15 pf 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. does not apply to irb pins. refer to tables 28 and 29 for irb i/o characteristics. 3. applies to reset and clk25 pins only.
lxt980/980a dual-speed, 5-port fast ethernet repeater 50 table 28: 100 mbps irb electrical characteristics parameter symbol min typ 1 max units test conditions output low voltage v ol C.3.7vr l = 330 w output rise or fall time t rf C410nsc l = 1 5 pf input high voltage v ih v cc - 2.0 C C v cmos inputs v cc - 1.0 C C v ir100clk (schmitt trigger) input low voltage v il C C 2.0 v cmos inputs C C 1.0 ir100clk (schmitt trigger) hysteresis voltage C 1.0 C C v ir100clk (schmitt trigger) ir100cfs current single drive C C 8.0 C ma r l = 240 w collision C C 16.0 C ma r l = 240 w ir100cfsbp current single drive C C 22.0 C ma r l = 91 w 2 collision C C 45.0 C ma r l = 91 w 2 ir100cfs/bp voltage single drive C C 2.8 C v C collision C C 0.6 C v C 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. 91 w resistors provide greater noise immunity. systems using 91 w resistors are backwards stackable with systems using 100 w resistors.
51 lxt980/980a test specifications table 29: 10 mbps irb electrical characteristics parameter symbol min typ 1 max units test conditions output low voltage v ol 0.1.4vr l = 330 w output rise or fall time t rf C410nsc l = 15 pf input high voltage v ih v cc - 2.0 C C v cmos inputs v cc - 2.0 C C v ir10clk (schmitt trigger) input low voltage v il C C 2.0 v cmos inputs C C 1.0 v ir10clk (schmitt trigger) hysteresis voltage C 0.5 C C v ir10clk (schmitt trigger) ir10cfs current single drive C C 3.2 C ma r l = 680 w collision C C 6.6 C ma r l = 680 w ir10cfsbp current single drive C C 8.1 C ma r l = 330 w collision C C 17.0 C ma r l = 330 w ir10cfs/bp voltage single drive C 1.9 2.8 3.2 v C collision C .25 0.6 0.8 v C 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. table 30: 100base-tx transceiver electrical characteristics parameter symbol min typ 1 max units test conditions peak differential output voltage (single ended) v p 0.95 1.0 1.05 v note 2 signal amplitude symmetry C 98 C 102 % note 2 signal rise/fall time t rf 3.0 C 5.0 ns note 2 rise/fall time symmetry t rfs C C 0.5 ns note 2 duty cycle distortion C C C +/- 0.5 ns offset from 8 ns pulse width at 50% of pulse peak, overshoot v o CC5%C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. measured at line side of transformer, line replaced by 100 w (.1%) resistor.
lxt980/980a dual-speed, 5-port fast ethernet repeater 52 table 31: 100base-fx transceiver electrical characteristics parameter symbol min typ 1 max units test conditions transmitter peak differential output voltage (single ended) v op 0.6 C 1.0 v C signal rise/fall time t rf C C 1.6 ns 10 <-> 90%, 2.0 pf load jitter (measured differentially) C C C 1.3 ns C receiver peak differential input voltage v ip 0.55 C 1.5 v C common mode input range v cmir 2.25 C v cc - 0.5 v C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 32: 10base-t transceiver electrical characteristics parameter symbol min typ 1 max units test conditions transmitter peak differential output voltage v p 2.2 2.5 2.8 v measured at line side of transformer, line replaced by 100 w ( .1%) resistor transmit timing jitter addition 2 C C 6.4 10 ns 0 line length for internal mau transmit timing jitter added by the mau and pls sections 2, 3 C C 3.5 5.5 ns after line model specified by ieee 802.3 for 10base-t inter- nal mau receiver receive input impedance z in C3.4C k w between tpip/tpin differential squelch threshold v ds 300 420 585 mv 5 mhz square wave input, 750 mvpp 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. parameter is guaranteed by design; not subject to production testing. 3. ieee802.3 specifies maximum jitter additions at 1.5 ns for the aui cable, 0.5 ns from the encoder, and 3.5 ns from the mau.
53 lxt980/980a test specifications figure 25: 100 mbps port-to-port delay timing table 33: 100 mbps port-to-port delay timing parameters parameter symbol min typ 1 max units 2 test conditions tpip/n or fibip/n to tpop/n or fibop/n, start of transmission t 1a CC46btC tpip/n or fibip/n to tpop/n or fibop/n, end of transmission t 1b CC46btC tpip/n or fibip/n collision to tpop/n or fibop/n, start of jam t 1c CC46btC tpip/n or fibip/n idle to tpop/n or fibop/n, end of jam t 1d CC46btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. tp / fib input #2 t 1c tp / fib input #1 tp / fib output jam t 1d t 1a tp / fib input tp / fib output t 1b normal propagation collision jamming
lxt980/980a dual-speed, 5-port fast ethernet repeater 54 figure 26: 100base-tx transmit timing - phy mode mii table 34: 100base-tx transmit timing parameters - phy mode mii parameter sym min typ 1 max units 2 test condition txd, tx_en, tx_er setup to tx_clk high t 2a 10 C C ns C txd, tx_en, tx_er hold from tx_clk high t 2b 5CC nsC tx_en sampled to crs asserted t 2c 0C4btC tx_en sampled to crs de-asserted t 2d 0C16btC tx_en sampled to tpop/n active (tx latency) t 2e CC46btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. tx_clk txd, tx_en, tx_er crs tpop/n t 2a t 2b t 2c t 2d t 2e
55 lxt980/980a test specifications figure 27: 100base-tx receive timing - phy mode mii table 35: 100base-tx receive timing parameters - phy mode mii parameter sym min typ 1 max units 2 test conditions tpip/n in to crs asserted t 3a CC46 bt C tpip/n quiet to crs de- asserted t 3b CC46 bt C crs asserted to rxd, rx_dv, rx_er t 3c 1C4 bt C crs de-asserted to rxd, rx_dv, rx_er de-asserted t 3d CC3 bt C rx_clk falling edge to rxd, rx_dv, rx_er valid t 3e CC10 ns C tpip/n in to col asserted t 3f CC46 bt C tpip/n quiet to col de- asserted t 3g CC46 bt C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. rx_clk rxd, rx_dv, rx_er crs tpip/n col t 3a t 3b t 3c t 3d t 3f t 3g t 3e
lxt980/980a dual-speed, 5-port fast ethernet repeater 56 figure 28: 100base-tx transmit timing - mac mode mii table 36: 100base-tx transmit timing parameters - mac mode mii parameter sym min typ 1 max units 2 test conditions rxd, rx_dv, rx_er setup to rx_clk high t 4a 10 C C ns C rxd, rx_dv, rx_er hold from rx_clk high t 4b 5CC nsC rxd sampled to tpo asserted t 4c CC46btC rxd sampled to tpo de-asserted t 4d CC46btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. rx_clk rxd, rx_dv, rx_er tpop/n t 4a t 4b t 4c t 4d
57 lxt980/980a test specifications figure 29: 100base-tx receive timing - mac mode mii table 37: 100base-tx receive timing - mac mode mii parameter sym min typ 1 max units 2 test conditions tpip/n in to txd, tx_en, tx_er t 5a CC46 bt C tpip/n quiet to txd de-asserted t 5b 13C46 bt C tx_clk rising edge to txd, tx_en, tx_er valid t 5c 0C25 ns C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. tx_clk txd, tx_en, tx_er tpip/n t 5a t 5c t 5b
lxt980/980a dual-speed, 5-port fast ethernet repeater 58 figure 30: 100base-fx transmit timing - phy mode mii table 38: 100base-fx transmit timing parameters - phy mode mii parameter sym min typ 1 max units 2 test conditions txd, tx_en, tx_er setup to tx_clk high t 6a 10 C C ns C txd, tx_en, tx_er hold from tx_clk high t 6b 5CC nsC tx_en sampled to crs asserted t 6c 0C4btC tx_en sampled to crs de-asserted t 6d 0C16btC tx_en sampled to fibop/n out (tx latency) t 6e CC46btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. tx_clk txd, tx_en, tx_er crs fibop/n t 6a t 6b t 6b t 6d t 6e
59 lxt980/980a test specifications figure 31: 100base-fx receive timing - phy mode mii table 39: 100base-fx receive timing - phy mode mii parameter sym min typ 1 max units 2 test conditions fibip/n in to crs asserted t 7a CC46btC fibip/n quiet to crs de- asserted t 7b CC46btC crs asserted to rxd, rx_dv, rx_er t 7c 1C4btC crs de-asserted to rxd, rx_dv, rx_er de-asserted t 7d CC3btC rx_clk falling edge to rxd, rx_dv, rx_er valid t 7e C C 10 ns C fibip/n in to col asserted t 7f CC46btC fibip/n quiet to col de- asserted t 7g CC46btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. rx_clk rxd, rx_dv, rx_er crs fibip/n col t 7a t 7b t 7c t 7d t 7f t 7g t 7e
lxt980/980a dual-speed, 5-port fast ethernet repeater 60 figure 32: 100base-fx transmit timing - mac mode mii table 40: 100base-fx transmit timing - mac mode mii parameter sym min typ 1 max units 2 test conditions rxd, rx_dv, rx_er setup to rx_clk high t 8a 10 C C ns C rxd, rx_dv, rx_er hold from rx_clk high t 8b 5CC nsC rxd sampled to fibop/n asserted t 8c CC46btC rxd sampled to fibop/n de- asserted t 8d CC46btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. rx_clk rxd, rx_dv, rx_er fibop/n t 8a t 8b t 8d t 8c
61 lxt980/980a test specifications figure 33: 100base-fx receive timing - mac mode mii table 41: 100base-fx receive timing - mac mode mii parameter sym min typ 1 max units 2 test conditions fibip/n in to txd, tx_en, tx_er t 9a CC46btC fibip/n quiet to txd de- asserted t 9b CC46btC tx_clk rising edge to txd, tx_en, tx_er valid t 9c 0 C 25 ns C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. tx_clk txd, tx_en, tx_er fibip/n t 9a t 9c t 9b
lxt980/980a dual-speed, 5-port fast ethernet repeater 62 figure 34: 10base-t transmit timing - phy mode mii table 42: 10base-t transmit timing parameters - phy mode mii parameter sym min typ 1 max units 2 test conditions txd, tx_en, tx_er setup to tx_clk high t 10a 10 C C ns C txd, tx_en, tx_er hold from tx_clk high t 10b 5CC nsC tx_en sampled to crs asserted t 10c 0.92btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 10base-t = 10 -7 s or 100 ns. tx_clk txd, tx_en, tx_er crs t 10a t 10b t 10c
63 lxt980/980a test specifications figure 35: 10base-t receive timing - phy mode mii table 43: 10base-t receive timing parameters - phy mode mii parameter sym min typ 1 max units 2 test conditions tpip/n in to crs asserted t 11a 56.68 btC crs asserted to rxd, rx_dv, rx_er t 11b 70 76 84 bt C rx_clk falling edge to rxd, rx_dv, rx_er valid t 11c C C 10 ns C tpip/n in to col asserted t 11d 67.49 btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 10base-t = 10 -7 s or 100 ns. rx_clk rxd, rx_dv, rx_er crs tpip/n col t 11a t 11b t 11c t 11d
lxt980/980a dual-speed, 5-port fast ethernet repeater 64 figure 36: 100 mbps irb timing table 44: 100 mbps irb timing parameters 1 parameter symbol min typ 2 max units 3 test conditions tpip/n or fibp/n to ir100dv low t 12a 18 24 30 bt C ir100dat to ir100clk setup time. t 12b C10C nsC ir100dat to ir100clk hold time. t 12c C0C nsC 1. this table contains propagation delays from the tp ports to the irb for normal repeater operation. all values in this table a re output timings. 2. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 3. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. tpip/n fibip/n ir100dv ir100cfs 1r100col ir100dat<4:0> t 12a t 12b ir100clk t 12c
65 lxt980/980a test specifications figure 37: 10 mbps irb receive timing table 45: 10 mbps irb receive timing parameters 1 parameter symbol min typ 2 max units 4 test conditions tpip/n to ir10ena low t 13a 35.17 btC ir10clk rising edge to ir10dat rising edge. t 13b 25 - 55 ns 330 w pull-up, 150 pf load on ir10dat. 1 k w pull-up, 150 pf load on irclk. all measurements at 2.5v. ir10clk rising edge to ir10dat falling edge. t 13c 5-25ns 1. this table contains propagation delays from the tp ports to the irb for normal repeater operation. all values in this table a re output timings. 2. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 3. there is a delay of approximately 13 to 16 bit times between the assertion of ir10ena and the assertion of ir10clk and ir10dat. this delay does not affect repeater operation because downstream devices begin generating preamble as soon as ir10ena is asserted. 4. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 10base-t = 10 -7 s or 100 ns. tpip/n ir10ena ir10dat t 13a t 13b ir10clk t 13c see table 45, note 3
lxt980/980a dual-speed, 5-port fast ethernet repeater 66 figure 38: 10 mbps irb transmit timing table 46: 10 mbps irb transmit timing parameters parameter symbol min typ 1 max units 2 test conditions macactive to ir10ena assertion delay 3 t 14a C 100 C ns macactive high to ir10ena low. 4 ir10dat (input) to ir10clk setup time t 14b C 20 C ns ir10dat valid to ir10clk rising edge. 4 ir10clk to ir10dat (input) hold time t 14c C 0 C ns ir10clk rising edge to ir10dat change. 4 ir10ena asserted to tpop/n active t 14d 55.1 6 btC 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 10base-t = 10 -7 s or 100 ns. 3. external devices should allow at least one 10 mhz clock cycle (10 ns) between assertion of macactive and ir10ena. 4. input. macactive ir10ena ir10dat t 14a t 14b ir10clk t 14c tpop/n t 14d
67 lxt980/980a test specifications figure 39: serial management interface timing table 47: serial interface timing characteristics 1 parameter symbol min typ 1 max units test conditions serclk input frequency C C C 2.0 mhz depending on reconfig, this is either an input or output. serclk output frequency C 625 C khz data to clock setup time t15a 0 C C ns srx valid to serclk rising edge. 2 clock to data hold time t15b 200 C C ns serclk rising edge to srx change. 2 data propagation delay t15c C C 200 ns serclk falling edge to stx valid. 3 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. input. 3. output. t15a t15b t15c serclk srx stx
lxt980/980a dual-speed, 5-port fast ethernet repeater 68 figure 40: prom interface timing table 48: prom interface timing characteristics parameter symbol min typ 1 max units test conditions prom_clk C C 1.0 mhz prom_clk frequency. clk to prom_cs delay t16a C 200 ns clk falling edge to prom_cs. clk to prom_dtout delay t16b C 20 ns clk falling edge to prom_dtout. prom_dtin to clk setup time t16c 20 C ns prom_dtin to clk rising edge. prom_dtin to clk hold time t16d 20 C ns prom_dtin to clk rising edge. prom_dtout prom_cs prom_clk t 16a t 16b prom_dtin t 16c t 16d
69 lxt980/980a register definitions register definitions the lxt980/980a register set is composed of multiple 32-bit registers of the types listed in table 49. all register addresses are hexadecimal. counter registers table 50 shows bit assignments. when reading a 64-bit counter, read the lower address (lower 32 bits of counter) first, followed by the upper address. the first read causes all 64 bits to be simultaneously latched into an internal holding register . the second read is directed to this holding register. the statistics bit must be set off to write to the counters. port counter registers the port counter descriptions in table 51 are intended to be illustrative. for the exact definition of these counters, refer to the repeater mib, rfc 1516. all counters count packets, octets or events that were received at each port. in the descriptions, the length of a packet never includes preamble or framing bits (start of frame, end of frame, dribble bits, etc.) , but an event does include these items. table 49: register set base address 1 register type bit assignments & description 00x port 1 counters (tp/fx) refer to tables 50 and 51. 01x port 2 counters (tp/fx) 02x port 3 counters (tp/fx) 03x port 4 counters (tp/fx) 04x port 5 counters (mii) 05x additional counters (100 only) 05x, 06x rmon counters refer to tables 50 and 52. 07x port addresses refer to tables 53 and 54. 08x authorized addresses refer to table 53. 08x, 09x global addresses refer to tables 53 and 55. 09x port control & status refer to tables 56 through 63. 09x, 0ax, 0bx, 188, 189, 190, 191 general setup/status refer to tables 64 through 82. 1. x = offset address of register desired. note that base register addresses for port counters are offset by 1 (00x refers to po rt 1, 01x to port 2, 02x to port 3, 03x to port 4 and 04x to port 5). table 50: counter register bit assignments 31 30 29 28 27 26 25: 7 6 5 4 3 2 1 0 d31 d30 d29 d28 d27 d26 d25:d7 d6 d5 d4 d3 d2 d1 d0
lxt980/980a dual-speed, 5-port fast ethernet repeater 70 table 51: port counter registers name offset addr 1 description registers used when running at 10 or 100 mbps rptrmonitorportreadableframes 0x0 counts valid-length (64 to 1518 bytes), valid-crc, col- lision-free packets. depending on the state of the count- mode bit (6) in the repeater configuration register, this counter will count either all packets (countmode=0) or only unicast packets (countmode=1). rptrmonitorportreadableoctets (lower/upper) 0x1, 0x2 counts the number of octets in all valid-length (64 to 1518 bytes), valid-crc, collision-free packets, not including preamble and framing bits. this register is not affected by the countmode bit. rptrmonitorportframechecksequence 0x3 counts valid length, collision-free packets that had fcs errors, but were correctly framed (had an integral num- ber of octets). rptrmonitorportalignmenterrors 0x4 counts valid length, collision-free packets that had fcs errors and were incorrectly framed (had a non-integral number of octets). rptrmonitorportframestoolong 0x5 counts packets that had a length greater than 1518 octets. rptrmonitorportshortevents 0x6 10m: counts events < 80 bit times. 100m: counts events < 88 bit times. rptrmonitorportrunts 0x7 10m: counts events > 80 and < 504 bit times. 100m: counts events > 92 and < 504 bit times. 2 rptrmonitorportcollisions 0x8 counts the number of collisions that occurred, not including late collisions. rptrmonitorportlateevents 0x9 counts the number of times collision was detected more than 512 bit times after the start of carrier. rptrmonitorportverylongevents 0xa counts the number of times any activity continued for more than 4 to 7.5 ms. rptrmonitorportdataratemismatches 0xb counts the number of times the incoming data rate mis- matched the local clock source enough to cause a fifo underflow or overflow. rptrmonitorportautopartitions 0xc counts the number of times this port has been parti- tioned by the auto-partition algorithm. rptrtracksourceaddrchanges 0xd counts the number of times the source address has changed. minimum roll-over time of 81 hours. 1. replace x in address with specific port to be addressed (offsets 0 through 4 correspond to ports 1 through 5). 2. for 100m: the short events register counts events < 88 bit times; the port runts register counts events > 92. a 4-bit-time differential exists because 100m operates with nibble boundaries, so data packets < 4 bits are counted as 4.
71 lxt980/980a register definitions rptrmonitorportbroadcastpkts 0xe counts the number of good broadcast packets received by this port. counter is not cleared by zerocount bit. rptrmonitorportmulticastpkts 0xf counts the number of good multicast packets received by this port. counter is not cleared by zerocount bit. registers used only when running at 100 mbps rptrmonitorportisolates - port 1 050 counts the number of times a port auto isolates. note: when these counters increment, none of the other port counters will increment since the frame never had a valid start. rptrmonitorportisolates - port 2 051 rptrmonitorportisolates - port 3 052 rptrmonitorportisolates - port 4 053 rptrmonitorportisolates - port 5 054 rptrmonitorsymbolerrorduringpacket - port 1 055 counts the number of time a packet contained symbol errors. only one symbol error is counted per packet. rptrmonitorsymbolerrorduringpacket - port 2 056 rptrmonitorsymbolerrorduringpacket - port 3 057 rptrmonitorsymbolerrorduringpacket - port 4 058 table 51: port counter registers C continued name offset addr 1 description 1. replace x in address with specific port to be addressed (offsets 0 through 4 correspond to ports 1 through 5). 2. for 100m: the short events register counts events < 88 bit times; the port runts register counts events > 92. a 4-bit-time differential exists because 100m operates with nibble boundaries, so data packets < 4 bits are counted as 4.
lxt980/980a dual-speed, 5-port fast ethernet repeater 72 rmon counter registers the interface counter descriptions in table 52 are intended to be illustrative. for the exact definition of these counters, ref er to the rmon mib, rfc 1757. all counters count events, octets or packets that were received from the interface. packet length never includes preamble or framing bits (start of frame, end of frame, dribble bits, etc.). table 52: rmon counter registers name type addr description etherstatsoctets r/w 05c, 05d number of data octets including those in bad packets and octets in fcs fields, but does not include preamble or other framing bits. etherstatspkts r/w 05e number of packets received (from network), including errored packets. etherstatsbroadcastpkts r/w 05f number of good broadcast packets received. counter is not cleared by zerocount bit. etherstatsmulticastpkts r/w 060 number of good multicast packets received. etherstatscrcalignerrors r/w 061 number of valid-length packets (64 to 1518 bytes inclusive) that had a bad frame check sequence (fcs). etherstatsundersizepkts r/w 062 number of well-formed packets that were smaller than 64 octets. etherstatsoversizepkts r/w 063 lxt980: number of well-formed packets that were longer than 1518 octets. lxt980a: number of well-formed packets that were longer than 1518 octets and smaller than 2044. etherstatsfragments r/w 064 number of ill-formed packets less than 64 octets. note: any event without a start-of-frame delimiter (0-octet packet) will be counted as a fragment, no matter how long it is. etherstatsjabbers r/w 065 lxt980: number of ill-formed packets longer than 1518 octets. an ill-formed packet is one with an fcs error. lxt980a: number of ill-formed packets longer than 1518 octets, and number of packets (good and bad) greater than/equal to 2044. an ill-formed packet is one with an fcs error. etherstatscollisions/ rptr monitor transmit collisions r/w 066 the best estimate of the total number of collisions on this interface. etherstatspkts64octets r/w 067 no. of packets (good and bad) that were 64 octets long. etherstatspkts65to127octets r/w 068 no. of packets (good and bad) between 65 and 127 octets long. etherstatspkts128to255octets r/w 069 no. of packets (good and bad) between 128 and 255 octets long. etherstatspkts256to511octets r/w 06a no. of packets (good and bad) between 256 and 511 octets long. etherstatspkts512to1023octets r/w 06b no. of packets (good and bad) between 512 and 1023 octets long. etherstatspkts1024to1518octets r/w 06c no. of packets (good and bad) between 1024 and 1518 octets long. not used r/w 06d rptrmonitortotaloctets (lower/upper) r/w 06e, 06f total number of octets contained in valid frames received on this segment. counter is not cleared by zerocount bit.
73 lxt980/980a register definitions ethernet address registers all ethernet address registers consist of two 32-bit registers that together contain a 48-bit ethernet address. refer to table 53 for register bit assignments. port address tracking registers the port address tracking register set is described in table 54. these registers continuously monitor the source addresses of packets emanating from the corresponding ports. refer to table 53 for bit assignments. table 53: ethernet address register bit assignments upper address bits 15:0 contain bits 47:32 of the ethernet address. lower address bits 31:0 contain bits 31:0 of the ethernet address. table 54: port address tracking registers name size, bits addr description rptraddrtracknewlastsrcaddress port 1 48 070, 071 stores the value of the last source address received. can also act as newlastsourceaddress via sw. these addresses power up unknown, but can be zeroed by software. example address: 00-20-7b-03-02-01 first read: msb 037b2000 lsb . second read: msb xxxx0102 lsb all addresses must read in order. only the first read updates the holding register. xs are currently defined as zeros. rptraddrtracknewlastsrcaddress port 2 48 072, 073 rptraddrtracknewlastsrcaddress port 3 48 074, 075 rptraddrtracknewlastsrcaddress port 4 48 076, 077 rptraddrtracknewlastsrcaddress port 5 (mii) 48 078, 079 1. all port address tracking registers are read/write.
lxt980/980a dual-speed, 5-port fast ethernet repeater 74 search address registers the search address register set is described in table 55. table 55: search address registers name type addr size (bits) description search address register refer to table 53 for bit assign- ments. r/w 08a, 08b 48 on-board address search register. should the user wish to find out if a particular source address has been seen on any of the ports, on any of the segments, this register would be used. each port within an lxt980 chip will be checked for traffic originating from the source address matching this register. if a match is found, the port number where the traffic originated will be saved thus allowing software to determine where the address is located. the register that contains the port from the search address match function is the search address match register. (default = xs) search port match register refer to table 56 for bit assign- ments. r 090 5 this register holds the port number of the host which uses the address specified in the search address register. when the auto-clear bit (bit 11) in the repeater configuration register is set to a 0, this register is cleared upon reading. if the auto-clear bit is set to a 1, this registers bit(s) are cleared by writing a 1 to the appropriate bit(s). (default = 0s)
75 lxt980/980a register definitions control and status registers the control and status register set includes general port control and status registers that conform to the bit assignments shown in tables 56, 58, and 60. additional control and status registers with alternate bit assignments are shown in tables 61 through 68. port link control register the port link control register is described in table 57. refer to table 56 for port link control register bit assignments. table 56: port link control and status register bit assignments 31:4 3 2 1 0 rsvd port 4port 3port 2port 1 table 57: port link control register name type addr description port link control r/w 091 this register controls the link function of the 4 twisted-pair ports of the lxt980. when disabled, a port will no longer be disconnected due to link fail. when enabled, the port will only remain connected to the network so long as link pulses are being received: 0 = disable, 1 = enable (default).
lxt980/980a dual-speed, 5-port fast ethernet repeater 76 general port control registers the general port control register set is described in table 59. refer to table 58 for the general port control registers bit assignments. table 58: general port control and status register bit assignments 31:5 4 3 2 1 0 rsvd port 5 (mii) port 4 port 3 port 2 port 1 table 59: general port control registers name type addr description port alternate partition algorithm control r/w 094 lxt980 provides per-port selection of partition algorithms. 0 = normal (default) 1 = alternate speed normal alternate 10m un-partition a port when data can be either received or transmitted from the port for 450-560 bit times without a collision on that port. un-partition a port only when data can be transmitted to the port for 450-560 bit times without a collision on that port. 100m un-partition a port only when data can be transmitted to the port for 450-560 bit times without a collision on that port. un-partition a port when data can be either received or transmitted from the port for 450-560 bit times without a collision on that port. lxt980a provides per-port selection of partition algorithms. 0 = normal 1 = alternate (default) speed normal alternate 10m un-partition a port when data can be either received or trans- mitted from the port for 450-560 bit times without a collision on that port. 100m un-partition a port only when data can be transmitted to the port for 450-560 bit times without a collision on that port. un-partition a port when data can be either received or transmitted from the port for 450-560 bit times without a collision on that port. port enable r/w 095 this register controls whether a port is enabled/disabled. if the mgr_pres signal is low on power up, then all ports will be disabled until such time that management software re-enables them. otherwise the ports will power on enabled. 0 = disable, 1 = enable (default = 1).
77 lxt980/980a register definitions port learn and speed control registers the port learn and speed control register set is described in table 61. refer to table 61 for the bit assignments of these registers. table 60: port learn and speed control registers 31:10 9 8 7 6 5 4 3 2 1 0 rsvd port 5 (mii) port 4 port 3 port 2 port 1 table 61: port learn and speed control registers name type addr description port authorized learn enable control r/w 096 this register sets the level of learning each port uses. the learn settings are as follows: bit 1 bit 0 function 0 0 learn new source addresses. 0 1 next lock. learn only the first source address encountered. after a port learns its first address, it changes the authorized learn bits (for that port) to a 10 to lock down the address. 1 0 lock. hardware locked-down the address. only software can write to this address. 11reserved. port speed control r/w 097 this register overrides the hardware settings. enabling auto-negotiation via software requires writing to both the port speed control register and the auto-negotiate configura- tion register (see table 82 on page 89). forcing a ports speed overrides and disables auto-negotiation. the mii (expansion) port is not software-configurable. default is set by pins spd0 and spd1. settings are as follows: spd1 spd0 function 0 0 if auto-negotiate is enabled, advertise all abilities. otherwise port is disabled. 0 1 force 10 mbps tp 1 0 force 100 mbps fiber (does not apply to mii) 1 1 force 100 mbps tp
lxt980/980a dual-speed, 5-port fast ethernet repeater 78 port status registers the port status register set is described in table 63. bit assignments are shown in table 62. table 62: port status register bit assignments 31:4 4 1 3 2 1 0 rsvd port 5 (mii) port 4 port 3 port 2 port 1 1. bit 4 used only in the port partition and port speed status registers. table 63: port status registers name type 1 addr description port link status r 098 a read of this register will reflect the current link status of the 4 twisted-pair ports within a lxt980 chip. a 1 indicates that the port is currently in the link_good state. (default = 0s) port polarity status r 099 a read of this register will reflect the current polarity status of the 4 twisted- pair ports within a lxt980 chip. a 1 indicates that the polarity has been crossed for a given port. (default = 0s) port partition status r 09a a read of this register will reflect the current partition status of all 5 ports within a lxt980 chip. a 1 indicates that the port has been partitioned out of the repeater. a 0 is read if the port is connected. (default = 0s) port speed status r 09c indicates the current status of each port. 0 = port is connected at 10 mbps 1 = port is connected at 100 mbps port isolation status (fast ethernet only) r 09d indicates the current isolation status of each port operating in fast ethernet. fast ethernet port isolation (clause 27.3.2 of 802.3u) 1. r = read only
79 lxt980/980a register definitions interrupt status/mask registers the interrupt status and mask registers are described in tables 65 and 66. refer to table 64 for bit assignments. table 64: interrupt status/mask register bit assignments 31:8 7 6 5 4 3 2 1 0 reserved far-end fault reserved jabber isolate partition fcc source address change speed change detected table 65: interrupt status/mask register name type addr description interrupt status register r(/w) 1 0ae this register captures status bits within the lxt980 and holds them. refer to table 66 for bit descriptions. interrupt mask register r/w 0af this register allows masking of individual interrupts. 0 = do not mask (default) 1 = mask 1. r(/w) when the register clear bit (bit11) in the repeater configuration register is set to a 0, this register is cleared up on reading. if the register clear bit is set to a 1, these register bit(s) are cleared by writing a 1 to the appropriate bit(s). table 66: interrupt status register bit definitions bit name type 1 description default 31:8 reserved r/w reserved - write as 0s; ignore on read. n/a 7 far end fault r/w a 1 indicates that one of four conditions has occurred: 1. a port in fiber mode received the remote fault code from its link partner. 2. a port in auto-negotiation received 3 flps in a row with the remote fault bit set. 3. a port is in fiber mode with remote fault reporting enabled, and either the receive pll is unlocked or the signal detect input has been lost. 4. a port in auto-negotiation is transmitting flps with the remote fault bit set. in conditions 1 and 2 the link partner has detected the remote fault condition and is sending it to the lxt980. in conditions 3 and 4 the lxt980 has detected the remote fault condition and is sending it to the link partner. 0 6 reserved r/w reserved - write as 0s; ignore on read. 0 1. r = read only; r/w = read/write.
lxt980/980a dual-speed, 5-port fast ethernet repeater 80 mii status register the mii status register is described in table 68. refer to table 67 for bit assignments. this is a 32-bit register. 5 jabber r a 1 indicates that a port is in jabber state. during 100 mbps operation, jabber occurs when any receiver remains active for more than 57,500 bit times. the lxt980 exits this state when all receivers return to the idle condition. during 10 mbps operation, jabber occurs when any port remains actively transmitting for longer than 40,000 to 75,000 bit times. the lxt980 will assert a minimum-ifg idle period when a port is jabbering. 0 4 isolate r/w a 1 indicates that a port has been isolated (100 mbps only). the lxt980 isolates any port that transmit more than two successive false carrier events. a false carrier event is defined as a packet that does not start with a /j/k symbol pair. 0 3 partition r/w a 1 indicates that a port has been partitioned. in 100 mbps operation, the lxt980 partitions any port that participates in excess of 60 consecutive collisions. in 10 mbps operation, the lxt980 parti- tions any port that participates in excess of 32 consecutive collisions. once partitioned, the lxt980 will continue monitoring and transmitting to the port, but will not repeat data received from the port until it properly un-partitions. 0 2fccr/wa 1 indicates that a port has received too many false carrier events 0 1sa change r/w a 1 indicates that a port address changed from that stored in the last- sourceaddress register. 0 0 speed change r/w a 1 indicates that a port speed change was detected. 0 table 67: mii status register bit assignment 31:2 1 0 reserved select 10 mbps or 100 mbps 0 = 10 mbps 1 = 100 mbps select connecting device type 0 = mac mode (connected to a phy) (available at 100 mbps only) 1 = phy mode (connected to a mac) (available at either 10 or 100 mbps) table 68: mii status register name type addr description mii register r 0b4 used to give the status of the mii port. default is set by pins. table 66: interrupt status register bit definitions C continued bit name type 1 description default 1. r = read only; r/w = read/write.
81 lxt980/980a register definitions configuration registers the configuration register set is described in table 69. bit assignments for the configuration registers are shown in tables 70 through 77. table 69: configuration registers name type 1 addr description repeater configuration register r/w 0ab refer to table 70 for bit assignments. repeater serial configuration register r 0ac this 8 bit register holds user-defined data. these bits may be used to indicate the type of board configuration, port count or other vendor-related data. default is set by pins. device/revision id register r 0ad this register follows the ieee 1149.1 specification. refer to table 72 for bit assignments. the upper 4 bits identify the device revision level. the next 16 bits store the part id number, which in this case is hexa- decimal 3d4. the next 11 bits contain a jedec manufac- turer id, which for level one is hexadecimal fe. the lowest bit (0) is set only for the first device in a chain. reserved r 0b0 ignore on read. global led control register r/w 0b1 refer to table 73 for bit assignments. this register reflects the led mode set by pins 207 and 208, and provides soft- ware control for the global fault led. led mode , bit encoding (read only from pins): bit 5 bit 4 mode selected 00mode 1 01mode 2 10mode 3 11reserved global fault led , bit encoding: bits 3 : 2 modes 1 & 3 mode 2 0 0 led off led off 0 1 2 hardware control hardware control 1 0 reserved led slow blink 1 1 3 led off led on steady 1. r = read only; w = write only; r/w = read /write. 2. default value if manager is not present. 3. default value if manager is present.
lxt980/980a dual-speed, 5-port fast ethernet repeater 82 port led control register r/w 0b2 this register provides a measure of software control over the port leds. refer to table 74 for bit assignments. during reset, the state of this register is all 1s. if a manager is present, this register remains in the all 1s state after reset. otherwise, the bits default to hardware control. encoding is as follows: bits 1 : 0 modes 1 & 3 mode 2 0 0 led off led off 0 1 reserved led fast blink 1 0 2 hardware control hardware control 1 1 3 led off led on steady led timer control register r/w 0b3 refer to table 75 for bit assignments. bits 8-15 of this regis- ter set the fast blink frequency of the leds. bits 0-7 set the slow blink frequency. the same formula is used in each case, with a maximum of 128 hz and a minimum of 0.5 hz. example: fast blink = x32 (0.4 sec) slow blink = xcc (1.6 sec) repeater reset register w 0b5 writing any data value to this register with the least significant bit (lsb) = 1 causes the repeater functional logic to reset. (all bits other than lsb do not matter.) the counters and configuration information will be held static and will not be reset. (default = 0s) software reset register w 0b6 writing any data value to this register with the least significant bit (lsb) = 1 is identical to a hardware reset. (all bits other than lsb do not matter.) everything is reset except the source address ram. (default = 0s) assign address register (1 and 2) w 188, 189 refer to table 76 for bit assignments. writing a valid 48-bit id (one that matches the eprom id) to this register causes the device to change its hub id to the contents of the eprom id register listed below. this register cannot be read. eprom address register (1 and 2) r 190, 191 these two registers contain the 48-bit id read in from eprom at power-up. refer to table 77 for bit assignments. table 69: configuration registers C continued name type 1 addr description 1. r = read only; w = write only; r/w = read /write. 2. default value if manager is not present. 3. default value if manager is present.
83 lxt980/980a register definitions repeater configuration register this register contains many of the global repeater settings. the repeater configuration register is described in table 71. refer to table 70 for bit assignments of the repeater configuration register. table 70: repeater configuration register bit assignments 31:13 12 11 10 9 8 7 6 5 4 3 2 1:0 reserved enable port late event auto clear stats enable send /t/r iso 100 iso 10 uni-cast frame count arbit input va l u e zero cntrs enable fifo error enable manchstr code violation reserved table 71: repeater configuration register bit definitions bit name type 1 description default 31:13 reserved r/w reserved - write as 0s; ignore on read. n/a 12 enable portn late event r/w a 0 does not allow out-of-window collisions to increment portns late event counter. a 1 does allow it. 0 11 auto-clear r/w a 0 causes interrupt status register and search port match register to automatically clear when read. a 1 requires that the appropriate register bits be written to be cleared. this is done by writing a 1 to the bit(s) that are to be cleared. 0 10 statistics enable r/w turns statistics gathering on and off. a 1 enables statistics gathering. 0 disables statistics gathering. 1 9 send /t/r r/w forces a good /t/r after each 100 mbps transmission. a 1 forces /t/r. 0 disables forced /t/r. 0 8 isolate 100 r/w isolates the ir100cfs stack signal and provides an output pin for dis- abling an external backplane transceiver. a 1 isolates. 0 does not isolate. 0 7 isolate 10 r/w isolates the ir10col and ir10cfs signals and provides an output pin for disabling an external backplane transceiver. a 1 isolates. 0 does not isolate. 0 6 countmode r/w changes the definition of portreadableframes to only count unicast frames. a 1 counts unicast only. 0 counts all. 0 5 arbitration input value r as read from input pin. n/a 4 zero counters r/w a 1 causes the lxt980 to sequentially walk through each counter loca- tion and zero its contents 2 . when all counter locations have been cleared 3 , this bit will be reset to a 0. 0 1. r = read only; r/w = read/write. 2. while zeroing is in progress, the cpu will be locked out from accessing the statistics ram until the zero counters bit has be en reset back to 0. this will be approximately 15 m s. 3. the rptrmonitorportbroadcastpkts and rptrmonitorportmulticastpkts counters (refer to table 51 on page 70) are not cleared by th e zero counters bit.
lxt980/980a dual-speed, 5-port fast ethernet repeater 84 - - 3enable fifo error r/w when set to 1, the lxt980 enters transmit collision upon detection of a data rate mismatch. 1 2enable manchester code violation r/w when set to 1, the lxt980 enters transmit collision upon detection of a manchester code violation (10 mbps only) 0 1:0 reserved r/w reserved - write as 0s; ignore on read. n/a table 72: device/revision register bit assignment 31:28 27:12 11:8 7:1 0 version part no. jedec continuation characters jedec id 1 1st in chain 2 0100 (lxt980) 0000 0011 1101 0100 0000 111 1110 see note 2 0110 (lxt980a) 1. the jedec id is an 8-bit identifier. however, the msb is for parity only and is ignored. level ones jedec id is fe (1111 1110) which becomes 111 1110. 2. first chain bit = 0 if chipid 1 000. first chain bit = 1 if chipid = 000. table 73: global led control register bit assignments 31:6 5 4 3 2 1:0 reserved mode control global fault led reserved table 74: port led control register bit assignments 31:10 9 8 7 6 5 4 3 2 1 0 rsvd port 5 (mii) port 4 port 3 port 2 port 1 table 71: repeater configuration register bit definitions C continued bit name type 1 description default 1. r = read only; r/w = read/write. 2. while zeroing is in progress, the cpu will be locked out from accessing the statistics ram until the zero counters bit has be en reset back to 0. this will be approximately 15 m s. 3. the rptrmonitorportbroadcastpkts and rptrmonitorportmulticastpkts counters (refer to table 51 on page 70) are not cleared by th e zero counters bit.
85 lxt980/980a register definitions table 75: led timer control register bit assignments 31:16 15:8 7:0 reserved slow blink frequency fast blink frequency 1. period = 7.8125 ms x (register value + 1) table 76: address assignment register bit assignments assign addr 1 31:0 bits (47:16) of the eprom serial number assign addr 2 31:21 20:16 15:0 zeros hub id(4:0) bits (15:0) of the eprom serial number table 77: eprom address register bit assignments eprom addr 1 31:0 bits(47:16) of the eprom serial number eprom addr 2 31:16 15:0 zeros bits (15:0) of the eprom serial number 2.frequency 1 7.8125m s registervalue 1 + () ---------------------------------------------------------------------------------- - =
lxt980/980a dual-speed, 5-port fast ethernet repeater 86 auto-negotiation registers table 78: auto-negotiation registers name size bits addr type 1 description auto-negotiate link partner ability #1 (port 1) 16 09e r refer to table 79 auto-negotiate link partner ability #2 (port 2) 16 09f r auto-negotiate link partner ability #3 (port 3) 16 0a0 r auto-negotiate link partner ability #4 (port 4) 16 0a1 r auto-negotiate status #1 (port 1) 16 0a2 r refer to table 80 auto-negotiate status #2 (port 2) 16 0a3 r auto-negotiate status #3 (port 3) 16 0a4 r auto-negotiate status #4 (port 4) 16 0a5 r auto-negotiate advertisement #1 (port 1) 16 0a6 r/w refer to table 81 auto-negotiate advertisement #2 (port 2) 16 0a7 r/w auto-negotiate advertisement #3 (port 3) 16 0a8 r/w auto-negotiate advertisement #4 (port 4) 16 0a9 r/w auto-negotiate configuration 8 0aa r/w refer to table 82 1. r = read only; r/w = read/write. table 79: auto-negotiation link partner ability registers bit name description type 1 default 15 next page 1 = link partner has ability to send multiple pages 0 = link partner has no ability to send multiple pages rn/a 14 acknowledge 1 = link partner has received link code word from lxt980 0 = link partner has not received link code word from lxt980 rn/a 13 remote fault 1 = remote fault. 0 = no remote fault. rn/a 12:10 reserved write as 0, ignore on read r n/a 9 100base-t4 1 = link partner is 100base-t4 capable. 0 = link partner is not 100base-t4 capable. rn/a 8100base-tx full-duplex 1 = link partner is 100base-tx full-duplex capable. 0 = link partner is not 100base-tx full-duplex capable. rn/a 7 100base-tx 1 = link partner is 100base-tx capable. 0 = link partner is not 100base-tx capable. rn/a 1. r = read only.
87 lxt980/980a register definitions 610base-t full-duplex 1 = link partner is 10base-t full-duplex capable. 0 = link partner is not 10base-t full-duplex capable. rn/a 5 10base-t 1 = link partner is 10base-t capable. 0 = link partner is not 10base-t capable. rn/a 4:0 selector field <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto-negotiation development. unspecified or reserved combinations shall not be transmitted. rn/a table 80: auto-negotiation status registers bit name description type 1 default 15:5 reserved write as zero, ignore on read. r 4 parallel detec- tion fault 1 = more than one of the pmas detects a valid link. 0 = no conflict. r/lh 3 link partner next page able 1 = link partner is next page able. 0 = link partner is not next page able. r 2 next page able 0 = local device is not next page able. r 1 page received 1 = three identical and consecutive link code words have been received from link partner. 0 = three identical and consecutive link code words have not been received from link partner. r/lh 0 link partner auto-negotia- tion able 1 = link partner is auto-negotiate able. 0 = link partner is not auto negotiate able. r/lh 1. r = read only; lh = latching high. table 79: auto-negotiation link partner ability registers C continued bit name description type 1 default 1. r = read only.
lxt980/980a dual-speed, 5-port fast ethernet repeater 88 table 81: auto-negotiation advertisement register bit name description type 1 default 15 next page 1 = phy has ability to send multi-pages. 0 = phy has no ability to send multi-pages. r0 14 reserved write as zero, ignore on read. r 0 13 remote fault 1 = remote fault. 0 = no remote fault. r/w 0 12:10 reserved write as zero r 0 9 100base-t4 1 = 100base-t4 capability is available. 0 = 100base-t4 capability is not available. the lxt980 does not support 100base-t4 operation. r0 8100base-tx fd 1 = dte is 100base-tx full-duplex capable. 0 = dte is not 100base-tx full-duplex capable. r0 7 100base-tx 1 = dte is 100base-tx capable. 0 = dte is not 100base-tx capable. r 2 1 6 10base-t fd 1 = dte is 10base-t full-duplex capable. 0 = dte is not 10base-t full-duplex capable. r0 5 10base-t 1 = dte is 10base-t capable. 0 = dte is not 10base-t capable. r 2 1 4:0 selector field, <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto-negotiation development. unspecified or reserved combinations should not be transmitted. r 00001 1. r = read only; r/w = read/write. 2. these settings are determined by the port speed control register and the auto negotiate configuration register.
89 lxt980/980a register definitions table 82: auto-negotiation configuration register bit name description type 1 default 7 restart negotiate (port 4) writing a 1 causes the port to renegotiate if its auto-negotiate enable bit is set to 1. writing a 1 to this bit overrides the port external configuration settings. these bits are self-clearing. w0 6 restart negotiate (port 3) w0 5 restart negotiate (port 2) w0 4 restart negotiate (port 1) w0 3 auto-negotiate enable (port 4) 1 = port auto negotiate is enabled. 0 = port auto negotiate is not enabled. enabling auto-negotiation via software requires writing to both the port speed control register and the auto-negotiate configuration register (see table 61 on page 77). if auto negotiate is not enabled, the port will take on the speed forced values set in the port speed control register. if auto negotiate is enabled, all abilities will be advertised. forcing a port speed via the port speed control register (refer to table 61) will always over- ride and disable auto-negotiation. r/w 1 2 auto-negotiate enable (port 3) r/w 1 1 auto-negotiate enable (port 2) r/w 1 0 auto-negotiate enable (port 1) r/w 1 1. w = write; r/w = read/write.
lxt980/980a dual-speed, 5-port fast ethernet repeater 90 mechanical specifications figure 41: package specifications dim millimeters min max a-4.10 a1 0.25 - a2 3.20 3.60 b 0.17 0.27 d 30.30 30.90 d 1 27.70 28.30 e 30.30 30.90 e 1 27.70 28.30 e .50 b asic l 0.50 0.75 l 1 1.30 ref q0 7 q 2 5 16 q 3 5 16 e / 2 a 1 a 2 l a b l 1 q 3 q 2 q d d 1 e e 1 e 208-pin plastic quad flat package ? part numbers: ? lxt980qc ? LXT980AHC ? commercial temperature range (0 c to 70 c)
91 lxt980/980a revision history revision history table 83: changes from rev 1.3 to 1.4 (3/99) section page change description led mode 2 26 add add link up to 10m blink description. table 84: changes from rev 1.2 to rev 1.3 (2/99) section page change description general description 1 add to the first paragraph, add the following sentence: this data sheet applies to all lxt980 products (lxt980, lxt980a, and any subsequent variants), except as specifically noted. pin assignments figure 1 4modify add pin 74: for lxt980a, pin name is auto_blink. add note at bottom of figure. add add data code, trace code, part#, and lot# information to pinout figure. signal descriptions 5-14 modify editorial clean-up: re-order, clarify information in type column. irb signal description 8 modify for ir100cfsb signal, change pull-up resistor value from 82 w to 91 w . power supply and indication signal description table 9 13 add add note regarding pin 74 (see gnd in symbol column). misc. signal desc. table 11 14 add add note regarding pin 74 (see auto_blink in symbol column). port leds 24 add add link loss paragraph explaining led indication during link loss. led mode 1 table 13 25 modify add to port n led3 row: change no link established to no link, (fast blink). add note at bottom of table explaining auto_blink pin for lxt980a. led mode 2 table 14 26 correct information and reformat to account for lxt980a and hardware control for 10m versus 100m operation. add auto_blank note at the bottom of table. led mode 3 table 15 27 delete for port n led row: delete established under blink column. irb signal details table 17 29 modify for ir100cfsbp signal, change pull-up resistor value from 82 w to 91 w . typical 100 mbps implementation figure 21 46 modify for ir100cfsbp signal, change pull-up resistor value from 82 w to 91 w .
lxt980/980a dual-speed, 5-port fast ethernet repeater 92 100 mbps irb electrical char. table 28 50 modify for ir100cfsbp , test conditions column: change rl value from 82 w to 91 w. 10 mbps irb receive timing parameters figure 37 table 45 65 modify change figure and table to correctly represent data to clock prop. delay, not setup and hold times, as previously shown. 10 mbps irb transmit timing parameters figure 38 table 46 66 delete in table 46: delete ir10clk to ir10dat (output) propagation delay parameter; in figure 38, delete associated timing references. port counter regs. table 51 70 modify add for rptrmonitorportrunts register, 100m operation: change >92 to > 92. add note 2 explaining 100m operation nibble boundaries. rmon counter registers table 52 72 add toetherstatsoversizepkts and etherstatsjabbers add lxt980 and lxt980a relevant information to description column. gen. port con. regs. table 59 76 add to port alternate partition algorithm control register: add bit description information for lxt980a. port learn and speed control regs. table 61 77 to port speed control register description: add information on enabling auto-negotiation via software. device/revision reg. table 72 84 modify add correct lxt980 value from 0000 to 0100. add lxt980a value of 0110. a/n config. reg. table 82 89 add to auto-negotiation configuration register description: add information on enabling auto-negotiation via software. mechanical specs. 90 add add LXT980AHC part number. backpage 100 modify update. table 84: changes from rev 1.2 to rev 1.3 (2/99) C continued section page change description
93 lxt980/980a revision history table 85: changes from rev 1.1 to rev 1.2 (12/98) section page change description features 1 modify change 0 - 70 temperature range to case temperature range: 0 - 115. pin assign figure 1 4 correct change irq to irq to correctly indicate as active low. change macactiv to macactive. (correct text throughout.) mode control signals table 1 5 add add pd to config<0:7> type column. mac mode mii interface signal 7 delete delete last sentence in transmit error description. irb signals table 4 7 modify re-write, expand description of ir100cfs signal. 8 re-write, expand description of ir100cfsbp , and ir100dv sig- nals. change irden to ir100den. add add schmitt mos pu to ir100sngl, ir100col, ir100dv, ir100dat<0:4>. add pd to ir100clk. add a 1k pull-up resistor to ir100clk; modify description accord- ingly. 9 modify change irden to ir10den. add add pd to ir10dat, ir10clk. add mos pu to ir10ena, ir10col. modify change analog to mos on ir10colbp. re-write, expand description of ir10cfs , ir10cfsbp , and macactive signals. change ircfs to ir10cfs . twisted-pair port signals 10 add to twisted-pair outputs and twisted-pair inputs descriptions add these pins can be left open when not used. smi signals 11 add add pd to serclk. modify re-write arbitration in/out description. to manager present description, change first sentence to read: this signal is sensed at power up and hardware reset . power supply & indication signals table 9 13 modify replace - under type column with respective analog and dig- ital indications. change 1% 22 k w resistor to 22.1 k w , 1% resistor. prom interface table 10 14 modify re-write, expand descriptions of prom_cs and prom_dtout. add add pd to prom_clk, prom_dtn. delete delete pd from prom_cs, prom_dtout. mii 20 add add following note: the mii does not auto-negotiate, auto speed change, auto-link, or partition.
lxt980/980a dual-speed, 5-port fast ethernet repeater 94 repeater operation 21 add add or one long collision approximately 575.2 m s long. modify in un-isolate bullet: change transmits to receives. in jabber bullet: change all receivers to all jabbering receivers. power requirements 23 modify re-write first and second sentences under power heading. bias resistor change 1% 22 k w resistor to 22.1 k w , 1% resistor. irb bus pull-ups 23 add add ir100clk. mac irb access 27 modify re-write first sentence to indicate macactive is a ttl-level pin. irb isolation add add a note: inter-board analog signals will be isolated internally by the device. irb signal details table 17 28 modify change no to 1 k w under pull-up heading for ir100clk signal. change ir100cfsbp pull-up resistor value to 82 w . mii port operation 29 delete delete first sentence of 2nd paragraph. mii port timing considerations 30 modify re-write paragraph. mii timing issues figure 8 clarify mii-to-mii, phy-to-mac prop. delay. auto-clearing registers 31 add add description/explanation of clear on read registers. smi message fields table 19 32 modify for chip id message: change eight modules to eight lxt980 devices on a board or sub-system. chain arbitration 35 add to second paragraph, add the following sentence: tie to arbout of the scc or to previous hub in the daisy chain. the first hub arbin can also be grounded. address re- arbitration add the following sentences: this message will be sent regardless of arbitration method; however, with chain arbitration mecha- nism, it will be sent once. the message can be ignored. general design guidelines 37-38 modify update section; remove references to separate analog & digital ground planes and associated ferrite bead filter. rbias pin 38 modify change 1% 22 k w resistor to 22.1 k w , 1% resistor. magnetics information table 23 table 24 39 modify remove suggested magnetics list and update magnetics specifica- tions. move differential to cmr from min to max column; indi- cate as -40 and -35 for.1 to 60 mhz and 60 to 100 mhz, respectively. pwr & gnd connections figure 18 42 modify removed filter bead separating analog and digital grounds. change 1% 22 k w resister to 22 .1 k w, 1%. table 85: changes from rev 1.1 to rev 1.2 (12/98) C continued section page change description
95 lxt980/980a revision history twisted-pair port interface figure 20 44 modify reverse rj45 connections to show repeater i/f, not nic. should be: tpop = 3, tpon = 6 tpip = 1, tpin = 2 typ. 100 mbps irb implement figure 21 45 add add two 1 k w resistors to ir100clk line, on either side of the 245 buffer. modify change ir100cfsbp pull-up resistor value to 82 w . test specifications 47 modify delete re-write note; delete over recommended range from all table titles (28-49). absolute max ratings table 25 modify increase max case temp to 130. revise warning to address immediate eos damage. 100 mbps irb electrical characteristics 48 modify change ir100cfsbp test condition r l value to 82 w. 10 mbps irb electrical characteristics table 29 49 modify output low voltage: change min, typ, and max values. ir10cfs current for single drive: change typ value. ir10cfs/bp voltage for single drive and collision: change min, typ, and max values. test spec tables 33 - 48 51-65 modify clarify definition of bit times (bt) for both 10 and 100base-tx. this appears as a note to the unit column. change timing parameter symbol convention. test spec figures 25 - 40 modify figures to correspond to timing parameter convention changes. test spec figure 34 table 42 60 delete delete tx_en sampled to tpop active (tx latency). 10t tx timing table 42 modify modify tx_en sampled to crs asserted min, typ, and max values. 10t rx timing table 43 61 modify tpip/n in to crs asserted: change min, typ, and max values. crs asserted to rxd, rx_dv, rx_er: change min, typ, and max values. tpip/n in to col asserted: change min, typ, and max values. 100 irb timing table 44 figure 36 62 delete modify delete ir100ena asserted to tpop/n or fibop/n active and cor- responding figure element. tpip/n or fibp/n to ir100dv low: change min, typ, and max values. 10 mbps irb receive timing table 45 63 modify tpip/n to ir10ena low: change min, typ values. table 85: changes from rev 1.1 to rev 1.2 (12/98) C continued section page change description
lxt980/980a dual-speed, 5-port fast ethernet repeater 96 . 10 irb tx timing table 46 64 modify ir10ena asserted to tpop/n active: change min, typ, and max values. port counter register table 51 67 modify rptrmonitorportshortevents counter should increment as follows: 10m: count events < 80 bit times. 100m: count events < 88 bit times. rptrmonitorportrunts counter should increment as follows: 10m: count events > 80 and < 504 bit times. 100m: count events > 92 and < 504 bit times. rmon counter registers table 52 69 - 70 add to etherstatsbroadcastpkts description add: counter is not cleared by zerocount bit. to rptrmonitortotaloctets description add: counter is not cleared by zerocount bit. repeater reset register table 69 78 correct rewrite repeater reset register description. rewrite software reset register description. led timer control register table 75 81 correct bit assignments 15:8 is slow blink frequency; 7:0 is fast blink frequency. throughout all modify replace module with board where appropriate. all all modify light editing throughout. backpage 94 modify update table 86: changes from rev 1.0 to rev 1.1 section page change description table 1, mode control signals 5 add added pull-up notation to port select signals table 4, irb signals 8 add add pull-down notation to pin 199, mmstrin. added schmitt trigger info to ir100clk table 7, serial i/f signals 11 add/ correct added pull-down & pull-up notations to various signals. changed serclk type from output to input/output table 8, led signals 12 add/ correct changed type from open drain to active low output. added pull-down notation to led select signals table 9, power signals 13 addition added pull-down notations to rps_pres signal. added pull-up notations to rps_fault signal. table 10, mode prom signals 14 add added note to prom_clk description regarding applicability to chipid=0. table 11, misc. signals 14 add added pull-down notations to chipid signals. table 85: changes from rev 1.1 to rev 1.2 (12/98) C continued section page change description
97 lxt980/980a revision history functional description 15-35 modify editorial rewrite of sections on repeater operation, irb operation, mii port operation. figure 5 app block diagram 17 modify added serial termination resistors to mii outputs. tables 16 & 17, irb signals 27 add added new tables to clarify interconnection and pull-up requirements. chain arbitration 35 add add sentence: tie to arbout of the scc or to previous hub in the daisy chain. the first hub arbin can also be grounded. application information 36-37 modify & add revised and expanded write-ups on general design guidelines, power & gnd filtering, tp & fiber interfaces, etc. table 23, magnetics list 38 add expanded list of available magnetics. table 23, magnetics specs 38 add added return loss specs for enhanced magnetics. figure 18 pwr & gnd 41 add added new diagram showing power & ground circuits figure 19 fiber i/f 42 modify deleted note 1 suggesting digital supply for fiber bias circuit in combi- nation tp & fiber applications. figure 20 tp i/f 43 modify & add changed note 2 to refer to tpi bypass cap, instead of chassis gnd bypass. added new material showing compensating inductor. figure 21 100m irb 44 modify added pull-ups to chipid 1 & 2, and added note specifying treatment of ir100cfsbp. figure 22 10m irb 44 modify added pull-ups to chipid 1 & 2, and added note specifying treatment of ir10cfsbp and ir10colbp. table 24, absolute max ratings 46 add added max case temp. table 25, ops conditions 46 add & modify added max case temp. increased fx mode power consumption. table 27 i/o characteristics 47 add defined schmitt trigger specs as applicable to clk25 & reset table 28 irb100 characteristics 47 add added schmitt trigger specs for ir100clk. table 29, irb10 characteristics 48 add added schmitt trigger specs for ir10clk. expanded table to address single & double drive values. table 30, tx characteristics 48 modify modified parameters to match lxt970. table 31, fx characteristics 49 modify modified parameters to match lxt970. figure 27 100tx receive 52 correct corrected diagram to match table (show t dpd instead of t dsu /t dh ). table 86: changes from rev 1.0 to rev 1.1 C continued section page change description
lxt980/980a dual-speed, 5-port fast ethernet repeater 98 tables 34, 36, 38, 40 & 42 tx timing 51-59 modify changed t dh (data hold from clock high) from 0 to 5 ns. table 46 10irb tx timing 63 correct corrected parameter symbols for t irdpd and t irtpon table 61 gen port control registers 72 modify added info to clarify the default and alternate partition algorithms. table 68 interrupt register 75 correct & add reversed settings. was active low (0 = interrupt. 1 = no interrupt, default). now active high (1 = interrupt. 0 = no interrupt, default). added material on jabber, isolate & partition conditions. added info to clarify mask/no mask settings. table 73 rptr config reg 80 modify renamed bit 11 as auto-clear and rewrote description to clarify func- tion. changed default value of bit 9 from 1 to 0. figure 41 pkg specs 87 modify replaced basic values with min & max for d, d1, e and e1. table 86: changes from rev 1.0 to rev 1.1 C continued section page change description
99 lxt980/980a notes notes
east west asia/pacific europe eastern area headquarters & northeastern regional office western area headquarters asia / pacific area headquarters european area headquarters 234 littleton road, unit 1a westford, ma 01886 usa tel: (978) 692-1193 fax: (978) 692-1124 3375 scott blvd., #110 santa clara, ca 95054 usa tel: (408) 496-1950 fax: (408) 496-1955 101 thomson road united square #08-01 singapore 307591 thailand tel: +65 353 6722 fax: +65 353 6711 parc technopolis-bat. zeta 3, avenue du canada - z.a. de courtaboeuf les ulis cedex 91974 france tel: +33 1 64 86 2828 fax: +33 1 60 92 0608 north central regional office south central regional office central asia/pacific regional office central and southern europe regional office one pierce place suite 500e itasca, il 60143 usa tel: (630) 250-6044 fax: (630) 250-6045 800 east campbell road suite 199 richardson, tx 75081 usa tel: (972) 680-5207 fax: (972) 680-5236 suite 305, 4f-3, no. 75, hsin tai wu road sec. 1, hsi-chih, taipei county, taiwan tel: +886 22 698 2525 fax: +886 22 698 3017 regus feringastrasse 6 d-85774 muenchen- unterfoerhring, germany tel: +49 89 99 216 375 fax: +49 89 99 216 319 southeastern regional office southwestern regional office northern asia/pacific regional office northern europe regional office 4020 westchase blvd suite 100 raleigh, nc 27607 usa tel: (919) 836-9798 fax: (919) 836-9818 28202 cabot road suite 300 laguna niguel, ca 92677 usa tel: (949) 365-5655 fax: (949) 365-5653 nishi-shinjuku, mizuma building 8f 3-3-13, nishi-shinjuku, shinjuku-ku tokyo, 160-0023 japan tel: +81 3 3347-8630 fax: +81 3 3347-8635 torshamnsgatan 35 164/40 kista/stockholm, sweden tel: +46 8 750 3980 fax: +46 8 750 3982 latin/south america 9750 goethe road sacramento, ca 95827 usa tel: (916) 855-5000 fax: (916) 854-1102 revision date status 1.4 03/99 minor correction to led mode 2 indications description. 1.3 02/99 add a8 design revision; minor editing. 1.2 12/98 additions to signal descriptions; add clear on read description; correct twisted-pair interface figure; add transmit/receive timing parameter values. ) copyright ? 1999 level one communications, inc., an intel company. specifications subject to change without notice. all rights reserved. printed in the united states of america. ds-t980-r1.4-0399 this product is covered by one or more of the following patents. additional patents pending. the products listed in this publication are covered by one or more of the following patents. additional patents pending. 5,008,637; 5,028,888; 5,057,794; 5,059,924; 5,068,628; 5,077,529; 5,084,866; 5,148,427; 5,153,875; 5,157,690; 5,159,291; 5,162,746; 5,166,635; 5,181,228; 5,204,880; 5,249,183; 5,257,286; 5,267,269; 5,267,746; 5,461,661; 5,493,243; 5,534,863; 5,574,726; 5,581,585; 5,608,341; 5,671,249; 5,666,129; 5,701,099 international the americas corporate headquarters 9750 goethe road sacramento, california 95827 telephone: (916) 855-5000 fax: (916) 854-1101 web: www.level1.com

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