9-11 file number 3683.7 note: the design of the sp720md-8, sp720md, SP720MM-8, and sp720mm scr/diode esd diode protection arrays is covered by littelfuse patent 4567500. 1-800-999-9445 or 1-847-824-1188 | copyright littelfuse, inc. 1999 sp720md-8, sp720md, SP720MM-8, sp720mm high reliability electronic protection array for esd and overvoltage protection the sp720 is a high reliability array of scr/diode bipolar structures for esd and over-voltage protection to sensitive input circuits. the sp720 has 2 protection scr/diode device structures at each in input. a total of 14 available in inputs can be used to protect up to 14 external signal or bus lines. over voltage protection is from the in to v+ or v -. the scr structures are designed for fast triggering at a threshold of one +v be diode threshold above v+ or at a -v be diode threshold below v-. from an in input, a clamp to v+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one v be above v+. a similar clamp to v- is activated if a negative pulse, one v be less than v-, is applied to an in input. the sp720md and sp720mm are high reliability ceramic packaged ics. refer to application note an9304 for general application information and to an9612 for further information on esd and transient rating capabilities of the sp720. features the sp720md-8 and SP720MM-8 are littelfuse class q ?quivalent parts and mil-prf-38535 non-compliant esd interface capability for hbm standards - modi?d mil std 3015.7 . . . . . . . . . . . . . . . . . . . .15kv - mil std 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . .6kv - iec 1000-4-2, direct discharge, single input. . . . . . . . . . . . . . . . . . . . . . . . 4kv (level 2) two inputs in parallel . . . . . . . . . . . . . . . . 8kv (level 4) - iec 1000-4-2, air discharge. . . . . . . . . . 15kv (level 4) high peak current capability - iec 1000-4-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3a - single pulse, 100 s pulse width . . . . . . . . . . . . . . 2a - single pulse, 4 s pulse width . . . . . . . . . . . . . . . . 5a designed to provide over-voltage protection - single-ended voltage range to . . . . . . . . . . . . . . .+30v - differential voltage range to . . . . . . . . . . . . . . . . 15v fast switching . . . . . . . . . . . . . . . . . . . . . . . 2ns risetime low input leakages . . . . . . . . . . . . . . 1na at 25 o c typical low input capacitance. . . . . . . . . . . . . . . . . . 3pf typical an array of 14 scr/diode pairs military temperature range . . . . . . . . . . . -55 o c to 125 o c applications microprocessor/logic input protection data bus protection analog device input protection voltage clamp ordering information part no. temp. range ( o c) package pkg. no. sp720md-8 -55 to 125 16 ld sbdip d16.3 sp720md -55 to 125 16 ld sbdip d16.3 SP720MM-8 -55 to 125 20 pad clcc j20.a sp720mm -55 to 125 20 pad clcc j20.a pinouts functional block diagram (sp720md) sp720md (sbdip) top view sp720mm (clcc) top view in in in in in in in v- v+ in in in in in in in 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 in in in in in in in nc nc v+ v- nc nc in in in in in in in 4 5 6 7 8 10 11 12 13 9 3212019 16 17 18 15 14 16 1 2 8 v+ 3 - 7 in 9 - 15 in in v- data sheet july 1999 [ /title (sp72 0md- 8, sp720 md, sp720 mm-8, sp720 mm) /sub- ject (high reli- ability elec- tronic protec- tion array for esd and over- volt- age protec-
9-12 absolute maximum ratings thermal information continuous supply voltage, [(v+) - (v-)] . . . . . . . . . . . . . . . . . +35v max. dc input current, i in . . . . . . . . . . . . . . . . . . . . . . . . . . 70ma input peak current, i in (refer to figure 3) . . . . . . . . . . 2a, 100 s esd capability, refer to ?sd capability and table 1, figure 1 operating conditions operating voltage range, single supply . . . . . . . . . . . . +2v to +30v operating voltage range, split supply . . . . . . . . . . . . 1v to 15v typical quiescent supply current . . . . . . . . . . . . . . . . . . . . . . .50na operating temperature range. . . . . . . . . . . . . . . . . -55 o c to 125 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) 16 ld sbdip package . . . . . . . . . . . . . 80 18 20 pad clcc package . . . . . . . . . . . . 70 16 maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .175 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .265 o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations t a = -55 o c to 125 o c, unless otherwise speci?d parameter symbol test conditions min typ max units operating voltage range v supply v supply = [(v+) - (v-)] 0 2 to 30 35 v peak forward/reverse voltage drop in to v- (with v- reference) v in - (v-) i in = -1a (1ms peak pulse) - -2 - v in to v+ (with v+ reference) v in - (v+) i in = +1a (1ms peak pulse) - +2 - v dc forward/reverse voltage drop in to v- (with v- reference) v in - (v-) i in = -100ma to v- -1.5 - - v in to v+ (with v+ reference) v in - (v+) i in = +100ma to v+ - - +1.5 v input leakage current i in v- < v in < v+, v supply = 30v -15 5 +15 na quiescent supply current i quiescent v- < v in < v+, v supply = 30v - 50 150 na equivalent scr on threshold note 3 - 1.1 - v equivalent scr on resistance v fwd /i fwd (note 3) - 1 - ? input capacitance c in -3-pf input switching speed t on -2-ns notes: 2. in automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse b attery. when the v+ and v- pins are connected to the same supply voltage source as the device or control line under protection, a current limiti ng resistor should be connected in series between the external supply and the sp720 supply pins to limit reverse battery current to within the rat ed maximum limits. bypass capacitors of typically 0.01 f or larger from the v+ and v- pins to ground are recommended. 3. refer to the figure 3 graph for definitions of equivalent ?cr on threshold?and ?cr on resistance? these characteristics a re given here for thumb-rule information to determine peak current and dissipation under eos conditions. h.v. supply v d in dut c d r 1 iec 1000-4-2: r 1 50 to 100m ? r d charge switch discharge switch mil std 3015.7: r 1 1 to 10m ? figure 1. electrostatic discharge test table 1. esd test conditions standard type/mode r d c d v d mil std 3015.7 modified hbm 1.5k ? 100pf 15kv standard hbm 1.5k ? 100pf 6kv iec 1000-4-2 hbm, air discharge 330 ? 150pf 15kv (level 4) hbm, direct discharge 330 ? 150pf 4kv (level 2) hbm, direct discharge, two parallel input pins 330 ? 150pf 8kv (level 4) eiaj ic121 machine model 0k ? 200pf 1kv sp720md-8, sp720md, SP720MM-8, sp720mm
9-13 esd capability esd capability is dependent on the application and de?ed test standard. the evaluation results for various test standards and methods based on figure 1 are shown in table 1. for the ?odified?mil-std-3015.7 condition that is defined as an ?n-circuit?method of esd testing, the v+ and v- pins have a return path to ground and the sp720 esd capability is typically greater than 15kv from 100pf through 1.5k ? . by strict definition of mil-std-3015.7 using ?in-to-pin?device testing, the esd voltage capability is greater than 6kv. the mil-std-3015.7 results were determined from at&t esd test lab measurements. the hbm capability to the iec 1000-4-2 standard is greater than 15kv for air discharge (level 4) and greater than 4kv for direct discharge (level 2). dual pin capability (2 adjacent pins in parallel) is well in excess of 8kv (level 4). for esd testing of the sp720 to eiaj ic121 machine model (mm) standard, the results are typically better than 1kv from 200pf with no series resistance. peak transient current capability the peak transient current capability rises sharply as the width of the current pulse narrows. destructive testing was done to fully evaluate the sp720 s ability to withstand a wide range of transient current pulses. the test circuit shown in figure 2 provides a positive pulse input. for a negative pulse input, the (-) current pulse input goes to an sp720 ?n input pin and the (+) current pulse input goes to the sp720 v- pin. the v+ to v- supply of the sp720 must be allowed to ?at (i.e., it is not tied to the ground reference of the current pulse generator). figure 3 shows the point of overstress as de?ed by increased leakage in excess of the data sheet published limits. the maximum peak input current capability is dependent on the v+ to v- voltage supply level, improving as the supply voltage is reduced. values of 0, 5, 15 and 30 voltages are shown. the safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in figure 3. when adjacent input pins are paralleled, the sustained peak current capability is increased to nearly twice that of a single pin. for comparison, tests were run using dual pin combinations 1+2, 3+4, 5+6, 7+9, 10+11, 12+13 and 14+15. the overstress curve is shown in figure 3 for a 15v supply condition. the dual pins are capable of 10a peak current for a 10 s pulse and 4a peak current for a 1ms pulse. the complete curve for single pulse peak current vs. pulse width time ranging up to 1 second is shown in figure 3. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 in in in in in in v- in v+ in in in in in in in r 1 ~ 10 ? typical sp720 v g adj. 10v/a typical c1 ~ 100 f figure 2. typical sp720 peak current test circuit with a variable pulse width input + - current sense voltage probe + - v x r 1 ( - ) (+) c1 variable time duration current pulse generator figure 3. typical single pulse peak current curves showing the measured point of overstress in amperes vs pulse width time in milliseconds (t a = 25 o c) 0.001 0.01 0.1 1 pulse width time (ms) peak current (a) 10 8 7 6 5 4 3 2 1 0 0v 5v 15v 100 1000 10 9 30v 15v caution: safe operating conditions limit of the values shown on each curve. pulse width to be no greater than 75% the maximum peak current for a given single pin stress curves dual pin stress curve v+ to v- supply sp720md-8, sp720md, SP720MM-8, sp720mm
9-14 figure 4. low current scr forward voltage drop curve figure 5. high current scr forward voltage drop curve figure 6. typical application of the sp720 as an input clamp for overvoltage, greater than 1v be above v+ or less than -1v be below v-. pinout shown is for the sp720md sbdip package 600 800 1000 1200 forward scr voltage drop (mv) 100 80 60 40 20 0 forward scr current (ma) single pulse t a = 25 o c 0123 forward scr voltage drop (v) 2.5 2 1.5 1 .5 0 forward scr current (a) single pulse equiv. sat. on threshold ~1.1v i fwd v fwd t a = 25 o c +v cc input drivers protection (1 of 14 on chip) sp720 input or signal sources in 9-15 in 1-7 sp720 linear or digital ic interface v- v+ to +v cc +v cc circuit sp720md-8, sp720md, SP720MM-8, sp720mm
9-15 power dissipation derating curves figure 7. sp720md derating curve for the 82 o c/w thermal resistance of the sidebraze 16 lead ceramic package, derated 12.2mw/ o c from a maximum p d of 1.0w at 93 o c figure 8. sp720mm derating curve for the 70 o c/w thermal resistance of the 20 pad ceramic lcc package, derated 14.3mw/ o c from a maximum p d of 1.0w at 105 o c 0 50 100 150 0.5 1.0 0.610w 175 125 power dissipation (w) ambient temperature ( o c) max dissipation max. derated 0 93 o c82 o c dissipation 0 50 100 150 0.5 1 0.714w 175 125 power dissipation (w) ambient temperature ( o c) max dissipation 105 o c70 o c max. derated dissipation sp720md-8, sp720md, SP720MM-8, sp720mm
9-16 sp720md-8 and SP720MM-8 dynamic burn-in circuits 16 lead ceramic sbdip notes: 4. all resistors 1k ? 10%. 5. v cc = 30v 1%. 6. f s = 0v to 30v 1%, 50% duty cycle. 7. c 1 = 22 f min tantalum, 50wv (33wv at 125 o c). 8. t amb = 125 o c. 20 pad clcc 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 v cc input signal c 1 f s 4 5 6 7 8 10 11 12 13 9 3212019 16 17 18 15 14 f s input signal v cc c1 0v 30v f s sp720md-8, sp720md, SP720MM-8, sp720mm
9-17 die characteristics die dimensions: 51 mils x 84 mils x 14 mils 1 mil metallization: type: al thickness: 17.5k ? 2.5k ? passivation: type: sio 2 thickness: 13k ? 2.6k ? substrate potential (powered up): v- worst case current density: 9.18 x 10 4 a/cm 2 at 70ma process: bipolar metallization mask layout sp720md-8, sp720md, SP720MM-8, sp720mm v cc (16) 9 (sbdip pinout) gnd (8) 1 sp720md-8, sp720md, SP720MM-8, sp720mm
9-18 sp720md-8, sp720md, SP720MM-8, sp720mm ceramic dual-in-line metal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer? identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa c a - b m d s s ccc c a - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d16.3 mil-std-1835 cdip2-t16 (d-2, configuration c) 16 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.840 - 21.34 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n16 168 rev. 0 4/94
9-19 sp720md-8, sp720md, SP720MM-8, sp720mm ceramic leadless chip carrier packages (clcc) d j x 45 o d3 b h x 45 o a a1 e l l3 e b3 l1 d2 d1 e 1 e2 e1 l2 plane 2 plane 1 e3 b2 0.010 e h s s 0.010 e f s s -e- 0.007 e f m s hs b1 -h- -f- j20.a mil-std-1835 cqcc1-n20 (c-2) 20 pad ceramic leadless chip carrier package symbol inches millimeters notes min max min max a 0.060 0.100 1.52 2.54 6, 7 a1 0.050 0.088 1.27 2.23 - b----- b1 0.022 0.028 0.56 0.71 2, 4 b2 0.072 ref 1.83 ref - b3 0.006 0.022 0.15 0.56 - d 0.342 0.358 8.69 9.09 - d1 0.200 bsc 5.08 bsc - d2 0.100 bsc 2.54 bsc - d3 - 0.358 - 9.09 2 e 0.342 0.358 8.69 9.09 - e1 0.200 bsc 5.08 bsc - e2 0.100 bsc 2.54 bsc - e3 - 0.358 - 9.09 2 e 0.050 bsc 1.27 bsc - e1 0.015 - 0.38 - 2 h 0.040 ref 1.02 ref 5 j 0.020 ref 0.51 ref 5 l 0.045 0.055 1.14 1.40 - l1 0.045 0.055 1.14 1.40 - l2 0.075 0.095 1.91 2.41 - l3 0.003 0.015 0.08 0.38 - nd 5 5 3 ne 5 5 3 n20 203 rev. 0 5/18/94 notes: 1. metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. unless otherwise speci?d, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. symbol ? is the maximum number of terminals. symbols ?d and ?e are the number of terminals along the sides of length ? and ?? respectively. 4. the required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. the corner shape (square, notch, radius, etc.) may vary at the manufacturer s option, from that shown on the drawing. 6. chip carriers shall be constructed of a minimum of two ceramic layers. 7. dimension ? controls the overall package thickness. the maxi- mum ? dimension is package height before being solder dipped. 8. dimensioning and tolerancing per ansi y14.5m-1982. 9. controlling dimension: inch.
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