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? technology sii 1362/a & sii 1364/a sdvo panellink transmitter data sheet document # sii -ds-0112-b1
sii 1362/a & sii 1364/a panellink transmitter data sheet ii sii -ds-0112-b1 silicon image, inc. sii -ds-0112-b1 march 2006 application information to obtain the most updated application notes and other useful information fo r your design, visit the silicon image web site at www.siliconimage.com or contac t your local silicon image sales office. copyright notice this manual is copyrighted by silic on image, inc. do not reproduce, tr ansform to any other format, or send/transmit any part of this documentation without t he expressed written permission of silicon image, inc. trademark acknowledgment silicon image, the silicon image logo, panellink ? , tmds ? and the panellink ? digital logo are registered trademarks of silicon image, inc. vesa ? is a registered trademark of the video electronics standards association. i 2 c is a trademark of philips semiconductor. intel ? is a registered trademark of intel corp. sdvo (serial digital video output) is a data format proprietary to intel corporation for use by intel graphics chipsets. all other trademarks are the property of their respective holders. disclaimer this document provides technical information for the user . silicon image, inc. reserves the right to modify the information in this document as necessary. the customer should make sure that they have the most recent data sheet version. silicon image, inc. holds no responsibilit y for any errors that may appear in this document. customers should take appropriate action to ensure thei r use of the products does not infringe upon any patents. silicon image, inc. respects valid patent rights of thir d parties and does not infringe upon or assist others to infringe upon such rights. all information contained herein is subject to change without notice. revision history revision date comment a 07/04 revision a release a1 08/05 added 1362a and 1364a part number. a2 08/05 adjusted 64 pin a1 & a2 overlap. b b1 10/05 03/06 added sii 1362a & 1364a new power numbers. updated pvcc1 voltage range to 3.30v + 10%. voltage regulation for pvcc1 omitted for sii 1362a & sii 1364a. included new qfn package dim ensions and ordering number. ? 2004-2006 silicon image. inc.
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 iii table of contents general d escripti on ............................................................................................................ ......................... 1 sii 1362/a & sii 1364/a pin di agrams........................................................................................................ 1 functional blocks.............................................................................................................. ........................... 3 panellink tmds digital core .................................................................................................... ................. 3 sdvo receiv er co re............................................................................................................. ..................... 3 i 2 c slave interface and display de tection........................................................................................ .......... 4 electrical sp ecificat ions ...................................................................................................... ........................ 5 absolute maxi mum condi tions .................................................................................................... ............... 5 normal operat ing condi tions .................................................................................................... ................. 5 dc digital i/o s pecificat ions.................................................................................................. ..................... 5 dc specific ations.............................................................................................................. .......................... 6 ac specif icati ons.............................................................................................................. .......................... 6 input timing diagrams.......................................................................................................... ....................... 7 pin descr iptions ............................................................................................................... ............................ 8 sdvo receiver core pins........................................................................................................ .................. 8 configuration/pr ogramming pins................................................................................................. ............... 8 differential signal data pins .................................................................................................. ..................... 9 i 2 c master inte rface pins ........................................................................................................ .................... 9 factory test mode pins ......................................................................................................... ..................... 9 power and gr ound pi ns.......................................................................................................... .................. 10 feature info rmation............................................................................................................ ........................ 11 i 2 c slave in terface .............................................................................................................. ...................... 11 design reco mmendati ons ......................................................................................................... ............... 12 ext_swing se lection ............................................................................................................ ................. 12 ext_res sele ction.............................................................................................................. .................... 12 sdvo i 2 c bus inte rface................................................................................................................ ............ 12 ddc i 2 c bus inte rface ................................................................................................................ .............. 12 eeprom i 2 c bus inte rface ................................................................................................................ ...... 13 pcb ground planes.............................................................................................................. .................... 13 power plane sequenci ng and swit ching ........................................................................................... ....... 13 voltage ripple regulat ion ...................................................................................................... .................. 13 power plane filters............................................................................................................ ....................... 16 filter capacitor and ferrite pl acement ......................................................................................... ........ 16 source termination resistor s on differentia l outputs ........................................................................... .. 17 transmitte r lay out ............................................................................................................. ....................... 18 hot plug ci rcuit ............................................................................................................... .......................... 20 package dimensions and marking speci fication................................................................................... .21 64-pin tqfp orderi ng inform ation ............................................................................................... ............ 21 64-pin qfn orderi ng inform ation ................................................................................................ ............. 22 48-pin ordering information .................................................................................................... .................. 23
sii 1362/a & sii 1364/a panellink transmitter data sheet iv sii -ds-0112-b1 list of tables table 1. sdvo clo ck multiplication ............................................................................................. .................. 4 table 2. absolute maximum c onditions........................................................................................... .............. 5 table 3. normal o perating c onditions ........................................................................................... ................ 5 table 4. dc digital i/o specif ications ......................................................................................... ................... 5 table 5. dc s pecificat ions ..................................................................................................... ........................ 6 table 6. ac s pecificat ions ..................................................................................................... ........................ 6 table 7. power regulat or circuit suggesti ons ................................................................................... ......... 13 table 8. power plane filter recommendations for sii 1362/a & sii 1364/a............................................... 16 table 9. routing guide lines for dv i traces..................................................................................... ............ 19 list of figures figure 1. si i 1362/a pin diagram - 48-pin pa ckage ...................................................................................... 1 figure 2. si i 1364/a pin diagram - 64-pin pa ckage ...................................................................................... 2 figure 3. functional block diagram ............................................................................................. .................. 3 figure 4. i 2 c data valid delay (dri ving read cycl e data).............................................................................. 7 figure 5. reset# minimum timing ................................................................................................ ............... 7 figure 6. i 2 c byte read.................................................................................................................... ............ 11 figure 7. i 2 c byte write ................................................................................................................... ............. 11 figure 8. variation of differential swing versus r ext_swing value................................................................ 12 figure 9. suggested 3.42v voltage supply circuit for sii 1362 and sii 1364 only...................................... 14 figure 10. suggested 5v voltage supply circuit ................................................................................. ........ 14 figure 11. suggested 1.8v voltage supply circui t ............................................................................... ....... 15 figure 12. suggested 2.5v voltage supply circui t ............................................................................... ....... 15 figure 13. decoupling and by pass capacitor plac ement........................................................................... .16 figure 14. differential output source term inations ............................................................................ ........ 17 figure 15. source terminat ion layout i llustra tion .............................................................................. ......... 17 figure 16. example of incorrect differential si gnal rout ing .................................................................... .... 18 figure 17. example of correct differential si gnal rout ing...................................................................... ..... 19 figure 18. source termination to dvi connector illustra tion.................................................................... ... 19 figure 19. recommended hot plug c onnecti on..................................................................................... ..... 20 figure 20. 64-pin tqfp package di mensi ons...................................................................................... ....... 21 figure 21. 64-pin qfn package di mensions and ep ad diagr am ............................................................... 22 figure 22. 48-pin lqfp package di mensi ons ...................................................................................... ....... 23
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 1 general description the sii 1362/a & sii 1364/a tmds transmitter uses panellink ? digital technology to support displays ranging from vga to uxga resolutions in a single link interface. the chip supports the intel-proprietary sdvo serial interface to provide a display interface to dvi monitors. designed explicitly to accommodate the ultra high- speeds needed for sdvo signaling, the sii 1362/a & sii 1364/a transmitter reduces pin count yet provides an upgrade path for future feature expansion. the innovat ive design of the sii 1362/a & sii 1364/a eases board design requirements as well. panellink digital technology simplifies pc design by resolving many of the system level issues associated with high-speed mixed signal design, providing the system designer with a digital interface solution that is quicker to market and lower in cost. features ? scaleable output bandwidth: 25 - 165 megapixels per second ? sii 1362/1364 fully compliant with intel sdvo 1.0 ? sii 1362a/1364a fully compliant with intel sdvo 1.1 ? i 2 c slave interface for access to internal registers ? dual i 2 c pass-through interfaces for host i 2 c access of edid (via ddc) and configuration eeprom (on 64-pin package only) ? monitor detection supported through hot plug or receiver sense ? low power: 1.8v core operation; power down mode ? cable distance support: greater than 10 meters ? dvi 1.0 compliant, with significantly greater margin than competitive solutions ? sii 1362/a: 48-pin lqfp without eeprom interface ? sii 1364: 64-pin tqfp package with eeprom interface ? sii 1364a: 64-pin tqfp or qfn package with eeprom interface. sii 1362/a & sii 1364/a pin diagrams figure 1. si i 1362/a pin diagram - 48-pin package txc- txc+ avcc tx0- tx0+ agnd tx1- tx1+ avcc tx2- tx2+ agnd ext_swing pvcc2 pgnd2 vcc htplg test gnd sdi+ sdi- vcc ext_res svcc sdr+ sdr- sgnd sdg+ sdg- svcc sdb+ sdb- sgnd sdc+ sdc- spvcc ovcc reset# spgnd sdsda sdscl a1 gnd sclddc sdaddc vcc pvcc1 agnd 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 sii 1362/a tx 48-pin lqfp (top view) sdvo interface dvi interface blue clock green red sdvo interrupt i 2 c from sdvo i 2 c to ddc filter pll main tmds pll
sii 1362/a & sii 1364/a panellink transmitter data sheet 2 sii -ds-0112-b1 reset# rsvd0 rsvd1 rsvd2 gnd sdsda sdscl a1 vcc gnd sclddc sdaddc sdarom sclrom vcc pgnd1 pvcc1 agnd txc- txc+ avcc tx0- tx0+ agnd tx1- tx1+ avcc tx2- tx2+ agnd ext_swing pgnd2 rsvd9 rsvd8 rsvd7 rsvd6 vcc htplg test gnd rsvd5 rsvd4 rsvd3 gnd sdi+ sdi- vcc ext_res svcc sdr+ sdr- sgnd sdg+ sdg- svcc sdb+ sdb- sgnd sdc+ sdc- spvcc spgnd ovcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 sii 1364/a tx 64-pin tqfp or qfn (top view) pvcc2 sdvo interface dvi interface i 2 c to config. prom blue clock green red sdvo interrupt i 2 c from sdvo i 2 c to ddc filter pll main tmds pll figure 2. si i 1364/a pin diagram - 64-pin package
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 3 functional blocks registers & configuration logic block sdsda sdscl htplg a1 i 2 c slave sdvo receiver core txc+ tx0+ tx1+ tx2+ ext_res panellink tmds digital core reset# ext_swing a1 sda scl sdc+ sdr+ sdg+ sdb+ sdi+ i 2 c logic sdarom sclrom sclddc sdaddc test figure 3. functional block diagram panellink tmds digital core the panellink tmds core encodes video information onto three tmds differential data lines and the differential clock. decoded video input data comes from the sdvo rece iver core. a resistor tied to the ext_swing pin is used to control the tmds swing amplitude. sdvo receiver core data is input to the sii 1362/a & sii 1364/a by way of the sdvo bus. sdvo dat a is encoded, therefore this core decodes the data per the intel specificati on before passing it to the tmds receiver core. refer to the intel ?serial digital video out (sdvo) port? specificat ion for further details. a resistor (value specified in the pin description section) must be connected between the ext_res pin and gr ound to set the sdvo circuit bias. the device may be powered down with an internal register. it is initialized or reset by using the reset# pin.
sii 1362/a & sii 1364/a panellink transmitter data sheet 4 sii -ds-0112-b1 the sdvo clock rate will always fall between 100mhz and 200mhz. anytime the effective pclk is below 100mhz, the sdvo clock will be a multiple of the pixel ra te as listed in the multiplier column of table 1. table 1. sdvo clock multiplication mode resolution (pixels) refresh (vsync) (hz) dvi clk (mhz) multiplier sdvo clk (mhz) vga 640x480 60 25 x4 100 svga 800x600 60 40 x4 160 xga 1024x768 60 65 x2 130 sxga 1280x1024 60 108 x1 108 sxga (hi ref) 1280x1024 75 135 x1 135 uxga 1600x1200 60 162 x1 162 i 2 c slave interface and display detection the sii 1362/a & sii 1364/a supports only i 2 c mode of operation. there is no st rap option mode. the logic uses a slave i 2 c interface capable of running up to 1mhz for communi cation with the host chipset. this slave interface is 3.3v-tolerant and accepts 2. 5v and 1.8v signaling as well. if the switch ing levels from the host are greater than 3.3v, then a voltage level shifter must be used. the sii 1362/a & sii 1364/a tx provides i 2 c ports to communicate with a configuration eeprom and the ddc bus with an attached monitor. the sdvo i 2 c port operates at 2.5v and does not require level shifters. the eeprom i 2 c port operates at 3.3v level, via internal 3.3v pull ups, for direct connection to a 3.3v eeprom. to operate the eeprom i 2 c port at 5v an external 3.3v to 5v level shifter is required. the ddc i 2 c port is set to operate at 5v without requiring any level shifters. a connected display edid may be detected using the dv i hot plug signal, through the htplg pin. a powered up attached receiver can be detected with t he receiver sense logic internal to the sii 1362/a & sii 1364/a. the state of the detection may be read from the registers and can optionally be si gnaled to the host by an interrupt. for systems with multiple sdvo devices , pin a1 can be used to change the slave i 2 c address of the sii 1362/a & sii 1364/a.
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 5 electrical specifications absolute maximum conditions absolute maximum conditions are defined as the worst-ca se condition the part will tolerate without sustaining damage. permanent device damage may occur if absolute maximum conditions are exceeded. proper operation under these conditions is not guaranteed. functional operat ion should be restricted to the conditions described under normal operating conditions. table 2. absolute maximum conditions symbol parameter min typ max units all 1.8v supply voltages -0.3 2.5 v all 3.3v supply voltages -0.3 4.0 v v i input voltage -0.3 v cc + 0.3 v v o output voltage -0.3 v cc + 0.3 v t j junction temperature (w ith power applied) 125 c t stg storage temperature -65 150 c normal operating conditions table 3. normal operating conditions symbol parameter min typ max units all 1.8v supply voltages 1.8 - 10% 1.8 1.8 + 10% v analog supply avcc 3.0 3.3 3.6 v main pll supply pvcc1 3.3 3.3 3 or 3.45 2 3.6 v filter pll supply pvcc2 3.0 3.3 3 or 3.45 2 3.6 v sdvo pll supply spvcc 3.0 3.3 3 or 3.45 2 3.6 v output driver suppl y ovcc 3.0 3.3 3.6 v v ccn pll supply voltage noise 100 mv p-p t a ambient temperature (wit h power applied) 0 25 70 c ja-64qfp 64-pin thermal resistance (junction to ambient) 50 c/w ja-64qfn 64-pin thermal resistance (junction to ambient) 4 25 c/w ja-48 48-pin thermal resistance (junction to ambient) 60 c/w notes: 1. airflow at 0m/s. 2. sii 1362 and sii 1364 only requirement 3.45v should be used w hen sharing the power supply with pvcc1. 3. sii 1362a and sii 1364a can operate within 3.30v + 10% for all 3.30v power supply pins. 4. sii 1364a qfn package only with epad soldered to landing area on four-layer board. dc digital i/o specifications under normal operating conditions unless otherwise specified. table 4. dc digital i/o specifications symbol parameter conditions min typ max units v ih high-level input voltage ? digital input pins 2.0 vcc + 0.3 v v il low-level input voltage ? digita l input pins -0.3 0.8 v v ih5v high-level input voltage ? 5v-t olerant pins 2.0 5.5 v v il5v low-level input voltage ? 5v-t olerant pins -0.3 0.8 v v cinl input clamp voltage 1 i cl = -18ma gnd -0.8 v v cipl input clamp voltage 1 i cl = 18ma vcc + 0.8 v i il input leakage current -10 10 a notes: 1. guaranteed by design. voltage undershoot or over shoot cannot exceed absol ute maximum conditions.
sii 1362/a & sii 1364/a panellink transmitter data sheet 6 sii -ds-0112-b1 dc specifications under normal operating conditions with r ext_swing = 360 ? and source termination present unless otherwise specified. table 5. dc specifications symbol parameter conditions min typ max units i dos differential output short circuit current 1 v out = 0v 5 a i pdq quiet power-down current 2 25 c ambient, v cc = 3.3v 3 ma i pd18 5 ma i pd33 power-down current 3 standby mode 3 5/0.5 6 ma i cct18 1.8v transmitter supply current typical 4 240 ma worst case 5 320 ma i cct33 3.3v transmitter supply current typical 4 50/80 6 ma worst case 5 80/110 6 ma all sdvo-related dc specifications ar e met. sdvo specifications are inte l-proprietary and are not published here. notes: 1. guaranteed by characterization. 2. quiet power-down current measured with no transmitter input pins toggling, but includes source termination current. 3. power-down current measured with device in d3 state and no sdvo input present. 4. typical uses a pattern containing a gray scale area, a checkerboar d area and a text area. 5. worst case uses a pattern containing a black and white checkerboard; each c hecker is one pixel wide. 6. sii 1362a and sii 1364a power consumption only. ac specifications under normal operating conditions unless otherwise specified. table 6. ac specifications symbol parameter conditions min typ max units figure notes f cip internal idck frequency one pixel per clock 25 165 mhz 2 c l = 400pf 1000 t i2cdvd sda data valid delay from scl high to low transition c l = 10pf 300 ns figure 4 1 t reset isel/rst# signal low time required for valid reset 50 s figure 5 all sdvo-related ac specifications are met by design but are intel- proprietary and are not published here. notes: 1. all standard mode (100khz and 400khz) & sdvo 1mhz i 2 c timing requirements are guaranteed by design. 2. minimum frequency (maximum idck period) defined per dvi 1.0 specificati on, section 2.3.1. 3. typical vcc is defined at 3.3v.
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 7 input timing diagrams all sdvo timings are met according to intel specifications and are not illustrated here. scl t i2cdvd sda figure 4. i 2 c data valid delay (driving read cycle data) v ih reset# vcc t reset figure 5. reset# minimum timing note that vcc must be stable between its lim its for normal operating conditions for t reset before reset# is high.
sii 1362/a & sii 1364/a panellink transmitter data sheet 8 sii -ds-0112-b1 pin descriptions sdvo receiver core pins pin name 64-pin # 48-pin # type description sdr+ sdr? sdg+ sdg? sdb+ sdb? 51 52 54 55 57 58 37 38 40 41 43 44 analog sdvo input data. this bus receives encoded serial data from the host graphics chipset. the signals are ac-coupled through capacit ors that are typically present on the motherboard and therefore not needed on an add2 card. sdc+ sdc? 60 61 46 47 analog sdvo input clock. the sdvo clock signal comes in on this signal pair. the signals are ac- coupled through capacitors that are ty pically present on the motherboard and therefore not needed on an add2 card. sdi+ sdi? 46 47 32 33 analog interrupt. enabled interrupts are transmitted to t he host chipset on this signal pair. the signals are ac-coupled through capac itors that are typically not present on the motherboard, so s eparate 100nf coupling capacitors are required on these pins on an add2 card. ext_res 49 35 analog external resistor. a resistor value 1.0k ? is connected from this pin to sgnd to generate a reference bias current for the sdvo analog circuits. configuration/programming pins pin name 64-pin # 48-pin # type description reset# 1 2 digital in reset. when low, the chip logic is reset and all register values are set to their initial default state. sdscl 7 5 in/out 5v- tolerant sdvo register access i 2 c clock. this 5v-tolerant pin operates with an external pull-up resistor to 1.8- 3.3v. it is typically pulled up to 2.5v with a 5.6k ? resistor for proper operation with the sdvo host. sdsda 6 4 in/out 5v- tolerant sdvo register access i 2 c data. this 5v-tolerant pin uses an open co llector output driver and requires a pull-up resistor to 1.8-3.3v for proper operation. it is typically pulled up to 2.5v with a 5.6k ? resistor for proper operation with the sdvo host. a1 8 6 digital in slave i 2 c address bit a1. this pin selects bit 1 of the i 2 c slave address. it has an internal weak pull-down resistor, so if the pi n is left unconnected the address will default to 0x70. low: address = 0x70 high: address = 0x72 htplg 39 29 digital in 5v- tolerant hot plug input. this pin is used to monitor the ?hot plug? detect signal (refer to the dvi specification). this input is 5v -tolerant and includes an internal pull down.
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 9 differential signal data pins pin name 64-pin # 48-pin # type description tx0+ tx0? tx1+ tx1? tx2+ tx2? 23 22 26 25 29 28 17 16 20 19 23 22 analog tmds low voltage differentia l signal output data pairs. txc+ txc? 20 19 14 13 analog tmds low voltage differential signal output clock pair. ext_swing 31 25 analog voltage swing adjust. a re sistor should tie this pin to avcc. this resistor sets the amplit ude of the voltage swing. a smaller resistor value sets a larger voltage swing and vice versa. recommended value is 360 ? , 5% tolerance used with source termination as described in the design recommendations section. this recommendation may change with future silicon revisions. i 2 c master interface pins pin name 64-pin # 48-pin # type description sdaddc 12 9 in/out 5v- tolerant ddc access i 2 c data. this pin should be connected to the ddc i 2 c data pin on the dvi connector. it uses an open collector output driver and requires a 2.2k ? pull-up resistor to 5v for proper operation. sclddc 11 8 in/out 5v- tolerant ddc access i 2 c clock. this pin should be connected to the ddc i 2 c clock pin on the dvi connector. it uses an open collector output driver and requires a 2.2k ? pull-up resistor to 5v for proper operation. sdarom 13 na in/out rom access ii 2 c data. only available on the 64-pin sii 1364/a, this pin should be connected to the eeprom i 2 c data pin. it uses an open collector output driver. this pin incorporates an internal pull-up re sistor to 3.3v and does not require an external 3.3v pull up. sclrom 14 na out rom access i 2 c clock. only available on the 64-pin sii 1364/a, this pin should be connected to the eeprom i 2 c clock pin. it uses an open collector output driver. this pin incorporates an internal pull-up re sistor to 3.3v and does not require an external 3.3v pull up. factory test mode pins pin name 64-pin # 48-pin # type description test 40 30 digital in factory test mode strap. tie this pin low for normal operation. rsvd0-9 2, 3, 4, 44, 43, 42, 37,36, 35, 34 na digital in/out reserved factory test mode signals. tie to gnd or leave as no connects.
sii 1362/a & sii 1364/a panellink transmitter data sheet 10 sii -ds-0112-b1 power and ground pins pin name 64-pin # 48-pin # type description vcc 9, 15, 38, 48 10, 28, 34 power digital core vcc, must be set to 1.8v nominal. avcc 21, 27 15, 21 power analog vcc for tmds tx core, must be set to 3.3v nominal. pvcc1 17 11 power tmds main pll analog vcc, must be set to 3.3-3.45v nominal for sii1362 and sii1364 only. sii1362a and sii1364a can be set to 3.3v nominal. pvcc2 32 26 power filter pll analog vcc, must be set to 3.3-3.45v nominal for sii1362 and sii1364 only. sii1362a and 1364a can be set to 3.3v nominal. svcc 50, 56 36, 42 power sdvo analog v cc, must be set to 1.8v nominal. spvcc 62 48 power sdvo pll analog vcc, mu st be set to 3.3-3.45v nominal for sii1362 and sii1364 only. sii1362a and 1364a can be set to 3.3v nominal. ovcc 64 1 power digital i/o vcc, must be set to 3.3v nominal. gnd 5, 10, 41, 45 7, 31 (39, 45) ground digital ground (shared with sdvo ground on 48-pin package) agnd 18, 24, 30 12, 18, 24 ground analog ground. pgnd1 16 (12) ground tmds main pll gr ound (shared with agnd on 48-pin package) pgnd2 33 27 ground tmds filter pll ground. sgnd 53, 59 39, 45 ground sdvo analog ground spgnd 63 3 ground sdvo pll ground. notes 1. connect all ground pins to main pcb ground plane. do not split planes. 2. apply separate filters to each pll vcc/gnd pair as noted in the design recommendations section.
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 11 feature information i 2 c slave interface the sii 1362/a & sii 1364/a slave state machine does not require an internal clock. it supports byte-read and byte-write operations, and also burst read/write to both the internal registers and to the eeprom and ddc. the 7-bit binary address of the i 2 c machine is ?0111 00a 1 r? where r =1 sets a read operation while r=0 sets a write operation. pin a1 by default has an internal pull dow n resistor. therefore, the port address is 0x70/0x71 by default. to set the i 2 c address for the sii 1362/a & sii 1364/a to 0x72/0x73, pin a1 must be pulled up through a resistor to vcc. the interface also accepts accesses at ports 0x a0/0xa1 that are destined for the eeprom or ddc. see figure 6 for a byte read operation and figure 7 for a byte write operation. s a 1 a c k s a 1 a c k a c k p slave address internal register address slave address data stop start start bus activity : sdvo i 2 c bus activity : master sda line w r r d a c k n o figure 6. i 2 c byte read s a 1 a c k a c k p slave address internal register address data stop start bus activity : sdvo i 2 c bus activity : master sda line a c k w r figure 7. i 2 c byte write multiple data bytes may be transferred in each transaction, r egardless of whether a read or a write is taking place. the operations will be similar to those in the figures ex cept that there will be more than one data phase. an ack will follow each byte, except the last byte in a read operat ion. byte addresses increment, with the least significant byte transferred first, and the mo st significant byte last. for more detailed information on i 2 c protocols refer to the i 2 c bus specification version 2.1 available from philips semiconductors inc.
sii 1362/a & sii 1364/a panellink transmitter data sheet 12 sii -ds-0112-b1 design recommendations ext_swing selection the recommended r ext_swing resistor value for the ext_swing pin is provided in the pin descriptions section. this value can be adjusted as needed to optimize the dvi signal swing levels according to the needs of the application. this adjustment might become necessa ry, for example, when deviating from the recommended source termination values (described in the source te rmination resistors on differ ential outputs section) to optimize for a specific board layout. figur e 8 illustrates the relationship of the r ext_swing resistor to the differential swing voltage, across representativ e extremes of the chip. differential swing (t_3.3v_rt) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 0 100 200 300 400 500 600 700 800 900 1000 1100 rext (ohm) differential vswing (mv) t1-3. 3v _rt t2-3. 3v _rt t3-3. 3v _rt t4-3. 3v _rt t5-3. 3v _rt t6-3. 3v _rt t7-3. 3v _rt t8-3. 3v _rt t9-3. 3v _rt t10-3.3v_rt t11-3.3v_rt t12-3.3v_rt figure 8. variation of differential swing versus r ext_swing value ext_res selection the resistor value specified in the pin descriptions section must connect the ext_res pin to sgnd. the resistor is used to generate a reference bias current for sdvo analog circuits. sdvo i 2 c bus interface to program the sii 1362/a & sii 1364/a via its slave i 2 c bus connection with the sdvo host, sdsda and sdscl swing level should be 2.5v. this is the standard sdvo signa ling level for this interface. these pins should be pulled to 2.5v with 5.6k ? resistors. ddc i 2 c bus interface the vesa ddc specification (available at http://www.vesa.org ) defines the ddc interconnect bus to be a 100kbit/s 5v signaling path. the ddc i 2 c pins on the sii 1362/a & sii 1364/a tx chip are 5v-tolerant. therefore, board designers can connect the pins without using a level-sh ifting circuit. these pins should be pulled to 5v with 2.2k ? resistors. if the host system is using a dvi-i connector to suppor t both a dvi and a vga (analog) connection, only the host vga i 2 c interface should be connected to the dvi- i connector. the ddc interface of the sii 1362/a & sii 1364/a tx chip should be tied only to 2.2k ? resistors to 5v but should not connect to the dvi-i connector.
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 13 eeprom i 2 c bus interface the 64-pin version of the sii 1362/a & sii 1364/a tx provides a communications path from the sdvo host to a configuration eeprom. the interface can support up to 400kb/s with commonly available eeproms. the interface pins are internally pulled up to 3.3v, and t herefore do not require external pull-up resistors. pcb ground planes all ground pins on the device should be connected to the same, contiguous ground plane in the pcb. this helps to avoid ground loops and inductances from one ground plane segment to another. such low-inductance ground paths are critical for return currents, which affe ct emi performance. the entire ground plane surrounding the panellink transmitter should be in one piece and include the ground vias for the dvi connector. power plane sequencing and switching as with any device using multiple power rails, the sii 1362/a & sii 1364/a tx employs esd protection diodes that can allow a current flow between the 3.3v and 1.8v planes. no special sequencing or voltage ramping precautions are necessary as long as both planes reach their nominal operating voltage within a few seconds of each other. however, if the 1.8v plane voltage remain s greater than any 3.3v pl ane voltage by more than one diode drop (0.7v), there will be a continuous current fl ow through the protection diodes that could damage the device over time. for this reason, it is recommended t hat the 1.8v power plane voltage not be allowed to exceed any 3.3v power plane voltage by more than 0. 7v under any steady-state operating condition. voltage ripple regulation the power supply to pvcc pins is very important to t he proper operation of the transmitter. table 7 provides simple regulator circuits that are appropriate for each chip power plane. please note that sii 1362a & sii 1364a do not require 3.45v regulation and as such desi gners can omit the voltage regulation component and use the 3.30v power supply available from the motherboard. tx sample regulator circuits are shown in the figures noted. note that alter native voltage regulator circuits should be considered only if they meet the lm317 standards of line/load regulation. table 7. power regulator circuit suggestions voltage to be regulated max current power plane, % of total load voltage regulation description active voltage regulator components figure 3.45v (for sii 1362 / sii 1364 only) 60ma pvcc1: 60-75% pvcc2: 5-15% spvcc: 15-35% 12v to 3.42 v lm317emp figure 9 3.3v 20ma avcc: 5-15% ovcc: 80-95% use available 3.3v none -- 5v 55ma external 12v to 5v lm317lm figure 10 1.8v 320ma svcc: 70-85% vcc: 25-35% 3.3v to 1.8v, low drop out regulation lm1117_1.8v figure 11 2.5v 10ma external 3.3v to 2.5v simple voltage divider r1= 316 ? 1%, r2 = 1.0k ? 1% figure 12
sii 1362/a & sii 1364/a panellink transmitter data sheet 14 sii -ds-0112-b1 240 ? 1% 412 ? 1% vin 12v vout 3.42v adj vin vout lm317emp figure 9. suggested 3.42v voltage s upply circuit for sii 1362 and sii 1364 only 240 ? 1% 732 ? 1% vin 12v vout 5v adj vin vout lm317l figure 10. suggested 5v voltage supply circuit
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 15 vin 3.3v vout 1.8v gnd vin vout lm1117-1.8 figure 11. suggested 1.8v voltage supply circuit 316 ? 1% 1k ? 1% vin 3.3v vout 2.5v figure 12. suggested 2.5v voltage supply circuit
sii 1362/a & sii 1364/a panellink transmitter data sheet 16 sii -ds-0112-b1 power plane filters recommended power plane filtering is shown in table 8. the value of the capacitors is chosen to approximately cover the range of 162.5mhz to 2.5ghz for high frequenc y noise. any higher frequency noise will be filtered by the inherent capacitance of the trace line follow ed by internal high frequency capacitors in the sii 1362/a & sii 1364/a tx. each group of pins should have one ferri te whose impedance value must be greater than 100 ? but smaller than 300 ? . table 8. power plane filter recommendations for sii 1362/a & sii 1364/a power supply component applications high frequency c1 mid band c2 storage c3 ferrite bead and voltage regulator avcc 1nf - one per pin 0.1uf - one per pin 10uf - one shared for two avcc pins one ferrite bead ovcc none required 0.1uf - one per pin 10uf - one on ovcc none required pvcc1 1nf - two per pin 0.1uf - two per pin none required pvcc2 1nf - two per pin 0.1uf - two per pin none required spvcc 1nf - two per pin 0.1uf - two per pin none required regulator required, shared by pvcc1, pvcc2 and spvcc. each power plane requires its own ferrite bead svcc 1nf - one per pin 0.1uf - one per pin 10uf - one shared for three svcc pins one ferrite bead vcc 1nf - one per pin 0.1uf - one per pin 10uf - one shared for all vcc pins one ferrite bead filter capacitor and ferrite placement designers should include decoupling and bypass capacitors at each power pin in the layout. place these components as close as possible to t he panellink device pins, and avoid rout ing through vias if possible, as shown in figure 13, which is representative of t he various types of power pins on the transmitter. ensure that the correct power and ground pin are coupled with the filter capacitors as illustrated in figure 13. for example, pvcc1 should have pgnd1 as its ground pin and pvcc2 should have pgnd2 as its ground pin. note that for the 48-pin package, pin 12 shoul d be used for the pgnd1 capacitor connection. l1 c1 vcc ferrite via to gnd vcc gnd c2 c3 figure 13. decoupling and bypass capacitor placement
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 17 source termination resistors on differential outputs source termination, consisting of a 300 ? resistor and a 0.1 f capacitor, should be used on the differential outputs of the sii 1362/a & sii 1364/a to improve signal swings. see figure 14 for an illustration. repeat the circuit for each of the four differential output pairs: tx0 , tx1 , tx2 , txc . note that the specific value for the source termi nation resistor and capacitor will depend on the pcb layout and construction. different values may be needed to cr eate the best dvi-compliant output waveforms. figure 14. differential output source terminations source termination suppresses signal reflection to prevent non-dvi compliant re ceivers from erroneously sampling the tmds signals when operating at high frequenc ies (beyond ~135mhz). the impact on dvi compliant receivers is minimal. therefore silicon image recommends s ource termination for applications at all frequencies. r c detail of source termination (magnified) r and c 0603 size components installed. figure 15. source termination layout illustration 300 ? 0.1uf tx0+ tx0- 300 ? 0.1uf tx1+ tx2- 300 ? 0.1uf tx3+ tx3- 300 ? 0.1uf txc+ txc-
sii 1362/a & sii 1364/a panellink transmitter data sheet 18 sii -ds-0112-b1 note that the capacitor is required to meet dvi idle mode dc offset requirements and must not be omitted. note also that the signal suppression requires the r ext_swing value to be changed. power consumption will be slightly higher when using source termination. the layout shown has been developed to minimize trace st ubs on the differential tmds lines, while providing pads for the source termination components (left-hand m agnified view). source termination components should be placed close to the transmitter pins. the resistor and capacitor are shown installed on the pads provided (right-hand magnified view). transmitter layout the routing for the sii 1362/a & sii 1364/a chip is relatively simple since no spiral skew compensation is needed. however, a few small precautions are required to achieve the full performance and reliability of dvi. the transmitter can be placed fairly far from the output connector, but care should be taken to route each differential signal pair together and achieve impedance of 100 ? between the differential signal pair. however, note that the longer the differential traces are betw een the transmitter and the output connector, the higher the chance that external signal noise will couple ont o the low-voltage signals and affect image quality. do not split or have asymmetric trac e routing between the differential signal pair. vias are very inductive and can cause phase delay if applied unevenly within a differential pai r. vias should be minimized or avoided if possible by placing all differential traces on the top layer of the pcb. figure 16 illustrates an incorrect routing of the differential signal from the sii 1362/a & sii 1364/a to the dvi connector. ` sii 1362 figure 16. example of incorrect differential signal routing figure 17 illustrates the correct method to route the differential signal from the sii 1362/a & sii 1364/a to the dvi connector. figure 18 illustrates recommended routing fo r differential traces at the dvi connector.
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 19 sii 1362 figure 17. example of correct differential signal routing in addition to following the trace routing recommendations , length differences between intra-pair traces and inter- pair traces should be controlled to minimize dvi skew. spacing between inter-pair dvi traces should be observed to reduce trace-to-trace couplings. for example, havi ng wider gaps between inter-pair dvi traces will minimize noise coupling. it is also strongly advised that ground not be placed adjacent to the dvi traces on the same layer. table 9 lists the recommended limits for the parameters listed above. table 9. routing guidelines for dvi traces parameter intra-pair (differential pair) length inter-pair (differential pair to differential pair) length recommended inter?pair trace separation based on 2 layer board recommended inter? pair trace separation based on 4 layer board max + 0.75? + 3? min 2x trace width 2x trace width the layout in figure 18 illustrates an optimized add2 ca rd with source termination and dvi connector mapping that follows the guidelines listed above. the trace length from the sii 1362/a & sii 1364/a to the dvi connector can be long; however, it is strongly recommended that the intra-pair and inter-pair trace lengths follow the guidelines provided above. figure 18. source termination to dvi connector illustration
sii 1362/a & sii 1364/a panellink transmitter data sheet 20 sii -ds-0112-b1 hot plug circuit the hot plug pin on the dvi connector carries a 5v return si gnal from the monitor to indicate that its edid is available for reading. the sii 1362/a & sii 1364/a chip can indicate a display-attached status) or generate an interrupt by monitoring this pin. the htplg input of the chip is 5v-tolerant. however, a protection circuit such as that shown in figure 19 is recommended to bring the dv i connector hot plug detect signal to the htplg pin on the sii 1362/a & sii 1364/a. 5v hot plug detect pin from dvi connector optional esd protection diodes (1n4148 typ.) 1-5k ? si i 1362/4 htplg input pin figure 19. recommended hot plug connection receiver sense indicates that a powered monitor is attached, but will not indicate the presence of a monitor that is powered off. therefore, in this default configuration t he host system must read edid at power-up regardless of the attach state reported by the sii 1362/a & sii 1364/a device, and must re-read edid any time the attach state changes. the chip defaults to using the receiver sense function, not the htplg input, for display-attached status after a reset. however, intel sdvo driver s automatically initializes the sii 1362/a & sii 1364/a tx to support the hot plug function.
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 21 package dimensions and marking specification 64-pin tqfp ordering information part numbers of universal package fo r both standard and pb-free applications: sii 1364 tx (sdvo 1.0 compliant): sii1364 ctu sii 1364a tx (sdvo 1.1 compliant): sii1364a ctu siinnnnlctu llllll.llll yyww ttttttm device # lot # date code revision code e1 f1 d1 g1 a2 a1 e b l1 c tmds ? panellink ? jedec package code ms026-acd typ max a thickness 1.20 a1 stand-off 0.15 a2 body thickness 1.00 1.05 d1 body size 10.00 e1 body size 10.00 f1 footprint 12.00 g1 footprint 12.00 l1 lead length 1.00 b lead width 0.20 0.27 c lead thickness 0.20 e lead pitch 0.50 dimensions in millimeters. overall thickness a=a1+a2. legend description siinnnnlctu device number sii 1364ctu or sii 1364actu llllll.llll lot number yy year of mfr ww week of mfr tttttt trace c ode m maturity code figure 20. 64-pin tqfp package dimensions
sii 1362/a & sii 1364/a panellink transmitter data sheet 22 sii -ds-0112-b1 64-pin qfn ordering information part number of universal package fo r both standard and pb-free applications: sii 1364a tx(sdvo 1.1 compliant): sii1364a cnu siixxxxcnu llllll.llll yyww ttttttm device # lot # date code revision code e d a2 a1 e b tmds ? panellink ? d2 e2 jedec package code mo-220 typ max a thickness 0.90 a1 stand-off 0.05 a2 body thickness .65 0.70 d body size 9.00 e body size 9.00 l1 terminal length 0.40 b terminal width 0.25 0.30 e terminal pitch 0.50 dimensions in millimeters. overall thickness a=a1+a2. universal package : sii xxxxcnu legend description llllll.llll lot number yy year of mfr ww week of mfr tttttt trace c ode m maturity code epad dimensions typ max d2 epad height 6.30 e2 epad width 6.30 ? t tolerance 0.05 dimensions in millimeters. epad is centered on the package center lines. figure 21. 64-pin qfn package dimensions and epad diagram
sii 1362/a & sii 1364/a panellink transmitter data sheet sii -ds-0112-b1 23 48-pin ordering information part numbers of universal package fo r both standard and pb-free applications: sii 1362 tx (sdvo 1.0 compliant): sii1362 clu sii 1362a tx (sdvo 1.1 compliant): sii1362a clu siinnnnlclu llllll.llll yyww ttttttm device # lot # date code revision code e1 f1 d1 g1 a2 a1 e b l1 c tmds ? panellink ? jedec package code ms026-bbc typ max a thickness 1.60 a1 stand-off 0.15 a2 body thickness 1.40 1.45 d1 body size 7.00 e1 body size 7.00 f1 footprint 9.00 g1 footprint 9.00 l1 lead length 1.00 b lead width 0.20 0.27 c lead thickness 0.20 e lead pitch 0.50 dimensions in millimeters. overall thickness a=a1+a2. legend description siinnnnlclu device number sii 1362clu or sii 1362aclu llllll.llll lot number yy year of mfr ww week of mfr tttttt trace c ode m maturity code figure 22. 48-pin lqfp package dimensions
sii 1362/a & sii 1364/a panellink transmitter data sheet 24 sii -ds-0112-b1 ? 2004-2006 silicon image. inc. silicon image, inc. tel: (408) 616-4000 1060 e. arques avenue sunnyvale, ca 94085 usa fax: (408) 830-9530 e-mail: salessupport@siimage.com web: www.siliconimage.com

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