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| ? 2007 national semiconductor corporation www.national.com 1 dp83848i phyter ? ? industrial temperature single port 10/100 mb/s ethernet physi cal layer transceiver february 2007 dp83848i phyter ? - industrial temperature single port 10/100 mb/s ethernet physical layer transceiver general description the dp83848i is a robust fully featured 10/100 single port physical layer device offering low power con- sumption, including several intelligent power down states. these low power modes increase overall prod- uct reliability due to decreased power dissipation. sup- porting multiple intelligent power modes allows the application to use the absolute minimum amount of power needed for operation. in addition to low power, the dp83848i is optimized for cable length perfor- mance far exceeding ieee specifications. the dp83848i includes a 25mhz clock out. this means that the application can be designed with a minimum of external parts, which in turn results in the lowest possible total cost of the solution. the dp83848i easily interfaces to twisted pair media via an external transformer and fully supports jtag ieee specification 1149.1 for ease of manufacturing. additionally both mii and rmii are supported ensuring ease and flexibility of design. the dp83848i features integrated sublayers to sup- port both 10base-t and 100base-tx ethernet proto- cols, which ensures compatibility and interoperability with all other standards based ethernet solutions. the dp83848i is offered in a small form factor (48 pin lqfp) so that a minimum of board space is needed. applications ? high end peripheral devices industrial controls and factory automation general embedded applications system diagram phyter ? is a registered trademark of national semiconductor. status 10base-t or 100base-tx mii/rmii/sni 25 mhz magnetics rj-45 clock leds dp83848i 10/100 mb/s media access controller mpu/cpu source typical application features low-power 3.3v, 0.18 m cmos technology low power consumption < 270mw typical 3.3v mac interface auto-mdix for 10/100 mb/s energy detection mode 25 mhz clock out sni interface (configurable) rmii rev. 1.2 interface (configurable) mii serial management interface (mdc and mdio) ieee 802.3u mii ieee 802.3u auto-negotiation and parallel detection ieee 802.3u endec, 10base-t transceivers and filters ieee 802.3u pcs, 100base-tx transceivers and filters ieee 1149.1 jtag integrated ansi x3.263 compliant tp-pmd physical sub- layer with adaptive equalization and baseline wander com- pensation error-free operation up to 150 meters programmable led support link, 10 /100 mb/s mode, activ- ity, and collision detect single register access for complete phy status 10/100 mb/s packet bist (built in self test) 48-pin lqfp package (7mm) x (7mm)
2 www.national.com dp83848i serial management tx_clk txd[3:0] tx_en mdio mdc col crs/crs_dv rx_er rx_dv rxd[3:0] rx_clk auto-negotiation state machine clock rx_data rx_clk tx_data tx_clk reference clock td rd leds generation mii/rmii/sni interfaces figure 1. dp83848i functional block diagram mii registers transmit block 10base-t & 100base-tx 10base-t & 100base-tx receive block auto-mdix boundary scan dac adc jtag led drivers mii/rmii/sni 3 www.national.com dp83848i table of contents 1.0 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 serial management interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.2 mac data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.3 clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.4 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.5 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.6 reset and power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2 1.7 strap options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.8 10 mb/s and 100 mb/s pmd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.9 special connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.10 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.11 package pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.1.1 auto-negotiation pin control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.2 auto-negotiation register control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.3 auto-negotiation parallel detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.4 auto-negotiation restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.5 enabling auto-negotiation via software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.6 auto-negotiation complete time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 auto-mdix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.3 phy address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.3.1 mii isolate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.4.1 leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.2 led direct control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5 half duplex vs. full duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.6 internal loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.7 bist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 mii interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.1.1 nibble-wide mii data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.2 collision detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.3 carrier sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 reduced mii interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.3 10 mb serial network interface (sni) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.4 802.3u mii serial management interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.4.1 serial management register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.2 serial management access protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.3 serial management preamble suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.0 architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 100base-tx transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.1.1 code-group encoding and injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.2 scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.3 nrz to nrzi encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.4 binary to mlt-3 convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 100base-tx receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.2.1 analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.2 digital signal processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.2.1 digital adaptive equalization and gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.2.2 base line wander compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.3 signal detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.4 mlt-3 to nrzi decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.5 nrzi to nrz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.6 serial to parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.7 descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 www.national.com dp83848i 4.2.8 code-group alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2.9 4b/5b decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2.10 100base-tx link integrity monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2.11 bad ssd detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3 10base-t transceiver module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.3.1 operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.2 smart squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.3 collision detection and sqe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.4 carrier sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.5 normal link pulse detection/generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 4.3.6 jabber function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3.7 automatic link polarity detection and correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3.8 transmit and receive filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3.9 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3.10 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.0 design guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 tpi network circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 5.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 5.3 clock in (x1) requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 5.4 power feedback circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5 power down/interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 5.5.1 power down control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5.2 interrupt mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.6 energy detect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6.0 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 6.2 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 7.0 register block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 7.1.1 basic mode control register (bmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 7.1.2 basic mode status register (bmsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.1.3 phy identifier register #1 (phyidr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.1.4 phy identifier register #2 (phyidr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.1.5 auto-negotiation advertisement register (anar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.1.6 auto-negotiation link partner ability register (anlpar) (base page) . . . . . . . . . . . . . . . . 46 7.1.7 auto-negotiation link partner ability register (anlpar) (next page) . . . . . . . . . . . . . . . . . 47 7.1.8 auto-negotiate expansion register (aner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1.9 auto-negotiation next page transmit register (a nnptr) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2 extended registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 7.2.1 phy status register (physts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.2.2 mii interrupt control register (micr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2.3 mii interrupt status and misc. control register (misr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.2.4 false carrier sense counter register (fcscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.2.5 receiver error counter register (recr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.2.6 100 mb/s pcs configuration and status register (pcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.2.7 rmii and bypass register (rbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.2.8 led direct control register (ledcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.2.9 phy control register (phycr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.2.10 10base-t status/control register (10btscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.2.11 cd test and bist extensions register (cdctrl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.2.12 energy detect control (edcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.0 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.1 dc specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 8.2 ac specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8.2.1 power up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.2.2 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.2.3 mii serial management timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.2.4 100 mb/s mii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.2.5 100 mb/s mii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.2.6 100base-tx transmit packet latency timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5 www.national.com dp83848i 8.2.7 100base-tx transmit packet deassertion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.2.8 100base-tx transmit timing (tr/f & jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.2.9 100base-tx receive packet latency timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.2.10 100base-tx receive packet deassertion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.2.11 10 mb/s mii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.2.12 10 mb/s mii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.2.13 10 mb/s serial mode transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 8.2.14 10 mb/s serial mode receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 8.2.15 10base-t transmit timing (start of packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.2.16 10base-t transmit timing (end of packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.2.17 10base-t receive timing (start of packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.2.18 10base-t receive timing (end of packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.2.19 10 mb/s heartbeat timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.2.20 10 mb/s jabber timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.2.21 10base-t normal link pulse timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.2.22 auto-negotiation fast link pulse (flp) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.2.23 100base-tx signal detect timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 8.2.24 100 mb/s internal loopback timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.2.25 10 mb/s internal loopback timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.2.26 rmii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.2.27 rmii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.2.28 isolation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.2.29 25 mhz_out timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.0 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6 www.national.com dp83848i list of figures figure 1. dp83848i functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 2. phyad strapping example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3. an strapping and led loading example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4. typical mdc/mdio read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5. typical mdc/mdio write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6. 100base-tx transmit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. 100base-tx receive block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8. eia/tia attenuation vs. frequency for 0, 50, 100, 130 & 150 meters of cat 5 cable . . . . . . . . . . . 28 figure 9. 100base-tx blw event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10. 10base-t twisted pair smart squelch operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 11. 10/100 mb/s twisted pair interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12. crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13. power feeback connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 www.national.com dp83848i list of tables table 1. auto-negotiation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 2. phy address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 3. led mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 4. supported packet sizes at +/-50ppm +/-100ppm for each clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 table 5. typical mdio frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 5. 4b5b code-group encoding/decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 6. 25 mhz oscillator specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 7. 50 mhz oscillator specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 8. 25 mhz crystal specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 9. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 10. register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 11. basic mode control register (bmcr), address 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 12. basic mode status register (bmsr), address 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 13. phy identifier register #1 (phyidr1), address 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 14. phy identifier register #2 (phyidr2), address 0x03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 15. negotiation advertisement register (anar), address 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 16. auto-negotiation link partner ability register (a nlpar) (base page), address 0x05 . . . . . . . .46 table 17. auto-negotiation link partner ability register (a nlpar) (next page), address 0x05 . . . . . . . . .47 table 18. auto-negotiate expansion register (aner), address 0x06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 19. auto-negotiation next page transmit register (annp tr), address 0x07 . . . . . . . . . . . . . . . . . . .48 table 20. phy status register (physts), address 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 21. mii interrupt control register (micr), address 0x11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 22. mii interrupt status and misc. control register (misr), address 0x12 . . . . . . . . . . . . . . . . . . . . . .52 table 23. false carrier sense counter register (fcscr), address 0x14 . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 24. receiver error counter register (recr), address 0x15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 25. 100 mb/s pcs configuration and status register (p csr), address 0x16 . . . . . . . . . . . . . . . . . . . .54 table 26. rmii and bypass register (rbr), addresses 0x17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 27. led direct control register (ledcr), address 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 28. phy control register (phycr), address 0x19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 29. 10base-t status/control register (10btscr), address 0x 1a . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 30. cd test and bist extensions register (cdctrl1), address 0x1b . . . . . . . . . . . . . . . . . . . . . . . . .59 table 31. energy detect control (edcr), address 0x1d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 8 www.national.com dp83848i pin layout top view ns package number vbh48a dgnd iognd x1 x2 iovdd33 mdc mdio reset_n led_link/an0 led_speed/an1 led_act/col/an_en 25mhz_out rbias pfbout avdd33 reserved reserved agnd pfbin1 td + td - agnd rd + rd - tx_clk tx_en txd_0 txd_1 txd_2 txd_3/sni_mode pwr_down/int tck tdo tms trst# tdi dp83848i 1 2 3 4 5 6 7 8 9 10 11 38 39 40 41 42 43 44 45 46 47 48 35 34 33 32 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 o pfbin2 rx_clk rx_dv/mii_mode crs/crs_dv/led_cfg rx_er / mdix_en col/phyad0 rxd_0/phyad1 rxd_1/phyad2 rxd_2/phyad3 rxd_3/phyad4 iognd iovdd33 24 37 36 12 9 www.national.com dp83848i 1.0 pin descriptions the dp83848i pins are classified into the following inter - face categories (each interface is described in the sections that follow): ? serial management interface ? mac data interface ? clock interface ? led interface ?jtag interface ? reset and power down ? strap options ? 10/100 mb/s pmd interface ? special connect pins ? power and ground pins note: strapping pin option. please see section 1.7 for strap definitions. all dp83848i signal pins are i/o cells regardless of the par - ticular use. the definitions below define the functionality of the i/o cells for each pin. 1.1 serial management interface 1.2 mac data interface type: i input type: o output type: i/o input/output type od open drain type: pd,pu internal pulldown/pullup type: s strapping pin (all strap pins have weak in - ternal pull-ups or pull-downs. if the default strap value is needed to be changed then an external 2.2 k ? resistor should be used. please see section 1.7 for details.) signal name type pin # description mdc i 31 management data clock: synchronous clock to the mdio management data input/output serial interface which may be asynchronous to transmit and receive clocks. the maximum clock rate is 25 mhz with no minimum clock rate. mdio i/o 30 management data i/o: bi-directional management instruc - tion/data signal that may be sourced by the station management entity or the phy. this pin requires a 1.5 k ? pullup resistor. signal name type pin # description tx_clk o 1 mii transmit clock: 25 mhz transmit clock output in 100 mb/s mode or 2.5 mhz in 10 mb/s mode derived from the 25 mhz reference clock. unused in rmii mode. the device uses the x1 reference clock in - put as the 50 mhz reference for both transmit and receive. sni transmit clock: 10 mhz transmit clock output in 10 mb sni mode. the mac should source tx_en and txd_0 using this clock. tx_en i, pd 2 mii transmit enable: active high input indicates the pres - ence of valid data inputs on txd[3:0]. rmii transmit enable: active high input indicates the pres - ence of valid data on txd[1:0]. sni transmit enable: active high input indicates the pres - ence of valid data on txd_0. txd_0 txd_1 txd_2 txd_3 i s, i, pd 3 4 5 6 mii transmit data: transmit data mii input pins, txd[3:0], that accept data synchronous to the tx_clk (2.5 mhz in 10 mb/s mode or 25 mhz in 100 mb/s mode). rmii transmit data: transmit data rmii input pins, txd[1:0], that accept data synchronous to the 50 mhz reference clock. sni transmit data: transmit data sni input pin, txd_0, that accept data synchronous to the tx_clk (10 mhz in 10 mb/s sni mode). 10 www.national.com dp83848i rx_clk o 38 mii receive clock: provides the 25 mhz recovered receive clocks for 100 mb/s mode and 2.5 mhz for 10 mb/s mode. unused in rmii mode. the device uses the x1 reference clock in - put as the 50 mhz reference for both transmit and receive. sni receive clock: provides the 10 mhz recovered receive clocks for 10 mb/s sni mode. rx_dv s, o, pd 39 mii receive data valid: asserted high to indicate that valid data is present on the corresponding rxd[3:0]. mii mode by de - fault with internal pulldown. rmii synchronous receive data valid: this signal provides the rmii receive data valid indication independent of carrier sense. this pin is not used in sni mode. rx_er s, o, pu 41 mii receive error: asserted high synchronously to rx_clk to indicate that an invalid symbol has been detected within a re - ceived packet in 100 mb/s mode. rmii receive error: assert high synchronously to x1 when - ever it detects a media error and rxdv is asserted in 100 mb/s mode. this pin is not required to be used by a mac, in either mii or rmii mode, since the phy is required to corrupt data on a receive error. this pin is not used in sni mode. rxd_0 rxd_1 rxd_2 rxd_3 s, o, pd 43 44 45 46 mii receive data: nibble wide receive data signals driven syn - chronously to the rx_clk, 25 mhz for 100 mb/s mode, 2.5 mhz for 10 mb/s mode). rxd[3:0] signals contain valid data when rx_dv is asserted. rmii receive data: 2-bits receive data signals, rxd[1:0], driv - en synchronously to the x1 clock, 50 mhz. sni receive data: receive data signal, rxd_0, driven syn - chronously to the rx_clk. rxd_0 contains valid data when crs is asserted. rxd[3:1] are not used in this mode. crs/crs_dv s, o, pu 40 mii carrier sense: asserted high to indicate the receive me - dium is non-idle. rmii carrier sense/receive data valid: this signal combines the rmii carrier and receive data valid indications. for a detailed description of this signal, see the rmii specifica - tion. sni carrier sense: asserted high to indicate the receive me - dium is non-idle. it is used to frame valid receive data on the rxd_0 signal. col s, o, pu 42 mii collision detect: asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 mb/s and 100 mb/s half duplex modes. while in 10base-t half duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1 s at the end of transmission to indicate heartbeat (sqe test). in full duplex mode, for 10 mb/s or 100 mb/s operation, this sig - nal is always logic 0. there is no heartbeat function during 10 mb/s full duplex operation. rmii collision detect: per the rmii specification, no col signal is required. the mac will recover crs from the crs_dv signal and use that along with its tx_en signal to determine col - lision. sni collision detect: asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 mb/s sni mode. signal name type pin # description 11 www.national.com dp83848i 1.3 clock interface 1.4 led interface see table 3 for led mode selection. signal name type pin # description x1 i 34 crystal/oscillator input: this pin is the primary clock reference input for the dp83848i and must be connected to a 25 mhz 0.005% ( + 50 ppm) clock source. the dp83848i supports ei - ther an external crystal resonator connected across pins x1 and x2, or an external cmos-level oscillator source connected to pin x1 only. rmii reference clock: this pin is the primary clock refer - ence input for the rmii mode and must be connected to a 50 mhz 0.005% ( + 50 ppm) cmos-level oscillator source. x2 o 33 crystal output: this pin is the primary clock reference out - put to connect to an external 25 mhz crystal resonator device. this pin must be left unconnected if an external cmos oscillator clock source is used. 25mhz_out o 25 25 mhz clock output: in mii mode, this pin provides a 25 mhz clock output to the sys - tem. in rmii mode, this pin provides a 50 mhz clock output to the sys - tem. this allows other devices to use the reference clock from the dp83848i without requiring additional clock sources. signal name type pin # description led_link s, o, pu 28 link led: in mode 1, this pin indicates the status of the link. the led will be on when link is good. link/act led: in mode 2 and mode 3, this pin indicates transmit and receive activity in addition to the status of the link. the led will be on when link is good. it will blink when the transmitter or receiver is active. led_speed s, o, pu 27 speed led : the led is on when device is in 100 mb/s and off when in 10 mb/s. functionality of this led is independent of mode selected. led_act/col s, o, pu 26 activity led: in mode 1, this pin is the activity led which is on when activity is present on either transmit or receive. collision/duplex led: in mode 2, this pin by default indi - cates collision detection. for mode 3, this led output may be programmed to indicate full-duplex status instead of collision. 12 www.national.com dp83848i 1.5 jtag interface 1.6 reset and power down 1.7 strap options the dp83848i uses many of the functional pins as strap options. the values of these pins are sampled during reset and used to strap the device into specific modes of opera - tion. the strap option pin assignments are defined below. the functional pin name is indicated in parentheses. a 2.2 k ? resistor should be used for pull-down or pull-up to change the default strap option. if the default option is required, then there is no need for external pull-up or pull down resistors. since these pins may have alternate func - tions after reset is deasserted, they should not be con - nected directly to vcc or gnd. signal name type pin # description tck i, pu 8 test clock this pin has a weak internal pullup. tdi i, pu 12 test data input this pin has a weak internal pullup. tdo o 9 test output tms i, pu 10 test mode select this pin has a weak internal pullup. trst# i, pu 11 test reset: active low asynchronous test reset. this pin has a weak internal pullup. signal name type pin # description reset_n i, pu 29 reset: active low input that initializes or re-initializes the dp83848i. asserting this pin low for at least 1 s will force a reset process to occur. all internal registers will re-initialize to their de - fault states as specified for each bit in the register block section. all strap options are re-initialized as well. pwr_down/int i, od, pu 7 see section 5.5 for detailed description. the default function of this pin is power down. power down: the pin is an active low input in this mode and should be asserted low to put the device in a power down mode. interrupt: the pin is an open drain output in this mode and will be asserted low when an interrupt condition occurs. although the pin has a weak internal pull-up, some applications may require an external pull-up resister. register access is required for the pin to be used as an interrupt mechanism. see section 5.5.2 interrupt mechanism for more details on the interrupt mechanisms. signal name type pin # description phyad0 (col) phyad1 (rxd_0) phyad2 (rxd_1) phyad3 (rxd_2) phyad4 (rxd_3) s, o, pu s, o, pd 42 43 44 45 46 phy address [4:0]: the dp83848i provides five phy address pins, the state of which are latched into the phyctrl register at system hardware-reset. the dp83848i supports phy address strapping values 0 (<00000>) through 31 (<11111>). a phy address of 0 puts the part into the mii isolate mode . the mii isolate mode must be se - lected by strapping phy address 0; changing to address 0 by reg - ister write will not put the phy in the mii isolate mode. please refer to section 2.3 for additional information. phyad0 pin has weak internal pull-up resistor. phyad[4:1] pins have weak internal pull-down resistors. 13 www.national.com 1.7 strap options (continued) dp83848i an_en (led_act/col) an_1 (led_speed) an_0 (led_link) s, o, pu 26 27 28 auto-negotiation enable: when high, this enables auto-negoti - ation with the capability set by ano and an1 pins. when low, this puts the part into forced mode with the capability set by an0 and an1 pins. an0 / an1: these input pins control the forced or advertised op - erating mode of the dp83848i according to the following table. the value on these pins is set by connecting the input pins to gnd (0) or v cc (1) through 2.2 k ? resistors. these pins should never be connected directly to gnd or vcc. the value set at this input is latched into the dp83848i at hard - ware-reset. the float/pull-down status of these pins are latched into the basic mode control register and the auto_negotiation advertisement register during hardware-reset. the default is 111 since these pins have internal pull-ups. mii_mode (rx_dv) sni_mode (txd_3) s, o, pd 39 6 mii mode select: this strapping option pair determines the operating mode of the mac data interface. default operation (no pull-ups) will enable normal mii mode of operation. strapping mii_mode high will cause the device to be in rmii or sni mode of operation, determined by the status of the sni_mode strap. since the pins include internal pull-downs, the default values are 0. the following table details the configurations: led_cfg (crs) s, o, pu 40 led configuration: this strapping option determines the mode of operation of the led pins. default is mode 1. mode 1 and mode 2 can be controlled via the strap option. all modes are con - figurable via register access. see table 3 for led mode selection. mdix_en (rx_er) s, o, pu 41 mdix enable: default is to enable mdix. this strapping option disables auto-mdix. an external pull-down will disable auto- mdix mode. signal name type pin # description an_en an1 an0 forced mode 0 0 0 10base-t, half-duplex 0 0 1 10base-t, full-duplex 0 1 0 100base-tx, half-duplex 0 1 1 100base-tx, full-duplex an_en an1 an0 advertised mode 1 0 0 10base-t, half/full-duplex 1 0 1 100base-tx, half/full-duplex 1 1 0 10base-t half-duplex 100base-tx, half-duplex 1 1 1 10base-t, half/full-duplex 100base-tx, half/full-duplex mii_mode sni_mode mac interface mode 0 x mii mode 1 0 rmii mode 1 1 10 mb sni mode 14 www.national.com dp83848i 1.8 10 mb/s and 100 mb/s pmd interface 1.9 special connections 1.10 power supply pins signal name type pin # description td-, td+ i/o 16, 17 differential common driver transmit output (pmd output pair). these differential outputs are automatically configured to either 10base-t or 100base-tx signaling. in auto-mdix mode of operation, this pair can be used as the re - ceive input pair. these pins require 3.3v bias for operation. rd-, rd+ i/o 13, 14 differential receive input (pmd input pair). these differential in - puts are automatically configured to accept either 100base-tx or 10base-t signaling. in auto-mdix mode of operation, this pair can be used as the transmit output pair. these pins require 3.3v bias for operation. signal name type pin # description rbias i 24 bias resistor connection. a 4.87 k ? 1% resistor should be con - nected from rbias to gnd. pfbout o 23 power feedback output. parallel caps, 10 f (tantalum pre - ferred) and 0.1 f, should be placed close to the pfbout. con - nect this pin to pfbin1 (pin 18) and pfbin2 (pin 37). see section 5.4 for proper placement pin. pfbin1 pfbin2 i 18 37 power feedback input. these pins are fed with power from pfbout pin. a small capacitor of 0.1 f should be connected close to each pin. note: do not supply power to these pins other than from pfbout. reserved i/o 20, 21 reserved: these pins must be pulled-up through 2.2 k ? resis - tors to avdd33 supply. signal name pin # description iovdd33 32, 48 i/o 3.3v supply iognd 35, 47 i/o ground dgnd 36 digital ground avdd33 22 analog 3.3v supply agnd 15, 19 analog ground 15 www.national.com dp83848i 1.11 package pin assignments vbh48a pin # pin name 1 tx_clk 2 tx_en 3 txd_0 4 txd_1 5 txd_2 6 txd_3/sni_mode 7 pwr_down/int 8 tck 9 tdo 10 tms 11 trst# 12 tdi 13 rd - 14 rd + 15 agnd 16 td - 17 td + 18 pfbin1 19 agnd 20 reserved 21 reserved 22 avdd33 23 pfbout 24 rbias 25 25mhz_out 26 led_act/col/an_en 27 led_speed/an1 28 led_link/an0 29 reset_n 30 mdio 31 mdc 32 iovdd33 33 x2 34 x1 35 iognd 36 dgnd 37 pfbin2 38 rx_clk 39 rx_dv/mii_mode 40 crs/crs_dv/led_cfg 41 rx_er/mdix_en 42 col/phyad0 43 rxd_0/phyad1 44 rxd_1/phyad2 45 rxd_2/phyad3 46 rxd_3/phyad4 47 iognd 48 iovdd33 vbh48a pin # pin name 16 www.national.com dp83848i 2.0 configuration this section includes information on the various configura - tion options available with the dp83848i. the configuration options described below include: ? auto-negotiation ? phy address and leds ? half duplex vs. full duplex ? isolate mode ? loopback mode ?bist 2.1 auto-negotiation the auto-negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest per - formance mode of operation supported by both devices. fast link pulse (flp) bursts provide the signalling used to communicate auto-negotiation abilities between two devices at each end of a link segment. for further detail regarding auto-negotiation, refer to clause 28 of the ieee 802.3u specification. the dp83848i supports four different ethernet protocols (10 mb/s half duplex, 10 mb/s full duplex, 100 mb/s half duplex, and 100 mb/s full duplex), so the inclusion of auto-negotiation ensures that the high - est performance protocol will be selected based on the advertised ability of the link partner. the auto-negotiation function within the dp83848i can be controlled either by internal register access or by the use of the an_en, an1 and an0 pins. 2.1.1 auto-negotiation pin control the state of an_en, an0 and an1 determines whether the dp83848i is forced into a specific mode or auto-negotia - tion will advertise a specific ability (or set of abilities) as given in table 1 . these pins allow configuration options to be selected without requiring internal register access. the state of an_en, an0 and an1, upon power-up/reset, determines the state of bits [8:5] of the anar register. the auto-negotiation function selected at power-up or reset can be changed at any time by writing to the basic mode control register (bmcr) at address 0x00h. 2.1.2 auto-negotiation register control when auto-negotiation is enabled, the dp83848i transmits the abilities programmed into the auto-negotiation adver - tisement register (anar) at address 04h via flp bursts. any combination of 10 mb/s, 100 mb/s, half-duplex, and full duplex modes may be selected. auto-negotiation priority resolution: ? (1) 100base-tx full duplex (highest priority) ? (2) 100base-tx half duplex ? (3) 10base-t full duplex ? (4) 10base-t half duplex (lowest priority) the basic mode control register (bmcr) at address 00h provides control for enabling, disabling, and restarting the auto-negotiation process. when auto-negotiation is dis - abled, the speed selection bit in the bmcr controls switching between 10 mb/s or 100 mb/s operation, and the duplex mode bit controls switching between full duplex operation and half duplex operation. the speed selection and duplex mode bits have no effect on the mode of oper - ation when the auto-negotiation enable bit is set. the link speed can be examined through the phy status register (physts) at address 10h after a link is achieved. the basic mode status register (bmsr) indicates the set of available abilities for technology types, auto-negotiation ability, and extended register capability. these bits are permanently set to indicate the full functionality of the dp83848i (only the 100base-t4 bit is not set since the dp83848i does not support that function). the bmsr also provides status on: ? whether or not auto-negotiation is complete ? whether or not the link partner is advertising that a re - mote fault has occurred ? whether or not valid link has been established ? support for management frame preamble suppression the auto-negotiation advertisement register (anar) indicates the auto-negotiation abilities to be advertised by the dp83848i. all available abilities are transmitted by default, but any ability can be suppressed by writing to the table 1. auto-negotiation modes an_en an1 an0 forced mode 0 0 0 10base-t, half-duplex 0 0 1 10base-t, full-duplex 0 1 0 100base-tx, half-duplex 0 1 1 100base-tx, full-duplex an_en an1 an0 advertised mode 1 0 0 10base-t, half/full-duplex 1 0 1 100base-tx, half/full-duplex 1 1 0 10base-t half-duplex 100base-tx, half-duplex 1 1 1 10base-t, half/full-duplex 100base-tx, half/full-duplex 17 www.national.com dp83848i anar. updating the anar to suppress an ability is one way for a management agent to change (restrict) the tech - nology that is used. the auto-negotiation link partner ability register (anlpar) at address 05h is used to receive the base link code word as well as all next page code words during the negotiation. furthermore, the anlpar will be updated to either 0081h or 0021h for parallel detection to either 100 mb/s or 10 mb/s respectively. the auto-negotiation expansion register (aner) indi - cates additional auto-negotiation status. the aner pro - vides status on: ? whether or not a parallel detect fault has occurred ? whether or not the link partner supports the next page function ? whether or not the dp83848i supports the next page function ? whether or not the current page being exchanged by auto-negotiation has been received ? whether or not the link partner supports auto-negotia - tion 2.1.3 auto-negotiation parallel detection the dp83848i supports the parallel detection function as defined in the ieee 802.3u specification. parallel detection requires both the 10 mb/s and 100 mb/s receivers to moni - tor the receive signal and report link status to the auto- negotiation function. auto-negotiation uses this informa - tion to configure the correct technology in the event that the link partner does not support auto-negotiation but is transmitting link signals that the 100base-tx or 10base- t pmas recognize as valid link signals. if the dp83848i completes auto-negotiation as a result of parallel detection, bits 5 and 7 within the anlpar register will be set to reflect the mode of operation present in the link partner. note that bits 4:0 of the anlpar will also be set to 00001 based on a successful parallel detection to indicate a valid 802.3 selector field. software may deter - mine that negotiation completed via parallel detection by reading a zero in the link partner auto-negotiation able bit once the auto-negotiation complete bit is set. if configured for parallel detect mode and any condition other than a sin - gle good link occurs then the parallel detect fault bit will be set. 2.1.4 auto-negotiation restart once auto-negotiation has completed, it may be restarted at any time by setting bit 9 (restart auto-negotiation) of the bmcr to one. if the mode configured by a successful auto- negotiation loses a valid link, then the auto-negotiation process will resume and attempt to determine the configu - ration for the link. this function ensures that a valid config - uration is maintained if the cable becomes disconnected. a renegotiation request from any entity, such as a manage - ment agent, will cause the dp83848i to halt any transmit data and link pulse activity until the break_link_timer expires (~1500 ms). consequently, the link partner will go into link fail and normal auto-negotiation resumes. the dp83848i will resume auto-negotiation after the break_link_timer has expired by issuing flp (fast link pulse) bursts. 2.1.5 enabling auto-negotiation via software it is important to note that if the dp83848i has been initial - ized upon power-up as a non-auto-negotiating device (forced technology), and it is then required that auto-nego - tiation or re-auto-negotiation be initiated via software, bit 12 (auto-negotiation enable) of the basic mode control register (bmcr) must first be cleared and then set for any auto-negotiation function to take effect. 2.1.6 auto-negotiation complete time parallel detection and auto-negotiation take approximately 2-3 seconds to complete. in addition, auto-negotiation with next page should take approximately 2-3 seconds to com - plete, depending on the number of next pages sent. refer to clause 28 of the ieee 802.3u standard for a full description of the individual timers related to auto-negotia - tion. 2.2 auto-mdix when enabled, this function utilizes auto-negotiation to determine the proper configuration for transmission and reception of data and subsequently selects the appropriate mdi pair for mdi/mdix operation. the function uses a ran - dom seed to control switching of the crossover circuitry. this implementation complies with the corresponding ieee 802.3 auto-negotiation and crossover specifications. auto-mdix is enabled by default and can be configured via strap or via phycr (0x19h) register, bits [15:14]. neither auto-negotiation nor auto-mdix is required to be enabled in forcing crossover of the mdi pairs. forced crossover can be achieved through the force_mdix bit, bit 14 of phycr (0x19h) register. note: auto-mdix will not work in a forced mode of opera - tion. 18 www.national.com dp83848i 2.3 phy address the 5 phy address inputs pins are shared with the rxd[3:0] pins and col pin as shown below. the dp83848i can be set to respond to any of 32 possible phy addresses via strap pins. the information is latched into the phycr register (address 19h, bits [4:0]) at device power-up and hardware reset. the phy address pins are shared with the rxd and col pins. each dp83848i or port sharing an mdio bus in a system must have a unique physical address. the dp83848i supports phy address strapping values 0 (<00000>) through 31 (<11111>). strapping phy address 0 puts the part into isolate mode . it should also be noted that selecting phy address 0 via an mdio write to phycr will not put the device in isolate mode. see section 2.3.1 for more information. for further detail relating to the latch-in timing requirements of the phy address pins, as well as the other hardware configuration pins, refer to the reset summary in section 6.0 . since the phyad[0] pin has weak internal pull-up resistor and phyad[4:1] pins have weak internal pull-down resis - tors, the default setting for the phy address is 00001 (01h). refer to figure 2 for an example of a phyad connection to external components. in this example, the phyad strap - ping results in address 00011 (03h). 2.3.1 mii isolate mode the dp83848i can be put into mii isolate mode by writing to bit 10 of the bmcr register or by strapping in physical address 0. it should be noted that selecting physical address 0 via an mdio write to phycr will not put the device in the mii isolate mode. when in the mii isolate mode, the dp83848i does not respond to packet data present at txd[3:0], tx_en inputs and presents a high impedance on the tx_clk, rx_clk, rx_dv, rx_er, rxd[3:0], col, and crs outputs. when in isolate mode, the dp83848i will continue to respond to all management transactions. while in isolate mode, the pmd output pair will not transmit packet data but will continue to source 100base-tx scrambled idles or 10base-t normal link pulses. the dp83848i can auto-negotiate or parallel detect to a specific technology depending on the receive signal at the pmd input pair. a valid link can be established for the receiver even when the dp83848i is in isolate mode. table 2. phy address mapping pin # phyad function rxd function 42 phyad0 col 43 phyad1 rxd_0 44 phyad2 rxd_1 45 phyad3 rxd_2 46 phyad4 rxd_3 figure 2. phyad strapping example col rxd_0 rxd_1 rxd_2 rxd_3 vcc 2.2k ? phyad0 = 1 phyad1 = 1 phyad2 = 0 phyad3 = 0 phyad4= 0 19 www.national.com dp83848i 2.4 led interface the dp83848i supports three configurable light emitting diode (led) pins. the device supports three led configu - rations: link, speed, activity and collision. function are multiplexed among the leds. the phy control register (phycr) for the leds can also be selected through address 19h, bits [6:5]. see table 3 for led mode selection. the led_link pin in mode 1 indicates the link status of the port. in 100base-t mode, link is established as a result of input receive amplitude compliant with the tp- pmd specifications which will result in internal generation of signal detect. a 10 mb/s link is established as a result of the reception of at least seven consecutive normal link pulses or the reception of a valid 10base-t packet. this will cause the assertion of led_link. led_link will deas - sert in accordance with the link loss timer as specified in the ieee 802.3 specification. the led_link pin in mode 1 will be off when no link is present. the led_link pin in mode 2 and mode 3 will be on to indicate link is good and blink to indicate activity is present on either transmit or receive activity. the led_speed pin indicates 10 or 100 mb/s data rate of the port. the standard cmos driver goes high when oper - ating in 100 mb/s operation. the functionality of this led is independent of mode selected. the led_act/col pin in mode 1 indicates the presence of either transmit or receive activity. the led will be on for activity and off for no activity. in mode 2, this pin indi - cates the collision status of the port. the led will be on for collision and off for no collision. the led_act/col pin in mode 3 indicates the presence of duplex status for 10 mb/s or 100 mb/s operation. the led will be on for full duplex and off for half duplex. in 10 mb/s half duplex mode, the collision led is based on the col signal. since these led pins are also used as strap options, the polarity of the led is dependent on whether the pin is pulled up or down. 2.4.1 leds since the auto-negotiation (an) strap options share the led output pins, the external components required for strapping and led usage must be considered in order to avoid contention. specifically, when the led outputs are used to drive leds directly, the active state of each output driver is dependent on the logic level sampled by the corresponding an input upon power-up/reset. for example, if a given an input is resistively pulled low then the corresponding output will be configured as an active high driver. conversely, if a given an input is resistively pulled high, then the corresponding output will be configured as an active low driver. refer to figure 3 for an example of an connections to external components. in this example, the an strapping results in auto-negotiation with 10/100 half/full-duplex advertised. the adaptive nature of the led outputs helps to simplify potential implementation issues of these dual purpose pins. table 3. led mode select mode led_cfg[1] (bit 6) led_cfg[0] (bit 5) or (pin40) led_link led_speed led_act/col 1 don?t care 1 on for good link off for no link on in 100 mb/s off in 10 mb/s on for activity off for no activity 2 0 0 on for good link blink for activity on in 100 mb/s off in 10 mb/s on for collision off for no collision 3 1 0 on for good link blink for activity on in 100 mb/s off in 10 mb/s on for full duplex off for half duplex led_link led_speed led_act/col vcc 2.2k ? 110 ? 110 ? 2.2k ? 110 ? an0 = 1 an1 = 1 an_en = 1 2.2k ? figure 3. an strapping and led loading example 20 www.national.com dp83848i 2.4.2 led direct control the dp83848i provides another option to directly control any or all led outputs through the led direct control reg - ister (ledcr), address 18h. the register does not provide read access to leds. 2.5 half duplex vs. full duplex the dp83848i supports both half and full duplex operation at both 10 mb/s and 100 mb/s speeds. half-duplex relies on the csma/cd protocol to handle colli - sions and network access. in half-duplex mode, crs responds to both transmit and receive activity in order to maintain compliance with the ieee 802.3 specification. since the dp83848i is designed to support simultaneous transmit and receive activity it is capable of supporting full- duplex switched applications with a throughput of up to 200 mb/s per port when operating in 100base-tx mode. because the csma/cd protocol does not apply to full- duplex operation, the dp83848i disables its own internal collision sensing and reporting functions and modifies the behavior of carrier sense (crs) such that it indicates only receive activity. this allows a full-duplex capable mac to operate properly. all modes of operation (100base-tx and 10base-t) can run either half-duplex or full-duplex. additionally, other than crs and collision reporting, all remaining mii signaling remains the same regardless of the selected duplex mode. it is important to understand that while auto-negotiation with the use of fast link pulse code words can interpret and configure to full-duplex operation, parallel detection can not recognize the difference between full and half- duplex from a fixed 10 mb/s or 100 mb/s link partner over twisted pair. as specified in the 802.3u specification, if a far-end link partner is configured to a forced full duplex 100base-tx ability, the parallel detection state machine in the partner would be unable to detect the full duplex capa - bility of the far-end link partner. this link segment would negotiate to a half duplex 100base-tx configuration (same scenario for 10 mb/s). 2.6 internal loopback the dp83848i includes a loopback test mode for facilitat - ing system diagnostics. the loopback mode is selected through bit 14 (loopback) of the basic mode control reg - ister (bmcr). writing 1 to this bit enables mii transmit data to be routed to the mii receive outputs. loopback status may be checked in bit 3 of the phy status register (physts). while in loopback mode the data will not be transmitted onto the media. to ensure that the desired operating mode is maintained, auto-negotiation should be disabled before selecting the loopback mode. 2.7 bist the dp83848i incorporates an internal built-in self test (bist) circuit to accommodate in-circuit testing or diagnos - tics. the bist circuit can be utilized to test the integrity of the transmit and receive data paths. bist testing can be performed with the part in the internal loopback mode or externally looped back using a loopback cable fixture. the bist is implemented with independent transmit and receive paths, with the transmit block generating a continu - ous stream of a pseudo random sequence. the user can select a 9 bit or 15 bit pseudo random sequence from the psr_15 bit in the phy control register (phycr). the received data is compared to the generated pseudo-ran - dom data by the bist linear feedback shift register (lfsr) to determine the bist pass/fail status. the pass/fail status of the bist is stored in the bist status bit in the phycr register. the status bit defaults to 0 (bist fail) and will transition on a successful comparison. if an error (mis-compare) occurs, the status bit is latched and is cleared upon a subsequent write to the start/stop bit. for transmit vod testing, the packet bist continuous mode can be used to allow continuous data transmission, setting bist_cont_mode, bit 5, of cdctrl1 (0x1bh). the number of bist errors can be monitored through the bist error count in the cdctrl1 (0x1bh), bits [15:8]. 21 www.national.com dp83848i 3.0 functional description the dp83848i supports several modes of operation using the mii interface pins. the options are defined in the follow - ing sections and include: ? mii mode ? rmii mode ? 10 mb serial network interface (sni) the modes of operation can be selected by strap options or register control. for rmii mode, it is recommended to use the strap option, since it requires a 50 mhz clock instead of the normal 25 mhz. in each of these modes, the ieee 802.3 serial manage - ment interface is operational for device configuration and status. the serial management interface of the mii allows for the configuration and control of multiple phy devices, gathering of status, error information, and the determina - tion of the type and capabilities of the attached phy(s). 3.1 mii interface the dp83848i incorporates the media independent inter - face (mii) as specified in clause 22 of the ieee 802.3u standard. this interface may be used to connect phy devices to a mac in 10/100 mb/s systems. this section describes the nibble wide mii data interface. the nibble wide mii data interface consists of a receive bus and a transmit bus each with control signals to facilitate data transfer between the phy and the upper layer (mac). 3.1.1 nibble-wide mii data interface clause 22 of the ieee 802.3u specification defines the media independent interface. this interface includes a dedicated receive bus and a dedicated transmit bus. these two data buses, along with various control and status sig - nals, allow for the simultaneous exchange of data between the dp83848i and the upper layer agent (mac). the receive interface consists of a nibble wide data bus rxd[3:0], a receive error signal rx_er, a receive data valid flag rx_dv, and a receive clock rx_clk for syn - chronous transfer of the data. the receive clock operates at either 2.5 mhz to support 10 mb/s operation modes or at 25 mhz to support 100 mb/s operational modes. the transmit interface consists of a nibble wide data bus txd[3:0], a transmit enable control signal tx_en, and a transmit clock tx_clk which runs at either 2.5 mhz or 25 mhz. additionally, the mii includes the carrier sense signal crs, as well as a collision detect signal col. the crs signal asserts to indicate the reception of data from the network or as a function of transmit data in half duplex mode. the col signal asserts as an indication of a collision which can occur during half-duplex operation when both a transmit and receive operation occur simultaneously. 3.1.2 collision detect for half duplex, a 10base-t or 100base-tx collision is detected when the receive and transmit channels are active simultaneously. collisions are reported by the col signal on the mii. if the dp83848i is transmitting in 10 mb/s mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state. this prevents a collision being reported incorrectly due to noise on the network. the col signal remains set for the dura - tion of the collision. if a collision occurs during a receive operation, it is immedi - ately reported by the col signal. when heartbeat is enabled (only applicable to 10 mb/s operation), approximately 1 s after the transmission of each packet, a signal quality error (sqe) signal of approx - imately 10 bit times is generated (internally) to indicate successful transmission. sqe is reported as a pulse on the col signal of the mii. 3.1.3 carrier sense carrier sense (crs) is asserted due to receive activity, once valid data is detected via the squelch function during 10 mb/s operation. during 100 mb/s operation crs is asserted when a valid link (sd) and two non-contiguous zeros are detected on the line. for 10 or 100 mb/s half duplex operation, crs is asserted during either packet transmission or reception. for 10 or 100 mb/s full duplex operation, crs is asserted only due to receive activity. crs is deasserted following an end of packet. 3.2 reduced mii interface the dp83848i incorporates the reduced media indepen - dent interface (rmii) as specified in the rmii specification (rev1.2) from the rmii consortium. this interface may be used to connect phy devices to a mac in 10/100 mb/s systems using a reduced number of pins. in this mode, data is transferred 2-bits at a time using the 50 mhz rmii_ref clock for both transmit and receive. the follow - ing pins are used in rmii mode: ? tx_en ?txd[1:0] ? rx_er (optional for mac) ? crs_dv ? rxd[1:0] ? x1 (rmii reference clock is 50 mhz) in addition, the rmii mode supplies an rx_dv signal which allows for a simpler method of recovering receive data without having to separate rx_dv from the crs_dv indication. this is especially useful for systems which do not require crs, such as systems that only support full- duplex operation. this signal is also useful for diagnostic testing where it may be desirable to loop receive rmii data directly to the transmitter. since the reference clock operates at 10 times the data rate for 10 mb/s operation, transmit data is sampled every 10 clocks. likewise, receive data will be generated every 10th clock so that an attached device can sample the data every 10 clocks. rmii mode requires a 50 mhz oscillator be connected to the device x1 pin. a 50 mhz crystal is not supported. 22 www.national.com dp83848i to tolerate potential frequency differences between the 50 mhz reference clock and the recovered receive clock, the receive rmii function includes a programmable elasticity buffer. the elasticity buffer is programmable to minimize propagation delay based on expected packet size and clock accuracy. this allows for supporting a range of packet sizes including jumbo frames. the elasticity buffer will force frame check sequence errors for packets which overrun or underrun the fifo. underrun and overrun conditions can be reported in the rmii and bypass register (rbr). the following table indi - cates how to program the elasticity buffer fifo (in 4-bit incre - ments) based on expected max packet size and clock accuracy. it assumes both clocks (rmii reference clock and far-end transmitter clock) have the same accuracy. 3.3 10 mb serial network interface (sni) the dp83848i incorporates a 10 mb serial network inter - face (sni) which allows a simple serial data interface for 10 mb only devices. this is also referred to as a 7-wire inter - face. while there is no defined standard for this interface, it is based on early 10 mb physical layer devices. data is clocked serially at 10 mhz using separate transmit and receive paths. the following pins are used in sni mode: ?tx_clk ?tx_en ?txd[0] ?rx_clk ?rxd[0] ? crs ?col 3.4 802.3u mii serial management interface 3.4.1 serial management register access the serial management mii specification defines a set of thirty-two 16-bit status and control registers that are acces - sible through the management interface pins mdc and mdio. the dp83848i implements all the required mii reg - isters as well as several optional registers. these registers are fully described in section 7.0 . a description of the serial management access protocol follows. 3.4.2 serial management access protocol the serial control interface consists of two pins, manage - ment data clock (mdc) and management data input/out - put (mdio). mdc has a maximum clock rate of 25 mhz and no minimum rate. the mdio line is bi-directional and may be shared by up to 32 devices. the mdio frame for - mat is shown below in tab l e 5 . the mdio pin requires a pull-up resistor (1.5 k ? ) which, during idle and turnaround, will pull mdio high. in order to initialize the mdio interface, the station management entity sends a sequence of 32 contiguous logic ones on mdio to provide the dp83848i with a sequence that can be used to establish synchronization. this preamble may be gener - ated either by driving mdio high for 32 consecutive mdc clock cycles, or by simply allowing the mdio pull-up resis - tor to pull the mdio pin high during which time 32 mdc clock cycles are provided. in addition 32 mdc clock cycles should be used to re-sync the device if an invalid start, opcode, or turnaround bit is detected. the dp83848i waits until it has received this preamble sequence before responding to any other transaction. once the dp83848i serial management port has been ini - tialized no further preamble sequencing is required until after a power-on/reset, invalid start, invalid opcode, or invalid turnaround bit has occurred. the start code is indicated by a <01> pattern. this assures the mdio line transitions from the default idle line state. turnaround is defined as an idle bit time inserted between the register address field and the data field. to avoid con - tention during a read transaction, no device shall actively drive the mdio signal during the first bit of turnaround. the addressed dp83848i drives the mdio with a zero for the second bit of turnaround and follows this with the required data. figure 4 shows the timing relationship between mdc and the mdio as driven/received by the sta - tion (sta) and the dp83848i (phy) for a typical register read access. for write transactions, the station management entity writes data to the addressed dp83848i thus eliminating the requirement for mdio turnaround. the turnaround time is filled by the management entity by inserting <10>. figure 5 shows the timing relationship for a typical mii register write access. table 4. supported packet sizes at +/-50ppm +/-100ppm for each clock start threshold rbr[1:0] latency tolerance recommended packet size at +/- 50ppm recommended packet size at +/- 100ppm 1 (4-bits) 2 bits 2400 bytes 1200 bytes 2 (8-bits) 6 bits 7200 bytes 3600 bytes 3 (12-bits) 10 bits 12000 bytes 6000 bytes 0 (16-bits) 14 bits 16800 bytes 8400 bytes 23 www.national.com dp83848i 3.4.3 serial management preamble suppression the dp83848i supports a preamble suppression mode as indicated by a one in bit 6 of the basic mode status regis - ter (bmsr, address 01h.) if the station management entity (i.e. mac or other management controller) determines that all phys in the system support preamble suppression by returning a one in this bit, then the station management entity need not generate preamble for each management transaction. the dp83848i requires a single initialization sequence of 32 bits of preamble following hardware/software reset. this requirement is generally met by the mandatory pull-up resistor on mdio in conjunction with a continuous mdc, or the management access made to determine whether pre - amble suppression is supported. while the dp83848i requires an initial preamble sequence of 32 bits for management initialization, it does not require a full 32-bit sequence between each subsequent transac - tion. a minimum of one idle bit between management transactions is required as specified in the ieee 802.3u specification. table 5. typical mdio frame format mii management serial protocol 24 www.national.com dp83848i 4.0 architecture this section describes the operations within each trans - ceiver module, 100base-tx and 10base-t. each opera - tion consists of several functional blocks and described in the following: ? 100base-tx transmitter ? 100base-tx receiver ? 10base-t transceiver module 4.1 100base-tx transmitter the 100base-tx transmitter consists of several functional blocks which convert synchronous 4-bit nibble data, as pro - vided by the mii, to a scrambled mlt-3 125 mb/s serial data stream. because the 100base-tx tp-pmd is inte - grated, the differential output pins, pmd output pair, can be directly routed to the magnetics. the block diagram in figure 6. provides an overview of each functional block within the 100base-tx transmit sec - tion. the transmitter section consists of the following functional blocks: ? code-group encoder and injection block ? scrambler block (bypass option) ? nrz to nrzi encoder block ? binary to mlt-3 converter / common driver the bypass option for the functional blocks within the 100base-tx transmitter provides flexibility for applications where data conversion is not always required. the dp83848i implements the 100base-tx transmit state machine diagram as specified in the ieee 802.3u stan - dard, clause 24. figure 6. 100base-tx transmit block diagram 4b5b code- group encoder & scrambler nrz to nrzi encoder 5b parallel to serial pmd output pair tx_clk txd[3:0] / tx_en binary to mlt-3 / common driver 125mhz clock bp_scr mux 100base-tx loopback mlt[1:0] divide by 5 25 www.national.com dp83848i table 5. 4b5b ccode-group encoding and injection the code-group encoder converts 4-bit (4b) nibble data generated by the mac into 5-bit (5b) code-groups for transmission. this conversion is required to allow control data to be combined with packet data code-groups. refer to table 5 for 4b to 5b code-group mapping details. the code-group encoder substitutes the first 8-bits of the mac preamble with a j/k code-group pair (11000 10001) upon transmission. the code-group encoder continues to replace subsequent 4b preamble and data nibbles with corresponding 5b code-groups. at the end of the transmit packet, upon the deassertion of transmit enable signal from the mac, the code-group encoder injects the t/r code-group pair (01101 00111) indicating the end of the frame. after the t/r code-group pair, the code-group encoder continuously injects idles into the transmit data stream until the next transmit packet is detected (reassertion of transmit enable). 4.1.1 scrambler the scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for data codes 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 a 10110 1010 b 10111 1011 c 11010 1100 d 11011 1101 e 11100 1110 f 11101 1111 idle and control codes h 00100 halt code-group - error code i 11111 inter-packet idle - 0000 ( note 1) j 11000 first start of packet - 0101 ( note 1) k 10001 second start of packet - 0101 ( note 1) t 01101 first end of packet - 0000 ( note 1) r 00111 second end of packet - 0000 ( note 1) invalid codes v 00000 v 00001 v 00010 v 00011 v 00101 v 00110 v 01000 v 01100 note: control code-groups i, j, k, t and r in data fields will be mapped as invalid codes, together with rx_er as - serted. 6. 26 www.national.com dp83848i 100base-tx applications). by scrambling the data, the total energy launched onto the cable is randomly distrib - uted over a wide frequency range. without the scrambler, energy levels at the pmd and on the cable could peak beyond fcc limitations at frequencies related to repeating 5b sequences (i.e., continuous transmission of idles). the scrambler is configured as a closed loop linear feed - back shift register (lfsr) with an 11-bit polynomial. the output of the closed loop lfsr is x-ord with the serial nrz data from the code-group encoder. the result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 db. the dp83848i uses the phy_id (pins phyad [4:0]) to set a unique seed value. 4.1.2 nrz to nrzi encoder after the transmit data stream has been serialized and scrambled, the data must be nrzi encoded in order to comply with the tp-pmd standard for 100base-tx trans - mission over category-5 unshielded twisted pair cable. 4.1.3 binary to mlt-3 convertor the binary to mlt-3 conversion is accomplished by con - verting the serial binary data stream output from the nrzi encoder into two binary data streams with alternately phased logic one events. these two binary streams are then fed to the twisted pair output driver which converts the voltage to current and alternately drives either side of the transmit transformer primary winding, resulting in a mlt-3 signal. the 100base-tx mlt-3 signal sourced by the pmd out - put pair common driver is slew rate controlled. this should be considered when selecting ac coupling magnetics to ensure tp-pmd standard compliant transition times (3 ns < tr < 5 ns). the 100base-tx transmit tp-pmd function within the dp83848i is capable of sourcing only mlt-3 encoded data. binary output from the pmd output pair is not possible in 100 mb/s mode. 4.2 100base-tx receiver the 100base-tx receiver consists of several functional blocks which convert the scrambled mlt-3 125 mb/s serial data stream to synchronous 4-bit nibble data that is pro - vided to the mii. because the 100base-tx tp-pmd is integrated, the differential input pins, rd , can be directly routed from the ac coupling magnetics. see figure 7 for a block diagram of the 100base-tx receive function. this provides an overview of each func - tional block within the 100base-tx receive section. the receive section consists of the following functional blocks: ? analog front end ? digital signal processor ? signal detect ? mlt-3 to binary decoder ? nrzi to nrz decoder ? serial to parallel ? descrambler ? code group alignment ?4b/5b decoder ? link integrity monitor ? bad ssd detection 4.2.1 analog front end in addition to the digital equalization and gain control, the dp83848i includes analog equalization and gain control in the analog front end. the analog equalization reduces the amount of digital equalization required in the dsp. 4.2.2 digital signal processor the digital signal processor includes adaptive equaliza - tion with gain control and base line wander compensa - tion. 27 www.national.com dp83848i 4b/5b decoder descrambler mlt-3 to binary decoder rx_clk rxd[3:0] / rx_er nrzi to nrz decoder code group alignment serial to parallel rx_dv/crs rx_data valid ssd detect rd +/? signal detect link integrity monitor digital signal processor analog front end figure 7. 100base-tx receive block diagram 28 www.national.com dp83848i 4.2.2.1 digital adaptive equalization and gain control when transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. in high-speed twisted pair signalling, the fre - quency content of the transmitted signal can vary greatly during normal operation based primarily on the random - ness of the scrambled data stream. this variation in signal attenuation caused by frequency variations must be com - pensated to ensure the integrity of the transmission. in order to ensure quality transmission when employing mlt-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. the selection of long cable lengths for a given implementation, requires significant compensa - tion which will over-compensate for shorter, less attenuat - ing lengths. conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. the compensation or equalization must be adap - tive to ensure proper conditioning of the received signal independent of the cable length. the dp83848i utilizes an extremely robust equalization scheme referred as ?digital adaptive equalization.? the digital equalizer removes isi (inter symbol interfer - ence) from the receive data stream by continuously adapt - ing to provide a filter with the inverse frequency response of the channel. equalization is combined with an adaptive gain control stage. this enables the receive 'eye pattern' to be opened sufficiently to allow very reliable data recovery. the curves given in figure 8 illustrate attenuation at certain frequencies for given cable lengths. this is derived from the worst case frequency vs. attenuation figures as speci - fied in the eia/tia bulletin tsb-36. these curves indicate the significant variations in signal attenuation that must be compensated for by the receive adaptive equalization cir - cuit. figure 8. eia/tia attenuation vs. frequency for 0, 50, 100, 130 & 150 meters of cat 5 cable 29 www.national.com dp83848i 4.2.2.2 base line wander compensation the dp83848i is completely ansi tp-pmd compliant and includes base line wander (blw) compensation. the blw compensation block can successfully recover the tp- pmd defined ?killer? pattern. blw can generally be defined as the change in the aver - age dc content, relatively short period over time, of an ac coupled digital transmission over a given transmission medium. (i.e., copper wire). blw results from the interaction between the low fre - quency components of a transmitted bit stream and the fre - quency response of the ac coupling component(s) within the transmission system. if the low frequency content of the digital bit stream goes below the low frequency pole of the ac coupling transformers then the droop characteris - tics of the transformers will dominate resulting in potentially serious blw. the digital oscilloscope plot provided in figure 9 illustrates the severity of the blw event that can theoretically be gen - erated during 100base-tx packet transmission. this event consists of approximately 800 mv of dc offset for a period of 120 s. left uncompensated, events such as this can cause packet loss. 4.2.3 signal detect the signal detect function of the dp83848i is incorporated to meet the specifications mandated by the ansi fddi tp- pmd standard as well as the ieee 802.3 100base-tx standard for both voltage thresholds and timing parame - ters. note that the reception of normal 10base-t link pulses and fast link pulses per ieee 802.3u auto-negotiation by the 100base-tx receiver do not cause the dp83848i to assert signal detect. 4.2.4 mlt-3 to nrzi decoder the dp83848i decodes the mlt-3 information from the digital adaptive equalizer block to binary nrzi data. 4.2.5 nrzi to nrz in a typical application, the nrzi to nrz decoder is required in order to present nrz formatted data to the descrambler. 4.2.6 serial to parallel the 100base-tx receiver includes a serial to parallel converter which supplies 5-bit wide data symbols to the pcs rx state machine. figure 9. 100base-tx blw event 30 www.national.com dp83848i 4.2.7 descrambler a serial descrambler is used to de-scramble the received nrz data. the descrambler has to generate an identical data scrambling sequence (n) in order to recover the origi - nal unscrambled data (ud) from the scrambled data (sd) as represented in the equations: synchronization of the descrambler to the original scram - bling sequence (n) is achieved based on the knowledge that the incoming scrambled data stream consists of scrambled idle data. after the descrambler has recog - nized 12 consecutive idle code-groups, where an unscrambled idle code-group in 5b nrz is equal to five consecutive ones (11111), it will synchronize to the receive data stream and generate unscrambled data in the form of unaligned 5b code-groups. in order to maintain synchronization, the descrambler must continuously monitor the validity of the unscrambled data that it generates. to ensure this, a line state monitor and a hold timer are used to constantly monitor the synchroniza - tion status. upon synchronization of the descrambler the hold timer starts a 722 s countdown. upon detection of sufficient idle code-groups (58 bit times) within the 722 s period, the hold timer will reset and begin a new count - down. this monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. if the line state monitor does not recognize sufficient unscrambled idle code-groups within the 722 s period, the entire descrambler will be forced out of the cur - rent state of synchronization and reset in order to re- acquire synchronization. 4.2.8 code-group alignment the code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the descrambler is bypassed, directly from the nrzi/nrz decoder) and con - verts it into 5b code-group data (5 bits). code-group align - ment occurs after the j/k code-group pair is detected. once the j/k code-group pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. 4.2.9 4b/5b decoder the code-group decoder functions as a look up table that translates incoming 5b code-groups into 4b nibbles. the code-group decoder first detects the j/k code-group pair preceded by idle code-groups and replaces the j/k with mac preamble. specifically, the j/k 10-bit code-group pair is replaced by the nibble pair (0101 0101). all subsequent 5b code-groups are converted to the corresponding 4b nibbles for the duration of the entire packet. this conver - sion ceases upon the detection of the t/r code-group pair denoting the end of stream delimiter (esd) or with the reception of a minimum of two idle code-groups. 4.2.10 100base-tx link integrity monitor the 100 base tx link monitor ensures that a valid and sta - ble link is established before enabling both the transmit and receive pcs layer. signal detect must be valid for 395us to allow the link mon - itor to enter the 'link up' state, and enable the transmit and receive functions. 4.2.11 bad ssd detection a bad start of stream delimiter (bad ssd) is any transition from consecutive idle code-groups to non-idle code-groups which is not prefixed by the code-group pair /j/k. if this condition is detected, the dp83848i will assert rx_er and present rxd[3:0] = 1110 to the mii for the cycles that correspond to received 5b code-groups until at least two idle code groups are detected. in addition, the false carrier sense counter register (fcscr) will be incremented by one. once at least two idle code groups are detected, rx_er and crs become de-asserted. 4.3 10base-t transceiver module the 10base-t transceiver module is ieee 802.3 compli - ant. it includes the receiver, transmitter, collision, heart - beat, loopback, jabber, and link integrity functions, as defined in the standard. an external filter is not required on the 10base-t interface since this is integrated inside the dp83848i. this section focuses on the general 10base-t system level operation. 4.3.1 operational modes the dp83848i has two basic 10base-t operational modes: ? half duplex mode ? full duplex mode half duplex mode in half duplex mode the dp83848i functions as a standard ieee 802.3 10base-t transceiver supporting the csma/cd protocol. full duplex mode in full duplex mode the dp83848i is capable of simulta - neously transmitting and receiving without asserting the collision signal. the dp83848i's 10 mb/s endec is designed to encode and decode simultaneously. ud sd n () = sd ud n () = 31 www.national.com dp83848i 4.3.2 smart squelch the smart squelch is responsible for determining when valid data is present on the differential receive inputs. the dp83848i implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. smart squelch operation is independent of the 10base-t operational mode. the squelch circuitry employs a combination of amplitude and timing measurements (as specified in the ieee 802.3 10bse-t standard) to determine the validity of data on the twisted pair inputs (refer to figure 10 ). the signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. once this first squelch level is overcome cor - rectly, the opposite squelch level must then be exceeded within 150 ns. finally the signal must again exceed the original squelch level within a 150 ns to ensure that the input waveform will not be rejected. this checking proce - dure results in the loss of typically three preamble bits at the beginning of each packet. only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. at this time, the smart squelch circuitry is reset. valid data is considered to be present until the squelch level has not been generated for a time longer than 150 ns, indicating the end of packet. once good data has been detected, the squelch levels are reduced to minimize the effect of noise causing premature end of packet detection. 4.3.3 collision detection and sqe when in half duplex, a 10base-t collision is detected when the receive and transmit channels are active simulta - neously. collisions are reported by the col signal on the mii. collisions are also reported when a jabber condition is detected. the col signal remains set for the duration of the collision. if the phy is receiving when a collision is detected it is reported immediately (through the col pin). when heartbeat is enabled, approximately 1 s after the transmission of each packet, a signal quality error (sqe) signal of approximately 10-bit times is generated to indi - cate successful transmission. sqe is reported as a pulse on the col signal of the mii. the sqe test is inhibited when the phy is set in full duplex mode. sqe can also be inhibited by setting the heartbeat_dis bit in the 10btscr register. 4.3.4 carrier sense carrier sense (crs) may be asserted due to receive activ - ity once valid data is detected via the squelch function. for 10 mb/s half duplex operation, crs is asserted during either packet transmission or reception. for 10 mb/s full duplex operation, crs is asserted only during receive activity. crs is deasserted following an end of packet. 4.3.5 normal link pulse detection/generation the link pulse generator produces pulses as defined in the ieee 802.3 10base-t standard. each link pulse is nomi - nally 100 ns in duration and transmitted every 16 ms in the absence of transmit data. link pulses are used to check the integrity of the connec - tion with the remote end. if valid link pulses are not received, the link detector disables the 10base-t twisted pair transmitter, receiver and collision detection functions. when the link integrity function is disabled (force_link_10 of the 10btscr register), a good link is forced and the 10base-t transceiver will operate regard - less of the presence of link pulses. end of packet start of packet v sq-(reduced) v sq- v sq+(reduced) v sq+ <150 ns <150 ns >150 ns figure 10. 10base-t twisted pair smart squelch operation 32 www.national.com dp83848i 4.3.6 jabber function the jabber function monitors the dp83848i's output and disables the transmitter if it attempts to transmit a packet of longer than legal size. a jabber timer monitors the transmit - ter and disables the transmission if the transmitter is active for approximately 85 ms. once disabled by the jabber function, the transmitter stays disabled for the entire time that the endec module's inter - nal transmit enable is asserted. this signal has to be de- asserted for approximately 500 ms (the ?unjab? time) before the jabber function re-enables the transmit outputs. the jabber function is only relevant in 10base-t mode. 4.3.7 automatic link polarity detection and correction the dp83848i's 10base-t transceiver module incorpo - rates an automatic link polarity detection circuit. when three consecutive inverted link pulses are received, bad polarity is reported. a polarity reversal can be caused by a wiring error at either end of the cable, usually at the main distribution frame (mdf) or patch panel in the wiring closet. the bad polarity condition is latched in the 10btscr regis - ter. the dp83848i's 10base-t transceiver module cor - rects for this error internally and will continue to decode received data correctly. this eliminates the need to correct the wiring error immediately. 4.3.8 transmit and receive filtering external 10base-t filters are not required when using the dp83848i, as the required signal conditioning is integrated into the device. only isolation transformers and impedance matching resis - tors are required for the 10base-t transmit and receive interface. the internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated by at least 30 db. 4.3.9 transmitter the encoder begins operation when the transmit enable input (tx_en) goes high and converts nrz data to pre- emphasized manchester data for the transceiver. for the duration of tx_en, the serialized transmit data (txd) is encoded for the transmit-driver pair (pmd output pair). txd must be valid on the rising edge of transmit clock (tx_clk). transmission ends when tx_en deasserts. the last transition is always positive; it occurs at the center of the bit cell if the last bit is a one, or at the end of the bit cell if the last bit is a zero. 4.3.10 receiver the decoder detects the end of a frame when no additional mid-bit transitions are detected. within one and a half bit times after the last bit, carrier sense is de-asserted. receive clock stays active for five more bit times after crs goes low, to guarantee the receive timings of the controller. 33 www.national.com dp83848i 5.0 design guidelines 5.1 tpi network circuit figure 11 shows the recommended circuit for a 10/100 mb/s twisted pair interface. to the right is a partial list of recommended transformers. it is important that the user realize that variations with pcb and component character - istics requires that the application be tested to ensure that the circuit meets the requirements of the intended applica - tion. pulse h1102 pulse h2019 pulse j0011d21 pulse j0011d21b figure 11. 10/100 mb/s twisted pair interface rj45 rd- rd+ td- td+ rd- rd+ td- td+ 1:1 0.1f* t1 1:1 common mode chokes may be required. 49.9 ? 49.9 ? 0.1f* vdd note: center tap is pulled to vdd *place capacitors close to the transformer center taps 0.1 f all values are typical and are +/- 1% place resistors and capacitors close to the device. vdd 49.9 ? 49.9 ? 0.1 f vdd 34 www.national.com dp83848i 5.2 esd protection typically, esd precautions are predominantly in effect when handling the devices or board before being installed in a system. in those cases, strict handling procedures need be implemented during the manufacturing process to greatly reduce the occurrences of catastrophic esd events. after the system is assembled, internal compo - nents are less sensitive from esd events. see section 8.0 for esd rating. 5.3 clock in (x1) requirements the dp83848i supports an external cmos level oscillator source or a crystal resonator device. oscillator if an external clock source is used, x1 should be tied to the clock source and x2 should be left floating. specifications for cmos oscillators: 25 mhz in mii mode and 50 mhz in rmii mode are listed in table 7 and ta b l e 8 . note: maximum reference clock jitter should not exceed 1ns peak-to-peak or 78ps rms from 50 khz to 1 mhz. crystal a 25 mhz, parallel, 20 pf load crystal resonator should be used if a crystal source is desired. figure 12 shows a typi - cal connection for a crystal resonator circuit. the load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. the oscillator circuit is designed to drive a parallel reso - nance at cut crystal with a minimum drive level of 100 w and a maximum of 500 w. if a crystal is specified for a lower drive level, a current limiting resistor should be placed in series between x2 and the crystal. as a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, c l1 and c l2 should be set at 33 pf, and r 1 should be set at 0 ?. specification for 25 mhz crystal are listed in ta b l e 9 . figure 12. crystal oscillator circuit x1 x2 c l2 c l1 r 1 table 6. table 7. 25 mhz oscillator specification parameter min typ max units condition frequency 25 mhz frequency tolerance + 50 ppm operational temperature frequency stability + 50 ppm 1 year aging rise / fall time 6 nsec 20% - 80% jitter (short term) 50 psec cycle-to-cycle jitter (long term) 1 nsec accumulative over 10us symmetry 40% 60% duty cycle table 8. 50 mhz oscillator specification parameter min typ max units condition frequency 50 mhz frequency tolerance + 50 ppm operational temperature frequency stability + 50 ppm operational temperature rise / fall time 6 nsec 20% - 80% jitter (short term) 50 psec cycle-to-cycle jitter (long term) 1 nsec accumulative over 10us symmetry 40% 60% duty cycle 35 www.national.com dp83848i 5.4 power feedback circuit to ensure correct operation for the dp83848i, parallel caps with values of 10 f (tantalum) and 0.1 f should be placed close to pin 23 ( pfbout ) of the device. pin 18 ( pfbin1 ) and pin 37 ( pfbin2 ) must be connected to pin 23 ( pfbout ), each pin requires a small capacitor (.1 f). see figure 13 below for proper connections. 5.5 power down/interrupt the power down and interrupt functions are multiplexed on pin 7 of the device. by default, this pin functions as a power down input and the interrupt function is disabled. setting bit 0 (int_oe) of micr (0x11h) will configure the pin as an active low interrupt output. 5.5.1 power down control mode the pwr_down/int pin can be asserted low to put the device in a power down mode. this is equivalent to setting bit 11 (power down) in the basic mode control register, bmcr (0x00h). an external control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. alternatively, the device can be configured to ini - tialize into a power down state by use of an external pull- down resistor on the pwr_down/int pin. since the device will still respond to management register accesses, setting the int_oe bit in the micr register will disable the pwr_down/int input, allowing the device to exit the power down state. 5.5.2 interrupt mechanisms the interrupt function is controlled via register access. all interrupt sources are disabled by default. setting bit 1 (inten) of micr (0x11h) will enable interrupts to be out - put, dependent on the interrupt mask set in the lower byte of the misr (0x12h). the pwr_down/int pin is asyn - chronously asserted low when an interrupt condition occurs. the source of the interrupt can be determined by reading the upper byte of the misr. one or more bits in the misr will be set, denoting all currently pending interrupts. reading of the misr clears all pending interrupts. example: to generate an interrupt on a change of link sta - tus or on a change of energy detect power state, the steps would be: ? write 0003h to micr to set inten and int_oe ? write 0060h to misr to set ed_int_en and link_int_en ? monitor pwr_down/int pin when pwr_down/int pin asserts low, user would read the misr register to see if the ed_int or link_int bits are set, i.e. which source caused the interrupt. after read - ing the misr, the interrupt bits should clear and the pwr_down/int pin will deassert. 5.6 energy detect mode when energy detect is enabled and there is no activity on the cable, the dp83848i will remain in a low power mode while monitoring the transmission line. activity on the line will cause the dp83848i to go through a normal power up sequence. regardless of cable activity, the dp83848i will occasionally wake up the transmitter to put ed pulses on the line, but will otherwise draw as little power as possible. energy detect functionality is controlled via register energy detect control (edcr), address 0x1dh. table 9. 25 mhz crystal specification parameter min typ max units condition frequency 25 mhz frequency tolerance + 50 ppm operational temperature frequency stability + 50 ppm 1 year aging load capacitance 25 40 pf .1 f 10 f pin 23 ( pfbout ) .1 f .1 f pin 18 ( pfbin1 ) pin 37 ( pfbin2 ) + - figure 13. power feeback connection 36 www.national.com dp83848i 6.0 reset operation the dp83848i includes an internal power-on reset (por) function and does not need to be explicitly reset for normal operation after power up. if required during normal opera - tion, the device can be reset by a hardware or software reset. 6.1 hardware reset a hardware reset is accomplished by applying a low pulse (ttl level), with a duration of at least 1 s, to the reset_n. this will reset the device such that all registers will be reinitialized to default values and the hardware con - figuration values will be re-latched into the device (similar to the power-up/reset operation). 6.2 software reset a software reset is accomplished by setting the reset bit (bit 15) of the basic mode control register (bmcr). the period from the point in time when the reset bit is set to the point in time when software reset has concluded is approx - imately 1 s. the software reset will reset the device such that all regis - ters will be reset to default values and the hardware config - uration values will be maintained. software driver code must wait 3 s following a software reset before allowing further serial mii operations with the dp83848i. 37 www.national.com dp83848i 7.0 register block table 10. register map offset access tag description hex decimal 00h 0 rw bmcr basic mode control register 01h 1 ro bmsr basic mode status register 02h 2 ro phyidr1 phy identifier register #1 03h 3 ro phyidr2 phy identifier register #2 04h 4 rw anar auto-negotiation advertisement register 05h 5 rw anlpar auto-negotiation link partner ability register (base page) 05h 5 rw anlparnp auto-negotiation link partner ability register (next page) 06h 6 rw aner auto-negotiation expansion register 07h 7 rw annptr auto-negotiation next page tx 08h-fh 8-15 rw reserved reserved extended registers 10h 16 ro physts phy status register 11h 17 rw micr mii interrupt control register 12h 18 ro misr mii interrupt status register 13h 19 rw reserved reserved 14h 20 ro fcscr false carrier sense counter register 15h 21 ro recr receive error counter register 16h 22 rw pcsr pcs sub-layer configuration and status register 17h 23 rw rbr rmii and bypass register 18h 24 rw ledcr led direct control register 19h 25 rw phycr phy control register 1ah 26 rw 10btscr 10base-t status/control register 1bh 27 rw cdctrl1 cd test control register and bist extensions register 1ch 28 rw reserved reserved 1dh 29 rw edcr energy detect control register 1eh-1fh 30-31 rw reserved reserved 38 www.national.com table 11. register table register name addr tag bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 basic mode control register 00h bmcr reset loop - back speed selection auto- neg enable power down isolate restart auto- neg duplex mode collision test re - served re - served re - served re - served re - served re - served re - served basic mode status register 01h bmsr 100base -t4 100base -tx fdx 100base -tx hdx 10base- t fdx 10base- t hdx re - served re - served re - served re - served mf pre - amble sup - press auto- neg com - plete remote fault auto- neg ability link status jabber detect extend - ed capa - bility phy identifier register 1 02h phyidr 1 oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb phy identifier register 2 03h phyidr 2 oui lsb oui lsb oui lsb oui lsb oui lsb oui lsb vndr_ mdl vndr_ mdl vndr_ mdl vndr_ mdl vndr_ mdl vndr_ mdl mdl_ rev mdl_ rev mdl_ rev mdl_ rev auto-negotiation advertisement register 04h anar next page ind re - served remote fault re - served asm_di r pause t4 tx_fd tx 10_fd 10 protocol selection protocol selection protocol selection protocol selection protocol selection auto-negotiation link partner ability regis - ter (base page) 05h anlpar next page ind ack remote fault re - served asm_di r pause t4 tx_fd tx 10_fd 10 protocol selection protocol selection protocol selection protocol selection protocol selection auto-negotiation link partner ability regis - ter next page 05h an - lparnp next page ind ack mes - sage page ack2 toggle code code code code code code code code code code code auto-negotiation expansion register 06h aner re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served pdf lp_np_ able np_ able page_ rx lp_an_ able auto-negotiation next page tx register 07h annptr next page ind re - served mes - sage page ack2 tog_tx code code code code code code code code code code code reserved 08-0fh re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served extended registers phy status register 10h physts re - served mdi-x mode rx err latch polarity status false carrier sense signal detect de - scram lock page receive mii inter - rupt remote fault jabber detect auto- neg com - plete loop - back sta - tus duplex status speed status link status mii interrupt control register 11h micr re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served tint inten int_oe mii interrupt status and misc. control reg - ister 12h misr re - served ed_int link_in t spd_in t dup_in t anc_in t fhf_int rhf_in t re - served unmsk_ ed unmsk_ link unmsk_ jab unmsk_ rf unmsk_ anc unmsk_ fhf unmsk_ rhf reserved 13h re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served false carrier sense counter register 14h fcscr re - served re - served re - served re - served re - served re - served re - served re - served fcscnt fcscnt fcscnt fcscnt fcscnt fcscnt fcscnt fcscnt receive error counter register 15h recr re - served re - served re - served re - served re - served re - served re - served re - served rxer - cnt rxer - cnt rxer - cnt rxer - cnt rxer - cnt rxer - cnt rxer - cnt rxer - cnt pcs sub-layer configuration and status register 16h pcsr re - served re - served re - served byp_4b 5b re - served tq_en sd_for ce_pma sd_ option desc_t ime re - served force_ 100_ok re - served re - served nrzi_ bypass scram_ bypass de scram_ bypass 39 www.national.com rmii and bypass register 17h rbr re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served rmii_m ode rmii_re v1_0 rx_ovf _sts rx_unf _sts rx_rd_ ptr[1] rx_rd_ ptr[0] led direct control register 18h ledcr re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served drv_sp dled drv_ln kled drv_ac tled spdled lnkled actled phy control register 19h phycr mdix_e n force_ mdix pause_ rx pause_ tx bist_fe psr_15 bist_ status bist_st art bp_str etch led_ cnfg[1] led_ cnfg[0] phy addr phy addr phy addr phy addr phy addr 10base-t status/control register 1ah 10bt_s erial 10bt_s erial reject 100 base t error range error range squelc h squelc h squelc h loopba ck_10_ dis lp_dis forc_ link_10 re - served polari - ty re - served re - served heart_ dis jabber _dis cd test control and bist extensions reg - ister 1bh cdctrl 1 bist_er ror_c ount bist_er ror_c ount bist_er ror_c ount bist_er ror_c ount bist_er ror_c ount bist_er ror_c ount bist_er ror_c ount bist_er ror_c ount re - served re - served bist_c ont_m ode cdpatte n_10 re - served 10meg_ patt_ga p cdpatt - sel cdpatt - sel reserved 1ch re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served energy detect control register 1dh edcr ed_en ed_aut o_up ed_aut o_dow n ed_man ed_bur st_dis ed_pw r_stat e ed_err _met ed_dat a_met ed_err _count ed_err _count ed_err _count ed_err _count ed_dat a_coun t ed_dat a_coun t ed_dat a_coun t ed_dat a_coun t reserved 1eh-1fh re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served re - served table 11. register table register name addr tag bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bi t 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40 www.national.com dp83848i 7.1 register definition in the register definitions under the ?default? heading, the following definitions hold true: ? rw = r ead w rite access ? sc =register sets on event occurrence and s elf- c lears when event ends ? rw/sc = r ead w rite access/ s elf c learing bit ? ro = r ead o nly access ? cor = c lear on r ead ? ro/cor = r ead o nly, c lear on r ead ? ro/p = r ead o nly, p ermanently set to a default value ? ll = l atched l ow and held until read, based upon the occurrence of the corresponding event ?lh = l atched h igh and held until read, based upon the occurrence of the corresponding event 41 www.national.com dp83848i 7.1.1 basic mode control register (bmcr) table 12. basic mode control register (bmcr), address 0x00 bit bit name default description 15 reset 0, rw/sc reset: 1 = initiate software reset / reset in process. 0 = normal operation. this bit, which is self-clearing, returns a value of one until the reset process is complete. the configuration is re-strapped. 14 loopback 0, rw loopback: 1 = loopback enabled. 0 = normal operation. the loopback function enables mii transmit data to be routed to the mii receive data path. setting this bit may cause the descrambler to lose synchronization and produce a 500 s ?dead time? before any valid data will appear at the mii receive outputs. 13 speed selection strap, rw speed select: when auto-negotiation is disabled writing to this bit allows the port speed to be selected. 1 = 100 mb/s. 0 = 10 mb/s. 12 auto-negotiation enable strap, rw auto-negotiation enable: strap controls initial value at reset. 1 = auto-negotiation enabled - bits 8 and 13 of this register are ig - nored when this bit is set. 0 = auto-negotiation disabled - bits 8 and 13 determine the port speed and duplex mode. 11 power down 0, rw power down: 1 = power down. 0 = normal operation. setting this bit powers down the phy. only the register block is en - abled during a power down condition. this bit is or?d with the input from the pwr_down/int pin. when the active low pwr_down/int pin is asserted, this bit will be set. 10 isolate 0, rw isolate: 1 = isolates the port from the mii with the exception of the serial man - agement. 0 = normal operation. 9 restart auto- negotiation 0, rw/sc restart auto-negotiation: 1 = restart auto-negotiation. re-initiates the auto-negotiation pro - cess. if auto-negotiation is disabled (bit 12 = 0), this bit is ignored. this bit is self-clearing and will return a value of 1 until auto-negotiation is initiated, whereupon it will self-clear. operation of the auto-negotiation process is not affected by the management entity clearing this bit. 0 = normal operation. 8 duplex mode strap, rw duplex mode: when auto-negotiation is disabled writing to this bit allows the port du - plex capability to be selected. 1 = full duplex operation. 0 = half duplex operation. 42 www.national.com dp83848i 7 collision test 0, rw collision test: 1 = collision test enabled. 0 = normal operation. when set, this bit will cause the col signal to be asserted in response to the assertion of tx_en within 512-bit times. the col signal will be de-asserted within 4-bit times in response to the de-assertion of tx_en. 6:0 reserved 0, ro reserved: write ignored, read as 0. table 12. basic mode control register (bmcr), address 0x00 (continued) bit bit name default description 43 www.national.com dp83848i 7.1.2 basic mode status register (bmsr) table 13. basic mode status register (bmsr), address 0x01 bit bit name default description 15 100base-t4 0, ro/p 100base-t4 capable: 0 = device not able to perform 100base-t4 mode. 14 100base-tx full duplex 1, ro/p 100base-tx full duplex capable: 1 = device able to perform 100base-tx in full duplex mode. 13 100base-tx half duplex 1, ro/p 100base-tx half duplex capable: 1 = device able to perform 100base-tx in half duplex mode. 12 10base-t full duplex 1, ro/p 10base-t full duplex capable: 1 = device able to perform 10base-t in full duplex mode. 11 10base-t half duplex 1, ro/p 10base-t half duplex capable: 1 = device able to perform 10base-t in half duplex mode. 10:7 reserved 0, ro reserved: write as 0, read as 0. 6 mf preamble suppression 1, ro/p preamble suppression capable: 1 = device able to perform management transaction with preamble suppressed, 32-bits of preamble needed only once after reset, invalid opcode or invalid turnaround. 0 = normal management operation. 5 auto-negotiation com - plete 0, ro auto-negotiation complete: 1 = auto-negotiation process complete. 0 = auto-negotiation process not complete. 4 remote fault 0, ro/lh remote fault: 1 = remote fault condition detected (cleared on read or by reset). fault criteria: far end fault indication or notification from link part - ner of remote fault. 0 = no remote fault condition detected. 3 auto-negotiation abili - ty 1, ro/p auto negotiation ability: 1 = device is able to perform auto-negotiation. 0 = device is not able to perform auto-negotiation. 2 link status 0, ro/ll link status: 1 = valid link established (for either 10 or 100 mb/s operation). 0 = link not established. the criteria for link validity is implementation specific. the occurrence of a link failure condition will causes the link status bit to clear. once cleared, this bit may only be set by establishing a good link condition and a read via the management interface. 1 jabber detect 0, ro/lh jabber detect: this bit only has meaning in 10 mb/s mode. 1 = jabber condition detected. 0 = no jabber. this bit is implemented with a latching function, such that the occur - rence of a jabber condition causes it to set until it is cleared by a read to this register by the management interface or by a reset. 0 extended capability 1, ro/p extended capability: 1 = extended register capabilities. 0 = basic register set capabilities only. 44 www.national.com dp83848i the phy identifier registers #1 and #2 together form a unique identifier for the dp83848i. the identifier consists of a concatenation of the organizationally unique identifier (oui), the vendor's model number and the model revision num - ber. a phy may return a value of zero in each of the 32 bits of the phy identifier if desired. the phy identifier is intended to support network management. national's ieee assigned oui is 080017h. 7.1.3 phy identifier register #1 (phyidr1) 7.1.4 phy identifier register #2 (phyidr2) 7.1.5 auto-negotiation advertisement register (anar) this register contains the advertised abilities of this device as they will be transmitted to its link partner during auto-nego - tiation. table 14. phy identifier register #1 (phyidr1), address 0x02 bit bit name default description 15:0 oui_msb <0010 0000 0000 0000>, ro/p oui most significant bits : bits 3 to 18 of the oui (080017h) are stored in bits 15 to 0 of this register. the most significant two bits of the oui are ignored (the ieee standard refers to these as bits 1 and 2). table 15. phy identifier register #2 (phyidr2), address 0x03 bit bit name default description 15:10 oui_lsb <0101 11>, ro/p oui least significant bits: bits 19 to 24 of the oui (080017h) are mapped from bits 15 to 10 of this register respectively. 9:4 vndr_mdl <00 1001>, ro/p vendor model number: the six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit 9). 3:0 mdl_rev <0000>, ro/p model revision number: four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant bit to bit 3). this field will be incremented for all major device changes. table 16. negotiation advertisement register (anar), address 0x04 bit bit name default description 15 np 0, rw next page indication: 0 = next page transfer not desired. 1 = next page transfer desired. 14 reserved 0, ro/p reserved by ieee: writes ignored, read as 0. 13 rf 0, rw remote fault: 1 = advertises that this device has detected a remote fault. 0 = no remote fault detected. 12 reserved 0, rw reserved for future ieee use: write as 0, read as 0 45 www.national.com dp83848i 11 asm_dir 0, rw asymmetric pause support for full duplex links: the asm_dir bit indicates that asymmetric pause is supported. encoding and resolution of pause bits is defined in ieee 802.3 annex 28b, tables 28b-2 and 28b-3, respectively. pause resolu - tion status is reported in phycr[13:12]. 1 = advertise that the dte (mac) has implemented both the op - tional mac control sublayer and the pause function as specified in clause 31 and annex 31b of 802.3u. 0= no mac based full duplex flow control. 10 pause 0, rw pause support for full duplex links: the pause bit indicates that the device is capable of providing the symmetric pause functions as defined in annex 31b. encoding and resolution of pause bits is defined in ieee 802.3 annex 28b, tables 28b-2 and 28b-3, respectively. pause resolu - tion status is reported in phycr[13:12]. 1 = advertise that the dte (mac) has implemented both the op - tional mac control sublayer and the pause function as specified in clause 31 and annex 31b of 802.3u. 0= no mac based full duplex flow control. 9 t4 0, ro/p 100base-t4 support: 1= 100base-t4 is supported by the local device. 0 = 100base-t4 not supported. 8 tx_fd strap, rw 100base-tx full duplex support: 1 = 100base-tx full duplex is supported by the local device. 0 = 100base-tx full duplex not supported. 7 tx strap, rw 100base-tx support: 1 = 100base-tx is supported by the local device. 0 = 100base-tx not supported. 6 10_fd strap, rw 10base-t full duplex support: 1 = 10base-t full duplex is supported by the local device. 0 = 10base-t full duplex not supported. 5 10 strap, rw 10base-t support: 1 = 10base-t is supported by the local device. 0 = 10base-t not supported. 4:0 selector <00001>, rw protocol selection bits: these bits contain the binary encoded protocol selector supported by this port. <00001> indicates that this device supports ieee 802.3u. table 16. negotiation advertisement register (anar), address 0x04 (continued) bit bit name default description 46 www.national.com dp83848i 7.1.6 auto-negotiation link partner ability register (anlpar) (base page) this register contains the advertised abilities of the link partner as received during auto-negotiation. the content changes after the successful auto-negotiation if next-pages are supported. table 17. auto-negotiation link partner ability register (anlpar) (base page), address 0x05 bit bit name default description 15 np 0, ro next page indication: 0 = link partner does not desire next page transfer. 1 = link partner desires next page transfer. 14 ack 0, ro acknowledge: 1 = link partner acknowledges reception of the ability data word. 0 = not acknowledged. the auto-negotiation state machine will automatically control the this bit based on the incoming flp bursts. 13 rf 0, ro remote fault: 1 = remote fault indicated by link partner. 0 = no remote fault indicated by link partner. 12 reserved 0, ro reserved for future ieee use: write as 0, read as 0. 11 asm_dir 0, ro asymmetric pause: 1 = asymmetric pause is supported by the link partner. 0 = asymmetric pause is not supported by the link partner. 10 pause 0, ro pause: 1 = pause function is supported by the link partner. 0 = pause function is not supported by the link partner. 9 t4 0, ro 100base-t4 support: 1 = 100base-t4 is supported by the link partner. 0 = 100base-t4 not supported by the link partner. 8 tx_fd 0, ro 100base-tx full duplex support: 1 = 100base-tx full duplex is supported by the link partner. 0 = 100base-tx full duplex not supported by the link partner. 7 tx 0, ro 100base-tx support: 1 = 100base-tx is supported by the link partner. 0 = 100base-tx not supported by the link partner. 6 10_fd 0, ro 10base-t full duplex support: 1 = 10base-t full duplex is supported by the link partner. 0 = 10base-t full duplex not supported by the link partner. 5 10 0, ro 10base-t support: 1 = 10base-t is supported by the link partner. 0 = 10base-t not supported by the link partner. 4:0 selector <0 0000>, ro protocol selection bits: link partner?s binary encoded protocol selector. 47 www.national.com dp83848i 7.1.7 auto-negotiation link partner ability register (anlpar) (next page) 7.1.8 auto-negotiate expansion register (aner) this register contains additional local device and link partner status information. table 18. auto-negotiation link partner ability register (anlpar) (next page), address 0x05 bit bit name default description 15 np 0, ro next page indication: 1 = link partner desires next page transfer. 0 = link partner does not desire next page transfer. 14 ack 0, ro acknowledge: 1 = link partner acknowledges reception of the ability data word. 0 = not acknowledged. the auto-negotiation state machine will automatically control the this bit based on the incoming flp bursts. software should not at - tempt to write to this bit. 13 mp 0, ro message page: 1 = message page. 0 = unformatted page. 12 ack2 0, ro acknowledge 2: 1 = link partner does have the ability to comply to next page mes - sage. 0 = link partner does not have the ability to comply to next page message. 11 toggle 0, ro toggle: 1 = previous value of the transmitted link code word equalled 0. 0 = previous value of the transmitted link code word equalled 1. 10:0 code <000 0000 0000>, ro code: this field represents the code field of the next page transmission. if the mp bit is set (bit 13 of this register), then the code shall be interpreted as a ?message page,? as defined in annex 28c of clause 28. otherwise, the code shall be interpreted as an ?unfor - matted page,? and the interpretation is application specific. table 19. auto-negotiate expansion register (aner), address 0x06 bit bit name default description 15:5 reserved 0, ro reserved: writes ignored, read as 0. 4 pdf 0, ro parallel detection fault: 1 = a fault has been detected via the parallel detection function. 0 = a fault has not been detected. 3 lp_np_able 0, ro link partner next page able: 1 = link partner does support next page. 0 = link partner does not support next page. 2 np_able 1, ro/p next page able: 1 = indicates local device is able to send additional ?next pages?. 1 page_rx 0, ro/cor link code word page received: 1 = link code word has been received, cleared on a read. 0 = link code word has not been received. 48 www.national.com dp83848i 7.1.9 auto-negotiation next page transmit register (annptr) this register contains the next page information sent by this device to its link partner during auto-negotiation. 0 lp_an_able 0, ro link partner auto-negotiation able: 1 = indicates that the link partner supports auto-negotiation. 0 = indicates that the link partner does not support auto-negotia - tion. table 20. auto-negotiation next page transmit register (annptr), address 0x07 bit bit name default description 15 np 0, rw next page indication: 0 = no other next page transfer desired. 1 = another next page desired. 14 reserved 0, ro reserved : writes ignored, read as 0. 13 mp 1, rw message page: 1 = message page. 0 = unformatted page. 12 ack2 0, rw acknowledge2: 1 = will comply with message. 0 = cannot comply with message. acknowledge2 is used by the next page function to indicate that lo - cal device has the ability to comply with the message received. 11 tog_tx 0, ro toggle: 1 = value of toggle bit in previously transmitted link code word was 0. 0 = value of toggle bit in previously transmitted link code word was 1. toggle is used by the arbitration function within auto-negotiation to ensure synchronization with the link partner during next page exchange. this bit shall always take the opposite value of the tog - gle bit in the previously exchanged link code word. 10:0 code <000 0000 0001>, rw this field represents the code field of the next page transmission. if the mp bit is set (bit 13 of this register), then the code shall be interpreted as a "message page?, as defined in annex 28c of ieee 802.3u. otherwise, the code shall be interpreted as an "unformat - ted page?, and the interpretation is application specific. the default value of the code represents a null page as defined in annex 28c of ieee 802.3u. table 19. auto-negotiate expansion register (aner), address 0x06 (continued) bit bit name default description 49 www.national.com dp83848i 7.2 extended registers 7.2.1 phy status register (physts) this register provides a single location within the register set for quick access to commonly accessed information. table 21. phy status register (physts), address 0x10 bit bit name default description 15 reserved 0, ro reserved: write ignored, read as 0. 14 mdi-x mode 0, ro mdi-x mode as reported by the auto-negotiation logic: this bit will be affected by the settings of the mdix_en and force_mdix bits in the phycr register. when mdix is en - abled, but not forced, this bit will update dynamically as the auto-mdix algorithm swaps between mdi and mdi-x configu - rations. 1 = mdi pairs swapped (receive on tptd pair, transmit on tprd pair) 0 = mdi pairs normal (receive on trd pair, transmit on tptd pair) 13 receive error latch 0, ro/lh receive error latch: this bit will be cleared upon a read of the recr register. 1 = receive error event has occurred since last read of rxercnt (address 0x15, page 0). 0 = no receive error event has occurred. 12 polarity status 0, ro polarity status: this bit is a duplication of bit 4 in the 10btscr register. this bit will be cleared upon a read of the 10btscr register, but not upon a read of the physts register. 1 = inverted polarity detected. 0 = correct polarity detected. 11 false carrier sense latch 0, ro/lh false carrier sense latch: this bit will be cleared upon a read of the fcsr register. 1 = false carrier event has occurred since last read of fcscr (ad - dress 0x14). 0 = no false carrier event has occurred. 10 signal detect 0, ro/ll 100base-tx unconditional signal detect from pmd. 9 descrambler lock 0, ro/ll 100base-tx descrambler lock from pmd. 8 page received 0, ro link code word page received: this is a duplicate of the page received bit in the aner register, but this bit will not be cleared upon a read of the physts register. 1 = a new link code word page has been received. cleared on read of the aner (address 0x06, bit 1). 0 = link code word page has not been received. 7 mii interrupt 0, ro mii interrupt pending : 1 = indicates that an internal interrupt is pending. interrupt source can be determined by reading the misr register (0x12h). reading the misr will clear the interrupt. 0= no interrupt pending. 6 remote fault 0, ro remote fault: 1 = remote fault condition detected (cleared on read of bmsr (ad - dress 01h) register or by reset). fault criteria: notification from link partner of remote fault via auto-negotiation. 0 = no remote fault condition detected. 50 www.national.com dp83848i 5 jabber detect 0, ro jabber detect: this bit only has meaning in 10 mb/s mode this bit is a duplicate of the jabber detect bit in the bmsr register, except that it is not cleared upon a read of the physts register. 1 = jabber condition detected. 0 = no jabber. 4 auto-neg complete 0, ro auto-negotiation complete: 1 = auto-negotiation complete. 0 = auto-negotiation not complete. 3 loopback status 0, ro loopback: 1 = loopback enabled. 0 = normal operation. 2 duplex status 0, ro duplex: this bit indicates duplex status and is determined from auto-nego - tiation or forced modes. 1 = full duplex mode. 0 = half duplex mode. note: this bit is only valid if auto-negotiation is enabled and com - plete and there is a valid link or if auto-negotiation is disabled and there is a valid link. 1 speed status 0, ro speed10: this bit indicates the status of the speed and is determined from auto-negotiation or forced modes. 1 = 10 mb/s mode. 0 = 100 mb/s mode. note: this bit is only valid if auto-negotiation is enabled and com - plete and there is a valid link or if auto-negotiation is disabled and there is a valid link. 0 link status 0, ro link status: this bit is a duplicate of the link status bit in the bmsr register, except that it will not be cleared upon a read of the physts regis - ter. 1 = valid link established (for either 10 or 100 mb/s operation) 0 = link not established. table 21. phy status register (physts), address 0x10 (continued) bit bit name default description 51 www.national.com dp83848i 7.2.2 mii interrupt control register (micr) this register implements the mii interrupt phy specific control register. sources for interrupt generation include: energy detect state change, link state change, speed status change, duplex status change, auto-negotiation complete or any of the counters becoming half-full. the individual interrupt events must be enabled by setting bits in the mii inter - rupt status and event control register (misr) . table 22. mii interrupt control register (micr), address 0x11 bit bit name default description 15:3 reserved 0, ro reserved: write ignored, read as 0 2 tint 0, rw test interrupt: forces the phy to generate an interrupt to facilitate interrupt test - ing. interrupts will continue to be generated as long as this bit re - mains set. 1 = generate an interrupt 0 = do not generate interrupt 1 inten 0, rw interrupt enable: enable interrupt dependent on the event enables in the misr reg - ister. 1 = enable event based interrupts 0 = disable event based interrupts 0 int_oe 0, rw interrupt output enable: enable interrupt events to signal via the pwr_down/int pin by configuring the pwr_down/int pin as an output. 1 = pwr_down/int is an interrupt output 0 = pwr_down/int is a power down input 52 www.national.com dp83848i 7.2.3 mii interrupt status and misc. control register (misr) this register contains event status and en ables for the interrupt function. if an ev ent has occurred sin ce the last read of this register, the corresponding status bit will be set. if the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. the micr register controls must also be set to allow interrupts. the status indi - cations in this register will be set even if the interrupt is not enabled table 23. mii interrupt status and misc. control register (misr), address 0x12 15 reserved 0, ro reserved: writes ignored, read as 0 14 ed_int 0, ro/cor energy detect interrupt: 1 = energy detect interrupt is pending and is cleared by the current read. 0 = no energy detect interrupt pending. 13 link_int 0, ro/cor change of link status interrupt: 1 = change of link status interrupt is pending and is cleared by the current read. 0 = no change of link status interrupt pending. 12 spd_int 0, ro/cor change of speed status interrupt: 1 = speed status change interrupt is pending and is cleared by the current read. 0 = no speed status change interrupt pending. 11 dup_int 0, ro/cor change of duplex status interrupt: 1 = duplex status change interrupt is pending and is cleared by the current read. 0 = no duplex status change interrupt pending. 10 anc_int 0, ro/cor auto-negotiation complete interrupt: 1 = auto-negotiation complete interrupt is pending and is cleared by the current read. 0 = no auto-negotiation complete interrupt pending. 9 fhf_int 0, ro/cor false carrier counter half-full interrupt: 1 = false carrier counter half-full interrupt is pending and is cleared by the current read. 0 = no false carrier counter half-full interrupt pending. 8 rhf_int 0, ro/cor receive error counter half-full interrupt: 1 = receive error counter half-full interrupt is pending and is cleared by the current read. 0 = no receive error carrier counter half-full interrupt pending. 7 reserved 0, ro reserved: writes ignored, read as 0 6 ed_int_en 0, rw enable interrupt on energy detect event 5 link_int_en 0, rw enable interrupt on change of link status 4 spd_int_en 0, rw enable interrupt on change of speed status 3 dup_int_en 0, rw enable interrupt on change of duplex status 2 anc_int_en 0, rw enable interrupt on auto-negotiation complete event 1 fhf_int_en 0, rw enable interrupt on false carrier counter register half-full event 0 rhf_int_en 0, rw enable interrupt on receive error counter register half-full event 53 www.national.com dp83848i 7.2.4 false carrier sense counter register (fcscr) this counter provides information required to implement the ?false carriers? attribute within the mau managed object class of clause 30 of the ieee 802.3u specification. 7.2.5 receiver error counter register (recr) this counter provides information required to implement the ?symbol error during carrier? attribute within the phy man - aged object class of clause 30 of the ieee 802.3u specification. table 24. false carrier sense counter register (fcscr), address 0x14 bit bit name default description 15:8 reserved 0, ro reserved: writes ignored, read as 0 7:0 fcscnt[7:0] 0, ro / cor false carrier event counter: this 8-bit counter increments on every false carrier event. this counter sticks when it reaches its max count (ffh). table 25. receiver error counter register (recr), address 0x15 bit bit name default description 15:8 reserved 0, ro reserved: writes ignored, read as 0 7:0 rxercnt[7:0] 0, ro / cor rx_er counter: when a valid carrier is present and there is at least one occurrence of an invalid data symbol, this 8-bit counter increments for each re - ceive error detected. this event can increment only once per valid carrier event. if a collision is present, the attribute will not incre - ment. the counter sticks when it reaches its max count. 54 www.national.com dp83848i 7.2.6 100 mb/s pcs configuration and status register (pcsr) table 26. 100 mb/s pcs configuration and status register (pcsr), address 0x16 bit bit name default description 15:13 reserved <00>, ro reserved: writes ignored, read as 0. 12 reserved 0 reserved: must be zero. 11 reserved 0 reserved: must be zero. 10 tq_en 0, rw 100mbs true quiet mode enable: 1 = transmit true quiet mode. 0 = normal transmit mode. 9 sd force pma 0 ,rw signal detect force pma: 1 = forces signal detection in pma. 0 = normal sd operation. 8 sd_option 1, rw signal detect option: 1 = enhanced signal detect algorithm. 0 = reduced signal detect algorithm. 7 desc_time 0, rw descrambler timeout: increase the descrambler timeout. when set this should allow the device to receive larger packets (>9k bytes) without loss of syn - chronization. 1 = 2ms 0 = 722us (per ansi x3.263: 1995 (tp-pmd) 7.2.3.3e) 6 reserved 0 reserved: must be zero. 5 force_100_ok 0, rw force 100mb/s good link: 1 = forces 100mb/s good link. 0 = normal 100mb/s operation. 4 reserved 0 reserved: must be zero. 3 reserved 0 reserved: must be zero. 2 nrzi_bypass 0, rw nrzi bypass enable: 1 = nrzi bypass enabled. 0 = nrzi bypass disabled. 1 reserved 0 reserved: must be zero. 0 reserved 0 reserved: must be zero. 55 www.national.com dp83848i 7.2.7 rmii and bypass register (rbr) this register configures the rmii mode of operation. when rmii mode is disabled, the rmii functionality is bypassed. 7.2.8 led direct control register (ledcr) this register provides the ability to directly control any or all led outputs. it does not provide read access to leds. table 27. rmii and bypass register (rbr), addresses 0x17 bit bit name default description 15:6 reserved 0, ro reserved : writes ignored, read as 0. 5 rmii_mode strap, rw reduced mii mode: 0 = standard mii mode 1 = reduced mii mode 4 rmii_rev1_0 0, rw reduce mii revision 1.0: 0 = (rmii revision 1.2) crs_dv will toggle at the end of a packet to indicate deassertion of crs. 1 = (rmii revision 1.0) crs_dv will remain asserted until final data is transferred. crs_dv will not toggle at the end of a packet. 3 rx_ovf_sts 0, ro rx fifo over flow status: 0 = normal 1 = overflow detected 2 rx_unf_sts 0, ro rx fifo under flow status: 0 = normal 1 = underflow detected 1:0 elast_buf[1:0] 01, rw receive elasticity buffer. this field controls the receive elastic - ity buffer which allows for frequency variation tolerance between the 50mhz rmii clock and the recovered data. the following val - ues indicate the tolerance in bits for a single packet. the minimum setting allows for standard ethernet frame sizes at +/-50ppm accu - racy for both rmii and receive clocks. for greater frequency tol - erance the packet lengths may be scaled (i.e. for +/-100ppm, the packet lengths need to be divided by 2). 00 = 14 bit tolerance (up to 16800 byte packets) 01 = 2 bit tolerance (up to 2400 byte packets) 10 = 6 bit tolerance (up to 7200 byte packets) 11 = 10 bit tolerance (up to 12000 byte packets) table 28. led direct control register (ledcr), address 0x18 bit bit name default description 15:6 reserved 0, ro reserved : writes ignored, read as 0. 5 drv_spdled 0, rw 1 = drive value of spdled bit onto led_spd output 0 = normal operation 4 drv_lnkled 0, rw 1 = drive value of lnkled bit onto led_lnk output 0 = normal operation 3 drv_actled 0, rw 1 = drive value of actled bit onto led_act/col output 0 = normal operation 2 spdled 0, rw value to force on led_spd output 1 lnkled 0, rw value to force on led_lnk output 0 actled 0, rw value to force on led_act/col output 56 www.national.com dp83848i 7.2.9 phy control register (phycr) table 29. phy control register (phycr), address 0x19 bit bit name default description 15 mdix_en strap, rw auto-mdix enable: 1 = enable auto-neg auto-mdix capability. 0 = disable auto-neg auto-mdix capability. the auto-mdix algorithm requires that the auto-negotiation en - able bit in the bmcr register to be set. if auto-negotiation is not enabled, auto-mdix should be disabled as well. 14 force_mdix 0, rw force mdix: 1 = force mdi pairs to cross. (receive on tptd pair, transmit on tprd pair) 0 = normal operation. 13 pause_rx 0, ro pause receive negotiated: indicates that pause receive should be enabled in the mac. based on anar[11:10] and anlpar[11:10] settings. this function shall be enabled according to ieee 802.3 annex 28b table 28b-3, ?pause resolution?, only if the auto-negotiated high - est common denominator is a full duplex technology. 12 pause_tx 0, ro pause transmit negotiated: indicates that pause transmit should be enabled in the mac. based on anar[11:10] and anlpar[11:10] settings. this function shall be enabled according to ieee 802.3 annex 28b table 28b-3, ?pause resolution?, only if the auto-negotiated high - est common denominator is a full duplex technology. 11 bist_fe 0, rw/sc bist force error: 1 = force bist error. 0 = normal operation. this bit forces a single error, and is self clearing. 10 psr_15 0, rw bist sequence select: 1 = psr15 selected. 0 = psr9 selected. 9 bist_status 0, ll/ro bist test status: 1 = bist pass. 0 = bist fail. latched, cleared when bist is stopped. for a count number of bist errors, see the bist error count in the cdctrl1 register. 8 bist_start 0, rw bist start: 1 = bist start. 0 = bist stop. 7 bp_stretch 0, rw bypass led stretching: this will bypass the led stretching and the leds will reflect the in - ternal value. 1 = bypass led stretching. 0 = normal operation. 57 www.national.com dp83848i 7.2.10 10base-t status/control register (10btscr) 6 5 led_cnfg[1] led_cnfg[0] 0, rw strap, rw leds configuration led_cnfg[1] led_ cnfg[0] mode description don?t care 1 mode 1 0 0 mode 2 10mode 3 in mode 1 , leds are configured as follows: led_link = on for good link, off for no link led_speed = on in 100 mb/s, off in 10 mb/s led_act/col = on for activity, off for no activity in mode 2 , leds are configured as follows: led_link = on for good link, blink for activity led_speed = on in 100 mb/s, off in 10 mb/s led_act/col = on for collision, off for no collision full duplex, off for half duplex in mode 3 , leds are configured as follows: led_link = on for good link, blink for activity led_speed = on in 100 mb/s, off in 10 mb/s led_act/col = on for full duplex, off for half duplex 4:0 phyaddr[4:0] strap, rw phy address: phy address for port. table 30. 10base-t status/control register (10btscr), address 0x1a bit bit name default description 15 10bt_serial strap, rw 10base-t serial mode (sni) 1 = enables 10base-t serial mode 0 = normal operation places 10 mb/s transmit and receive functions in serial network interface (sni) mode of operation. has no effect on 100 mb/s operation. 14:12 reserved 0, rw reserved: must be zero. 11:9 squelch 100, rw squelch configuration: used to set the squelch ?on? threshold for the receiver. default squelch on is 330mv peak. 8 loopback_10_d is 0, rw in half-duplex mode, default 10base-t operation loops transmit data to the receive data in addition to transmitting the data on the physical medium. this is for consistency with earlier 10base2 and 10base5 implementations which used a shared medium. setting this bit disables the loopback function. this bit does not affect loopback due to setting bmcr[14]. table 29. phy control register (phycr), address 0x19 (continued) bit bit name default description 58 www.national.com dp83848i 7 lp_dis 0, rw normal link pulse disable : 1 = transmission of nlps is disabled. 0 = transmission of nlps is enabled. 6 force_link_10 0, rw force 10mb good link: 1 = forced good 10mb link. 0 = normal link status. 5 reserved 0, rw reserved: must be zero. 4 polarity ro/lh 10mb polarity status: this bit is a duplication of bit 12 in the physts register. both bits will be cleared upon a read of 10btscr register, but not upon a read of the physts register. 1 = inverted polarity detected. 0 = correct polarity detected. 3 reserved 0, rw reserved: must be zero. 2 reserved 1, rw reserved: must be set to one. 1 heartbeat_dis 0, rw heartbeat disable: this bit only has influence in half-duplex 10mb mode. 1 = heartbeat function disabled. 0 = heartbeat function enabled. when the device is operating at 100mb or configured for full duplex operation, this bit will be ignored - the heartbeat func - tion is disabled. 0 jabber_dis 0, rw jabber disable: applicable only in 10base-t. 1 = jabber function disabled. 0 = jabber function enabled. table 30. 10base-t status/control register (10btscr), address 0x1a bit bit name default description 59 www.national.com dp83848i 7.2.11 cd test and bist extensions register (cdctrl1) table 31. cd test and bist extensions register (cdctrl1), address 0x1b bit bit name default description 15:8 bist_error_co unt 0, ro bist error counter: counts number of errored data nibbles during packet bist. this value will reset when packet bist is restarted. the counter sticks when it reaches its max count. 7:6 reserved 0, rw reserved: must be zero. 5 bist_cont_mod e 0, rw packet bist continuous mode: allows continuous pseudo random data transmission without any break in transmission. this can be used for transmit vod testing. this is used in conjunction with the bist controls in the phycr register (0x19h). for 10mb operation, jabber function must be dis - abled, bit 0 of the 10btscr (0x1ah), jabber_dis = 1. 4 cdpatten_10 0, rw cd pattern enable for 10mb: 1 = enabled. 0 = disabled. 3 reserved 0, rw reserved: must be zero. 2 10meg_patt_ga p 0, rw defines gap between data or nlp test sequences: 1 = 15 s. 0 = 10 s. 1:0 cdpattsel[1:0] 00, rw cd pattern select[1:0]: if cdpatten_10 = 1: 00 = data, eop0 sequence 01 = data, eop1 sequence 10 = nlps 11 = constant manchester 1s (10mhz sine wave) for harmonic dis - tortion testing. 60 www.national.com dp83848i 7.2.12 energy detect control (edcr) table 32. energy detect control (edcr), address 0x1d bit bit name default description 15 ed_en 0, rw energy detect enable: allow energy detect mode. when energy detect is enabled and auto-negotiation is disabled via the bmcr register, auto-mdix should be disabled via the phy - cr register. 14 ed_auto_up 1, rw energy detect automatic power up: automatically begin power up sequence when energy detect data threshold value (edcr[3:0]) is reached. alternatively, device could be powered up manually using the ed_man bit (ecdr[12]). 13 ed_auto_down 1, rw energy detect automatic power down: automatically begin power down sequence when no energy is de - tected. alternatively, device could be powered down using the ed_man bit (edcr[12]). 12 ed_man 0, rw/sc energy detect manual power up/down: begin power up/down sequence when this bit is asserted. when set, the energy detect algorithm will initiate a change of energy de - tect state regardless of threshold (error or data) and timer values. in managed applications, this bit can be set after clearing the ener - gy detect interrupt to control the timing of changing the power state. 11 ed_burst_dis 0, rw energy detect bust disable: disable bursting of energy detect data pulses. by default, energy detect (ed) transmits a burst of 4 ed data pulses each time the cd is powered up. when bursting is disabled, only a single ed data pulse will be send each time the cd is powered up. 10 ed_pwr_state 0, ro energy detect power state: indicates current energy detect power state. when set, energy detect is in the powered up state. when cleared, energy detect is in the powered down state. this bit is invalid when energy detect is not enabled. 9 ed_err_met 0, ro/cor energy detect error threshold met: no action is automatically taken upon receipt of error events. this bit is informational only and would be cleared on a read. 8 ed_data_met 0, ro/cor energy detect data threshold met: the number of data events that occurred met or surpassed the en - ergy detect data threshold. this bit is cleared on a read. 7:4 ed_err_count 0001, rw energy detect error threshold: threshold to determine the number of energy detect error events that should cause the device to take action. intended to allow aver - aging of noise that may be on the line. counter will reset after ap - proximately 2 seconds without any energy detect data events. 3:0 ed_data_count 0001, rw energy detect data threshold: threshold to determine the number of energy detect events that should cause the device to take actions. intended to allow averag - ing of noise that may be on the line. counter will reset after approx - imately 2 seconds without any energy detect data events. 61 www.national.com dp83848i 8.0 electrical specifications note: all parameters are guaranteed by test, statistical analysis or design. absolute maximum ratings recommended operating conditions absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. they are not meant to imply that the device should be operated at these limits. 8.1 dc specs supply voltage (v cc ) -0.5 v to 4.2 v dc input voltage (v in ) -0.5v to v cc + 0.5v dc output voltage (v out ) -0.5v to v cc + 0.5v storage temperature (t stg ) -65 o c to 150c max case temp for t a = 85c 107 c max. die temperature (tj) 150 c lead temp. (tl) (soldering, 10 sec.) 260 c esd rating (r zap = 1.5k, c zap = 100 pf) 4.0 kv supply voltage (v cc ) 3.3 volts + .3v industrial - ambient temperature (t a ) -40 to 85 c power dissipation (p d ) 267 mw thermal characteristic max units theta junction to case (t jc ) 28.7 c / w theta junction to ambient (t ja ) degrees celsius/watt - no airflow @ 1.0w note: this is done with a jedec (2 layer 2 oz cu.) thermal test board 83.6 c / w symbol pin types parameter conditions min typ max units v ih i i/o input high voltage nominal v cc 2.0 v v il i i/o input low voltage 0.8 v i ih i i/o input high current v in = v cc 10 a i il i i/o input low current v in = gnd 10 a v ol o, i/o output low voltage i ol = 4 ma 0.4 v v oh o, i/o output high voltage i oh = -4 ma vcc - 0.5 v i oz i/o, o tri-state leakage v out = v cc + 10 a v tptd_100 pmd output pair 100m transmit voltage 0.95 1 1.05 v v tptdsym pmd output pair 100m transmit voltage symmetry + 2 % v tptd_10 pmd output pair 10m transmit voltage 2.2 2.5 2.8 v c in1 i cmos input capacitance 5 pf c out1 o cmos output capacitance 5 pf 62 www.national.com 8.1 dc specs (continued) dp83848i sd thon pmd input pair 100base-tx signal detect turn- on threshold 1000 mv diff pk-pk sd thoff pmd input pair 100base-tx signal detect turn- off threshold 200 mv diff pk-pk v th1 pmd input pair 10base-t re - ceive threshold 585 mv i dd100 supply 100base-tx (full duplex) 81 ma i dd10 supply 10base-t (full duplex) 92 ma i dd supply power down mode 14 ma symbol pin types parameter conditions min typ max units 63 www.national.com dp83848i 8.2 ac specs 8.2.1 power up timing parameter description notes min typ max units t2.1.1 post power up stabilization time prior to mdc preamble for register accesses mdio is pulled high for 32-bit serial man - agement initialization x1 clock must be stable for a min. of 167ms at power up. 167 ms t2.1.2 hardware configuration latch- in time from power up hardware configuration pins are de - scribed in the pin description section x1 clock must be stable for a min. of 167ms at power up. 167 ms t2.1.3 hardware configuration pins transition to output drivers 50 ns vcc hardware reset_n mdc 32 clocks latch-in of hardware configuration pins dual function pins become enabled as outputs input output t2.1.3 t2.1.2 t2.1.1 x1 clock 64 www.national.com dp83848i 8.2.2 reset timing note: it is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide fast rc time constants in order to latch-in the proper value prior to the pin transitioning to an output driver. parameter description notes min typ max units t2.2.1 post reset stabilization time prior to mdc preamble for reg - ister accesses mdio is pulled high for 32-bit serial man - agement initialization 3 s t2.2.2 hardware configuration latch- in time from the deassertion of reset (either soft or hard) hardware configuration pins are de - scribed in the pin description section 3 s t2.2.3 hardware configuration pins transition to output drivers 50 ns t2.2.4 reset pulse width x1 clock must be stable for at min. of 1us during reset pulse low time. 1 s vcc hardware reset_n mdc 32 clocks latch-in of hardware configuration pins dual function pins become enabled as outputs input output t2.2.3 t2.2.2 t2.2.1 x1 clock t2.2.4 65 www.national.com dp83848i 8.2.3 mii serial management timing 8.2.4 100 mb/s mii transmit timing parameter description notes min typ max units t2.3.1 mdc to mdio (output) delay time 0 30 ns t2.3.2 mdio (input) to mdc setup time 10 ns t2.3.3 mdio (input) to mdc hold time 10 ns t2.3.4 mdc frequency 2.5 25 mhz parameter description notes min typ max units t2.4.1 tx_clk high/low time 100 mb/s normal mode 16 20 24 ns t2.4.2 txd[3:0], tx_en data setup to tx_clk 100 mb/s normal mode 10 ns t2.4.3 txd[3:0], tx_en data hold from tx_clk 100 mb/s normal mode 0 ns mdc mdc mdio (output) mdio (input) valid data t2.3.1 t2.3.2 t2.3.3 t2.3.4 tx_clk txd[3:0] tx_en valid data t2.4.2 t2.4.3 t2.4.1 t2.4.1 66 www.national.com dp83848i 8.2.5 100 mb/s mii receive timing note: rx_clk may be held low or high for a longer period of time during transition between reference and recovered clocks. minimum high and low times will not be violated. 8.2.6 100base-tx transmit packet latency timing note: for normal mode, latency is determined by measuring the time from the first rising edge of tx_clk occurring after the assertion of tx_en to the first bit of the ?j? code group as output from the pmd output pair. 1 bit time = 10 ns in 100 mb/s mode. parameter description notes min typ max units t2.5.1 rx_clk high/low time 100 mb/s normal mode 16 20 24 ns t2.5.2 rx_clk to rxd[3:0], rx_dv, rx_er delay 100 mb/s normal mode 10 30 ns parameter description notes min typ max units t2.6.1 tx_clk to pmd output pair latency 100 mb/s normal mode 6 bits rx_clk rxd[3:0] rx_dv t2.5.2 t2.5.1 t2.5.1 valid data rx_er tx_clk tx_en txd pmd output pair (j/k) idle data t2.6.1 67 www.national.com dp83848i 8.2.7 100base-tx transmit packet deassertion timing note: deassertion is determined by measuring the time from the first rising edge of tx_clk occurring after the deasser - tion of tx_en to the first bit of the ?t? code group as output from the pmd output pair. 1 bit time = 10 ns in 100 mb/s mode. parameter description notes min typ max units t2.7.1 tx_clk to pmd output pair deassertion 100 mb/s normal mode 6 bits tx_clk txd tx_en pmd output pair (t/r) data idle t2.7.1 (t/r) data idle 68 www.national.com dp83848i 8.2.8 100base-tx transmit timing (t r/f & jitter) note: normal mismatch is the difference between the maximum and minimum of all rise and fall times note: rise and fall times taken at 10% and 90% of the +1 or -1 amplitude parameter description notes min typ max units t2.8.1 100 mb/s pmd output pair t r and t f 3 4 5 ns 100 mb/s t r and t f mismatch 500 ps t2.8.2 100 mb/s pmd output pair transmit jitter 1.4 ns pmd output pair t2.8.1 t2.8.1 t2.8.1 t2.8.1 +1 rise +1 fall -1 fall -1 rise eye pattern t2.8.2 t2.8.2 90% 10% 10% 90% pmd output pair 69 www.national.com dp83848i 8.2.9 100base-tx receive packet latency timing note: carrier sense on delay is determined by measuring the time from the first bit of the ?j? code group to the assertion of carrier sense. note: 1 bit time = 10 ns in 100 mb/s mode note: pmd input pair voltage amplitude is greater than the signal detect turn-on threshold value. 8.2.10 100base-tx receive packet deassertion timing note: carrier sense off delay is determined by measuring the time from the first bit of the ?t? code group to the deasser - tion of carrier sense. note: 1 bit time = 10 ns in 100 mb/s mode parameter description notes min typ max units t2.9.1 carrier sense on delay 100 mb/s normal mode 20 bits t2.9.2 receive data latency 100 mb/s normal mode 24 bits parameter description notes min typ max units t2.10.1 carrier sense off delay 100 mb/s normal mode 24 bits crs rxd[3:0] pmd input pair rx_dv rx_er idle data t2.9.1 t2.9.2 (j/k) crs t2.10.1 pmd input pair data idle (t/r) 70 www.national.com dp83848i 8.2.11 10 mb/s mii transmit timing note: an attached mac should drive the transmit signals using the positive edge of tx_clk. as shown above, the mii signals are sampled on the falling edge of tx_clk. 8.2.12 10 mb/s mii receive timing note: rx_clk may be held low for a longer period of time during transition between reference and recovered clocks. minimum high and low times will not be violated. parameter description notes min typ max units t2.11.1 tx_clk high/low time 10 mb/s mii mode 190 200 210 ns t2.11.2 txd[3:0], tx_en data setup to tx_clk fall 10 mb/s mii mode 25 ns t2.11.3 txd[3:0], tx_en data hold from tx_clk rise 10 mb/s mii mode 0 ns parameter description notes min typ max units t2.12.1 rx_clk high/low time 160 200 240 ns t2.12.2 rx_clk to rxd[3:0], rx_dv delay 10 mb/s mii mode 100 ns t2.12.3 rx_clk rising edge delay from rxd[3:0], rx_dv valid 10 mb/s mii mode 100 ns tx_clk txd[3:0] tx_en valid data t2.11.2 t2.11.3 t2.11.1 t2.11.1 rx_clk rxd[3:0] rx_dv t2.12.2 t2.12.1 t2.12.1 t2.12.3 valid data 71 www.national.com dp83848i 8.2.13 10 mb/s serial mode transmit timing 8.2.14 10 mb/s serial mode receive timing note: rx_clk may be held high for a longer period of time during transition between reference and recovered clocks. minimum high and low times will not be violated. parameter description notes min typ max units t2.13.1 tx_clk high time 10 mb/s serial mode 20 25 30 ns t2.13.2 tx_clk low time 10 mb/s serial mode 70 75 80 ns t2.13.3 txd_0, tx_en data setup to tx_clk rise 10 mb/s serial mode 25 ns t2.13.4 txd_0, tx_en data hold from tx_clk rise 10 mb/s serial mode 0 ns parameter description notes min typ max units t2.14.1 rx_clk high/low time 35 50 65 ns t2.14.2 rx_clk fall to rxd_0, rx_dv delay 10 mb/s serial mode -10 10 ns tx_clk txd[0] tx_en valid data t2.13.3 t2.13.4 t2.13.1 t2.13.2 rx_clk rxd[0] rx_dv t2.14.2 t2.14.1 t2.14.1 valid data 72 www.national.com dp83848i 8.2.15 10base-t transmit timing (start of packet) note: 1 bit time = 100 ns in 10mb/s. 8.2.16 10base-t transmit timing (end of packet) parameter description notes min typ max units t2.15.1 transmit output delay from the falling edge of tx_clk 10 mb/s mii mode 3.5 bits t2.15.2 transmit output delay from the rising edge of tx_clk 10 mb/s serial mode 3.5 bits parameter description notes min typ max units t2.16.1 end of packet high time (with ?0? ending bit) 250 300 ns t2.16.2 end of packet high time (with ?1? ending bit) 250 300 ns tx_clk tx_en txd pmd output pair t2.15.1 t2.15.2 tx_clk tx_en pmd output pair 00 11 pmd output pair t2.16.1 t2.16.2 73 www.national.com dp83848i 8.2.17 10base-t receive timing (start of packet) note: 10base-t rx_dv latency is measured from first bit of preamble on the wire to the assertion of rx_dv note: 1 bit time = 100 ns in 10 mb/s mode. 8.2.18 10base-t receive timing (end of packet) parameter description notes min typ max units t2.17.1 carrier sense turn on delay (pmd input pair to crs) 630 1000 ns t2.17.2 rx_dv latency 10 bits t2.17.3 receive data latency measurement shown from sfd 8 bits parameter description notes min typ max units t2.18.1 carrier sense turn off delay 1.0 s tprd crs rx_clk rx_dv 1st sfd bit decoded rxd[3:0] t2.17.1 t2.17.2 t2.17.3 101010 101011 preamble sfd data 0000 1 0 1 pmd input pair rx_clk crs idle t2.18.1 74 www.national.com dp83848i 8.2.19 10 mb/s heartbeat timing 8.2.20 10 mb/s jabber timing parameter description notes min typ max units t2.19.1 cd heartbeat delay all 10 mb/s modes 1200 ns t2.19.2 cd heartbeat duration all 10 mb/s modes 1000 ns parameter description notes min typ max units t2.20.1 jabber activation time 85 ms t2.20.2 jabber deactivation time 500 ms tx_clk tx_en col t2.19.1 t2.19.2 txe pmd output pair col t2.20.2 t2.20.1 75 www.national.com dp83848i 8.2.21 10base-t normal link pulse timing note: these specifications represent transmit timings. 8.2.22 auto-negotiation fast link pulse (flp) timing note: these specifications represent transmit timings. parameter description notes min typ max units t2.21.1 pulse width 100 ns t2.21.2 pulse period 16 ms parameter description notes min typ max units t2.22.1 clock, data pulse width 100 ns t2.22.2 clock pulse to clock pulse period 125 s t2.22.3 clock pulse to data pulse period data = 1 62 s t2.22.4 burst width 2 ms t2.22.5 flp burst to flp burst period 16 ms t2.21.2 t2.21.1 normal link pulse(s) clock pulse data pulse clock pulse flp burst flp burst fast link pulse(s) t2.22.1 t2.22.1 t2.22.2 t2.22.3 t2.22.4 t2.22.5 76 www.national.com dp83848i 8.2.23 100base-tx signal detect timing note: the signal amplitude on pmd input pair must be tp-pmd compliant. 8.2.24 100 mb/s internal loopback timing note1: due to the nature of the descrambler function, all 100base-tx loopback modes will cause an initial ?dead-time? of up to 550 s during which time no data will be present at the receive mii outputs. the 100base-tx timing specified is based on device delays after the initial 550 s ?dead-time?. note2: measurement is made from the first rising edge of tx_clk after assertion of tx_en. parameter description notes min typ max units t2.23.1 sd internal turn-on time 1 ms t2.23.2 sd internal turn-off time 350 s parameter description notes min typ max units t2.24.1 tx_en to rx_dv loopback 100 mb/s internal loopback mode 240 ns t2.23.1 sd+ internal t2.23.2 pmd input pair tx_clk tx_en txd[3:0] crs rx_clk rxd[3:0] rx_dv t2.24.1 77 www.national.com dp83848i 8.2.25 10 mb/s internal loopback timing note: measurement is made from the first rising edge of tx_clk after assertion of tx_en. parameter description notes min typ max units t2.25.1 tx_en to rx_dv loopback 10 mb/s internal loopback mode 2 s tx_clk tx_en txd[3:0] crs rx_clk rxd[3:0] rx_dv t2.25.1 78 www.national.com dp83848i 8.2.26 rmii transmit timing parameter description notes min typ max units t2.26.1 x1 clock period 50 mhz reference clock 20 ns t2.26.2 txd[1:0], tx_en, data setup to x1 rising 4 ns t2.26.3 txd[1:0], tx_en, data hold from x1 rising 2 ns t2.26.4 x1 clock to pmd output pair latency from x1 rising edge to first bit of symbol 17 bits x1 txd[1:0] tx_en valid data t2.26.2 t2.26.3 t2.26.1 pmd output pair symbol t2.26.4 79 www.national.com dp83848i 8.2.27 rmii receive timing note: per the rmii specification, output delays assume a 25pf load. note: crs_dv is asserted asynchronously in order to minimize latency of control signals through the why. crs_dv may toggle synchronously at the end of the packet to indicate crs deassertion. note: rx_dv is synchronous to x1. while not part of the rmii specification, this signal is provided to simplify recovery of receive data. parameter description notes min typ max units t2.27.1 x1 clock period 50 mhz reference clock 20 ns t2.27.2 rxd[1:0], crs_dv, rx_dv and rx_er output delay from x1 rising 2 14 ns t2.27.3 crs on delay from jk symbol on pmd receive pair to initial assertion of crs_dv 18.5 bits t2.27.4 crs off delay from tr symbol on pmd receive pair to initial deassertion of crs_dv 27 bits t2.27.5 rxd[1:0] and rx_er latency from symbol on receive pair. elasticity buffer set to default value (01) 38 bits crs_dv x1 rxd[1:0] rx_er t2.27.2 t2.27.1 t2.27.2 pmd input pair idle data (j/k) t2.27.3 t2.27.5 data (tr) t2.27.4 rx_dv t2.27.2 t2.27.2 80 www.national.com dp83848i 8.2.28 isolation timing 8.2.29 25 mhz_out timing note: 25 mhz_out characteristics are dependent upon the x1 input characteristics. parameter description notes min typ max units t2.28.1 from software clear of bit 10 in the bmcr register to the transi - tion from isolate to normal mode 100 s t2.28.2 from deassertion of s/w or h/w reset to transition from isolate to normal mode 500 s parameter description notes min typ max units t2.29.1 25 mhz_out high/low time mii mode 20 ns rmii mode 10 ns t2.29.2 25 mhz_out propagation delay relative to x1 8 ns clear bit 10 of bmcr (return to normal operation from isolate mode) h/w or s/w reset (with phyad = 00000) mode isolate normal t2.28.2 t2.28.1 x1 t2.29.2 25 mhz_out t2.29.1 t2.29.1 81 www.national.com dp83848i notes: inches (millimeters) unless otherwise noted dp83848i phyter ? ? industrial temperature singl e port 10/100 mb/s ethernet physical layer transceiver national does not assume any re sponsibility for us e of any circuitry described, no circuit patent licenses are implied and nati onal reserves the right at any time without notice to change said circuitry and specifications. life support policy national?s products are not authorized for use as critical components in life support devices or systems without the express writte n approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any co mponent of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to af- fect its safety or effectiveness. national semiconductor corporation tel: 1-800-272-9959 fax: 1-800-737-7018 email: support@nsc.com national semiconductor europe fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 francais tel: +33 (0) 1 41 91 8790 national semiconductor japan ltd. tel: 81-3-5639-7560 fax: 81-3-5639-7507 www.national.com national semiconductor asia pacific customer response group tel: 65-254-4466 fax: 65-250-4466 email: ap.support@nsc.com banned substance compliance national semiconductor certifies that the products and packing materi als meet the provisions of t he customer products stewardsh ip specification (csp-9-111c2) and t he banned substances and materials of interest sp ecification (csp-9-111s2) and contain no ?ban ned substances? as defined in csp-9-111s2. leadfree products are rohs compliant. 9.0 physical dimensions lead quad frame package (lqfp) ns package number vbh48a |
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