caesar clock generator w198 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07312 rev. ** revised february 13, 2002 features ? three clock outputs less than 250 ps cycle-to-cycle jitter supports 3.3v to 5v operation ttl compatible logic: v il = 0.8v max., v ih = 2 . 0 v m i n . , v ol = 0.4v max. and v oh = 2.4v min. oe pin has internal pull-up resistor 45/55% duty cycle on all outputs 40 ? output drivers accepts 20mhz input reference built-in crystal oscillator circuit. the load presented to the crystal is 12pf. available in 16-pin ssop (shrink small outline package) general description the w198 is designed to meet the needs of hps ? caesar ? dat data storage system. given a single crystal input frequency of 20 mhz, two plls are utilized to deliver all the required fre- quencies. a frequency decoder is utilized to select required outputs table 1. frequency selection fs2 fs1 fs0 cicero julius galactic x 0 0 108 mhz x0190 mhz x1054 mhz x110 mhz 0xx 60 mhz 1 x x 2.857 mhz xxx 20 mhz block diagram pin configuration xtal osc x1 x2 pll 1 cicero julius pll 2 fs0 fs1 oe fs2 galactic vdd fs0 fs1 fs2 galactic vdd gnd julius 16 15 14 13 12 11 10 9 x1 x2 gnd vdd cicero gnd oe vdd 1 2 3 4 5 6 7 8
w198 document #: 38-07312 rev. ** page 2 of 6 note: 1. all inputs, except x1 or x2, have an internal pull-up resistor. unconnected inputs will assume a logic high condition. pin definitions [1] pin name pin no. pin type pin description oe 7 i output enable: when low, this input signal puts all outputs into a high-imped- ance state. cicero 5 o clock output: refer to table 1 for frequency selection. output voltage swing is set by vdd julius 9 o clock output: refer to table 1 for frequency selection. output voltage swing is set by vdd galactic 12 o clock output: refer to table 1 for frequency selection. output voltage swing is set by vdd. fs0:1 15,14 i frequency selection inputs 0 and 1: the fs0 (lsb) and fs1 (msb) input sig- nals are used to select the cicero frequencies output. (see table 1 for frequency reference) fs2 13 i frequency selection input 2: the fs2 input signal is used to select the julius frequency output. (see table 1 for frequency reference) x1 1 i external crystal input: this pin has dual functions. it can be used as an external 20-mhz crystal connection or as an external reference frequency input. x2 2 i external crystal output: an input connection for an external 20-mhz crystal. if using an external reference, this pin must be left unconnected. vdd 4,8,11,16 p power supply connections : connect all vdd pins to the same voltage, either 3.3v or 5.0v. each vdd pin should have a decoupling capacitor (such as 0.1 f) placed as close to the pin as possible.
w198 document #: 38-07312 rev. ** page 3 of 6 power supply connections the recommended single voltage power supply configuration for the w198 is shown schematically in figure 1 . these rec- ommendations should be followed to both ensure adequate device performance and to control emi. the major consider- ations can be summarized as follows: 1. decoupling capacitor ? a 0.1- f decoupling capacitor should be used for each vdd pin to minimize crosstalk be- tween output frequencies. the trace to the vdd pin and to the ground via should be as short as possible. 2. ferrite bead (fb) ? a common supply connection should be used for all w198 vdd pins. a ferrite bead should be used on this common supply as shown to remove high fre- quency system noise. 3. 22- f supply filter capacitor ? the 22- f capacitor filters low-frequency supply noise that may produce clock output jitter. depending on the particular application, this capacitor may not be required; its use should be considered optional. mounting pads should be implemented in pcb layout. use of this capacitor in production should be determined upon prototype evaluation. 4. pcb power supply traces should be at least 20 mils wide to assure adequate trade impedance. ground connections all ground connections should be made to the main system ground plane. these connections should be as short as pos- sible. no cuts should be made in the ground plane around the clock device since this can increase system emi and reduce clock performance. clock output lines 1. the clock line width should be set to provide a 60 ? trace impedance. this width will vary depending on the pcb ma- terial; the pcb supplier can suggest what width to use for a 60 ? clock line. in general, an 8-mil trace will provide a 60 ? impedance on a multi-level board. 2. the series termination resistor (sometimes called ? damping resistor ? ) must be placed in series with the clock line as close to the clock output as possible (within one inch). 3. assume an output resistance from the w198 of 40 ? , choose series resistors appropriate to the number of driven traces. figure 1. test circuit vdd fs0 fs1 fs2 galactic gnd julius 16 15 14 13 12 11 10 9 x1 x2 gnd vdd cicero gnd oe vdd 1 2 3 4 5 6 7 8 0.1 f 0.1 f 0.1 f 0.1 f 22 f c1 fb system vdd w198 vdd
w198 document #: 38-07312 rev. ** page 4 of 6 absolute maximum ratings stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t b ambient temperature under bias ? 55 to +125 c t a operating temperature 0 to +70 c dc electrical characteristics: t a = 0 c to +70 c, v dd = 3.3v5% or 5.0v10% parameter description test condition min. typ. max. unit i dd supply current note: cicero clk outputs = 108 mhz output loaded 50 ma v il input low voltage v cc = 5.0v 0.8 v v ih input high voltage v cc = 5.0v 2.0 v v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ? 1 ma 3.1 v i il input low current 10 a i ih input high current 10 a r p input pull-up resistor v in = 0v 500 k ? c i input capacitance except x1 and x2 6 pf l i input inductance except x1 and x2 7 nh c l xtal load capacitance total load to crystal 12 pf ac electrical characteristics: t a = 0 c to +70 c, v cc = 3.3v5% or 5.0v10% [2] parameter description test condition min. typ. max. unit clock outputs t jc output clock jitter, cycle-to-cycle 175 250 ps z o output buffer impedance 40.0 ? d t output duty cycle 45.0 50.0 55.0 % t r rise time between 0.4v and 2.4v 0.6 1.0 1.5 ns t f fall time between 2.4v and 0.4v 0.6 1.0 1.5 ns t pu stabilization time from power-up to within 0.1% of final frequency 1.5 3.0 ms freq_tt frequency transition time pin 9 (julius) pin 5 (cicero) 0.342 0.362 0.36 0.381 0.378 0.40 mhz/s f a long term output frequency stability [3] over v dd and t a range 0.01 % notes: 2. all ac tests are performed using the circuit shown in figure 1 to simulate typical system load conditions. measurements are taken at the load. threshold voltage for timing measurements is 1.5v. 3. consideration of reference crystal shift only. ordering information ordering code package name package type w198 h 16-pin soic (209 mil)
w198 document #: 38-07312 rev. ** page 5 of 6 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 16-pin shrink small outline package (ssop, 209 mils)
w198 document #: 38-07312 rev. ** page 6 of 6 document title: w198 caesar clock generator document number: 38-07312 rev. ecn no. issue date orig. of change description of change ** 111391 02/25/02 ika convert from icw format to cypress format new data sheet
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