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ca20c03a des encryption processor tundra semiconductor corporation 3-1 warning : these devices cannot be shipped outside north america without written authorization from canadian external affairs and depa rtment of national defence or the us state department and department of defence. table 3-1 : ca20c03a transfer rates product code data transfer rates - ecb mode (mbytes per second) system clock ca20c03a-5 0.77 5 mhz ca20c03a-10 1.54 10 mhz ca20c03a-16 2.46 16 mhz ca20c03a-20 3.08 20 mhz ca20c03a-25 3.85 25 mhz the ca20c03a is an improved version of the des encryption processor designed by tundra semiconductor corporation. data transfer rates up to 3.85 mbytes per second encrypt and decrypt using data encryption standard (des) adopted by the u.s. department of commerce, national bureau of standards (nbs) - publication fips pub 46 (1-15-1977) validated by the national institute for standards and technology (nist) in accordance with the procedures speci?d in nbs publication 500-20 electronic code book (ecb) and cipher block chaining (cbc) encrypt and decrypt 64-bit data words using 56- bit key words parity check on key word loading key stored in device is not externally accessible standard 8-bit microprocessor interface battery back-up capability of internal key register low power cmos with ttl i/o compatibility available in plcc, pdip, and tqfp packages the tundra semiconductor corporation ca20c03a des encryption processor is designed to encrypt and decrypt 64- bit blocks of data using the algorithm speci?d in the federal information processing data encryption standard - publication fips pub 46 (1-15-1977). des is the standard data encryption algorithm used for ?e and communications encryption, and as such is widely established in the security, ?ance and banking industries. the ca20c03a encrypt 64- bit clear text words using 56-bit, user-speci?d keys to produce 64-bit cipher text words. when reversed, the cipher text words are decrypted to produce the original clear text words. if your application requires strictly wd2001 mode then please contact the factory for documentation. the ca20c03a is implemented in low power cmos technologies with ttl compatible i/o. it is offered in 28-pin pdip, 28-lead plcc, and 44-pin tqfp packaging. application areas for the ca20c03a des chip spans a diverse industrial base of ?ancial, information processing, telecommunications and data communications companies. secure brokerage transactions electronic fund transfers secure banking/business accounting mainframe communications remote and host computer communications secure disk or magnetic tape data storage secure packet-switching transmission 3 data encryption products 3.1 ca20c03a&w
ca20c03a tundra semiconductor corporation 3-2 tundra semiconductor corporation figure 3-1 : ca20c03a block diagram command register status register parity detect key register (56 bits) data register (64 bits) iv register (64 bits) static data register (64 bits) nbs algorithm interface control bb cbc/ecb ivir spir v dd we a1 re clk cs dor dir kr v ss e/d act kpe mr crps a0 static key register (56 bits) master control temp register (64 bits) 8?it dal bus (bits 0 ?7) to system bus dal 0 . . dal 7
tundra semiconductor corporation ca20c03a tundra semiconductor corporation 3-3 figure 3-2 : ca20c03a pin con?uration b) 28-pin plcc a) 28-pin pdip 1 3 2 5 4 7 6 9 8 10 11 12 13 14 bb 1 cbc/ebc ivir spir v dd we a1,o/n re clk cs dal1 dal3 dal5 dal7 15 16 17 18 19 20 21 22 23 24 25 26 27 28 dor dir kr act kpe mr crps a0, nk dal6 dal4 dal2 dal0 ca20c03a e/d v ss (gnd) bb 1 v ss (gnd) crps a0, nk cbc/ebc ivir spir v dd we a1,o/n re clk cs dal1 dal3 dal5 dal7 1 3 2 4 26 27 28 567891011 12 13 14 15 16 17 18 dor dir kr e/d act kpe mr dal6 dal4 dal2 dal0 ca20c03a 22 21 20 19 23 24 25 c) 44-pin tqfp bb 1 cbc/ebc ivir spir v dd dal3 dal5 dal7 1 3 2 4 26 27 28 5 6 7 8 9 10 11 12 13 14 15 16 17 18 dor dir kr dal6 dal4 dal2 dal0 ca20c03a 22 21 20 19 23 24 25 we re clk cs dal1 v ss (gnd) crps a0, nk e/d act kpe mr a1,o/n 33 31 32 30 29 44 43 42 41 40 39 38 34 35 36 37 n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c
ca20c03a tundra semiconductor corporation 3-4 tundra semiconductor corporation table 3-2 : pin description symbol pin type name and function plcc pdip tqfp a0, nk 19 19 24 i address 0, new key: when is logic 1 or open, a high on this input addresses the command or status register (see table 3-18). when and a1, o/ are logic 0, a high on this input requests that a new key be loaded in the key register. device responds by activating the kr pin. a1, o/ 6 6 2 i address 1, old/new: when is logic 1 or open, and this input is logic 1, the status register is addressed ( = 0, a0 = 1). when this input is logic 0, the command register is addressed ( = 0, a0 = 1). this input is ignored when a0 = 0. note that this input has an internal pull-up resistor. when is logic 0 (low) and this input is logic 0, the device is in ca20c03a mode. when this input is logic 1, the device is in wd2001 mode. the only way to return to ca20c03a mode from wd2001 mode is to reset the device. caution: in wd2001 mode, pin 6 of the ca20co3a device must not be connected to +12v as it will irreparably damage the device. act 232329i/o activate: when is logic 1 or open, this pin is an output re?cting the status of the activate bit (bit 1) of the command register. when is logic 0, this pin is an input that overrides the activate bit of the command register. bb 1 1 40 i/o battery back-up key: when is logic 1 (open), this pin is an output re?cting the status of the battery back-up key bit (bit 5) of the command register. when is logic 0 or low, this pin is an input that overrides the battery back-up key bit. cbc/ 2 2 42 i/o cipher block chaining/electronic code book: when is logic 1 or open, this pin is an output pin re?cting the status of cbc/ bit (bit 7) of the command register. when is logic 0, this pin is an input pin and overrides the cbc/ bit of the command register. clk 9 9 9 i clock: system clock input. 20 20 25 i command register pin select: this input selects dal bus or input pin programming of the command register. high or open selects dal bus programming. low selects input pin programming.this input incorporates an internal pull-up resistor. 10 10 10 i chip select: is made low to access registers within the device. dal 7 - 0 11-18 11-18 11,12,15, 16,18,19,2 1,23 i/o data lines: eight active true, tri-state, bi-directional i/o lines used for information transfer to and from the des device. all command register , status register , key word and data word transfers are via this bus. dir 27 27 36 o data-in request: this output is active high when the des device is requesting that byte of the data word be written into the data register (the data register is automatically addressed when dir is active, unless overridden by a0). dor 28 28 37 o data-out request: this output is active high when the des device is requesting that a byte of the data word be read from the data register (the data register is automatically addressed when the dor is active, unless overridden by a0). /d 24 24 31 i/o encrypt/decrypt: when is high or open, this pin is an output re?cting the status of the encrypt/decrypt bit (bit 3) of the command register. when is low, this pin is an input pin that overrides the encrypt/decrypt bit of the command register. crps crps n n crps cs cs crps crps crps crps crps ecb crps ecb crps ecb crps crps crps cs cs e crps crps
tundra semiconductor corporation ca20c03a tundra semiconductor corporation 3-5 ivir 3 3 43 o initial vector-in request: this output is active high when the device is requesting that a byte of the iv word be written into the iv register (the iv register is automatically addressed when ivir is active, unless overridden a0). 22 22 28 o key parity error: this output is active low when enabled via the command register bit 2 (keoe) and a parity error has been detected during loading of the key register. kr 26 26 34 o key request: this output is active high when the des device is requesting that a byte of the key word be written into the key register. (the key register is automatically addressed when kr is active, unless overridden by a0.) 21 21 26 i master reset: active low resets the command and status registers and resets internal circuitry. (requires active clock for reset operation.) 888i read enable: the contents of the selected register are placed on the dal bus lines when and are made low. spir 4 4 44 o special pattern-in: this output is active high during battery back-up mode, when the device is requesting that a byte of the special pattern word be written into the data register (the data register is automatically addressed when spir is active, unless overridden by a0). v dd 551- power supply: +5 v 10% v ss 25 25 33 - ground: ground 777i write enable: information on the dal bus lines is written into the selected register when and are made low. table 3-2 : pin description cont'd symbol pin type name and function plcc pdip tqfp kpe mr mr re cs re we cs we
ca20c03a tundra semiconductor corporation 3-6 tundra semiconductor corporation notes for tables 3a, 3b, and 3c: 1. all output timing speci?ations re?ct the following: high output 2.0v, low output 0.8v 2. clock input: clock signal duty cycle is 50% 10%. there is no minimum frequency. 3. t mr is 2 clks in all cases for the ca20c03a device. 4. time between consecutive or pulses: t br = t bw = 2 clock periods minimum . 5. act, /d, and cbc/ are valid 2clk + 450 ns from - of a command register write operation. 6. output is valid within 2clk + 450 ns from - of a write of a key word byte that results in a parity error. 7. act, /d, bb and cbc/ are valid 2clk + 30 ns from - of a command register write operation (for ca20c03a). 8. output is valid within 1clk + 30 ns from - of a write of a key word byte that results in a parity error (for ca20c03a). table 3-3a : ac characteristics for ca20c03a (5, 10, 16 mhz) t a = 0 to 70 c, v dd = +5.0v 10%, v ss = 0v symbol parameter test condition limits 5mhz limits 10mhz limits 16mhz unit min max min max min max t br - to next 2clk 2clk 2clk ns t bw - to next 2clk 2clk 2clk ns t cy clock cycle time 200 100 62.5 ns t dar dor - from - 2clk+30 2clk+30 2clk+30 ns t daw kr - , dir - , ivir - , and spir - from - 2clk+30 2clk+30 2clk+30 ns t ddr dor from 150 80 50 ns t ddw kr , dir , ivir , spir from cload = 50 pf 150 80 50 ns t df - to dal ?at 10 100 10 50 5 35 ns t dh dal hold from - 20 15 10 ns t dvw dal setup we - 80 40 30 ns t mr master reset pulse width 2clk 2clk 2clk m s t rach a0, a1, cs hold from - 000ns t racs a0, a1, cs setup to 25 15 5 ns t rd pulse width 200 100 60 ns t rdv to dal valid cload = 50pf 150 90 50 ns t wac h a0, a1, cs hold from - 000ns t wac s a0, a1,cs setup to 25 15 5 ns t wr pulse width 125 95 60 ns re re we we re we re we re we re re re re we we we re we e ecb we kpe we e ecb we kpe we
tundra semiconductor corporation ca20c03a tundra semiconductor corporation 3-7 notes for tables 3a, 3b, and 3c continued: 9. kr activation is valid within 2clk + 30 ns from - (for ca20c03a) and 3clk + 450 ns from - of a write operation that pro- grams a 1 into the command register activate bit (or from a act input - , if = 0). 10. initial dir activation is valid within 20clk + 30 ns from - of the 8th write into the key register. 11. initial dor activation is valid within 20clk + 30 ns from - of the 8th write into the data register. 12. when reading the data register (in response to dor), subsequent data bytes are made available internally to the dal output b uffers within 2clk + 30 ns from - . 13. after reading the data register in response to dors, dir is activated and valid within 2clk + 30 ns from - of the 8th read from the data register. 14. all output timings assume cload = 50pf. table 3-3b : ac characteristics for ca20c03a (20, 25 mhz) t a = 0 to 70 c, v dd = +5.0v 10%, v ss = 0v symbol parameter test condition limits 20mhz limits 25mhz unit min max min max t br - to next 2clk 2clk ns t bw - to next 2clk 2clk ns t cy clock cycle time 50 40 ns t dar dor - from - 2clk+30 2clk+30 ns t daw kr - , dir - , ivir - and spir - from - 2clk+30 2clk+30 ns t ddr dor from 40 35 ns t ddw kr , dir , ivir , spir from cload = 50 pf 40 35 ns t df - to dal ?at 525520ns t dh dal hold from - 55ns t dvw dal setup we - 20 20 ns t mr master reset pulse width 2clk 2clk m s t rach a0, a1, cs hold from - 00ns t racs a0, a1, cs setup to 55ns t rd pulse width 50 40 ns t rdv to dal valid cload = 50pf 45 35 ns t wac h a0, a1, cs hold from - 00ns t wac s a0, a1,cs setup to 55ns t wr pulse width 45 35 ns re re we we re we re we re we re re re re we we we we we crps we we re re
ca20c03a tundra semiconductor corporation 3-8 tundra semiconductor corporation figure 3-3 : typical key or data register load timing t daw t ddw t wr t dvw t dh t bw kr, dir, ivir, spir cs we dal figure 3-4 : typical register read timing dor cs re dal t dar t ddr t rdv t rd t df t br figure 3-5 : read timing a0, a1 cs re dal t rach t rdv t df t rd t racs
tundra semiconductor corporation ca20c03a tundra semiconductor corporation 3-9 figure 3-6 : write timing a0, a1 cs we dal t wach t dh t wr t wacs t dvw
ca20c03a tundra semiconductor corporation 3-10 tundra semiconductor corporation note: the following timing parameters only apply when the timing of figure 8 is used. figure 3-7 : typical i/o timing figure 3-8 : maximum throughput timing for the ca20c03a device table 3-4 : maximum throughput i/0 timing for the ca20c03a device symbol 5 mhz 10 mhz 16 mhz 20 mhz 25 mhz unit min max min max min max min max min max t wr 125 185 65 85 30 45 25 35 20 25 ns t rd 125 185 65 85 30 45 25 35 20 25 ns t rdv 125 65 30 25 25 ns t 1 22222ns t 2 13 13 13 13 13 ns clock rd or wr 3 cycles clock rd or wr 2 cycles t 1 t 2 using the ca20c03a to attain maximum throughput in order to obtain maximum throughput from the ca20c03a, the number of cycles used to perform i/o operations is minimized. the throughput is dictated by eight bytes written to the device plus 20 cycles for processing, plus eight bytes read from the device for each 64-bit block. if the data sheet is followed explicitly, it would take 24 cycles per i/o operation for a total of 48 cycles (i.e. three cycles for each byte written to or read from the device as dictated by t bw timing parameters). so for each 64-bit block, 48 plus 20, or 68 cycles are required, giving a maximum throughput of: 8bytes/(68 cycles x (40ns/cycle) = 2.95 mbytes/s. the number of cycles per byte can be reduced to two by following a few simple timing rules. the timing parameters t bw and t br specify two cycles between the rising edge of a read or write and the falling edge of the next read or write. figure 3-7 shows this timing and hence the three clock cycles per byte. in actual fact, two falling edges of the clock are required between the rising edge of a read or write and the falling edge of the next read or write. figure 3-8 shows how two cycles are achieved in this case. so for each 64-bit block, 32 plus 20, or 52 cycles are required, giving a maximum throughput of: 8bytes/(52 cycles x (40ns/cycle) = 3.85 mbytes/s two new timing parameters, t 1 and t 2 , are introduced (see figure 3-8), and modi?ations are made to and (see table 3-5 below). wr rd
tundra semiconductor corporation ca20c03a tundra semiconductor corporation 3-11 notes: 1. i il applies only to inputs without pull-up resistors. 2. i ll applies only to inputs with pull-up resistors. the power dissipation ?ure is based on typical internal logic dissipation plus the worst case set of outputs simultaneously ac tive with maximum rated loads. stresses beyond those listed above may cause permanent damage to the device. these are stress ratings only, and functional oper ation of the device at these or any other conditions beyond those indicated in the operational sections of this speci?ation is not implied. exposure to maximum rating condi- tions for extended periods may affect device reliability. table 3-5 : dc characteristics (t a = 0 to 70 c, v dd = +5.0v 10%, v ss = 0v) symbol parameter test conditions limits unit min max i il input leakage current v ih = 5.5 v -10 +10 m a v il = 0 v -10 +10 m a i ll input low current on ca20c03a , a1, o/ pins. v il = 0 v 1 ma i ol output leakage current 0 v v in v dd -10 10 m a i ddop operating current v in = v dd or v ss 2 ma/mhz i ddsb standby current v in = v dd or v ss v dd = 5.5 v, outputs open 1.0 (0.1 typ) m a v ih voltage input high 2.4 v v il voltage input low (all inputs) 0.8 v v oh voltage output high i oh = -100 m a 2.8 v v ol voltage output low i ol = +1.6 ma 0.4 v v bb min. battery back-up voltage 2.0 v i dr data retention current in battery back-up mode v bb = 2.0 v 15.0 m a table 3-6 : recommended operating conditions dc supply voltage (v dd ) +4.5 v to +5.5 v power dissipation (p dd ) 0.5 w ambient operating temperature (t a commercial) 0 to +70 c table 3-7 : absolute maximum ratings dc supply voltage (v dd ) -0.3 to +7.0 v input voltage (v in ) -0.3 to vdd +0.3 v dc input current (i in ) -10 to +10 ma storage temperature, plastic (t stg ) -40 to +125 c crps n
ca20c03a tundra semiconductor corporation 3-12 tundra semiconductor corporation functional description the static key register during the key veri?ation process. when the ca20c03a is programmed for the cipher block chaining (cbc) mode, the initial vector (iv) is requested by the device after the key word is loaded into the key register and is ready to be used for encryption or decryption. the initial vector register is loaded with eight successive bytes (most signi?ant byte ?st) of initial vector data at the start of each encryption or decryption process. to encrypt plain data, the data register is loaded with eight successive bytes (most signi?ant byte ?st) of the ?st plain text block. the contents of the data register are then added (modulo 2) to the contents of the initial vector register one bit at a time. the modi?d text is then encrypted to the des algorithm and the resulting encrypted (cipher) text is loaded into the initial vector register for the next block of plain text to be modi?d, as well as being ready to be read out. this cycle is repeated until all required data is encrypted. to decrypt encrypted data, the data register is loaded with eight successive bytes (8-bit) of the ?st cipher text block. the contents of the data register are loaded into the temp register and at the same time they are decrypted to the des algorithm. the resulting text in the data register is added (modulo 2) with the contents of the initial vector register. the contents of the initial vector register becomes plain text and are loaded into the data register, ready to be read out. the contents of the temp register are then loaded into the initial vector register to allow for the next block of cipher text to be decrypted. this cycle is repeated until all required data is decrypted. when the ca20c03a is programmed for electronic code book (ecb) mode, neither the initial vector register nor the temp register are used. the data word is requested by the device after the key word is loaded in the key register and ready to be used for encryption or decryption. in both encryption and decryption, the data register is loaded with eight successive bytes (8-bit) of text, then the contents of the data register go through the des algorithm calculation. the resulting text in the data register is ready to be read out. it is read by reading eight successive bytes (8-bit). the data transfer into or out of the devices registers (key register, data register, iv register) through the dal bus is accomplished by loading or reading out eight successive bytes (8-bit). the ?st byte written to or read from these registers is always the most signi?ant byte. the data transfer between registers (key register, static key register, data register, static data register, iv register and temp register) is performed internally and automatically by this device. the ca20c03a data encryption standard (des) device consists of eight registers, two ciphering options, the des algorithm and key parity checking. the ca20c03a also contains the necessary logic to implement a battery back-up key option. the eight registers include a 56-bit key register, a 64-bit data register, a 64-bit initial vector register, a 64-bit temp register, two 8-bit registers for both command and status, a 56-bit static key register, and a 64-bit static data register. a block diagram of the ca20c03a is shown in figure 1. the ca20c03a devices can be programmed for encryption or decryption using either the electronic code book (ecb) or cipher block chaining (cbc) modes with or without a battery back-up key . data is encrypted or decrypted with a 64-bit, user-de?ed key word . data encrypted with a given key word can be decrypted only using the same key word . the key register is loaded by the system with eight successive bytes beginning with the most signi?ant byte of the key. parity is checked on each byte of the key word as it is loaded into the key register. the least signi?ant bit (dal0) of each 8-bit byte is reserved for odd parity for that byte and is not used in the algorithm calculation (see table 3-8 and table 3-9 below for key word loads and data loads and reads). table 3-8 : format for key word loads table 3-9 : format for data loads and reads in a mode without a battery back-up key , the key word is requested after each activation and should be loaded into the key register. the static key register and static data register are not used in this mode. in a mode with a battery back-up key , the key word is requested only when the user requests a new key by programming the command register, or when the key word stored in the static key register is found no longer valid after power-up key veri?ation. in this mode, the key word is loaded into the static key register, and a special 64-bit pattern is requested and encrypted by the ca20c03a. the encrypted pattern is loaded in the static data register. during power-down or power failure, the contents of these two static registers are retained by the battery back-up power. as soon as the power is up again, the contents in the static data register are used to verify and validate the contents in 7654321p arity dal7 dal6 dal5 dal4 dal3 dal2 dal1 dal0 76543210 dal7 dal6 dal5 dal4 dal3 dal2 dal1 dal0
tundra semiconductor corporation ca20c03a tundra semiconductor corporation 3-13 register descriptions table 3-10 : command register this 8-bit read/write register controls the operation of the ca20c03a. it is normally loaded only once for an entire encryption or decryption process. note: all bits of the command register are reset to logic 0 upon when = 1, except bit 2 (keoe) which is set to 1. when = 0, this register is disregarded after . bits function 7-0 cbc/ nk bb n/u /d keoe act n/o name description new/old (n/o) when logic 0, the des device is backward compatible with the wd2001 device in both hardware & software. when logic 1, the des device is in ca20c03a mode. activate (act) this bit must be logic 1 for encrypt/decrypt operation. when this bit is set from logic 0 to logic 1, one of the following events happen: initiates loading the key register in non-battery back-up key mode. initiates loading the key register in battery back-up key mode while nk (command bit) is logic 1 initiates special pattern-in request in battery back-up key mode while nk = 0 and kv (status bit) is logic 1. initiates a data-in request in battery back-up key mode while nk = 0, kv = 0, and cbc/ (command bit) is logic 0. initiates an initial vector-in request in battery back-up key mode while nk = 0, kv = 0 and cbc/ = 1. key error output when logic 0, the key parity error output pin ( ) remains inactive regardless of the status of the key parity error bit (status bit 5). when logic 1, the key parity error output pin is active when the kpe bit (status bit 5) is logic 1. this bit set to logic 1 upon a . encrypt/decrypt ( /d) when logic 0, data is to be encrypted. when logic 1, data is to be decrypted. n/u not used. battery back-up key (bb) when logic 0, the des device is in non-battery back-up key mode. when logic 1, the des device is in battery back-up key mode. this bit is only used in the ca20c03a device. new key request (nk) this bit is ignored in non-battery back-up key mode. while in battery back-up key mode, a key request is initiated when nk = 1, or the device skips the key loading process and does either the cipher block chaining process or the electronic code process when nk = 0. this bit is only used in the ca20c03a device. cipher block chaining/ (cbc/ ) when logic 0, the des device encrypts/decrypts data using the electronic code book method. when logic 1, the des device encrypts/decrypts data using the cipher block chaining method. ecb e ecb ecb kpe master reset e electronic code book ebc master reset crps crps master reset
ca20c03a tundra semiconductor corporation 3-14 tundra semiconductor corporation table 3-11 : status register this 8-bit read-only register monitors the status of the device. note: upon and is logic 1, the status register is not addressable because the device comes up in the wd2001 mode. once the command register is programmed into the new mode (write 1 to the n/o bit) the status register is addressable and will have all bits reset to 0, except the kv bit which is set to a logic 1. when = 0 and a1, o/ = 0, all bits are reset to 0 except kv (bit 0) which is set to logic 1. bits function 7-0 dor dir kpe kr ivir spir rlk kv name description key verification request (kv) if the pin is logic 1, this bit is set each time the n/o bit of the command request (kv) register is set from logic 0 to logic 1. if the pin is logic 0 and n/o is logic 0, this bit is set upon each . it is reset at the end of the key veri?ation process while the key is valid, or at the end of the key reloading process. this bit is only used in the ca20c03a device. reload key request (rlk) this bit is set when the user requests a new key (nk = 1) in battery back-up key mode (bb = 1) or at the end of the key veri?ation process when the key is found not valid. when this bit is set, the key reloading process starts. this bit is reset at the end of the key reloading process. the reset occurs when the encrypted special pattern (encrypted by the new loaded key ) is loaded into the static data register from the data register. if this bit becomes set, it can only be cleared through the key reloading process or by performing a master reset (i.e. deactivating the device by writing to the command registers will not reset this bit). this bit is only used in the ca20c03a device. special pattern-in request (spir) this bit is set to logic 1 when the act bit is programmed from logic 0 to logic 1, bb = 1, nk = 0, and kv = 1, or when kr is reset from logic 1 to logic 0 and rlk = 1. it is reset upon loading of the last (8th) byte of the special pattern into the data register. this bit is only used in the ca20c03a device. initial vector-in request (ivir) this bit is set to logic 1 upon one of the following conditions: completion of key register loading while bb = 0 and cbc/ = 1. completion of key reloading process while bb = 1 and cbc/ = 1 (ca20c03a device only). completion of key veri?ation process and the key being found valid while bb = 1 and cbc/ = 1 (ca20c03a device only). the act bit is set from logic 0 to logic 1 while bb = 1, nk = 0, kv = 0 and cbc/ = 1 (ca20c03a device only). this bit is reset upon loading of the last (8th) byte of the initial vector . key request (kr) this bit is set to logic 1 when act is programmed from logic 0 to logic 1 and bb = 0 or, when rlk is set intern ally from logic 0 to logic 1 (ca20c03a device only). it is reset upon loading of the last (8th) byte of the key register. key parity error (kpe) this bit is set internally upon detection of a parity error during loading of the key register. it is res et when act is programmed from logic 1 to logic 0 (i.e., the device is deactivated). data-in request (dir) this bit is set to logic 1 upon one of the following conditions: completion of key register loading while bb = 0 and cbc/ = 0. completion of the key reloading process while bb = 1 and cbc/ = 0 (ca20c03a device only). completion of the key veri?ation process and the key being found valid while bb = 1 and cbc/ = 0 (ca20c03a device only). the act bit is set from logic 0 to logic 1 while bb = 1, nk = 0, kv = 0 and cbc/ = 0 (ca20c03a device only). completion of iv register loading while bb = 1 and cbc/ = 1 (ca20c03a device only). completion of data register reading (i.e.: the last data-out request has been serviced by an 8-byte read and the data register is now emptied and ready to be loaded with the next data word). this bit is reset upon loading of the last (8th) byte of the data register. data-out request (dor) this bit is set upon completion of the internal encrypt/decrypt calculation of a data word . it is reset upon reading the last (8th) byte of the data register. crps crps master reset ecb ecb ecb ecb ecb ecb ecb ecb ecb master reset cprs cprs n
tundra semiconductor corporation ca20c03a tundra semiconductor corporation 3-15 table 3-12 : key register (load only) this 56-bit register contains the key which is used to encrypt or decrypt the data with the des algorithm. the key register can be loaded with eight successive bytes only when there is a key request (status bit and output). the key register can also be parallel loaded from static key register in battery back-up key mode. this is a write-only register. table 3-13 : static key register this 56-bit register contains the current key for data encryption and decryption using the des algorithm. the static key register is updated when a new key is loaded into the key register and when the device is programmed for battery back- up mode. the contents of this register are retained by battery power during power-down or power failure. if the device is programmed for a mode without a battery back-up key, this register is not used. the register is not accessible to the user. table 3-14 : data register this 64-bit register contains the plain or cipher text either to be read out or that has been loaded in. during encryption, the data register is loaded with plain text and contains cipher text to be read out. during decryption, the data register is loaded with cipher text and contains plain text to be read out. the data register is always read or loaded with eight successive bytes (8-bit). the data register can only be loaded when there is a data-in request or special pattern-in request (status bit and output). similarly, the data register can only be read when there is a data-out request (status bit and output). however, when the device is programmed for a mode with battery back-up, the contents of this register can be parallel loaded into the static data register when the special pattern for key veri?ation is encrypted. data reg. bits 55..49 48..42 ?? 15..07 06..00 dal bits 7..1 7..1 ?? 7..1 7..1 byte loaded 1st 2nd ?? 7th 8th data reg. bits 55..49 48..42 ?? 15..07 06..00 dal bits 7..1 7..1 ?? 7..1 7..1 byte loaded 1st 2nd ?? 7th 8th data reg. bits 63..56 55..48 ?? 15..8 07..00 dal bits 7..0 7..0 ?? 7..0 7..0 byte loaded 1st 2nd ?? 7th 8th table 3-15 : static data register this 64-bit register contains the encrypted special pattern for key veri?ation. when the device is programmed for a mode with a battery back-up, the static data register is updated whenever a new key is loaded in. the special pattern is loaded in the data register and encrypted by the new key, then the new encrypted special pattern is loaded into the static data register. the contents of this register are retained by battery power during power-down or power failure. if the device is programmed for a mode without a battery back-up key, the register is not used. this register is not accessible to the user. table 3-16 : initial vector (iv) register this 64-bit register contains the initial vector or cipher text for the cipher block chaining mode. this register is ?st loaded with the eight successive bytes (8-bit) of the initial vector register for the ?st block of plain or cipher text. after the current text in the data register (plain or cipher) has been processed (encrypted or decrypted), this register is loaded with the current cipher text from the data register (encrypt) or the next block of text from the temp register (decrypt). this register is not used in the electronic code book mode. table 3-17 : temp register this 64-bit register is a temporary storage place used in the cipher block chaining mode. this register temporarily stores the current cipher text, before this text is loaded into the iv register during the decryption process. this register is loaded with the eight bytes of cipher text from the data register. it is not used in the electronic code book mode and is not accessible to the user. data reg. bits 63..56 55..48 ?? 15..8 07..00 dal bits 7..0 7..0 ?? 7..0 7..0 byte loaded 1st 2nd ?? 7th 8th data reg. bits 63..56 55..48 ?? 15..8 07..00 dal bits 7..0 7..0 ?? 7..0 7..0 byte loaded 1st 2nd ?? 7th 8th data reg. bits 63..56 55..48 ?? 15..8 07..00 dal bits 7..0 7..0 ?? 7..0 7..0 byte loaded 1st 2nd ?? 7th 8th
ca20c03a tundra semiconductor corporation 3-16 tundra semiconductor corporation des encryption modes cipher block chaining (cbc) mode overview the cipher block chaining mode also operates on 64 bit data blocks, but preprocesses the information before passing it to the des algorithm. an input data block is ?st exored with a 64 bit initial vector (iv), then processed by the des algorithm. the resulting ciphered-output block is loaded into the iv register, to be exored with the next input block. this chaining of cipher text blocks provides different outputs for identical input blocks. it also gives an error extension characteristic which protects against fraudulent data insertion, deletion or alteration in a block sequence (see figure10). a one-bit error in the input text block, the key or the initial vector causes an average error rate of 50% in all subsequent output blocks. thus, the cbc mode is far better suited to high-speed data communications applications. cipher feedback (cfb) and output feedback (ofb) these two des modes can be implemented with the ca20c03a using the ecb mode with additional software overhead. for more information refer to the publication: cryptography and data security , by d. denning, addison- wesley publishing company, inc., 1982. electronic code book (ecb) mode overview the electronic code book is a direct implementation of the des algorithm in which the same plain text always generates the same ciphered text for a given cryptographic key. the ca20c03a determines the codebook entries each time. a single bit error or change, in either the input text block or the key, causes an average bit error rate of 50% for its output block. however, an error in one text block does not affect any other block. in other words, there is no error extension between blocks generated using the ecb mode. the input and output block size is ?ed at 64 bits. since data blocks are independently ciphered, this mode is suitable for disk applications (see figure 9). the ecb mode has the weakness that identical block of plain text generate identical blocks of ciphered text. this violates one of the basic laws of encryption security, namely: never encrypt a given piece of information the same way twice as it makes it easier for an attacker to break the code. this shortcoming in the ecb mode is resolved by the cipher block chaining mode. figure 3-9 : electronic codebook (ecb) mode ecb encryption plain text (64 bits) input block des encrypt output block cipher text (64 bits) ecb decryption cipher text (64 bits) input block des decrypt output block plain text (64 bits)
tundra semiconductor corporation ca20c03a tundra semiconductor corporation 3-17 figure 3-10 : cipher block chaining (cbc) mode initialization vector (iv) initialization vector (iv) time = 1 d 1 i 1 des encrypt c 1 c 1 des decrypt i 1 d 1 + + time = 2 d 2 i 2 des encrypt c 2 c 2 des decrypt i 2 d 2 + + time = n d n i n des encrypt c n c n des decrypt i n d n + + encrypt decrypt d j i j c j = data block at time j = encryption input block at time j = cipher block at time j = exclusive-or + legend
ca20c03a tundra semiconductor corporation 3-18 tundra semiconductor corporation ca20c03a modes of operation the ca20c03a can operate in two major encryption modes: electronic code book (ecb) mode and cipher block chaining (cbc) mode (each an implementation of the des algorithm). each of these two modes can be selected with or without battery back-up, giving a total of four operational modes (for the ca20c03a): electronic code book without a battery back-up key cipher block chaining without a battery back-up key electronic code book with a battery back-up key cipher block chaining with a battery back-up key the ca20c03a can also be programmed to operate in a wd2001 mode, which offers ecb type encryption only. when the n/o bit is programmed to logic 1, the device is in the ca20c03a mode, and either ecb or cbc type encryption modes can be selected. when the n/o bit is logic 0, the device is in wd2001 mode. all modes are described in more detail below. wd2001 compatibility mode to ensure backward compatibility with the wd2001 device, the ca20c03a can also be programmed to emulate functions in the wd2001 (ecb mode only). this is determined by the setting of bit 0 (n/o) in the command register, which indicates whether the ca20c03a is in wd2001 mode (ecb) or in ca20c03a mode (ecb or cbc). when the n/o bit is programmed to logic 0, the device is in the wd2001 mode (ecb) and only the command/status, data, and key registers are then available. the pinouts and the operation of the device and the functions of the three registers in this mode are exactly the same as in the wd2001 (refer to ca20c01 data sheet for detailed operational information). if wd2001 mode is in use in a ca20c03a device, pin 6 of the device can be connected to +5 v, or left unconnected. caution: pin 6 of a ca20c03a device must not be connected to +12 v as it will irreparably damage the device. electronic code book without a battery back-up key the ca20c03a operates in this mode when bit 5 (bb), and bit 7 (cbc/ ) in the command register are set to logic 0. after the device is selected to be in this mode, it is initiated by setting bit 1 (act) in the command register to logic 1. the ca20c03a responds by activating the key request (kr, pin 26) output. a0 must be deactivated (to allow the ca20c03a to internally address the key register) before loading the 64-bit ecb key word into the key register. the key register is loaded with eight successive bytes (8-bit) by activating eight times (with active). when is activated, the ca20c03a deactivates the key request (kr) output. when is deactivated, the ca20c03a activates the kr output. the ca20c03a activates eight key requests to ?l up the key register. x = dont care the kr output can either be used for asynchronous handshaking (as in dma control) or, after the ?st activated kr, further activations can be ignored and the key register can be loaded synchronously (as in programmed i/o) by eight successive activations of . each byte of the key word is checked for odd parity when it is loaded into the key register (see figure 3-11). if a parity error is detected, the ca20c03a sets bit 5 ( kpe, key parity error ) in the status register to logic 1. if bit 2 ( keoe, key error output enable ) in the command register has been set, the device also activates the (pin 22) output. bit 5 ( kpe, key parity error ) in the status register is reset to logic 0 when bit 1 ( act, activate ) in the command register is reset to logic 0. after loading the eighth byte of the key word into the key register, the ca20c03a sets dir, data-in request in the status register and activates the data-in request (dir, pin 27) output (see figure 3-12). the 64-bit data word should then be loaded into the data register, which is loaded in the same manner as the key register by eight successive activations of data-in request (dir, pin 27) output and input. after the eighth (last) byte of the data word has been loaded, the ca20c03a starts its operation internally by encrypting or decrypting the data to the des algorithm. upon completion of this operation, the encrypted or decrypted data is loaded into the data register, the ca20c03a sets bit 7 ( dor, data-out request ) in the status register and activates the data-out request (dor, pin 28) output (see figure 3-13). the data word must then be read from the data register in the same manner as it was loaded (by eight successive table 3-18 : ca20c03a register select register a0 a1 status 0 1 1 1 command 0 1 0 1 key, iv and data 0 0 x 1 we cs we we cs crps we kpe we
tundra semiconductor corporation ca20c03a tundra semiconductor corporation 3-19 activations of data-out request output and input). after the ?st request, further activations of the dir and dor outputs can be ignored and the data register can be loaded or read by eight successive activations of or . after the eighth (last) byte of the data register has been read, the ca20c03a reactivates the data-in-request . the cycle of loading the data register, encrypting or decrypting of the data to the des algorithm, and reading the new data from the data register is repeated until all required data has been encrypted or decrypted with the current key word . figures 3-11 to 3-13 are ?wcharts which will aid in the understanding of the device operation in this mode. when this is completed, bit 1 ( act, activate ) in the command register should be reset to logic 0 to lock the last key word loaded into the ca20c03a. this prevents the access and use by an unauthorized user. to resume operation, the activate bit must be reset to logic 1. this activates the key request and a new key must be loaded before the data register can be accessed. plain data is encrypted by loading it into the data register, and encrypted data is read from the data register after /d, /decrypt in the command register has been set to logic 0. data is decrypted by loading it into the data register, and plain data is read from the data register after /d, /decrypt in the command register has been set to logic 1. caution: to accomplish switching from encryption to decryption (or vice versa) with the same key word before a data word transfer is initiated, a0 must be set to 1 and a1 to 0. the ca20c03a then overrides the internal addressing of the data register and addresses the command register, which can now be reprogrammed. when a0 is deactivated, the device then internally addresses the data register, while awaiting the loading of the next data word. cipher block chaining without a battery back-up key the ca20c03a operates in this mode when bit 5 (bb) and bit 7 (cbc/ ) in the command register are set respectively to logic 0 and logic 1. once the device is programmed in this mode, it can be initiated by setting bit 1 (act) in the command register to logic 1. the ca20c03a now responds by activating the key request (kr) output. refer to table 3-18 for register selection. a0 must be deactivated (to address the key register internally), and the key register must be loaded with the 64- bit key word in the same manner as performed in the electronic code book mode without a battery back-up key. when the eighth (last) byte of the key word is loaded in the key register, the ca20c03a sets bit 3 ( iv-in request ) in the status register and activates the iv-in request (ivir) output. the 64-bit initial vector word must then be loaded into the iv register in the same manner as the key register was loaded, that is, by eight successive activations of iv-in request output and input. after the eighth (last) byte of the initial vector word has been loaded, the ca20c03a sets bit 6 ( data-in request ) in the status register and activates the data-in request (dir) output. the 64-bit data word must then be loaded into the data register in the same manner as the key register was loaded, that is, by eight successive activations of data-in request output and input. the plain text is loaded into the data register when the /decrypt bit has been set to logic 0. when this is completed, that is, after the eighth (last) byte of the plain data word has been loaded into the device, the contents of the iv register are added to the plain text consecutively bit by bit with modulo 2 arithmetic and the ca20c03a begins the internal calculation of the des algorithm for the cipher text. re we re e encrypt e encrypt ebc we we encrypt figure 3-11 : key word loading procedure (ecb mode only) enter master reset d a load (read) command (status) register activated ? no yes key request is activated load byte of key word key parity error? 8 th byte? b yes yes no no set key parity error bit a0? 1 0 load (read) command (status) register is activate reset? a no
ca20c03a tundra semiconductor corporation 3-20 tundra semiconductor corporation when completed, this data is loaded into both the data register and the iv register (where it overrides the original initial vector word ). after (parallel) loading the new data into these two registers, the ca20c03a sets bit 7 ( data-out request ) in the status register and activates the data-out request (dor) output. the new cipher data word must then be read from the data register in the same manner as it was loaded, that is, by eight successive activations of data-out request output and input. after the eighth (last) byte of the data register contents have been read, the ca20c03a reactivates the data-in request and the next cycle can begin. this continues until all required (plain) data has been encrypted with the current key word in the manner previously described, that is, by: loading the data register with plain text adding the (previous) cipher text contents of the iv register to the contents of the data register calculating the des algorithm for cipher text loading it into the iv register for operation (addition) to the 64-bit (plain) data word reading it (cipher text) from the data register. when decrypting, bits 1 (act) and bit 3 ( /decrypt ) in the command register are set to 1 respectively. this activates the key request output indicating that the original key must now be loaded into the key register. after the key is loaded, the ca20c03a requests that the initial vector be loaded into the iv register. when this is completed, the data request input pin is activated and the ?st eight bytes of cipher data need to be loaded into the data register. after the eight bytes of the cipher data word have been loaded into the device, the contents of the data register are transferred into the temp register and the ca20c03a begins the internal calculation of the des algorithm for clear data. when completed, this data is added consecutively bit by bit to the contents of the iv register using modulo 2 arithmetic. the modi?d plain text data is then loaded into the data register while the contents of the temp register are loaded into the iv register, overriding the existing initial vector . after completion of these operations, bit 7 ( data-out request ) in the status register is set and the data-out request (dor) output is activated. the plain data word must then be read from the data request in the same manner as it was loaded, that is, by eight successive activations of data-out request output and input. re encrypt re figure 3-12 : activating dir output procedure (ecb mode only) load (read) command (status) register yes algorithm is executed load byte of data word 8 th byte? yes no no a0? 1 0 b data-in request is activated c d is activate reset? figure 3-13 : activating dor output procedure (ecb mode only) load (read) command (status) register yes read byte of data word 8 th byte? yes no no a0? 1 0 is activate reset? c data-out request is activated b d
tundra semiconductor corporation ca20c03a tundra semiconductor corporation 3-21 after the eighth (last) byte of the data register contents have been read, the ca20c03a reactivates the data-in request and the next cycle can begin. this continues until all required (cipher) data has been decrypted with the current key word in the manner previously described: load the data register with cipher text load the contents of the data register into the temp register calculate the des algorithm for clear text add the clear text contents in the temp register to the (previous) cipher text contents in the iv register load plain text into the data register transfer the contents of the temp register to the iv register for the next 64-bit cipher data word read plain text from the data register. as previously explained, for data-in , iv-in , and data-out , after the ?st request, further activations of dir, ivir, and dor outputs aren't necessary. loading the iv register and the data register is performed by eight successive activations of and reading the data register is performed by eight successive activations of . when all required data has been encrypted or decrypted with the current key word , bit 1 ( activate ) in the command register should be programmed to logic 0 to lock the last key loaded into the ca20c03a. this prevents the access and use of it by an unauthorized user. to resume operation, the activate bit must be programmed to logic 1. this activates the key request and a new key must be loaded before the data register can be accessed. caution: at the end of each encrypted or decrypted ?e (or message), the ca20c03a is waiting for the data word, not for the reloading of the initial vector: that is, dir output is active. in order to activate the ivir output and re-load the initial vector, the device has to be restarted. this can be accomplished by deactivating the ca20c03a and then reactivating it once more. this forces the re-loading of the key word. this procedure should be followed even when it is desired to use the same key word for the encryption or decryption of the next ?e (or message). we re electronic code book with a battery back-up key the ca20c03a operates in this mode when bit 5 (bb) and bit 7 (cbc/ ) in the command register are set respectively to logic 1 and logic 0. after the device is programmed for this mode, it is initiated by setting the act bit in the command register to logic 1. the ca20c03a responds in one of the following ways: when bit 6 ( nk, new key ) in the command register is set to logic 1, the ca20c03a responds by setting bit 1 ( rlk, reload key ) and bit 4 ( kr, key request ) in the status register. it also sets the key request output in the key reloading state. caution: the rlk bit can only be reset by the key reloading process or by performing a master reset. deactivating the device by writing to the command register will not reset this bit. a0 needs to be deactivated to allow the ca20c03a to select the key register internally and load it with the 64- bit key word (in the same manner as in the electronic code book mode without a battery back-up key). refer to table 16 for register selection. when the eighth (last) byte of the key word has been loaded into the static key register then bit 2 ( special pattern-in request ) in the status register is set and the special pattern-in request (spir, pin 4) output is activated. the 64-bit special pattern must now be loaded into the data register in the same manner as the key register, that is, by eight successive activations of special pattern-in request input and we input. when the eighth byte of the special pattern has been loaded into the data register, the device starts to encrypt the special pattern word in electronic code book mode. upon completion of the des algorithm calculation, the cipher data is then loaded into the static data register, and the ca20c03a resets reload key bit and the key verification bit in the status register. the device is now out of the key reloading state and continues in electronic code book mode by setting bit 6 ( data-in request ) in the status register and activating the data-in request (dir, pin 27) output. ecb
ca20c03a tundra semiconductor corporation 3-22 tundra semiconductor corporation when bit 6 ( new key ) in the command register is set to logic 0 and bit 0 ( key verification ) in the status register is set to logic 1, the ca20c03a responds by setting bit 2 ( special pattern-in ) in the status register. the device also activates the special pattern-in (spir) output, loads the contents of the static key register into the key register in order to encrypt the special pattern , and enters the key veri?ation state. a0 must be deactivated (to allow the ca20c03a to address the data register internally) and the data register must be loaded with the 64-bit special pattern word in the same manner as the key register was loaded, that is, by eight successive activations of special pattern-in request output and input. when the eighth byte of the special pattern has been loaded into the data register, the ca20c03a starts to encrypt the special pattern word in the electronic code book mode. upon the completion of the des algorithm calculation, the cipher data is compared with the contents of the static data register. if they are not the same, the ca20c03a sets bit 1 ( reload key ) and bit 4 ( key request ) in the status register and activates the key request (pin 26) output to start the key reloading process as was previously described. upon the completion of the key reloading operation, the device sets bit 6 ( data-in request ) in the status register and activate the data-in request (dir, pin 27) output to start the electronic code book mode. if the new cipher data and contents of the static data register are the same, the ca20c03a resets bit 0 ( key verification ), sets bit 6 ( data-in request ) in the status register, and activates the data-in request (dir, pin 27) output to start the electronic code book mode. when bit 6 ( new key ) in the command register is set to logic 0 and bit 0 ( key verification ) in the status register is set to logic 0, the ca20c03a loads the contents of the static key register into the key register, sets bit 6 ( data-in request ) in the status register and activates the data-in request (dir, pin 27) output to start the electronic code book mode. the operation is the same as previously described in the electronic code book mode without a battery back-up key . we note that to accomplish switching from encryption to decryption (or vice versa) without deactivating the ca20c03a, and before a data word transfer is initiated, a0 must be set to 1 and a1 to 0 to address the command register and override the addressing of the data register internally. the command register can now be re-programmed. when a0 is reset to logic 0, the ca20c03a will now address the data register internally while awaiting the loading of the next data word. cipher block chaining with a battery back-up key the ca20c03a operates in this mode when the bb and cbc/ bits in the command register are set to logic 1. after the device is programmed for this mode, it is initiated by setting the act bit in the command register to logic1. the ca20c03a responds in one of the three ways previously described in the section electronic code book with a battery back-up key . however, after completion of the key reload or key veri?ation operations, the device starts operating in the cipher block chaining mode instead of the electronic code book mode. it sets initial vector-in request in the status register and activates the initial vector-in request (ivir) output. when the ca20c03a is in the cipher block chaining mode, its operation is the same as previously described in cipher block chaining without a battery back-up key . a sample battery back-up circuit is shown in figure 14. note that at the end of each encrypted or decrypted ?e (or message), the ca20c03a is waiting for the data word , not for the reloading of the initial vector ; that is, dir output is active. in order to activate the ivir output and re-load the initial vector, the device has to be re-started by deactivating and then reactivating it. this restart procedure forces the re- loading of the key word and should be followed even when the same key word is desired for the encryption or decryption of the next ?e (or message). ecb
tundra semiconductor corporation ca20c03a tundra semiconductor corporation 3-23 command select option the ca20c03a can be programmed through the dal bus lines or through the input pins. when the command register pin select ( , pin 20) input is set to logic 0, the (a1,o/ ), act, /d, bb, (a0,nk), and cbc/ pins are enabled as inputs which override bits 0, 1, 3, 5, 6, and 7 in the command register. this override allows input pins to control the ca20c03a. bit 2 (keoe) in the command register remains at logic 1. the a1 and a0 bits are disregarded in this option, and the command and status registers cannot be accessed using the dal bus lines. note that the act pin must be toggled from logic 1 to logic 0 to clear a parity error detection when operating in this mode. all other operations are the same as described previously. caution: upon , while and a1,o/ pins are logic 0, the ca20c03a does not return to the 2001 mode, but stays in the ca20c03a mode and sets bit 0 (kv) in the status register. crps n e ecb master reset crps n figure 3-14 : ca20c03a battery back-up circuit example +5 v 1 2 7 6 3 4 5 8 ce (from decoder) v bat2 (note 1) v bat1 v ss v dd cs ++ notes: 1. v bat2 is optional (use if double redundant back-up is required for failsoft operation). 2. dallas semiconductor ds1210 non-volatile controller. ca20c03a des processor ds1210 (note 2) v cco 3 v 3 v
ca20c03a tundra semiconductor corporation 3-24 tundra semiconductor corporation note for table 3-19 and table 3-20: the plain text in both cases is the ascii code for ?ow is the time for all . these seven -bit characters are writ- ten in hexadecimal notation: 0, b6, b5, b4, b3, b2, b1, b0. table 3-19 : test data for electronic codebook (ecb) mode e-key=d-key= 0123456789abcdef encryption time plain text cipher text 1 4e6f772069732074 3fa40e8a984d4815 2 68652074696d6520 6a271787ab8883f9 3 666f7220616c6c20 893d51ec4b563b53 decryption time cipher text plain text 1 3fa40e8a984d4815 4e6f772069732074 2 6a271787ab8883f9 68652074696d6520 3 893d51ec4b563b53 666f7220616c6c20 table 3-20 : test data for cipher block chaining (cbc) mode e-key = d-key = 0123456789abcdef ive = ivd = 1234567890abcdef encryption time plain text cipher text 1 4e6f772069732074 e5c7cdde872bf27c 2 68652074696d6520 43e934008c389c0f 3 666f7220616c6c20 683788499a7c05f6 decryption time cipher text plain text 1 e5c7cdde872bf27c 4e6f772069732074 2 43e934008c389c0f 68652074696d6520 3 683788499a7c05f6 666f7220616c6c20

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