SIHG47N60EF www.vishay.com vishay siliconix s13-2236-rev. d, 28-oct-13 1 document number: 91559 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 e series power mosfet with fast body diode ? ? ? ? ? ? ? features ? fast body diode mosfet using e series technoloy ? reduced t rr , q rr , and i rrm ? low figure-of-merit (fom) r on x q g ? low input capacitance (c iss ) ? low switching losse s due to reduced q rr ? ultra low gate charge (q g ) ?avalanche energy rated (uis) ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? telecommunications - server and telecom power supplies ? lighting - high-intensity lighting (hid) - light emitting diodes (leds) ? consumer and computing - atx power supplies ? industrial - welding - battery chargers ? renewable energy - solar (pv inverters) ? switching mode power supplies (smps) ? applications using th e following topologies - llc - phase shifted bridge (zvs) - 3-level inverter - ac/dc bridge notes a. repetitive rating; puls e width limited by maximu m junction temperature. b. v dd = 50 v, starting t j = 25 c, l = 73.5 mh, r g = 25 ? , i as = 6.4 a. c. 1.6 mm from case. d. i sd ? i d , di/dt = 100 a/s, starting t j = 25 c. product summary v ds (v) at t j max. 650 r ds(on) max. at 25 c ( ? )v gs = 10 v 0.067 q g max. (nc) 225 q gs (nc) 31 q gd (nc) 63 configuration single n-channel mosfet g d s to-247ac g d s ordering information package to-247ac lead (pb)-free and halo gen-free SIHG47N60EF-ge3 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 600 v gate-source voltage v gs 20 gate-source voltage ac (f > 1 hz) 30 continuous drain current (t j = 150 c) v gs at 10 v t c = 25 c i d 47 a t c = 100 c 29 pulsed drain current a i dm 138 linear derating factor 3w/c single pulse avalanche energy b e as 1500 mj maximum power dissipation p d 379 w operating junction and storage temperature range t j , t stg -55 to +150 c drain-source voltage slope t j = 125 c dv/dt 37 v/ns reverse diode dv/dt d 9.7 soldering recommendations (peak temperature) c for 10 s 300 c
SIHG47N60EF www.vishay.com vishay siliconix s13-2236-rev. d, 28-oct-13 2 document number: 91559 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. c oss(er) is a fixed capacitance that gives the same energy as c oss while v ds is rising from 0 % to 80 % v dss . b. c oss(tr) is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 % to 80 % v dss . thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -40 c/w maximum junction-to-case (drain) r thjc -0.33 specifications (t j = 25 c, unless otherwise noted) parameter symbol test cond itions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 600 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = 1 ma -- v/c gate-source threshold voltage (n) v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = 600 v, v gs = 0 v - - 1 a v ds = 480 v, v gs = 0 v, t j = 125 c - - 500 drain-source on-sta te resistance r ds(on) v gs = 10 v i d = 24 a - 0.056 0.067 ? forward transconductance g fs v ds = 30 v, i d = 24 a - 17 - s dynamic input capacitance c iss v gs = 0 v, v ds = 100 v, f = 1 mhz - 4854 - pf output capacitance c oss - 195 - reverse transfer capacitance c rss -6- effective output capacitance, energy related a c o(er) v ds = 0 v to 480 v, v gs = 0 v - 208 - effective output capacitance, time related b c o(tr) - 651 - total gate charge q g v gs = 10 v i d = 24 a, v ds = 480 v - 150 225 nc gate-source charge q gs -31- gate-drain charge q gd -63- turn-on delay time t d(on) v dd = 480 v, i d = 24 a, v gs = 10 v, r g = 4.4 ? -3060 ns rise time t r -6192 turn-off delay time t d(off) -94141 fall time t f -5887 gate input resistance r g f = 1 mhz, open drain - 0.67 - ? drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the ? integral reverse ? p - n junction diode --47 a pulsed diode forward current i sm --138 diode forward voltage v sd t j = 25 c, i s = 24 a, v gs = 0 v - 0.9 1.2 v body diode reverse recovery time t rr t j = 25 c, i f = i s = 24 a, di/dt = 100 a/s, v r = 25 v - 168 336 ns body diode reverse recovery charge q rr -1.22.4c reverse recovery current i rrm -14-a s d g
SIHG47N60EF www.vishay.com vishay siliconix s13-2236-rev. d, 28-oct-13 3 document number: 91559 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics, t c = 25 c fig. 2 - typical output characteristics, t c = 150 c fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - c oss and e oss vs. v ds v d s , drain-to- s ource voltage (v) i d , drain-to- s ource current (a) 0 25 50 75 100 125 150 0 5 10 15 20 25 30 5.0 v top 15 v 14 v 13 v 12 v 11 v 10 v 9.0 v 8.0 v 7.0 v bottom 6.0 v t j = 25 c v d s , drain-to- s ource voltage (v) 0 5 10 15 20 25 30 0 20 40 60 80 100 i d , drain-to- s ource current (a) top 15 v 14 v 13 v 12 v 11 v 10 v 9.0 v 8.0 v 7.0 v 6.0 v bottom 5.0 v t j = 150 c v gs , g ate-to- s ource voltage (v) i d , drain-to- s ource current (a) 0 30 120 150 0 5 10 15 20 25 60 90 t j = 150 c t j = 25 c v d s = 26 v - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 3.0 t j , junction temperature (c) r d s (on) , drain-to- s ource on re s i s tance (normalized) v = i = gs d 10 v 24 a 1 10 100 1000 10 000 c, capacitance (pf) v d s , drain-to- s ource voltage (v) 0 100 200 300 400 500 600 100 000 v gs = 0 v, f = 1 mhz c i ss = c g s + c gd , c d s s horted c r ss = c gd c o ss = c d s + c gd c i ss c o ss c r ss 0 5 10 15 20 25 30 50 500 5000 0 100 200 300 400 500 600 e o ss (j) c o ss (pf) v d s c o ss e o ss
SIHG47N60EF www.vishay.com vishay siliconix s13-2236-rev. d, 28-oct-13 4 document number: 91559 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 7 - typical gate charge vs. gate-to-source voltage fig. 8 - typical source-drain diode forward voltage fig. 9 - maximum safe operating area fig. 10 - maximum drain cu rrent vs. case temperature fig. 11 - temperature vs . drain-to-source voltage q g , total g ate charge (nc) v gs , g ate-to- s ource voltage (v) 0 4 8 12 16 20 24 0 50 100 150 200 250 300 v = 120 v d s v = 300 v d s v = 480 v d s v s d , s ource-to-drain voltage (v) i s d , rever s e drain current (a) 0.1 1 10 100 1000 0.2 0.4 0.6 0.8 1 1.4 1.8 v = 0 v gs t = 25 c j t = 150 c j 1.2 1.6 v d s - drain-to- s ource voltage (v) i d , drain current (a) 1000 1 10 100 1 10 100 1000 0.01 bvd ss limited i dm limited operation in this area limited by r ds(on) * t c = 25 c t j = 150 c single pulse 100 s 1 ms 10 ms 0.1 5 10 15 20 25 30 35 40 45 25 50 75 100 125 150 i d , drain current (a) t c , ca s e temperature (c) 0 50 600 625 650 675 700 725 775 800 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 v d s , drain-to- s ource breakdown voltage (v) t j , junction temperature (c) 750 i d = 1 ma
SIHG47N60EF www.vishay.com vishay siliconix s13-2236-rev. d, 28-oct-13 5 document number: 91559 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 12 - normalized thermal transient impedance, junction-to-case fig. 13 - switching time test circuit fig. 14 - switching time waveforms fig. 15 - unclamped inductive test circuit fig. 16 - unclamped inductive waveforms fig. 17 - basic ga te charge waveform fig. 18 - gate charge test circuit pul s e time ( s ) 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 normalized effective tran s ient thermal impedance duty cycle = 0.5 0.2 0.1 s ingle pul s e 0.02 0.05 pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f r g i as 0.01 t p d.u.t l v ds + - v dd 10 v var y t p to obtain required i as i as v ds v dd v ds t p q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
SIHG47N60EF www.vishay.com vishay siliconix s13-2236-rev. d, 28-oct-13 6 document number: 91559 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 19 - for n-channel ? ? ? ? ? ? ? ? ? ? vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91559 . p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd
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