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lt8500 1 8500f typical a pplica t ion fea t ures descrip t ion 48-channel led pwm generator with 12-bit resolution and 50mhz cascadable serial interface the lt ? 8500 is a pulse width modulation (pwm) genera - tor with 48 independent channels. each channel has an individually adjustable 12-bit (4096-step) pwm register and a 6-bit (64-step) 50% correction register. all controls are programmable via a simple serial data interface. three banks of 16-channels each can be configured such that they operate 120 out-of-phase with each other. the lt8500 features two diagnostic information flags: synchronization error and open led. the flags are sent, with additional state information, on the serial data interface during status read back. the 50mhz cascadable serial data interface includes buffering and skew-balancing, making the chip suitable for pwm intensive applications such as large screen lcd dynamic backlighting and mono-, multi- and full-color led displays. the lt8500 is also ideally suited to control three lt3595a led drivers. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. a pplica t ions n 3v to 5.5v input voltage n 48 independent pwm outputs n ttl/cmos logic 50mhz serial data interface n 12-bit (4096 steps) pwm width resolution n 6-bit (64 steps) pwm correction (50% of programmed p wm width) n up to 6.1khz pwm frequency (p wmck = 25mhz) n phase-shift option reduces switching noise n directly controls three lt3595a 16-channel led drivers n diagnostic information: sync error/open led flags n 56-pin (5mm 9mm 0.75mm) qfn package n large screen display led backlighting n mono-, multi-, full-color led displays n led billboards and signboards n motor control n industrial control n automated test equipment n robotics 8500 ta01a sdi scki ldiblank pwmck openled sdo sck0 osc pwm[48:1] 48 pwm outputs 5-wire serial data interface diagnostic circuit ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pwm[48:1] pwm[48:1] ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? lt8500 (n) lt8500 (2) lt8500 (1) 48 pwm outputs 48 pwm outputs sdi scki ldiblank pwmck openled sdo sck0 sdi scki ldiblank pwmck openled sdo sck0
lt8500 2 8500f p in c on f igura t ion a bsolu t e maxi m u m r a t ings v cc ............................................................... C0 .3v to 6v sdi, scki, pwmck, openled , ldiblank ......... C 0.3v to lesser of 6v and (v cc + 0.3v) operating junction temperature range (note 2) .................................................. C 40c to 125c storage temperature range .................. C 65c to 150c (note 1) 19 20 21 22 top view 57 gnd uhh package 56-lead (5mm 9mm) plastic qfn 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 39 40 41 42 43 44 45 46 8 7 6 5 4 3 2 1pwm1 pwm24 pwm23 pwm22 pwm21 pwm28 pwm27 pwm26 pwm25 pwm32 pwm31 pwm30 pwm29 pwm20 pwm19 pwm18 pwm17 pwm40 pwm12 pwm5 pwm6 pwm7 pwm8 ldiblank sdi pwmck scko vcc scki sdo openled pwm33 pwm34 pwm35 pwm36 pwm45 pwm2 pwm3 pwm4 pwm13 pwm14 pwm15 pwm16 pwm9 pwm10 pwm11 pwm39 pwm38 pwm37 pwm44 pwm43 pwm42 pwm41 pwm48 pwm47 pwm46 38 37 36 35 34 33 32 31 30 29 9 10 11 12 13 14 15 16 17 18 t jmax = 125c, ja = 35c/w, jc = 5c/w exposed pad (pin 57) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt8500euhh#pbf lt8500euhh#trpbf 8500 56-lead (5mm 9mm) plastic qfn C40c to 125c lt8500iuhh#pbf lt8500iuhh#trpbf 8500 56-lead (5mm 9mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
lt8500 3 8500f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 3.3v, unless otherwise noted. symbol parameter conditions min typ max unit supply v cc v cc operating voltage l 3.0 5.5 v digital inputs: scki, sdi, ldiblank, openled , pwmck v ih v il input logic levels high level voltage low level voltage v cc = 5v v cc = 3.3v v cc = 5v v cc = 3.3v l l l l 4.0 2.7 1.0 0.6 v v v v i in input current pin voltage = v cc or gnd excluding openled C1 1 a r pu openled pull-up resistor v cc = 5.5v 70 100 130 k c in input capacitance (note 4) pin to gnd 3 pf digital outputs: scko, sdo, pwm[48:1] v oh v ol sdo, scko output voltages high level voltage low level voltage i out = C6ma, v cc = 5v i out = C3ma, v cc = 3.3v i out = 6ma, v cc = 5v i out = 3ma, v cc = 3.3v l l l l 4.0 2.7 1.0 0.6 v v v v v oh v ol pwm [48:1] output voltages high level voltage low level voltage i out = C3ma, v cc = 5v i out = C1.5ma, v cc = 3.3v i out = 3ma, v cc = 5v i out = 1.5ma, v cc = 3.3v l l l l 4.0 2.7 1.0 0.6 v v v v ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 3.3v, and all inputs are rail-to-rail unless otherwise noted. symbol parameter conditions min typ max unit f scki data shift clock frequency scki C scki (figure 4) l 50 mhz f pwmck pwmck clock frequency pwmck C pwmck (figure 5) l 25 mhz t wh-scki minimum scki high time (note 3) scki = high 2 ns t wl-scki minimum scki low time (note 3) scki = low 2 ns t wh-ldi ldiblank pulse duration (ldi function) ldiblank = high (figure 4) l 8 5,000 ns t wh-blank ldiblank pulse duration (blank function) ldiblank = high (figure 4) l 50,000 ns t su-sdi sdi-scki setup time (note 3) sdi C scki (figure 4) l 3 ns t hd-sdi scki-sdi hold time (note 3) scki C sdi (figure 4) l 1.75 ns t su-ldi scki-ldiblank setup time (note 3) scki C ldiblank (figure 4) scki 50% duty cycle l 10 ns t hd-ldi ldiblank-scki hold time (note 3) ldiblank C scki (figure 4) l 5 ns t pd-sdo scki-sdo propagation delay (note 3) scki C sdo (figure 4) l 15 25 ns t pd-sck scki-scko propagation delay (note 3) scki C scko (figure 4) l 10 20 ns t hd-sdo scko-sdo hold time (note 3) scko C sdo (figure 4) l 2.75 ns t dc-sck scki-scko duty cycle change (note 4) difference between scki = high time and scko = high time, c load = 25pf C0.2 ns
lt8500 4 8500f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt8500e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt8500i is guaranteed over the full C40c to 125c operating junction temperature range. note 3: propagation delays, setup/hold times and hi times are measured from 50% to 50%. note 4: this parameter is correlated to lab measurements and is not subject to production testing. ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 3.3v, and all inputs are rail-to-rail unless otherwise noted. symbol parameter conditions min typ max unit t pd-pwm pwmck-pwm[48:1] propagation delay (note 3) pwmck C pwm (figure 5) l 32 50 ns t r-sdo sdo, scko rise time (note 4) c load = 25pf, 30% to 70% 2 ns t f-sdo sdo, scko fall time (note 4) c load = 25pf, 70% to 30% 2 ns t r-pwm pwm[48:1] rise time (note 4) c load = 25pf, 30% to 70% 12 ns t f-pwm pwm[48:1] fall time (note 4) c load = 25pf, 70% to 30% 12 ns ti m ing diagra m scki 8500 td01 sdi ldiblank sdo scko t su-sdi t hd-sdi t su-ldi t wh-ldi t hd-ldi 1/f scki t wh-scki t wl-scki t pd-sdo t hd-sdo t pd-sck
lt8500 5 8500f typical p er f or m ance c harac t eris t ics i cc vs v cc , scki = 12mhz, sdi = 6mhz, pwmck = 0mhz i cc vs v cc , scki = 20mhz, sdi = 10mhz, pwmck = 10mhz i cc vs v cc , scki = 50mhz, sdi = 25mhz, pwmck = 25mhz i cc vs v cc , scki = 0mhz, sdi = 0mhz, pwmck = 0mhz i cc vs v cc , scki = 0mhz, sdi = 0mhz, pwmck = 10mhz i cc vs v cc , scki = 0mhz, sdi = 0mhz, pwmck = 25mhz for the i cc vs v cc graphs, the following conditions apply: 23pf load on scko. pwm outputs enabled: duty cycle = 1365/4096, 10pf average load on pwms. v cc (v) 3 i cc (ma) 3.0 2.5 1.5 0.5 2.0 1.0 0 4 8500 g01 5.5 4.5 3.5 5 v cc (v) 3 i cc (ma) 3.0 2.5 1.5 0.5 2.0 1.0 0 4 8500 g02 5.5 4.5 3.5 5 v cc (v) 3 i cc (ma) 3.0 2.5 1.5 0.5 2.0 1.0 0 4 8500 g03 5.5 4.5 3.5 5 v cc (v) 3 i cc (ma) 30 25 15 5 20 10 0 4 8500 g04 5.5 4.5 3.5 5 v cc (v) 3 i cc (ma) 30 25 15 5 20 10 0 4 8500 g05 5.5 4.5 3.5 5 v cc (v) 3 i cc (ma) 30 25 15 5 20 10 0 4 8500 g06 5.5 4.5 3.5 5 v oh vs v cc v ol vs v cc v cc (v) 0 v ol (v) 0.6 0.5 0.3 0.1 0.4 0.2 0 3 8500 g07 6 4 21 5 pwms at 3ma scko, sdo at 6ma pwms at 1.8ma v cc (v) 0 v cc ? v oh (v) 0.6 0.5 0.3 0.1 0.4 0.2 0 3 8500 g08 6 4 21 5 pwms at 3ma scko, sdo at 6ma pwms at 1.8ma
lt8500 6 8500f p in func t ions pwm[48:1] (pins 1 to 33, 42 to 56): pulse width modulated (pwm) output pins. pulse width is determined by com - paring the value in the pwmrsync latches to an internal pwmck counter. outputs are high when the value in the pwmck counter is less than the value in pwmrsync[n]. the pwm frequency is determined by the signal applied to the pwmck pin. openled (pin 34): not open led input pin. this input passes diagnostic information to the host via the status frame. when used with lt3595a led drivers, it connects to the wired-or (open collector) openled outputs which indicate an open in one or more of the led strings. the user can run a self test on the lt8500 to detect which pwm output is associated with an open led string, or other fault. this pin has an internal 100k pull-up to the v cc supply rail. sdo (pin 35): serial data output pin. this pin is the output of the shift register (sr), and cascades data to downstream chips or returns data to the host. scki (pin 36): serial clock input pin. this clock pin pro- vides timing for the serial interface and the calculation of pwm values in the correction multiplier. this clock is independent of pwmck. v cc (pin 37): supply pin. 3.0v to 5.5v. must be locally bypassed with a capacitor to ground. scko (pin 38): serial clock output pin. buffered pass through of scki. this pin cascades the clock to the next chip or to the host. pwmck (pin 39): pwm clock input pin. this pin provides pwm timing for the outputs. each pwm signal is gener - ated by counting the pulses on this clock from zero to the calculated value in the pwm synchronization register (pwmrsync). this clock is independent of scki. sdi (pin 40): serial data input pin. this pin provides serial interface data to issue commands and set up the individual pwm channels. ldiblank (pin 41): latch data in/blank input pin. this is a dual function pin. ldi function: the internal ldi signal is directly con - nected to the ldiblank pin. a logic high on the pin always asserts the ldi function. the rising edge of ldiblank captures the decoded command field (cmd, cr[7:0]) of the shift register (sr[7:0]). the high level of ldiblank latches data from the correction multiplier into the pwm registers (pwmr). when ldiblank is high, status information is loaded into the shift register (sr) to shift out on sdo when the next frame shifts in on sdi. see more details in the operation section. blank function: asserting ldiblank high for more than 50s turns off all pwm[48:1] outputs and resets the chip. to avoid inadvertently resetting the chip, do not assert ldiblank high for more than 5s. gnd (exposed pad pin 57): this is the ground reference for the chip.
lt8500 7 8500f b lock diagra m 8500 bd v cc 37 openled 34 crd, phs, syc, olt, cr[4:7]* sd ld cr[0:7]* ctrl frame data (sr[8:583])* shift register (sr[0:583])* status (cor?s, oled?s) sdi ldiblank pwmck gnd *reverse indexing is used to indicate physical bit order. 40 scki 36 41 39 57 8 288 = {sr[14:19], sr[26, 31],..., sr[578:583]}* 6 cor[n] correction multiplier 288 48 6 576 sel ld ld pwmr[n] en 12 12 12 pwmrsync[n] en 12-bit pwm generation pwmck counter por pd sdo 35 scko 38 pwmxx pwm channel 48 100k figure 1. block diagram
lt8500 8 8500f o pera t ion o verview the lt8500 controls 48 pulse width modulated (pwm[48:1]) outputs, suitable for control applications such as driving three lt3595a led drivers. the chips operation is best understood by referring to the block diagram in figure 1. the major blocks inside the lt8500 are: a 584-bit shift register (sr[0:583]), 48 6-bit correction registers (cor[1:48]), a correction multiplier, 48 pwm channels and a pwmck clock counter. each pwm channel stores data for the associated pwmx output pin and includes a pwm register (pwmr) and a pwm synchronization reg - ister (pwmrsync). the lower 8 bits of the 584-bit shift register are the command register (cr[0:7]) and the rest of the shift register contains the frame data. a comparison of a channels pwmrsync register to the pwmck counter generates the respective pwm output signal. the input of the 584-bit shift register (sr[0]) is connected to the sdi signal. sdi is also an input to the correction multiplier. the output of the 584-bit shift register (sr[583]) is connected to sdo. the user communicates with the part by controlling the serial interface pins sdi, scki and ldiblank. a serial data frame, called a command frame, is shifted into the part on sdi using scki as the clock signal. at the same time, the status frame is shifted out on sdo. a rising edge on the ldiblank pin terminates a frame. a frame consists of a 12-bit data field for each pwm channel, followed by an 8-bit command field, totaling (12 48) + 8 = 584 bits. the data is transmitted with the most significant channel first, and each field is transmitted msb first. the frame formats and timing are illustrated in figures 3 and 4, respectively. there are eight commands, two of which update the pwm[48:1] outputs. the commands are summarized in table 2. within this document, command frames will be referred to by the commands they issue, such as update frame or correction frame. with a 50mhz scki, a single frame can be transmitted in 11.7s (584 sckis + ldi), for a frame rate of 85.5khz. a 25mhz pwmck creates a pwm period (4096 pwmcks) of 164s, or a pwm output frequency of 6.1khz. update frames are used to serially load the 12-bit values for each of the 48 pwm channels. the lt8500 contains a correction multiplier that can automatically scale the 12-bit pwm channel data before its stored. by default, the correction multiplier is enabled and scales incoming channel data according to: pwm out n = chan n (nom) ? 2 3 ? ? ? ? ? ? ? cor n + 32 64 ? ? ? ? ? ? where pwm outn is the number of pwmck cycles that pwm n is high, chan n (nom) is the n th channel field in the frame, and cor n is the n th programmed correction setting (corn = 0 to 63). see table 1 for examples. otherwise, when the correction multiplier is disabled, the incoming data is stored unchanged: pwm outn = chan n (nom) the correction multiplier is disabled by the correction reg- ister disable bit (crd), which is toggled by the correction toggle command (cmd = 0x7x). by default, the correction multiplier is enabled after power-up and the crd bit is low. the result generated by the correction multiplier moves to the respective pwmrsync register after an update frame. an update frame does this either synchronously or asynchronously. a synchronous update frame will copy the data to the pwmr on the subsequent rising edge of ldi which marks the end of the frame, and then from the pwmr to the pwmrsync register at the beginning of a pwm period. a pwm period starts when the free-running pwmck counter is zero. otherwise, the asynchronous update frame will copy the data from the correction mul- tiplier, through the pwmr to the pwmrsync at the same time, on the subsequent rising edge of ldi which marks the end of the frame. as soon as the pwmrsync registers are updated with their new values, the pwm outputs will reflect the update. as mentioned earlier, the pwmr outputs are generated by comparing the respective pwmrsync values to the pwmck counter.
lt8500 9 8500f o pera t ion s tart -u p the lt8500 is ready to communicate after power -up, if the ldiblank pin is low. the pwm[48:1] outputs remain disabled (logic 0) until an output enable frame is sent. the recommended sequence of events for start-up is: 1. apply power and drive ldiblank low. sdo will go low when the on-chip power -on-reset (por) de-asserts. 2. send a correction register frame (cmd = 0x20) on the serial interface. this sets the correction factor on each channel. 3. send an update frame (cmd = 0x00 or cmd = 0x10) on the serial interface. this sets the pulse width of each channel. 4. send an output enable frame (cmd = 0x30) on the serial interface. this enables the modulated pulses on the p wm[48:1] outputs. the pwm clock (pwmck) should be turned on before step 4. the start of a pwm period, when all pwm[48:1] channels turn on, is synchronized to the output enable frame when the outputs are disabled prior to the frame. figure 2. serial interface topologies s erial d ata i nterface the lt8500 has a 50mhz cascadable serial data inter face with full buffering and skew balancing on clock and data. the interface uses a novel 5-wire (ldiblank, scki, sdi, scko, and sdo) topology and can be connected to a variety of digital controllers, such as microcontrollers, digital signal processors (dsps), or field programmable gate arrays (fpgas). topology two topologies shown in figure 2 are supported for cas - cading the lt8500. for higher speeds and a large number of lt8500s, consider the novel 5-wire topology. for lower speeds and few lt8500s, consider the conventional 4-wire topology. whichever topology is used, signal integrity should be carefully evaluated, especially for the clocks. the 5-wire topology eliminates the need for global scki routing and reduces the need for buffer insertion for the scki signal. instead, it provides the scko signal along with the sdo signal to drive the next chip. the skew inside the chip between the scki and sdi signals is balanced internally. the skew outside the chip between the scko and sdo signals can be easily balanced by parallel routing 8500 f02 ldi scki sdi sck0 sdo host controller ldi scki sdi sdo scko lt8500 (1) ldi scki sdi sck0 sdo lt8500 (2) ldi scki sdi sck0 sdo lt8500 (n) ldi scki sdi sdo host controller conventional 4-wire topology novel 5-wire topology ldi scki sdi sdo lt8500 (1) ldi scki sdi sdo lt8500 (2) ldi scki sdi sdo lt8500 (n)
lt8500 10 8500f o pera t ion figure 3. serial data frame format 8500 f03 cor 48, 6 bits cor 1, 6 bits msb lsb msb cr, 8 bits msb lsb x x x x x x x x x x x x pwm 48, 12 bits pwm 1, 12 bits 584 bits msb lsb msb cr, 8 bits msb lsb lsb lsb cor 48, 6 bits cor 1, 6 bits msb cor frame update frame status frame command register (cr): see table 2 for command register decoding. fault = 0, ok = 1 last command openled tested = 1, openled not tested = 0 out-of-sync = 1, ok = 0 phase-shifted = 1, not shifted = 0 correction disabled = 1, correction enabled = 0 lsb msb cr[7:4] lsb 0 0 0 0 0 nol48 0 0 0 0 o lt syc phs crd 0 nol1 nol48-nol1: cr[7:4]: olt: syc: phs: crd: status frame:
lt8500 11 8500f figure 4. serial data input and output timing chart o pera t ion scki 4 input data status data 8500 f04 582 582 583 cr0 cr1 cr0 crd cr1 phs cr2 crd cr1 cor 48 msb (new) cor 48 msb (prior) pwm 48 msb cor 48 msb (new) crd cor 48 msb-1 (prior) cr0 cr0 cr1 x crd phs cr1 cr2 pwm 48 msb pwm 48 msb-1 pwm 48 msb cor 48 msb-1 cor 48 msb-5 cor 48 msb-4 dc 48 msb-3 all correction registers updated from shift register on ldi after a correction frame (cmd = 0x2x) all pwm registers are updated from correction multiplier on ldi after an update frame (cmd = 0x2x or 0x1x) cor 48 msb cor 48 msb 583 0 0 sdi ldi sr[1] cors pwmrs sr[0] sdo t wh-ldi t wl-scki t wh-scki t hd-ldi t su-ldi 1/f sck1 t su-sdi t hd-sdi scko 4 582 582 583 583 0 0 t pd-sck t pd-sdo t hd-sdo
lt8500 12 8500f these two signals between chips. when properly balanced in this way, the scko/sdo timing will meet the timing requirements of scki/sdi on the next cascaded chip, enabling faster clock speeds and more chips in cascade. the host controller sends the sdi signal with the scki signal, and receives the sdo signal with the scko signal. the controller will see skew between scki and scko, and will need to operate on two clock planes depending on the number of cascaded lt8500s and system timing constraints. a duty cycle change (t dc-sck ) will also occur between scki and scko, limiting the number of lt8500s in a chain, depending on scki speed. this change results from a slight difference in propagation delays of the posi- tive and negative edges of scki. ldiblank skew between chips may require balancing in timing critical systems, otherwise the host should increase the delay between scki and ldi to avoid violating ldi to scki setup and hold times (t su-ldi and t hd-ldi ). in summary, the 5-wire topology extends the maximum number of cascadable chips, boosts the series data interface clock frequency, eliminates global scki routing, reduces the need of buf- fer insertion for scki signals, and offers an easier pcb layout. in a low-speed application with a small number of cascaded chips, the 5-wire topology can be simplified to the 4-wire topology by ignoring the scko output. in a 4-wire topology, the ldiblank and scki signals need global routing while the sdi signal only needs local routing between chips. scko is ignored. when a large number of chips are in cascade, or long board traces are used, external clock-tree buffers with corresponding driving capability might be needed for the ldiblank and scki signals to minimize signal skews. the propagation delay caused by the buffer insertion on the scki signal yields the skew between the scki and sdi signals, which usually requires balancing. since both the sdi and sdo signals require the same scki signal to send and receive, the propagation delay between the sdi and sdo signals limits the number of chips in cascade and the series data interface clock frequency. communication figure 3 shows two command frames sent on sdi, and one status frame received on sdo. all the frames have the same 584-bit length and are transmitted with the most significant channel first, and each field is transmitted with msb first. the command frames are sent with the scki signal and the status frame is received with the scko signal. the command field determines the function of a frame, according to table 2. the status frame consists of the four msbs of the last command (cr[7:4]), the open led self test bit (olt), the synchronization error status bit (syc), the phase-shift status bit (phs), the correction register disable status bit (crd), and individual openled fault bits (nol[48:1]), as well as each 6-bit correction register (cor[48:1]). logic zeros fill in the unused bits of the status frame. refer to figure 3. figure 4 illustrates the timing relationship among serial input and serial output signals in more detail. one correc- tion register frame followed by an update frame is sent through the sdi, scki, and ldiblank pins. at the same time, two status frames are received through the sdo, scko, and ldiblank pins. the rising edges of scki shift a frame of data into shift register sr[0:583]. after 584 clock cycles, all bits of data sit in the shift register waiting for the ldi signal. an asynchronous ldiblank high signal captures the decoded 8-bit cmd field (cr[7:0]), executing commands and routing data accordingly. at the same time, a frame of status information, including the 4 msbs of the cmd field (cr[7:4]), status bits, cor registers, and individual open led fault flags, is parallel loaded into the 584-bit shift register and will be shifted out as the next frame shifts in. ldiblank = ldi + blank the ldiblank pin is a dual function input, determined by the duration of a logic high on the pin. ldi is the latch data input, which signals the end of a frame and executes the command in the cmd field (cr[7:0]). the blank signal turns off the pwm[48:1] outputs and performs a global reset of the part, including the shift register in the serial interface. a logic high on ldiblank always asserts ldi, while a logic high greater than the minimum ldiblank pulse duration for blank (t wh-blank ) also asserts blank. blank will never be asserted if the pin is held high less than the maximum ldiblank pulse duration for ldi (t wh-ldi ). between maximum t wh-ldi and minimum t wh-blank , blank becomes asserted at an undetermined time. o pera t ion
lt8500 13 8500f o pera t ion a rising edge on the ldi signal is always interpreted as the end of a frame. the next rising edge of scki after the falling edge of ldiblank is always interpreted as the start of a new frame. an out-of-sync error bit (syc) is provided in the status frame to alert the system if the part saw an ldi unexpectedly. this occurs when ldi and scki are both hi, or when ldi is hi on other than a frame boundary (n ? 584 sckis). the syc bit is for information only, it has no other effect on the part. if the syc bit is set, none of the other data in the status frame is reliable and the effect of the prior frame is unknown; the lt8500 assumes the systems timing of the ldi is correct and considers the next scki as the start of the next frame. openled the openled pin provides status information to the host by reporting its state in the status frame. the state of the pin is captured by each rising edge of pwmck and is reported in two ways. in typical use, the status frame receives the captured state of the pin on the rising edge of the first scki after ldiblank goes low. this state is duplicated 48 times and reported in the lsb of each pwm channel in the status frame. the state will normally be a logic 1 due to the on-chip pull-up resistor. alternatively, the lt8500 supports a diagnostic self test frame (cmd = 0x5x) that reports the openled state differently. in this case, the lt8500 sequentially pulses pwm[1] through pwm[48] high for 64 pwmck cycles each. the state of the openled pin is captured for each channel while the corresponding pwm pin is high. this by-channel data is shifted out in the status frame as the next frame is shifted in. in addition, the status frame will set the open led test bit (olt), indicating that the openled data in the current status frame is from the self test. the status frame will return to typical reporting on the following frame. when the lt8500 is used with the lt3595a, the openled pin and the self test provide a diagnostic routine to identify the location of open led faults. see diagnostic information flags in the applications information section. o utputs after power-up or reset, no p wm[48:1] output will turn on until an output enable frame is sent. the 12-bit pwmck counter is free-running from the pwmck clock when outputs are enabled. when an output enable frame is sent, the pwmck counter increments to one on the second ris - ing edge of pwmck after the rising edge of ldiblank, as shown in figure 5. by default, all outputs with non-zero values in pwmrsync will turn on when the pwmck counter is one. alternatively, if the phase-shift bit (phs) is set, the pwm[48:1] outputs will turn on as illustrated in the phase-shift synchronous updates in figure 6, case a. further discussion of the phase-shift function follows. each subsequent rising edge of pwmck increases the pwmck counter by one. any pwm channel will be turned off when its pwmrsync value is equal to the value in the pwmck counter. an output disable frame resets the pwmck counter immediately after ldi, and turns off all the pwm channels on the next rising edge of pwmck after ldi. figure 5 shows the pwm output enable timing chart. 8500 f05 pwmck ldi, cmd = 0x30 pwm 1 f pwmck 0 1 2 3 t pd-pwm figure 5. pwm output enable timing chart assumes outputs were previously disabled p hase d ifference b etween 16-c hannel b anks by default, the rising edges of all pwm[48:1] channels occur on the same rising edge of pwmck. this event begins a pwm period of 4096 pwmck cycles. the lt8500 provides a phase-shift toggle command (cmd = 0x6x) to reduce system noise and current spikes result - ing from 48 pins switching at once. the function of this command is illustrated in figure 6, case a. in phase-shift mode, the pwm[48:1] outputs are divided into three 16-channel banks that are 120 degrees out-of-phase with each other within a pwm period. this means that channels pwm[48:33] will turn on with the rising edge of pwmck(1), then channels pwm[32:17] will turn on with the rising edge of pwmck(1365), 1/3 of the pwm period, and channels pwm[16:1] will turn on with the rising edge of pwmck(2730), 2/3 of the pwm period.
lt8500 14 8500f o pera t ion pwm c alculation by d igital m ultiplication of c orrection r egister and p wm u pda te v alues the correction multiplier is used to automatically scale the 12-bit pwm channel data before storing the p wm update value for the respective channel. the correction multiplier is disabled by the correction register disable bit (crd), which is toggled by the correction toggle command (cmd=0x7x). when the correction multiplier is disabled, the incoming data is stored unchanged: pw m outn = chan n(nom) the correction multiplier is enabled by default (crd=0) and scales incoming channel data according to: pwm out n = chan n (nom) ? 2 3 ? ? ? ? ? ? ? cor n + 32 64 ? ? ? ? ? ? where pwm outn is the number of pwmck cycles that pwm n is high, chan n (nom) is the n th channel field in the frame, and cor n is the n th programmed correction setting (corn = 0 to 63). see table 1 for examples. the 6-bit cor value sets a multiplier of 0.5x to ~1.5x (exactly 1.484375, or ((63 + 32)/64)) with 64 values and a midrange, signifying a multiple of 1.0, at 32 (0x20). in order to avoid overflow in the pwm registers when the multiplier is greater than 1.0, the nominal pwm update value (chann) is first prescaled on chip by 2/3. this means that the full-scale width for a channel with a mul- tiplier of 1.0 (chann = 4095, corn = 32) will result in a pwm outn width of 4095 ? (2/3) ? 1.0 = 2730, not 4095. so, a correction multiplier of ~1.5 (cor n = 63) yields a corrected pwm width of 4052 = 4095 ? (2/3) ? 1.484375. the pwm outn width is always rounded to the nearest whole number. table 1 shows examples of pwm calculations for selected register values. this means the maximum pwm duty cycle with crd=0 is 4052/4096, and with crd=1 it is 4095/4096. c ommand d escrip tions the lt8500 implements eight commands, outlined in t able 2. the commands (cmd) are encoded in the eight lsbs of a command frame, and so reside in the eight lsbs of the shift register when a frame has been completely shifted in. the command field is executed by the rising edge of ldi. only the four msbs of the command field are decoded for commands. synchronous update frame: cmd = 0x0x a synchronous update frame updates pwm[48:1] with the data in the frame, after processing through the correction multiplier. the pwmr is updated when ldiblank goes high. the pwmrsync register will be written from the pwmr synchronously to the start of the pwm period (on pwmck 1). this command eliminates shortened pwm runt pulses. the value in the pwmrsync registers will update the pwm outputs on the next rising edge of pwmck. examples are shown in figure 6, cases b and e. table 1. example pwm width calculations (base 10) with correction enabled (crd = 0) a pwm update value sent on sdi b prescaled pwm (a ? 2/3) c correction register (cor) value d multiplier (c + 32)/64 e pwm width (b?d) (in units of t pwmck ) 3 2 63 1.484375 3 120 80 63 1.484375 119 120 80 32 1.0 80 120 80 0 0.5 40 1200 800 63 1.484375 1188 1200 800 32 1.0 800 1200 800 0 0.5 400 4095 2730 63 1.484375 4052 4095 2730 32 1.0 2730 4095 2730 0 0.5 1365
lt8500 15 8500f asynchronous update frame: cmd = 0x1x an asynchronous update frame updates pwm[48:1] with the data in the frame, after processing through the correc- tion multiplier. the pwmr is updated when ldiblank goes high. the pwmrsync register will be written immediately (asynchronously), through the pwmr, when ldi is high. the value in the pwmrsync registers will update the pwm outputs on the next rising edge of pwmck. examples are shown in figure 6, cases c and f. correction frame: cmd = 0x2x a correction frame updates the correction registers (cor) with the six msbs of each channels data field in the frame. the cors are used by the correction multiplier to adjust the pwm width, prescaled by 2/3, by a multiplier of between 0.5 and ~1.5. example pwm width calculations are shown in table 1. in typical applications, this com - mand will only be run once after power-up to initialize the system. therefore, a correction frame will not update the pwm outputs. the update frame that follows a correction frame will reflect the cor update. output enable frame: cmd = 0x3x an output enable frame starts a pwm period, and enables the pwm outputs, on the second pwmck edge after ldiblank goes high. there is no effect on either sdo or scko. the data in the output enable frame is irrelevant to the command, but allows a daisy chain of lt8500s to function properly. output disable frame: cmd = 0x4x an output disable frame immediately resets the pwmck counter when ldi goes high, and disables the pwm outputs on the next rising edge of pwmck. there is no effect on either sdo or scko. the data in the output disable frame is irrelevant to the command, but allows a daisy chain of lt8500s to function properly. self test frame: cmd = 0x5x the self test frame can be used for diagnostics on each pwm[48:1], including identifying open led strings on an lt3595a. after ldiblank goes hi, the lt8500 pulses pwm[1] through pwm[48] sequentially for 64 pwmck cycles each. the state of the openled pin is captured for each channel while the corresponding pwm pin is high. this by-channel data is subsequently shifted out in the status frame. in addition, the status frame will set the open led test bit (olt) to confirm that the openled data in the current status frame is from the self test. for all other commands, the state of the openled pin is captured once on the first scki of the frame. the same value is then reported in the status frame on all 48 channels. the data in the self test frame is irrelevant to the command, but allows a daisy chain of lt8500s to function properly. o pera t ion table 2. command register decoding cmd (cr[7:0]) name summary frame data 0000_xxxx synchronous update frame update pwms synchronously to pwm period pwm update by channel 0001_xxxx asynchronous update frame update pwms asynchronously to pwm period pwm update by channel 0010_xxxx correction frame set pwm correction factor correction by channel 0011_xxxx output enable frame enable pwm outputs dont care 0100_xxxx output disable frame disable (drive low) pwm outputs dont care 0101_xxxx self test frame initiates self test dont care 0110_xxxx phase-shift toggle frame toggle 16-channel bank 120 phase-shift (phs) dont care 0111_xxxx correction toggle frame toggle correction disable bit in multiplier (crd) dont care 1xxx_xxxx reserved do not use C
lt8500 16 8500f o pera t ion phase-shift toggle frame: cmd = 0x6x the phase-shift toggle frame toggles the phase-shift (phs) bit, which is off by default. when phs is set, it sets the rising edges of the pwm outputs, by banks of 16 chan - nels, out-of-phase with each other by 120 degrees. this means that channels pwm[48:33] will start the pwm cycle with a rising edge at the beginning of a pwm period, then channels pwm[32:17] will start their pwm cycle 1/3 of the time into a pwm period, and channels pwm[16:1] will start 2/3 of the time into a pwm period. the state of the phs bit is returned in every status frame. the data in the phase-shift toggle frame is irrelevant to the command, but allows a daisy chain of lt8500s to function properly. correction toggle frame: cmd = 0x7x the correction toggle frame toggles the correction register disable (crd) bit, which is off by default. when crd is set, it disables use of the correction registers (cors) in the correction multiplier, instead multiplying the incoming data from sdi by 1. this causes the data in an update frame to reach the pwmrsync registers unchanged. the state of the crd bit is returned in every status frame. the data in the correction toggle frame is irrelevant to the command, but allows a daisy chain of lt8500s to function properly. examples of pwm updates for selected cases figure 6 shows examples of the effect of various commands on the pwm output waveforms. these example waveforms assume all three channels shown are always programmed for the same pwm width. for each case, a representative channel is shown from each of the three 16 channel banks, pwm[48:33], pwm[32:17], and pwm[16:1]. case a illustrates the phase-shift mode in steady-state, with pwms programmed for a width of 256 pwmck cycles. pwm[48], from bank 2, rises at the beginning of the pwm period. pwm[32], from bank 1, rises 1/3 of the way into the pwm period of bank 2, or 1365 pwmck cycles later. pwm[16], from bank 0, rises 2/3 of the way into the pwm period of bank 2, or 2730 pwmck cycles later. case b illustrates a synchronous update frame (cmd = 0x0x) while in phase-shift mode, as in case a. the ldi signal goes active 512 pwmck cycles into the pwm period, after pwm[48] has turned off. the update frame programs a pwm width of 1024, but the synchronous update command prevents a channel from updating except at the beginning of its pwm period. as a result, pwm[48] remains low until the next pwm period, when the updated width drives it high for 1024 pwmck cycles. pwm[32] begins its pwm period at pwmck 1365, and pwm[16] starts at pwmck 2730, both updated to 1024 pwmck cycles. case c illustrates an asynchronous update frame (cmd = 0x1x) while in phase-shift mode, as in case a. the ldi signal goes active 512 pwmck cycles into the pwm period, after pwm[48] has turned off. the update frame programs a pwm width of 1024, and because it is an asynchronous update, pwm[48] immediately rises and stays high until pwmck 1024. pwm[32] and pwm[16] (and all pwms) are also updated, but no rising edge occurs until their pwm period begins due to the phase-shifting. case d illustrates the default (not phase-shifted) mode in steady-state. all pwm outputs rise on the same pwmck edge at the beginning of the pwm period. case e illustrates a synchronous update frame (cmd = 0x0x) without phase-shifting, as in case d. the ldi signal goes active 512 pwmck cycles into the pwm period, after the pwms have turned off. the update programs a pwm width of 1024, but the synchronous update command prevents a channel from updating except at the beginning of its pwm period. as a result, all pwms remain low until the next pwm period, when the updated width drives them high for 1024 pwmck cycles. case f illustrates an asynchronous update frame (cmd = 0x1x) without phase-shifting, as in case d. the ldi signal goes active 512. pwmck cycles into the pwm period, after the pwms have turned off. the update programs a pwm width of 1024, and because it is an asynchronous update, all pwms immediately rise and stay high until pwmck 1024.
lt8500 17 8500f figure 6. examples of pwm outputs for selected command cases o pera t ion 8500 f06 pwm [48] pwm [32] pwm [16] 256 ? t pwmck 512 ? t pwmck 2730 ? t pwmck 1365 ? t pwmck pwm [48] pwm [32] pwm [16] ldi pwm [48] pwm [32] pwm [16] pwm [48] pwm [32] pwm [16] pwm [48] pwm [32] pwm [16] pwm [48] pwm [32] pwm [16] 4096 ? t pwmck 1024 ? t pwmck case a: steady state with phase-shift case c: asynchronous update with phase-shift case d: default steady state (no phase-shift) case e: synchronous update (no phase-shift) case f: asynchronous update (no phase-shift) case b: synchronous update with phase-shift ldi
lt8500 18 8500f a pplica t ions i n f or m a t ion this section is illustrated with an led dimming applica- tion, but is relevant to other applications as well. the lt8500 provides 48 pwm outputs, such as for driving three lt3595a led drivers. the lt8500 provides an led dot correction function using digital multiplication of the correction register (cor) and the pwm update value, which is prescaled by 2/3. this results in a dot corrected pwm duty cycle. optionally, the pwm update can be written directly (unchanged) by setting the correction register disable bit (cmd = 0x7x). when this bit is set, the multiplication is bypassed and dot correction, if any, must be calculated off-chip. the pwm duty cycle in this case will be the nominal value sent in the update frame, divided by 4096. the part provides a status frame with openled and cor data for each channel, and global state data indicating self testing (such as for open leds), out- of-sync error, phase-shift status, and direct data status. the status frame is shifted out of the part whenever a new frame is shifted in. an on-chip self test is available (cmd = 0x5x) to determine which channel is responsible for a fault, such as open leds. the openled pin and self test are especially suited for use with the lt3595a. in this application, the self test will identify which channels have opens in their led strings. this applications information section serves as a guideline for avoiding common pitfalls for the typical application. setting grayscale by pwm updates although adjusting the led current changes its luminous intensity, or brightness, it will also affect the color match - ing between led channels by shifting the chromaticity coordinate. the best way to adjust the brightness is to control the amount of led on/off time by pulse width modulation (pwm). the lt8500 can adjust the brightness for each channel independently. the 12-bit pwm registers (pwmr), used for grayscale (gs) dimming, results in 4095 different brightness steps from 0% to 99.98%. the brightness level, or pwm duty cycle, gs n % for channel n can be calculated as: gs n %= gsr n (calc) 4096 ? 100% where gsr n (calc) is the nth calculated grayscale register (same as pwmr) setting (gsr n (calc) = 0 to 4052 with dot correction enabled). setting dot correction the lt8500 can adjust the pwm duty cycle for each chan - nel independently. the duty cycle adjustment, also called dot correction, is mainly used to calibrate the brightness deviation between led channels. the 6-bit (64 values) dot correction registers (dcr, same as cor) adjust each pwm duty cycle from 0.5x to ~1.5x of the duty cycle, prescaled by 2/3, sent to the grayscale register (gsr) according to pwm out n = chan n (nom) ? 2 3 ? ? ? ? ? ? ? cor n + 32 64 ? ? ? ? ? ? where pwm outn is the nth pwm duty cycle, gsr n (nom) is the nominal grayscale value sent to the nth channel and dcr n is the nth programmed dot correction setting (dcr n = 0 to 63). cascading devices and determining serial data interface clock in a large lcd backlighting or led display system, mul - tiple lt8500 chips can be easily cascaded to drive all led drivers, such as the lt3595a, and their associated led strings. the lt8500 adopts a novel 5-wire topology, which balances clock skew and eases pcb layout. the time required to send a set of cascaded frames is 584 scki cycles per lt8500, plus another cycle time for ldi. assuming ldi is externally balanced, the minimum serial data interface clock frequency ? sck for a large display system can be calculated as: ? sck = [(n chips ? 584) + 1] ? ? refresh where n chips is the number of cascaded lt8500s and ? refresh is the refresh rate of the whole system. status frame information the status frame is captured and shifted out of sdo as a new data frame shifts in on sdi. the format of a status frame is shown in figure 5. with the exception of the diagnostic flags (syc and nol[48:1]), the data in the status frame does not change without a command from
lt8500 19 8500f the user interface. it can therefore be monitored to con - firm proper communication with the chip. the following non-diagnostic status information is continually provided in the status frame: dot correct registers for each channel (cor[48:1]), open led testing bit (olt), phase-shift bit (phs), correction register disable (crd) bit. there are five unused bits, [5:1], in the field associated with each channel, all of which are always set to logic zero. diagnostic information flags the lt8500 features two kinds of diagnostic information flags: global out-of-sync error (syc) and 48 individual open led flags (nol[48:1]). an out-of-sync error occurs when the part sees an ldi signal unexpectedly, whether before 584 scki clocks, or coinciding with scki high. either of these events can corrupt the data and the state of the chip. the syc bit is available in every status frame to notify the system if an erroneous ldi was seen since the first rising edge of scki of the last frame. a series of multiple ldis between frames, with no scki, is not an out-of-sync error. recovery from an out-of-sync error may require the user to completely rewrite the data and state of the chip. the ldi signal resets the serial interface. the openled bits, nol[48:1], are well suited for use with the lt3595a, and indicate an open circuit has been detected on at least one of the 48 led strings driven by the three lt3595as. the part monitors the three lt3595a wired-or openled pins that detect open led strings for each lt3595a. when one of the lt3595as detects an open led string, it will pull openled low during the pwm high time for that led string. the state of openled is captured by the lt8500 on the rising edge of the first scki of a new frame (after ldi). since scki and pwmck are asynchronous, the detection of an open led string by this method is a probability function dependent on the frame rate and pwm duty cycle. if a new frame begins when the pwm pin associated with an open led string is high, the openled pin will be driven low and captured in the status register, but if a new frame begins when the associated pwm pin is low, the openled pin will be pulled high and the status register will capture a default high. when a low openled pin is captured, signaling an open, each of the 48 openled (nol[48:1]) status flags will be cleared. upon detecting this condition in the status frame, or as a polling strategy, the host may request an led self test (cmd = 0x5x), where the lt8500 will test each channel to determine which, if any, is open. the test drives each pwm pin high, one at a time, in order, for 64 pwmck cycles each, and captures the cor - responding value on the openled pin for the associated pwm channel. these results will overwrite the nol flags in the status frame and the open led test bit (olt) will be set in the status frame to indicate that the nol data in this status frame is given by channel. in the next frame, the olt bit will be cleared and all 48 nol bits will again reflect the state of the openled pin. pcb layout guidelines the following guidelines should be considered when de- signing printed circuit boards (pcbs) using the lt8500. these guidelines are more important as clock speeds and daisy chain sizes increase. 1. match the line lengths and delays between sdi and scki to each lt8500. 2. ensure the timing of ldi to each chip meets scki to ldi setup and hold requirements. in a 5-pin topology, scki is delayed by each chip in the daisy chain, so ldi may need extra delay to match the delayed scki down the chain. see the discussion on topology in the operation section. 3. avoid cross talk between the communication signals (sdi, scki, ldi, sdo, scko) and the pwms. even though the pwms signals toggle at a slow rate, all of their rising edges can occur within a few nanoseconds of each other. 4. buffer the signals returning to the host if their paths are long. 5. hi gh speed techniques: standard high speed pcb design techniques should be used on high frequency clock and data lines. these include short path lengths, shielding of high speed data cables and traces, minimized parasitic capacitance, and reducing antennas and reflections. 6. a ceramic bypass capacitor should be placed close to the v cc pin. a pplica t ions i n f or m a t ion
lt8500 20 8500f typical a pplica t ions four typical applications are shown in figures 7 to 10. figures 7 and 8 illustrate the 5-pin and 4-pin topologies for daisy chains as discussed earlier in this data sheet. figure 9 illustrates a single lt8500 controlling 48 resistor ballasted led strings. figure 10 illustrates a novel use of the lt8500 as a 48-channel digital-to-analog converter (dac). using a simple rc filter on each pwm output, the resulting converter has very good error characteristics as shown in the accompanying differential linearity error (dle) and integrated linearity error (ile) charts (figures 11 and 12). the dle measurements were taken from an all codes test, and were compensated for power supply variation on v cc of less than 0.01% over the course of the test. the ile is simply the sum of all previous com- pensated dle measurements. the units of the dle and ile measurements are in pwm lsbs.
lt8500 21 8500f typical a pplica t ions figure 8. lt8500 daisy chain driving lt3595as using 4-pin topology figure 7. lt8500 daisy chain driving lt3595as using 5-pin topology 8500 ta03 sdi scki ldiblank pwmck v cc scki v cc rset gnd 3.3v v cc 40v sdo sck0 lt8500 16 16 lt3595a r1 30k pwm1-16 pwm1-16 v in pwm17-32 gnd pwm33-48 openled openled v cc rset gnd v cc lt3595a r2 30k pwm1-16 v in openled v cc rset gnd v cc lt3595a r3 30k pwm1-16 v in openled sdi scki ldiblank pwmck v cc ldi pwmck v cc sdi ldi pwmck v cc v cc rset gnd 3.3v v cc sdo sck0 sdo lt8500 lt3595a r1 30k pwm1-16 pwm1-16 v in pwm17-32 pwm33-48 openled openled v cc rset gnd v cc lt3595a r2 30k pwm1-16 v in openled v cc rset gnd v cc lt3595a r3 30k pwm1-16 v in openled ? ? ? ? gnd 16 16 16 16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8500 ta02 sdi scki ldiblank pwmck v cc v cc rset gnd 3.3v v cc 40v sdo sck0 lt8500 gnd lt3595a r1 30k pwm1-16 pwm1-16 v in pwm17-32 pwm33-48 openled openled v cc rset gnd v cc lt3595a r2 30k pwm1-16 v in openled v cc rset gnd v cc lt3595a r3 30k pwm1-16 v in openled sdi scki ldiblank pwmck v cc ldi pwmck v cc sdi scki ldi pwmck v cc v cc rset gnd 3.3v v cc sdo sck0 sdo sck0 lt8500 16 16 16 gnd lt3595a r1 30k pwm1-16 pwm1-16 v in pwm17-32 pwm33-48 openled openled v cc rset gnd v cc lt3595a r2 30k pwm1-16 v in openled v cc rset gnd v cc lt3595a r3 30k pwm1-16 v in openled 16 16 16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
lt8500 22 8500f typical a pplica t ions figure 9. single lt8500 driving 48 resistor ballasted led strings from a v dd rail figure 10. single lt8500 implementing 48 digital-to-analog converter (dac) channels 8500 ta04 lt8500 host v cc pwmck openled pwmck ok to float ok to float sdi scki 3.0v to 5.5v ldiblank sdo scko gnd m1 pwm1 pwm48 ? ? ? ? ? ? ? ? ? ? cmldm7003 m48 v dd 12v v dd ? ? ? 8500 ta05 lt8500 host v cc pwmck openled pwmck ok to float ok to float sdi scki 3.0v to 5.5v ldiblank sdo scko gnd pwm1 pwm48 ? ? ? ? ? ? ? ? ? ? 100k 1f analog out1 100k 1f analog out48 figure 11. dac differential linearity error (dle) figure 12. dac integrated linearity error (ile) pwm width code 0 dle (pwm lsb) 1.0 0.8 0.4 0 0.6 0.2 ?0.2 ?0.6 ?0.4 ?0.8 ?1.0 1536 8500 ta06 4096 2048 2560 3072 1024512 3584 pwm width code 0 ile (pwm lsb) 1.0 0.8 0.4 0 0.6 0.2 ?0.2 ?0.6 ?0.4 ?0.8 ?1.0 1536 8500 ta07 4096 2048 2560 3072 1024512 3584
lt8500 23 8500f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion uhh package 56-lead (5mm 9mm) plastic qfn (reference ltc dwg # 05-08-1727 rev a) 5.00 0.10 (2 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 55 1 2 bottom view?exposed pad 3.45 0.10 7.13 0.10 6.80 ref 9.00 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 0.20 0.05 (uh) qfn 0406 rev a 0.40 bsc 0.200 ref 0.200 ref 0.00 ? 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 3.60 ref 0.40 0.10 0.00 ? 0.05 0.75 0.05 0.70 0.05 0.40 bsc 6.80 ref (2 sides) 3.60 ref (2 sides) 4.10 0.05 (2 sides) 5.50 0.05 (2 sides) 7.13 0.05 3.45 0.05 8.10 0.05 (2 sides) 9.50 0.05 (2 sides) 0.20 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer uhh package 56-lead plastic qfn (5mm 9mm) (reference ltc dwg # 05-08-1727 rev a) 56
lt8500 24 8500f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2011 lt 0611 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt3746 55v, 1mhz 32-channel full featured 30ma step-down led driver v in(min) = 6v, v in(max) = 55v, v out(max) = 13v, dimming = 5,000:1 true color pwm, i sd < 1a, package 5mm 9mm qfn-56 lt3595/ lt3595a 45v, 2.5mhz 16-channel, 50ma full featured boost led driver v in(min) = 4.5v, v in(max) = 45v, v out(max) = 45v, dimming = 5,000:1 true color pwm, i sd < 1a, package 5mm 9mm qfn-56 lt3754 60v, 1mhz boost 16-channel, 50ma led driver with true color 3,000:1 pwm dimming and 2% current matching v in(min) = 4.5v, v in(max) = 40v, v out(max) = 60v, dimming = 3,000:1 true color pwm, i sd < 1a, package 5mm 5mm qfn-32 lt3598 44v, 1.5a, 2.5mhz boost 6-channel, 30ma led driver v in(min) = 3v, v in(max) = 30v(40v max ), v out(max) = 44v, dimming = 1,000:1 true color pwm, i sd < 1a, package 4mm 4mm qfn-24 lt3599 44v, 2a, 2.5mhz boost 4-channel, 120ma led driver v in(min) = 3v, v in(max) = 30v(40v max ), v out(max) = 44v, dimming = 1,000:1 true color pwm, i sd < 1a, package 4mm 4mm qfn-24 single lt8500 driving 48 resistor ballasted led strings from a v dd rail 8500 ta08 lt8500 host v cc pwmck openled pwmck ok to float ok to float sdi scki 3.0v to 5.5v ldiblank sdo scko gnd m1 pwm1 pwm48 ? ? ? ? ? ? ? ? ? ? cmldm7003 m48 v dd 12v v dd ? ? ?

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