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rt8100 preliminary 1 ds8100-03 august 2007 www.richtek.com features z z z z z analogous current mode design z z z z z 2.5v to 12v switching source power z z z z z 0.8v to 3.3v output voltage regulation z z z z z adjustable v in feed-forward ramp slope z z z z z adjustable operation frequency z z z z z precise core voltage regulation z z z z z precise dcr current sensing with high quality capacitor, x7r z z z z z 1.5% system accuracy z z z z z input voltage : 12v and 5v bias z z z z z enable function z z z z z rohs compliant and 100% lead (pb)-free z z z z z over current protection z z z z z external soft start setting z z z z z operation frequency up to 1.0mhz z z z z z dual mode voltage control ` tracking mode ` stand-alone mode z z z z z output current indication z z z z z 16-lead vqfn package applications z mb memory and chipset core power z middle-high graphic card gpu and memory core power z general-purpose fields including server, nb, bare-bone and mini-system synchronous buck pwm dc/dc with dual voltage control mode general description the rt8100 is an advanced dc/dc synchronous buck pwm controller with several innovative functions for specific customer ? s asic only. the part features richtek ? s innovative design and topology say ? analogous current mode ? for current sensing and full functions for various applications including adjustable soft start, free-run and adjustable operation frequency and enable; the part is with design of 12v+12v boot strapped driver which is capable to drive up to 20amp output current; moreover the part is with implementation of accuracy dcr current sensing topology. there are several specific features implemented and reserved for the specific customer ? s special applications including dual v core control mode including tracking and stand-alone mode, and output current indication. the part is proposed with a small footprint of vqfn-16l 3x3 package. pin configurations ordering information (top view) vqfn-16l 3x3 note : richtek pb-free and green products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ` 100% matte tin (sn) plating. package type qv : vqfn-16l 3x3 (v-type) operating temperature range p : pb free with commercial standard g : green (halogen free with commer- cial standard) rt8100 5vsb lgate 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 rr i_ind rt pi ss pvcc fb csn csp comp phase 12vcc boot ugate gnd 17
rt8100 preliminary 2 ds8100-03 august 2007 www.richtek.com typical application circuit boot ugate phase lgate rr 12vcc 5vsb pvcc rt8100 15 4 16 1 11 12 13 14 csp csn comp pi v in 8 5 6 v out 10 2 ss rt i_ind fb 12v cc 5vsb 5vsb 9 3 7 opt. figure 1. 12v-5v pi application circuit figure 2. 12v-5v internal v ref application circuit boot ugate phase lgate rr 12vcc 5vsb pvcc rt8100 15 4 16 1 11 12 13 14 csp csn comp pi v in 8 5 6 v out 10 2 ss rt i_ind fb 12v cc 5vsb pi 9 3 7 0 nc 0
rt8100 preliminary 3 ds8100-03 august 2007 www.richtek.com figure 3. single 5v pi application circuit figure 4. single 5v internal v ref application circuit boot ugate phase lgate rr 12vcc 5vsb pvcc rt8100 15 4 16 1 11 12 13 14 csp csn comp pi v in 8 5 6 v out 10 2 ss rt i_ind fb 5vsb 5vsb pi 9 3 7 phase 0 nc boot ugate phase lgate rr 12vcc 5vsb pvcc rt8100 15 4 16 1 11 12 13 14 csp csn comp pi v in 8 5 6 v out 10 2 ss rt i_ind fb 5vsb 9 3 7 opt. 0 phase 5vsb 5vsb
rt8100 preliminary 4 ds8100-03 august 2007 www.richtek.com functional pin description 5vsb(pin 1), 12vcc (pin 16) the 5vsb pin is the external standby 5v power. the 12vcc pin is the external 12v power. rt (pin 2) timing resistor. connect a resistor from rt to gnd to set the clock frequency. the free running frequency is 200khz. i_ind (pin 3) current indicating pin. this pin uses voltage level to indicate the current of inductor. connect this pin with a resistor to ground to set the voltage. i_ ind = 4 x i x i x : internal gm sensed current, please refer to the application information. rr (pin 4) ramp resistor. this pin is used to set the ramp voltage. connecting a resistor from this pin to the converter input power sets the ramping slope of the control loop of the converter. since it is connected to the converter input power, the ramp slope is input-feed-forwarded. as v in > 1.8v, rr pin is enabled for ramp setting. csn (pin 5) current sense negative input. this pin is negative input node of the current sense amplifier used for dcr current sensing. connect this pin with a resistor to the output node. csp (pin 6) current sense positive input. this pin is positive input nodes of the current sense amplifier used for dcr current sensing. connect this pin to the junction of the filter resistor and capacitor. comp (pin 7) compensation pin. this pin is the o utput node of the erro r amplifier. fb (pin 8) feedback pin. this pin is negative input pin of the error amplifier. pi (pin 9) external reference voltage pin. this pin sets the voltage of fb pin when close loop. stand_alone : pull high to 5vsb tracking : connect to external reference voltage. the pi pin will sink 4ma for 15 s when the ocp function acts. ss (pin 10) soft-start pin. this pin provides soft-start function for its controller. the comp voltage of the converter follows the ramping voltage on the ss pin. pvcc (pin 11) driver power. lgate (pin 12) lower gate drive. this pin drives the gate of the lowside mosfet. phase (pin 13) this pin is return node of the high-side driver. connect this pin to high-side mosfet source together with the low- side mosfet drain and the inductor. ugate (pin 14) upper gate drive. this pin drives the gate of the highside mosfet. boot (pin 15) bootstrap power pin. this pin powers the high-side mosfet driver. connect this pin to the junction of the bootstrap capacitor. gnd [exposed pad (17)] the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation.
rt8100 preliminary 5 ds8100-03 august 2007 www.richtek.com function block diagram operation rt8100 is a highly flexible, high performance and high precision synchronous buck controller specifically designed for high-end graphic core power supply as well as ddr applications, with highly reduced external components and costs. rt8100 uses richtek proprietary analogous current mode tm topology which mimics the traditional peak current mode by sensing the valley current of the inductor via dcr sensing techniques and simulating the current ramp with an artificial ramp set externally. the analogous current mode topology benefits all the advantages of peak current mode converter with much higher noise immunity than conventional one. since the compensation is easier and with less constraint than that in voltage mode, using low esr output capacitor as mlcc is possible, which therefore dramatically reduce the board size as well as the cost and has better transient response due to higher control bandwidth. rt8100 also adopts v in feedfoward for ramp setting, which decreases the complexity for compensation by keeping the modulator gain constant along line variations. the wide input voltage range of the converter ranges from 3.3v to 12v. the output voltage can be set from 0.8v to 3.3v with external resistor divider. the power sequence of rt8100 includes : 1 : por function 2 : v in power supply detection 3 : pi pin setting to enable the whole chip. the external elements selection of rt8100 includes : 1 : rt pin resister to gnd to set the operation frequency of the chip. 2 : csn pin resister to set the current gain(ratio of inductance current i l and sensed current ix). 3 : rr pin resister to v in to set the slope of the v in feed forward ramp and the effective slope compens ation of current mode. 4 : use r csn resister to set the over current level. 5 : capacitor at ss pin to set the soft-start time. 6 : type two compensation at comp pin. en & v in detection soft stsrt pwm logic ramp current generator power_sel v ref_sel oscillator free running 200khz current to voltage converter v ref 5vsb lgate clk phase pi rt csn csp rr i_ind ss pvcc 12vcc boot ugate gnd + - + - + - s/h s/h ocp gm to rr pin pwmcp clk comp fb por driver pvcc x4
rt8100 preliminary 6 ds8100-03 august 2007 www.richtek.com power on reset the por circuitry monitors the supply voltage of the chip. when the chip power supply exceeds 4.2v, the chip releases the reset state and works according to the settings. once the supply voltage is lower than 4.0v, por circuitry resets the chip. v in detection the v in detection circuitry monito rs the switching power source when power up. as v in > 1.8v, rr pin is enabled for ramp setting and the chip is in ramp setting mode. the voltage at rr pin will be about 0.5v. otherwise, the chip will be in v in detection mode and rr pin is disabled for ramp setting until v in > 1.8v. in v in detection mode, the ugate and lgate will be off and ss will be pulled low by a constant current of 10ua. the chip will enter the ramp setting mode and ss will re-softstart when v in > 1.8v. enable after por reset, the chip monitors the voltage of pi pin. when pi is higher than 0.3v, the chip is e nabled. the chip is disabled when v pi is lower than 0.3v. with a precise threshold voltage, the pi pin can be used for power sequence. soft-start a constant current of 10ua starts to charge the capacitor connected to ss pin right after the chi p has been powered up and enabled. the ramp voltage on ss pin is also used to clamp the comp voltage during soft-start, which automatically constraints the output current due to the nature of current mode topology. this brings up sma ller inrush current and smooth output voltage ramp. the ss pins are also used as the timer during ocp hiccup. frequency setting the converter switching frequency is programmed by connecting a resistor from the rt pin to gnd. the frequency vs. r rt plot is shown in ? typical operating characteristics ? . output voltage setting and control control loops consist of an error amplifier, a pulse width modulator, current feed back components, a gate driver and power components. the internal high accuracy bias provides the reference voltage of 0.8v at the non-inverting input of both error amplifiers. the output voltage is programmed by using a voltage divider at output and feeding the voltage division back to corresponding error amplifiers. as conventional current mode pwm controller, the output voltage is locked at the v ref of error amplifier and the error signal is used as the control signal of pulse width modulator. the pwm signals are generated by comparison of ea output and current ramp waves. power stage transforms v in to output by pwm signal on-time ratio.
rt8100 preliminary 7 ds8100-03 august 2007 www.richtek.com electrical characteristics parameter symbol test conditions min typ max units supply input 12v cc 4.5 12 15 power supply voltage 5v sb -- 5 -- v power on reset v 5vsbrth 3.8 4.2 4.4 v power on reset hysteresis v 5vsbhys -- 0.3 -- v on v en -- 0.3 -- v pi threshold hysteresis v en -- 50 -- mv power supply current i vcc 5v sb = 5v, 12v cc = 12v, v in = 0v -- 10 -- ma soft start soft start current i ss 8 10 15 a to be continued (v in = 12v, t a = 25 c unless otherwise specified) absolute maximum ratings (note 1) z supply voltage, v cc -------------------------------------------------------------------------------------- 16v z boot, v boot - v phase ------------------------------------------------------------------------------------ 16v z phase to gnd dc ------------------------------------------------------------------------------------------------------------- ? 5v to 15v < 200ns ------------------------------------------------------------------------------------------------------ ? 10v to 30v z boot to phase ------------------------------------------------------------------------------------------ 15v z boot to gnd dc ------------------------------------------------------------------------------------------------------------- ? 0.3v to v cc +15v < 200ns ------------------------------------------------------------------------------------------------------ ? 0.3v to 42v z ugate ------------------------------------------------------------------------------------------------------- v phase - 0.3v to v boot + 0.3v z lgate ------------------------------------------------------------------------------------------------------- gnd - 0.3v to v cc + 0.3v z input, output or i/o voltage ------------------------------------------------------------------- ---------- gnd-0.3v to 7v z power dissipation, p d @ t a = 25 c vqfn-16l 3x3 --------------------------------------------------------------------------------------------- 1.47w z package thermal resistance (note 4) vqfn-16l 3x3, ja ---------------------------------------------------------------------------------------- 68 c/w z junction temperature ------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) --------------------------------------------------------------- 260 c z storage temperature range ---------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 2) hbm (human body mode) ------------------------------------------------------------------------------ 1.5kv mm (ma chine mode) -------------------------------------------------------------------------------------- 150v recommended operating conditions (note 3) z supply voltage, v cc -------------------------------------------------------------------------------------- 12v 10% z ambient temperature range ---------------------------------------------------------------------------- 0 c to 70 c z junction temperature range ---------------------------------------------------------------------------- 0 c to 125 c
rt8100 preliminary 8 ds8100-03 august 2007 www.richtek.com parameter symbol test conditions min typ max units oscillator free running frequency f osc 170 200 230 khz frequency variation ? 15 -- 15 % frequency range 50 200 1000 khz maximum duty cycle 70 75 80 % up-ramp setting pin v rr r rr = 120k 0.3 0.5 0.7 v reference voltage feedback voltage v fb v fb = 0.8v -- 1.5 -- % error amplifier dc gain 60 70 -- db gain-bandwidth product gbw c load = 5pf 6 10 -- mhz trans-conductance gm r load = 20k 600 660 -- a/v max current (source & sink) i out v out = 0.5 x v 5vsb 300 360 -- a current sense gm amplifier input offset voltage v vosgm r sense = 2k ? 5 -- 5 mv i omax i iomaxgm r sense = 2k 90 -- -- a gate driver upper drive source i ugate boot ? phase = 12v, boot ? v ugate = 1v 0.15 0.35 -- a upper drive sink r ugate v ugate = 1v -- 3.5 7 lower drive source i lgate pv cc = 12v, pv cc ? v lgate = 1v 0.5 0.35 -- a lower drive sink r lgate v lgate = 1v -- 2 4 protection over current i oc -- 80 -- a note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. the device is not guaranteed to function outside its operating conditions. note 4. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard.
rt8100 preliminary 9 ds8100-03 august 2007 www.richtek.com efficiency vs. output current 50 54.5 59 63.5 68 72.5 77 81.5 86 90.5 95 0 5 10 15 20 25 output current (a) efficiency (%) typical operating characteristics v in = 12v load transient regulation (falling) time (50us/div) v out (200mv/div) lgate (10v/div) ugate (10v/div) i load (10a/div) frequency vs. r rt 0 100 200 300 400 500 600 700 800 900 1000 1 10 100 1000 10000 r rt (k ) frequency (khz) 1 r rt connected to gnd r rt connected to 5vsb (k ) v in = 5v dead time (falling) lgate ugate time (25ns/div) phase ugate ? phase (5v/div) dead time (rising) lgate ugate time (25ns/div) phase ugate ? phase (5v/div) load transient regulation (rising) time (10us/div) v out (200mv/div) lgate (10v/div) ugate (10v/div) i load (10a/div)
rt8100 preliminary 10 ds8100-03 august 2007 www.richtek.com standalone ocp time (50ms/div) v out (500mv/div) ss (2v/div) ugate (10v/div) pi (1v/div) power off time (50ms/div) v out (500mv/div) ss (2v/div) ugate (10v/div) 5vsb (2v/div) tracking ocp time (5 s/div) ss (2v/div) ugate (10v/div) pi (1v/div) pi power on time (5ms/div) v out (500mv/div) ss (5v/div) ugate (10v/div) pi (500mv/div) pi power off time (1ms/div) v out (500mv/div) ss (5v/div) ugate (10v/div) pi (500mv/div) power on time (10ms/div) v out (500mv/div) ss (2v/div) ugate (20v/div) i load (1a/div)
rt8100 preliminary 11 ds8100-03 august 2007 www.richtek.com gm 0 50 100 150 200 250 300 350 0 2 4 6 8 101214161820 output current (a) i i_ind (ua)
rt8100 preliminary 12 ds8100-03 august 2007 www.richtek.com the external resistor rr is used to sets the internal ramp voltage proportional to current. the simulated ramp voltage is also used to implement the slope compensation set together using a single resistor rr. the relationships between rr and the internal voltage ramp is : where v rr : the voltage at rr pin to 0.5v rr : the resistance at rr pin k : the slope compensation coefficient, which is the ratio of the desired compensation slope to the down ramp slope. the ramp voltage is summed up with the sensed baseline voltage to form a complete current feedback signal. the simulated ramp signal is fed to the comparator of the pwm modulator, comparing with error amplifier output to generate pwm pulses. gate control a. before ss signal reach the bottom of the ramp voltage, ugate and lgate will be off. b. if pi pin is pulled low ugate and lgate will be off. c. when oc function occurs a constant current of 10 a starts to discharge the capacitor connected to ss pin right away. when oc occurs, ugate and lgate will be off. when the voltage at the capacitor connected to ss pin pass about 0.4v, a constant current of 10 a starts to charge the capacitor. the pwm signal is enable to pass to ugate and lgate. d. when fault conditions occur or ss < 0.4v, the current sense function will be disable. the current sense gm converts the voltage drop on the capacitor in the dcr sensing network together with the resistor r csn connected from the v out to the csn pin. r csn defines the trans-conductance of the gm stage. an extra external resistor connected from r csn to gnd is recommended to offer the capability of sensing negative inductor current in applications where negative currents are possible at light load conditions. the sensed current ix is : , at steady state. , provided r dc is left opened. the valley of the sensed current ix is sampled and held and converted to a dc voltage as a baseline of the current feedback ramp. c x r = dcr l dc out csn l x r v r dcr i i + = csn l x r dcr i i = figure 5 () 15k dcr ) l v k l v v ( 64p r x v v rr 64p rr v v 15k r dcr ) l v k l v v ( out out in csn rr in rr in csn out out in + ? ? = ? = + ? application information current sense, ramp setting rt8100 senses the inductor current through inductor dcr and feeds the current signal back to the control loop. the current sensing circuitry, as in figure 5 consists of an rc filter, a current sensing gm together with two external resistors. the current flowing the inductor as well as the dcr causes a ripple voltage proportional to inductor ripple current across the equivalent inductor dcr as in figure 5, the ripple voltage can be obtained using an rc filter in parallel with the inductor, if the component values satisfy the following relationships. + - gm i x csn(pin) csp(pin) r csn r dc r l dcr c
rt8100 preliminary 13 ds8100-03 august 2007 www.richtek.com feedback loop compensation first, the ramp signal applied to the pwm comparator is proportional to the input voltage provided via the rr pin. this keeps the modulator gain constant when the input voltage varies. second, the inductance valley current proportional signal is derived from the voltage drop across the esr of the inductance is added to the ramp signal. this effectively creates an internal current control loop. the resistor connected to the csn pin sets the gain in the current feedback loop. the following expression estimates the required value of the current sense resistor depending on the maximum load current and the value of the inductance dcr. a 80 dcr x i r max csn = 1) modulator frequency equations rt8100 is a analogous current mode buck converter using the high gain error amplifier with transconductance (ota, operational transconductance amplifier), as figure 6 shown. the transconductance : v m = (ea+) - (ea-) ; i out = e/a output current. m out v i gm = figure 6. ota topology this transfer function of ota is dominated by a higher dc gain and the output filter (l out and c out ) with a double pole frequency at f lc and a zero at f esr . the dc gain of the modulator is the input voltage (v in ) divided by the peak to peak oscillator voltage v ramp . v out r out gm ea+ ea- - + out out p(lc) c l 2 1 f = the next step of compensation design is to calculate the esr zero. the esr zero is contributed by the esr associated with the output capacitance. note that this requires that the output capacitor should have enough esr to satisfy stability requirements. the esr zero of the output capacitor expressed as follows : esr c 2 1 f out z(esr) = 2) compensation frequency equations the compensation network consists of the error amplifier and the impedance networks z c and z f as figure 7 shown. figure 7. compensation loop ? ? ? ? ? ? + = = = c2 c1 c2 c1 r2 2 1 f c1 r1 2 1 f c2 r2 2 1 f p2 p1 z1 figure 8 shows the dc-dc converter's gain vs. frequency. the compensation gain uses external impedance networks zc and zf to provide a stable, high bandwidth loop. high crossover frequency is desirable for fast transient response, but often jeopardize the system stability. in order to cancel one of the lc filter poles, place f z1 before the lc filter resonant frequency. in the experience, place f z1 at 10% lc filter resonant frequency. crossover frequency should be higher than the esr zero but less than 1/5 of the switching frequency. the f p2 should be place at half the switching frequency. the first step is to calculate the complex conjugate poles contributed by the lc output filter. the output lc filter introduces a double pole, 40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. the resonant frequency of the lc filter expressed as follows : + - gm v ref v comp c2 r2 c1 r f v out fb r1
rt8100 preliminary 14 ds8100-03 august 2007 www.richtek.com protection ocp the rt8100 use cycle by cycle current comparison. the over current level is set by r csn resistor. when oc function occurs and ss > (5vsb ? 1.3), a constant current of 10 a starts to discharge the capacitor connected to ss pin right away. when oc occurs ugate and lgate will be off. when the voltage at the capacitor connected to ss pin pass about 0.4v, a constant current of 10 a starts to charge the capacitor. figure 8. type 2 bode plot f r e q u e n c y 1 0 h z 1 0 0 h z 1 . 0 k h z 1 0 k h z 1 0 0 k h z 1 . 0 m h z v d b ( v o ) v d b ( c o m p 2 ) v d b ( l o ) - 4 0 0 4 0 8 0 - 6 0 10 1 00 1k 10k 1 00k 1m 80 40 0 20 60 -20 -40 -60 loop gain compensation gain modulator gain frequency (hz) gain (db) there is another type of compensation called type 3 compensation that adds a pole-zero pair to the type 2 network. it's used to compensate output capacitor whose esr value is much lower (pure mlcc or oscon capacitors). as shown in figure 9, to insert a network between v out and fb in the original type 2 compensation network can result in type 3 compensation. figure 10 shows the difference of their ac response. type 3 compensation has an additional pole-zero pair that causes a gain boost at the flat gain region. but the gain boosted is limited by the ratio (r1+r4)/r4; if r3 << r4. + - gm v comp c2 r2 c1 r4 v out r1 r3 c3 fb figure 9. additional network of type 3 compensation (add between v out and fb) figure 10. ac response curves of type 2 and 3 pole f z2 add type 3 compensation original type 3 compensation f p1 f p2 f z1 f p3 type 3 will induce three poles and two zeros. zeros : c3 r3) r1 2 1 f c2 r2 2 1 f z2 z1 + = = ( ; r3 r1 c1 r3 r1 2 1 f c3 r3 2 1 f c2 c1 c2 c1 r2 2 1 f p3 p2 p1 ? ? ? ? ? ? + = = ? ? ? ? ? ? + = poles : which is in the origin. we recommend f z1 placed in 0.5 x f p(lc) ; f z2 placed in f p(lc) ; f p1 placed in f esr and f p2 placed in 0.5 x f sw . figure 11 shows type 3 bode plot. figure 11. type 3 bode plot loop gain -80 -60 -40 -20 0 20 40 60 234567 log frequency db compensation gain gain modulator gain
rt8100 preliminary 15 ds8100-03 august 2007 www.richtek.com csn l x r i dcr i = the pwm signal is enable to pass to the ugate and lgate. if the oc protection occurs three times, ocsd will be activated and shut down the chip and pull low pi about 15 s in tracking mode. rt8100 uses an external resistor r csn to set a programm- able over current trip point. ocp comparator compares inductor current with this reference current. rt8100 uses hiccup mode to eliminate fault detection of ocp or reduce output current when output is shorted to ground. figure 12 + - i x 80 a ocp comparator otp monitor the temperature near the driver part within the chip. shutdown the chip when otp. component selection components should be appropriately selected to ensure stable operation, fast transient response, high efficiency, minimum bom cost and maximum reliability. output inductor selection the selection of output inductor is based on the considerations of efficiency, output power and operating frequency. for a synchronous buck converter, the ripple current of inductor ( i l ) can be calculated as follows : generally, an inductor that limits the ripple current between 20% and 50% of output current is appropriate. make sure that the output inductor could handle the maximum output current and would not saturate over the operation temperature range. output capacitor selection the output capacitors determine the output ripple voltage ( v out ) and the initial voltage drop after a high slew-rate load transient. the selection of output capacitor depends on the output ripple requirement. the output ripple voltage is described as follows : d) (1 c x l x f v x 8 1 esr x i v out 2 osc out l out ? + = l x f x v v x ) v (v i osc in out out in l ? = for electrolytic capacitor application, typically 90~95% of the output voltage ripple is contributed by the esr of output capacitors. paralleling lower esr ceramic capacitor with the bulk capacitors could dramatically reduce the equivalent esr and consequently the ripple voltage. input capacitor selection use mixed types of input bypass capacitors to control the input voltage ripple and switching voltage spike across the mosfets. the buck converter draws pulsewise current from the input capacitor during the on time of upper mosfet. the rms value of ripple current flowing through the input capacitor is described as : the input bulk capacitor must be cable of handling this ripple current. sometime, for higher efficiency the low esr capacitor is necessarily. appropriate high frequency ceramic capacitors physically near the mosfets effectively reduce the switching voltage spikes. mosfet selection the selection of mosfets is based upon the considerations of r ds(on) , gate driving requirements, and thermal management requirements. the power loss of upper mosfet consists of conduction loss and switching loss and is expressed as : where t rise and t fall are rising and falling time of v ds of upper mosfet respectively. r ds(on) and q g should be simultaneously considered to minimize power loss of upper mosfet. the power loss of lower mosfet consists of conduction loss, reverse recovery loss of body diode, and conduction loss of body diode and is express as : d) (1 x d x i i out in(rms) ? = osc fall rise in out ds(on) out sw_upper _upper cond upper f x ) t (t x x v i 2 1 d x r x i p p p + + = + = osc diode f out osc in rr ds(on) out diode rr _lower cond lower f x t x x v i x 2 1 f x x v q d) (1 x r x i p p p p + + ? = + + =
rt8100 preliminary 16 ds8100-03 august 2007 www.richtek.com where t diode is the conducting time of lower body diode. special control scheme is adopted to minimize body diode conducting time. as a result, the r ds(on) loss dominates the power loss of lower mosfet. use mosfet with adequate r ds(on) to minimize power loss and satisfy thermal requirements. bypass capacitor notes input capacitor c in is typically chosen based on the ripple current requirements. c out is typically selected based on both current ripple rating and esr requirement. pwm layout considerations layout is very important in high frequency switching converter design. if designed improperly, the pcb could radiate excessive noise and contribute to the converter instability. first, place the pwm power stage components. mount all the power components and connections in the top layer with wide copper areas. the mosfets of buck, inductor, and output capacitor should be as close to each other as possible. this can reduce the radiation of emi due to the high frequency current loop. if the output capacitors are placed in parallel to reduce the esr of capacitor, equal sharing ripple current should be considered. place the input capacitor directly to the drain of high-side mosfet. in multi-layer pcb, use one layer as power ground and have a separate control signal ground as the reference of the all signal. to avoid the signal ground is effect by noise and have best load regulation, it should be connected to the ground terminal of output. furthermore, follows below guidelines can get better performance of ic : 1. a multi-layer printed circuit board is recommended. 2. use a middle layer of the pc board as a ground plane and making all critical component ground connections through vias to this layer. 3. use another solid layer as a power plane and break this plane into smaller islands of common voltage levels. 4. keep the metal running from the phase terminal to the output inductor short. 5. use copper filled polygons on the top and bottom circuit layers for the phase node. 6. the small signal wiring traces from the lgate and ugate pins to the mosfet gates should be kept short and wide enough to easily handle the several amperes of drive current. 7. the critical small signal components include any bypass capacitors, feedback components, and compensation components. position those components close to their pins with a local gnd connection, or via directly to the ground plane. 8. r t resistors should be near the r t pin respectively, and gnd return should be short, and kept away from the noisy mosfet gnd. 9. place the compensation components close to the fb and comp pins. 10. the feedback resistors should also be located as close as possible to the relevant fb pin with vias tied straight to the ground plane as required. 11. minimize the length of the connections between the input capacitors, c in and the power switches by placing them nearby. 12. position both the ceramic and bulk input capacitors as close to the upper mosfet drain as possible, and make the gnd returns (from the source of lower mosfet to v in , c vin , gnd) short. 13. position the output inductor and output capacitors between the upper mosfet and lower mosfet and the load. 14. because rt8100 use dcr sense topology, dcr sense point is output inductor from end to end. 15. csn and fb must be independent path. below pcb gerber files are our test board for your reference :
rt8100 preliminary 17 ds8100-03 august 2007 www.richtek.com figure 13. component side figure 14. bottom
rt8100 preliminary 18 ds8100-03 august 2007 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 8f, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com outline dimension a a1 a3 d e 1 d2 e2 l b e see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.800 1.000 0.031 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 1.300 1.750 0.051 0.069 e 2.950 3.050 0.116 0.120 e2 1.300 1.750 0.051 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 v-type 16l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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