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1 www.fairchildsemi.com fm93c56a rev. a fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) general description the fm93c56a is 2048 bits of cmos nonvolatile eeprom ( electrically erasable programmable read only memory) with microwire serial interface. fm93c56a can be configured for either 128 x 16 bit or 256 x 8 bit array using an organization (org) input pin. this device is fabricated using fairchild semiconductor's floating gate cmos process for high reliability, high endurance and low power consumption. this device is available in 8-pin dip, so and tssop packages. the microwire serial interface offered by this eeprom en- ables simple interface to a wide variety of microcontrollers and microprocessors. there are 7 instructions that operate the fm93c56a: read, erase/write enable, erase, write, erase/ write disable, write all and erase all. january 2000 features 2.7v to 5.5v operation in all modes typical active current 200 a 10 a standby current typical 1 a standby current typical (l) 0.1 a standby current typical (lz) self-timed programming cycle device status indication during programming mode no erase required before write reliable cmos floating gate technology microwire compatible serial i/o 40 years data retention endurance: 1,000,000 data changes packages available: 8-pin tssop, 8-pin so, 8-pin dip schmitt trigger inputs and v cc lockout to prevent data corruption ds800029-1 instruction decoder control logic, and clock generators high voltage generator and program timer instruction register address register eeprom array 2048 bits (128x16) or (256x8) read/write amps data in/out register 16 (or 8) bits decoder 1 of 128 (or 256) data out buffer v pp v cc cs sk di do gnd org ?1999 fairchild semiconductor corporation block diagram
2 www.fairchildsemi.com fm93c56a rev. a fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) connection diagram dual-in-line package (n) 8-pin so package (m8) and 8-pin tssop package (mt8) v cc org v ss cs sk di do 1 2 3 4 8 7 6 5 nc top view see package number n08e, m08a and mtc08 fm93c56a ds800029-2 pin names pin description cs chip select sk serial data clock di serial data input do serial data output v ss ground org memory organization select nc no connect v cc positive power supply ordering information fm 93 c xx a t lz e xx letter description package n 8-pin dip m8 8-pin so8 mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current blank normal pin out t rotated die pin out a x8 or x16 configuration density 56 2k c cmos cs data protect and sequential read interface 93 microwire fm fairchild non-volatile memory rotated die (93c56at) org do di nc v cc cs sk 1 2 3 4 8 7 6 5 v ss fm93c56a
3 www.fairchildsemi.com fm93c56a rev. a fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages with respect to ground v cc +1 to -0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v operating conditions ambient operating temperature fm93c56a 0 c to +70 c fm93c56ae -40 c to +85 c fm93c56av -40 c to +125 c power supply (v cc ) range 4.5v to 5.5v dc and ac electrical characteristics 4.5v v cc 5.5v symbol parameter part number conditions min max units i cca operating current cs = v ih sk = 1 mhz 1 ma i ccs standby current cs = 0v org = v cc or nc 50 a i il input leakage v in = 0v to v cc (note 2) -1 1 a i ilo input leakage org tied to v cc -1 1 a org pin org tied to v ss (note 3) -2.5 2.5 i ol output leakage v in = 0v to v cc -1 1 a v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v v ol1 output low voltage i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = -400 a 2.4 v v ol2 output low voltage i ol = 10 a 0.2 v v oh2 output high voltage i ol = -10 av cc -0.2 v f sk sk clock frequency (note 4) 0 1 mhz t skh sk high time fm93c56a 250 ns fm93c56ae 300 t skl sk low time 250 ns t sks sk setup time sk must be at v il for 50 ns t sks before cs goes high t cs minimum cs (note 5) 250 ns low time t css cs set-up time 50 ns t dh d0 hold time 70 ns t dis di set-up time fm93c56a 100 ns fm93c56ae/v 200 t csh cs hold time 0 ns t dih di hold time 20 ns t pd output delay 500 ns t sv cs to status valid 500 ns t df cs to do in hi-z 100 ns t wp write cycle time 10 ms
4 www.fairchildsemi.com fm93c56a rev. a fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v .03v/1.8v 1.0v 0.8v/1.5v 10 a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v 2.1ma/-0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf) absolute maximum ratings (note 1) ambient storage temperature ?5 c to +150 c all input or output voltage +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v dc and ac electrical characteristics v cc = 2.7v to 5.5v unless otherwise specified symbol parameter part number conditions min. max. units i cca operating current cs = v ih , sk = 250khz 1ma i ccs standby current cs = v il l 10 a lz 1 a i il input leakage v in = 0v to v cc (note 2) 1 a i ilo input leakage org tied to v cc -1 1 a org pin org tied to v ss (note 3) -2.5 2.5 i ol output leakage v in = 0v to v cc 1 a v il input low voltage -0.1 0.15 v cc v v ih input high voltage 0.8 v cc v cc +1 v ol output low voltage i ol = 10 a 0.1 v cc v v oh output high voltage i oh = -10 a 0.9 v cc v f sk sk clock frequency (note 4) 0 250 khz t skh sk high time 1 s t skl sk low time 1 s t sks sk setup time sk must be at v il for 0.2 s t sks before cs goes high t cs minimum cs (note 5) 1 s low time t css cs setup time 0.2 s t dh do hold time 70 ns t dis di setup time 0.4 s t csh cs hold time 0 ns t dih di hold time 0.4 s t pd output delay 2 s t sv cs to status valid 1 s t df cs to do in hi-z cs = v il 0.4 s t wp write cycle time 15 ms operating range ambient operating temperature fm93c56al/lz 0 c to +70 c fm93c56ale/lze -40 c to +85 c fm93c56a lv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 5.5v capacitance t a = 25 c, f = 1 mhz symbol test typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20 na range. note 3 : the org pin may draw > 1 a when in the x8 mode ude to an internal pull-up transistor. note 4 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 5 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagrams in the following pages.)
5 www.fairchildsemi.com fm93c56a rev. a fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) microwire i/o pin description chip select (cs): this pin enables and disables the microwire device and performs 3 general functions: 1. when in the low state, the microwire device is disabled and the output tri-stated (high impedance). if this pin is brought high (rising edge active), all internal registers are reset and the device is enabled, allowing microwire communication via di/do pins. to restate, the cs pin must be held high during all device communication and opcode functions. if the cs pin is brought low, all functions will be disabled and reset when cs is brought high again. the exception to this is when a programming cycle is initiated (see 2 and 3). again, all activity on the cs, di and do pins is ignored until cs is brought high. 2. after entering all required opcode and address data, bringing cs low initiates the (asynchronous) programming cycle. 3. when programming is in progress, the data-out pin will display the programming status as either busy (do low) or ready (do high) when cs is brought high. (again, the output will be tri-stated when cs is low.) to restate, during programming, the cs pin may be brought high and low any number of times to view the programming status without affect the programming operation. once programming is completed (output in ready state), the output is 'cleared' (returned to normal tri-state condition) by clocking in a start bit. after the start bit is clocked in, the output will return to a tri-stated condition. when clocked in, this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. serial clock (sk): this pin is the clock input (rising edge active) for clocking in all opcodes and data on the di pin and clocking out all data on the do pin. however, this pin has no effect on the asynchronous program- ming cycle (see the cs pin section) as the busy/ready status is a function of the cs pin only. data-in (di): all serial communication into the device is performed using this input pin (rising edge active). in order to avoid false start bits, or related issues, it is advised to keep the di pin in the low state unless actually clocking in data bits (start bit, opcode, address or incoming data bits to be programmed). please note that the first '1' clocked into the device (after cs is brought high) is seen as a start bit and the beginning of a serial command string, so caution must be observed when bringing cs high. data-out (do): all serial communication out of the device, read data ( during normal reads) as well as ready/busy status indication ( during programming ) are performed using this output pin. note that, during read operations, the eeprom device starts to drive the do output pin "active" after the last address bit (a0) is clocked in. hence in applications where 3-wire configuration is required ( where di and do pins are tied together ) caution must be observed for correct operation. please refer an-758 for further information. organization (org): this pin controls the device architecture (8-bit data word vs. 16-bit data word). if the org pin is brought to v cc , the device is configured wiht a 16-bit data word and if the org pin is brought to v ss (ground), the device is configured with an 8-bit data word. if the org pin is left floating, the device will default to a 16-bit data word. instruction set for the fm93c56a org memory pin configuration # of address bits logic 0 256 x 8 9 bits 1 128 x 16 8 bits note: the leading (msb) bit is a "don't care," but must be included in the address string.
6 www.fairchildsemi.com fm93c56a rev. a fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) 128 by 16-bit organization (fm93c56a when org = v cc or nc) instruction sb op-code address data comments 2 bits 8 bits 16 bits read 1 10 a7?0 read data stored in selected registers. ewen 1 00 11xxxxxx enables programming modes. ewds 1 00 00xxxxxx disables all programming modes. erase 1 11 a7?0 erase selected register. write 1 01 a7?0 d15?0 writes data pattern d15?0 into selected register. eral 1 00 10xxxxxx erases all registers. wral 1 00 01xxxxxx d15?0 writes data pattern d15?0 into all registers. note: the a7 bit is a "don't care" bit, but must be entered in the address string. note: x = don't care. 256 by 8-bit organization (fm93c56a when org = gnd) instruction sb op-code address data comments 2 bits 9 bits 8 bits read 1 10 a8?0 read data stored in selected registers. ewen 1 00 11xxxxxxx enables programming modes. ewds 1 00 00xxxxxxx disables all programming modes. erase 1 11 a8?0 erase selected register. write 1 01 a8?0 d7?0 writes data pattern d7?0 into selected registers. eral 1 00 10xxxxxxx erases all registers. wral 1 00 01xxxxxxx d7?0 writes data pattern d7?0 into all registers. note: the a8 bit is a "don't care" bit, but must be entered in the address string. note: x = don't care. functional description programming: 1. programming is initiated by clocking in the start bit, opcode bits, address bits and the 8/16 data bits (refer to the org pin section). 2. programming is started by bringing the cs pin low. once the programming cycle is started, it cannot be stopped. (bringing v cc low will stop any programming, but will also result in data corruption.) 3. the status of the programming cycle (busy or ready) is observed by bringing the cs pin high and observing the output state. if the output is low, the device is still program- ming (busy). if the output is high, the programming cycle has been completed and the device is ready for the next operation. note that the output will be tri-stated each time cs is brought low and the ready/busy status will be shown each time cs is brought high. 4. after programming, the ready state (output high) can be reset and the output tri-stated by clocking in a single start bit. this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. in any case, clocking in a '1' bit will tri-state the output. read (read) the read instruction outputs serial data on the do pin. after a read instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a serial-out shift register. a dummy bit (logical 0) precedes the serial data output string. output data changes are initiated by a low to high transition of sk after the last address bit (a0) is clocked in. erase/write enable (ewen) when v cc is applied to the part, it ?owers up?in the erase/write disable (ewds) state. therefore, all programming modes must be preceded by an erase/write enable (ewen) instruction. once an erase/write enable instruction is executed, programming remains enabled until an erase/write disable (ewds) instruction is executed or v cc is removed from the part.
7 www.fairchildsemi.com fm93c56a rev. a fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) functional description (continued) erase/write disable (ewds): to protect against accidental data overwrites, the erase/write disable (ewds) instruction disables all programming modes and should follow all programming operations. execution of a read instruction is independent of both the ewen and ewds instruc- tions. erase (erase): the erase instruction will program all bits in the specified register to the logical ??state. please refer to the programming section for details. write (write): the write instruction is followed by 16 bits of data (or 8 bits of data when using the fm93c56a in the x8 organization) to be written into the specified address. please refer to the program- ming section for details. erase all (eral): the eral instruction will simultaneously program all registers in the memory array to the logical ??state. write all (wral): the wral instruction will simultaneously program all registers with the data pattern specified in the instruction. status valid v ih v il cs v ih v il sk v ih v il di v oh v ol do (read) v oh v ol do (program) t css t sks t dis t dih t pd t dh t df t df t dh t sv t skh t skl t csh ds800029-4 timing diagrams for the fm93c56a synchronous data timing
8 www.fairchildsemi.com fm93c56a rev. a fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) cs sk di 1 . . . org = v cc , 4 x's org = v ss , 5 x's t cs ewen do = hi-z 0011 xx cs sk di 1 . . . org = v cc , 4 x's org = v ss , 5 x's t cs ewds do = hi-z 0000 xx erase 111 a n . . . a 0 cs busy ready hi-z hi-z standby do sk di t cs t wp ds800029-6 ds800029-7 ds800029-8 timing diagrams for the fm93c56a (continued) 1 cs sk di do 10 0d n . . . d 0 a n . . . a 0 t cs read ds800029-5 key for timing diagrams organization of address and data fields for fm93c56a org pin organization a n d n v cc or nc 128 x 16 a7 d15 v ss 256 x 8 a8 d7 note: the msb is "don't care."
9 www.fairchildsemi.com fm93c56a rev. a fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) eral 00 110xx . . . cs busy ready standby do sk di t wp t cs org = v cc , 4 x's org = v ss , 5 x's ready status signal resets to hi-z after clocking in one sk cycle with di = 1 wral 000 11xxd n d 0 . . . . . . cs do sk di org = v cc , 4 x's org = v ss , 5 x's busy ready standby t wp t cs ready status signal resets to hi-z after clocking in one sk cycle with di = 1 ds800029-10 ds800029-11 timing diagrams for the fm93c56a (continued) write 1 . . . . . . t cs 0 1 a n a 0 d 0 d n cs busy ready do sk di t wp ds800029-9
10 www.fairchildsemi.com fm93c56a rev. a fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 physical dimensions inches (millimeters) unless otherwise noted molded small outline package (m8) package number m08a
11 www.fairchildsemi.com fm93c56a rev. a fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a land pattern recommendation detail a typ. scale: 40x physical dimensions inches (millimeters) unless otherwise noted 8-pin molded tssop, jedec (mt8) package number mtc08
12 www.fairchildsemi.com fm93c56a rev. a fm93c56a 2k-bit serial cmos eeprom (microwire? synchronous bus) physical dimensions inches (millimeters) unless otherwise noted 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident molded dual-in-line package (n) package number n08e life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841

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