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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . 3 a 5 v 1 m h z s y n c h r o n o u s b u c k c o n v e r t e r f e a t u r e s g e n e r a l d e s c r i p t i o n high efficiency up to 95% - automatic pfm/pwm mode operation adjustable output voltage from 0.6v to v pvdd integrated 65m w high side / 55m w low side mosfets low dropout operation: 100% duty cycle stable with low esr ceramic capacitors power-on-reset detection on vdd and pvdd integrated soft-start and soft-stop over-temperature protection over-voltage protection under-voltage protection high/ low side current limit power good indication enable/shutdown function small tdfn3x3-10 and sop-8p packages lead free and green devices available (rohs compliant) a p p l i c a t i o n s notebook computer & umpc lcd monitor/tv set-top box dsl, switch hubr portable instrument apw8804 is a 3a synchronous buck converter with inte- grated 65m w high side and 55m w low side power mosfets. the apw8804, design with a current-mode control scheme, can convert wide input voltage of 2.6v to 6v to the output voltage adjustable from 0.6v to 6v to provide excellent output voltage regulation. the apw8804 is equipped with an automatic pfm/pwm mode operation. at light load , the ic operates in the pfm mode to reduce the switching losses. at heavy load, the ic works in pwm mode. at pwm mode, the switching frequency is set by the external resistor. the apw8804 is also equipped with power-on-reset, soft- start, soft-stop, and whole protections (under-voltage, over-voltage, over-temperature and current-limit) into a single package. this device, available tdfn3x3-10 and sop-8p, provides a very compact system solution external components and pcb area. s i m p l i f i e d a p p l i c a t i o n c i r c u i t pvdd vdd pok en o ff o n v in lx fb gnd apw 8804 v out ( option )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n p i n c o n f i g u r a t i o n n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v pvdd , v vdd input supply voltage - 0.3 ~ 6.5 v <30ns pulse width - 3 ~v pv dd + 3 v v lx lx to gnd voltage >30ns pulse width - 1 ~v pv dd +0.3 v pok , fb, en to gnd voltage - 0.3 ~ 6.5 v p d power dissipation 2 w t j junction temper ature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering temperature , 10 seconds 26 0 o c nc 1 lx 3 10 pvdd lx 2 en 5 9 pvdd 7 nc 8 vdd tdfn 3x3-10 (top view) 11 gnd pok 4 6 fb apw8804 exposed pad 11 gnd note1: stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. lx 1 lx 2 pok 3 5 fb en 4 6 gnd 7 vdd 8 pvdd apw8804 sop-8p (top view) 9 gnd 9 gnd exposed pad the pin 6 must be connected to the pin 9 (exposed pad) apw 8804 handling code tem perature range package code apw 8804 xxxxx package code ka : sop-8p qb : tdfn3x3-10 operating ambient temperature range i : -40 to 85 o c handling code tr : tape & reel assembly material g : halogen and lead free device apw 8804 xxxxx apw 8804 ka : apw 8804 qb : xxxxx - date code assembly material xxxxx - date code
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 3 t h e r m a l c h a r a c t e r i s t i c s symbol parameter typical value unit q ja junction - to - ambient resistance in free air (note 2) sop - 8p tdfn3x3 - 10 60 50 o c/w q jc junction - to - case resistance in free air (note 3) sop - 8p tdfn3x3 - 10 20 10 o c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. the exposed pad of sop-8p or tdfn3x3-10 is soldered directly on the pcb. note 3: the case temperature is measured at the center of the exposed pad on the underside of the sop-8p or tdfn3x3-10 package. symbol parameter range unit v vdd control and driver supply voltage 2.6 ~ 6 v v pvdd input supply voltage 2~6 v v out converter output voltage 0.6~6 v l inductance 1~3.3 m h i out converter output current 0~3 a t a ambient temperature - 40 ~ 85 o c t j juncti on temperature - 40 ~ 125 o c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 4 ) e l e c t r i c a l c h a r a c t e r i s t i c s apw8804 symbo parameter test conditions min. typ. max. unit supply current i vdd vdd supply current v fb =0.7v - 460 - m a i vdd_sdh vdd shutdown supply current en=gnd - - 1 m a power - on - r eset (por) vdd por voltage threshold v vdd rising 2.3 2.4 2.5 v vdd por hysteresis - 0.2 - v pvdd por voltage threshold 1.5 1.7 1.9 v pvdd por hysteresis - 0.2 - v reference voltage - 0.6 - v v ref reference voltage all temperature - 1 - +1 % output accuracy i out =10ma ~3a, v vdd = 2.6~5 v - 1.5 - +1.5 % unless otherwise specified, these specifications apply over v vdd =v pvdd =5v, v out =3.3v, t a =25 o c. n o t e 4 : r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) apw8804 symbo parameter test conditions min. typ. max. unit oscillator and duty cycle f osc oscillator frequency 0.85 1 1.15 mhz maximum converter ? s duty v fb =0.7v - 100 - % minimum on time - 100 - ns power mosfet high side p - mosfet resistanc e v vdd =5v, i lx =0.5a, t a =25 o c - 65 80 m w low side n - mosfet resistance v vdd =5v, i lx =0.5a, t a =25 o c - 55 75 m w high / low side mosfet leakage current - - 1 m a current - mode pwm converter gm error amplifier transconductance - 550 - m a/v error amplifier dc gain comp=nc - 80 - db current s ense transresistance - 400 - m w t d dead time - 20 - ns protecti ons i lim mosfet current - limit peak current 4 4.5 5 a t otp over - t emperature trip point - 1 5 0 - c over - t emperature hysteresis - 30 - c over - voltage protection threshold 120 - 135 %v ref under - voltage protection threshold 45 50 55 %v ref soft - start, enable, and input currents soft - start time - 1 - ms en enable threshold v en rising voltage to enable device - - 1.4 v en shutdown threshold v en falling voltage to shutdown dev ice 0.5 - - v en pull low resistance - 500 - k w pok in from lower (pok goes high) 87 90 93 %v out pok low hysteresis (pok goes low) - 5 - %v out pok in from higher (pok goes high) 122 125 128 %v out pok threshold pok high hysteresis (pok goes low) - 5 - %v out power good pull low resistan ce - 100 - w unless otherwise specified, these specifications apply over v vdd =v pvdd =5v, v out =3.3v, t a =25 o c.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 5 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s r e f e r t o t h e ? t y p i c a l a p p l i c a t i o n c i r c u i t ? . t h e t e s t c o n d i t i o n i s v v d d = 5 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . output voltage vs . load current load current , i out ( a ) o u t p u t v o l t a g e , v o u t ( v ) 1 . 7 1 . 72 1 . 74 1 . 76 1 . 78 1 . 8 1 . 82 1 . 84 1 . 86 1 . 88 1 . 9 0 0 . 5 1 1 . 5 2 2 . 5 3 efficiency vs . load current load current , i out ( a ) e f f i c i e n c y ( % ) 50 60 70 80 90 100 0 1 2 3 v out = 3 . 3 v v vdd = 5 v 50 60 70 80 90 100 0 1 2 3 v out = 1 . 8 v v vdd = 3 . 3 v v vdd = 5 v efficiency vs . load current e f f i c i e n c y ( % ) load current , i out ( a ) load current , i out ( a ) e f f i c i e n c y ( % ) efficiency vs . load current v vdd = 3 . 3 v v vdd = 5 v v out = 1 . 05 v 50 60 70 80 90 100 0 1 2 3 supply voltage vs . p - fet current limit 0 1 2 3 4 5 6 2 3 4 5 6 supply voltage , v vdd ( v ) p - f e t c u r r e n t l i m i t , i l i m ( a ) 0 10 20 30 40 50 60 70 80 90 100 2 3 4 5 6 supply voltage , v vdd ( v ) m o s f e t o n r e s i s t a n c e , r o n ( m w ) n - fet p - fet supply voltage vs . mosfet on resistance
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 6 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 5 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . time : 200 m s / div enable without loading v pok , 5 v / div v en i l , 1 a / div v out , 1 v / div , dc 3 4 1 2 time : 200 m s / div shutdown 4 3 1 2 v pok , 5 v / div v en i l , 1 a / div v out , 1 v / div , dc enable with 1 . 8 a loading time : 200 m s / div 4 3 1 2 v pok , 5 v / div v en i l , 1 a / div v out , 1 v / div , dc shutdown time : 200 m s / div 4 3 1 2 v pok , 5 v / div v en i l , 1 a / div v out , 1 v / div , dc
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 7 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p l i c a t i o n c i r c u i t . t h e t e s t c o n d i t i o n i s v i n = 5 v , t a = 2 5 o c u n l e s s o t h e r w i s e s p e c i f i e d . time : 20 m s / div load transient response i out , 1 a / div v out , 100 mv / div , ac 1 2 1 a 2 . 5 a time : 50 m s / div load transient response 1 2 i out , 1 a / div v out , 100 mv / div , ac 1 . 5 a 10 ma over voltage protection time : 20 m s / div 3 1 2 v pok , 5 v / div i l , 1 a / div v out , 1 v / div , dc normal operating waveform time : 1 m s / div 3 1 2 v lx , 5 v / div i l , 1 a / div v out , 20 mv / div , dc
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 8 p i n d e s c r i p t i o n pin no. tdfn3x3 - 10 sop - 8p name function 1 - nc no connection. 2,3 1,2 lx power switching output. lx is the junction of the high - side and low - side power mosfets to supply power to the output lc filter. 4 3 pok power good output. this pin is open - dra in logic output that is pulled to the ground when the output voltage is out of regulation point . 5 4 en e nable input. en is a digital input that turns the regulator on or off. drive en high to turn on the regulator, drive it low to turn it off. 6 5 fb ou tput feedback input. the apw8804 senses the feedback voltage via fb and regulates the voltage at 0.6v. connecting fb with a resistor - divider from the converter ? s output sets the output voltage. 7 - nc no connection. 8 7 vdd signal input. vdd supplies the control circuitry, gate drivers. connecting a ceramic bypass capacitor from vdd to gnd to eliminate switching noise and voltage ripple on the input to the ic. 9,10 8 pvdd power input. pvdd supplies the step - down converter switches. connecting a ceramic b ypass capacitor from pvdd to gnd to eliminate switching noise and voltage ripple on the input to the ic. 11 9 gnd (exposed pad) ground and exposed pad. connect the exposed pad to the system ground plan with large copper area for dissipating heat into the ambient air. - 6 gnd ground. power and signal ground.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 9 b l o c k d i a g r a m lx gate control fault logics error amplifier fb inhibit por power-on- reset current sense amplifier oscillator slope compensation current compartor over temperature protection current limit gate gm pvdd otp current sense amplifier loc loc vdd en 50%v ref soft - start shutdown pok gnd gate driver uvp v ref ovp 125%v ref 90%v ref 0.6v zero crossing comparator 125%v ref pok
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 1 0 t y p i c a l a p p l i c a t i o n c i r c u i t pvdd vdd pok en o ff o n v in 5 v lx fb gnd apw 8804 v out 1 . 8 v / 3 a c out 22 m fx 2 c in 22 m f l 1 1 m h r 1 24 k r 2 12 k c 1 ( option ) r 3 100 k pvdd vdd pok en o ff o n v in 2 ~ 6 v lx fb gnd apw 8804 v out 1 v / 3 a c out 22 m fx 2 c in 22 m f l 1 1 m h r 1 10 k r 2 1 5 k c 1 ( option ) r 3 100 k c vdd 1 m f v dd 2 . 6 ~ 6 v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 1 1 f u n c t i o n d e s c r i p t i o n v d d a n d p v d d p o w e r - o n - r e s e t ( p o r ) t h e a p w 8 8 0 4 k e e p s m o n i t o r i n g t h e v o l t a g e o n v d d a n d p v d d p i n s t o p r e v e n t w r o n g l o g i c o p e r a t i o n s w h i c h m a y o c c u r w h e n v d d o r p v d d v o l t a g e i s n o t h i g h e n o u g h f o r i n t e r n a l c o n t r o l c i r c u i t r y t o o p e r a t e . t h e v d d p o r r i s i n g t h r e s h o l d i s 2 . 4 v ( t y p i c a l ) w i t h 0 . 2 v h y s t e r e s i s a n d p v d d p o r r i s i n g t h r e s h o l d i s 1 . 7 v w i t h 0 . 2 v h y s t e r e s i s . d u r i n g s t a r t - u p , t h e v d d a n d p v d d v o l t a g e m u s t e x c e e d t h e e n a b l e v o l t a g e t h r e s h o l d . t h e n , t h e i c s t a r t s a s t a r t - u p p r o c e s s a n d r a m p s u p t h e o u t p u t v o l t a g e t o t h e v o l t - a g e t a r g e t . o u t p u t u n d e r - v o l t a g e p r o t e c t i o n ( u v p ) in the operational process, if a short-circuit occurs, the output voltage will drop quickly. before the current-limit circuit responds, the output voltage will fall out of the re- quired regulation range. the under-voltage continually monitors the fb voltage after soft-start is completed. if a load step is strong enough to pull the output voltage lower than the under-voltage threshold, the ic starts soft-stop function and shuts down converter?s output. the under-voltage threshold is 50% of the nominal out- put voltage. the under-voltage comparator has a built-in 3 m s noise filter to prevent the chips from wrong uvp shut- down being caused by noise. apw8804 will be latched after under-voltage protection. o v e r - v o l t a g e p r o t e c t i o n ( o v p ) t h e o v e r - v o l t a g e f u n c t i o n m o n i t o r s t h e o u t p u t v o l t a g e b y f b p i n . w h e n t h e f b v o l t a g e i n c r e a s e s o v e r 1 2 5 % o f t h e r e f e r e n c e v o l t a g e d u e t o t h e h i g h - s i d e m o s f e t f a i l u r e o r f o r o t h e r r e a s o n s , t h e o v e r - v o l t a g e p r o t e c t i o n c o m p a r a t o r w i l l t r i g g e r s o f t - s t o p f u n c t i o n a n d s h u t d o w n t h e c o n v e r t e r o u t p u t . o v e r - t e m p e r a t u r e p r o t e c t i o n ( o t p ) the over-temperature circuit limits the junction tempera- ture of the apw8804. when the junction temperature ex- ceeds t j =+160 o c, a thermal sensor turns off the both power mosfets, allowing the devices to cool. the ther- mal sensor allows the converters to start a start-up pro- cess and to regulate the output voltage again after the junction temperature cools by 50 o c. the otp is designed c u r r e n t - l i m i t p r o t e c t i o n t h e a p w 8 8 0 4 m o n i t o r s t h e o u t p u t c u r r e n t , f l o w s t h r o u g h t h e h i g h - s i d e a n d l o w - s i d e p o w e r m o s f e t s , a n d l i m i t s t h e c u r r e n t p e a k a t c u r r e n t - l i m i t l e v e l t o p r e v e n t t h e i c f r o m d a m a g i n g d u r i n g o v e r l o a d , s h o r t - c i r c u i t a n d o v e r - v o l t a g e c o n d i t i o n s . t y p i c a l h i g h s i d e p o w e r m o s f e t c u r - r e n t l i m i t i s 4 . 5 a , a n d l o w s i d e m o s f e t c u r r e n t l i m i t i s 1 . 9 a . soft-start t h e a p w 8 8 0 4 h a s a b u i l t - i n s o f t - s t a r t t o c o n t r o l t h e r i s e r a t e o f t h e o u t p u t v o l t a g e a n d l i m i t t h e i n p u t c u r r e n t s u r g e d u r i n g s t a r t - u p . d u r i n g s o f t - s t a r t , a n i n t e r n a l v o l t a g e r a m p c o n n e c t e d t o o n e o f t h e p o s i t i v e i n p u t s o f t h e e r r o r a m p l i f i e r , r i s e s u p t o r e p l a c e t h e r e f e r e n c e v o l t a g e ( 0 . 6 v ) u n t i l t h e v o l t a g e r a m p r e a c h e s t h e r e f e r e n c e v o l t a g e . d u r - i n g s o f t - s t a r t w i t h o u t o u t p u t o v e r - v o l t a g e , t h e a p w 8 8 0 4 c o n v e r t e r ? s s i n k i n g c a p a b i l i t y i s d i s a b l e d u n t i l t h e o u t p u t v o l t a g e r e a c h e s t h e v o l t a g e t a r g e t . s o f t - s t o p a t t h e m o m e n t o f s h u t d o w n c o n t r o l l e d b y e n s i g n a l , u n - d e r - v o l t a g e e v e n t o r over-voltage event , t h e a p w 8 8 0 4 i n i - t i a t e s a s o f t - s t o p p r o c e s s t o d i s c h a r g e t h e o u t p u t v o l t a g e i n t h e o u t p u t c a p a c i t o r s . c e r t a i n l y , t h e l o a d c u r r e n t a l s o d i s c h a r g e s t h e o u t p u t v o l t a g e . d u r i n g s o f t - s t o p , t h e i n t e r - n a l v o l t a g e r a m p ( v r a m p ) f a l l s d o w n t o r e p l a c e t h e r e f e r - e n c e v o l t a g e . t h e l o w s i d e m o s f e t t u r n s o n e a c h c y c l e t o d i s c h a r g e t h e o u t p u t v o l t a g e . t h e r e f o r e , t h e o u t p u t v o l t - a g e f a l l s d o w n s l o w l y a t t h e l i g h t l o a d . a f t e r t h e s o f t - s t o p i n t e r v a l e l a p s e s , t h e s o f t - s t o p p r o c e s s e n d s a n d t h e i c t u r n s o f f . with a 50 o c hysteresis to lower the average t j during continuous thermal overload conditions, increasing life- time of the apw8804. e n a b l e a n d s h u t d o w n driving en to ground places the apw8804 in shutdown. in shutdown mode, the internal n-channel power mosfet turns off, all internal circuitry shuts down and the quiescent supply current reduces to less than 1 m a.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 1 2 f u n c t i o n d e s c r i p t i o n ( c o n t . ) p o w r g o o d i n d i c a t o r p o k i s a c t i v e l y h e l d l o w i n s h u t d o w n a n d s o f t - s t a r t s t a t u s . i n t h e s o f t - s t a r t p r o c e s s , t h e p o k i s a n o p e n - d r a i n . w h e n t h e s o f t - s t a r t i s f i n i s h e d , t h e p o k i s r e l e a s e d . i n n o r m a l o p e r a t i o n , t h e p o k w i n d o w i s f r o m 9 0 % t o 1 2 5 % o f t h e c o n v e r t e r r e f e r e n c e v o l t a g e . w h e n t h e o u t p u t v o l t a g e h a s t o s t a y w i t h i n t h i s w i n d o w , p o k s i g n a l w i l l b e c o m e h i g h . w h e n t h e o u t p u t v o l t a g e o u t r u n s 9 0 % o r 1 2 5 % o f t h e t a r g e t v o l t a g e , p o k s i g n a l w i l l b e p u l l e d l o w i m m e d i a t e l y . i n o r d e r t o p r e v e n t f a l s e p o k d r o p , c a p a c i t o r s n e e d t o p a r a l l e l a t t h e o u t p u t t o c o n f i n e t h e v o l t a g e d e v i a t i o n w i t h s e v e r e l o a d s t e p t r a n s i e n t .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 1 3 a p p l i c a t i o n i n f o r m a t i o n input capacitor selection b e c a u s e b u c k c o n v e r t e r s h a v e a p u l s a t i n g i n p u t c u r r e n t , a l o w e s r i n p u t c a p a c i t o r i s r e q u i r e d . t h i s r e s u l t s i n t h e b e s t i n p u t v o l t a g e f i l t e r i n g , m i n i m i z i n g t h e i n t e r f e r e n c e w i t h o t h e r c i r c u i t s c a u s e d b y h i g h i n p u t v o l t a g e s p i k e s . a l s o , t h e i n p u t c a p a c i t o r m u s t b e s u f f i c i e n t l y l a r g e t o s t a - b i l i z e t h e i n p u t v o l t a g e d u r i n g h e a v y l o a d t r a n s i e n t s . f o r g o o d i n p u t v o l t a g e f i l t e r i n g , u s u a l l y a 2 2 m f i n p u t c a p a c i t o r i s s u f f i c i e n t . i t c a n b e i n c r e a s e d w i t h o u t a n y l i m i t f o r b e t t e r i n p u t - v o l t a g e f i l t e r i n g . c e r a m i c c a p a c i t o r s s h o w b e t t e r p e r f o r m a n c e b e c a u s e o f t h e l o w e s r v a l u e , a n d t h e y a r e l e s s s e n s i t i v e a g a i n s t v o l t a g e t r a n s i e n t s a n d s p i k e s c o m - p a r e d t o t a n t a l u m c a p a c i t o r s . p l a c e t h e i n p u t c a p a c i t o r a s c l o s e a s p o s s i b l e t o t h e i n p u t a n d g n d p i n o f t h e d e v i c e f o r b e t t e r p e r f o r m a n c e . inductor selection for high efficiencies, the inductor should have a low dc resistance to minimize conduction losses. especially at high-switching frequencies, the core material has a higher impact on efficiency. when using small chip inductors, the efficiency is reduced mainly due to higher inductor core losses. this needs to be considered when selecting the appropriate inductor. the inductor value de- termines the inductor ripple current. the larger the induc- tor value, the smaller the inductor ripple current and the lower the conduction losses of the converter. conversely, larger inductor values cause a slower load transient response. a reasonable starting point for setting ripple current, d i l, is 40% of maximum output current. the rec- ommended inductor value can be calculated as below: l sw in out out i f v v 1 v l d ? ? ? ? ? - 3 i l(max) = i out(max) + 1/2 x d i l to avoid the saturation of the inductor, the inductor should be rated at least for the maximum output current of the converter plus the inductor ripple current. output voltage setting in the adjustable version, the output voltage is set by a resistive divider. the external resistive divider is con- nected to the output, allowing remote voltage sensing as ? ? ? ? ? + = ? ? ? ? ? + = 2 r 1 r 1 6 . 0 2 r 1 r 1 v v ref out shown in ?typical application circuits?. a suggestion of maximum value of r2 is 20k w to keep the minimum cur- rent that provides enough noise rejection ability through the resistor divider. the output voltage can be calculated as below: output capacitor selection the current-mode control scheme of the apw8804 al- lows the use of tiny ceramic capacitors. the higher ca- pacitor value provides the good load transients response. ceramic capacitors with low esr values have the lowest output voltage ripple and are recommended. if required, tantalum capacitors may be used as well. the output ripple is the sum of the voltages across the esr and the ideal output capacitor. ? ? ? ? ? + ? ? ? ? ? - @ d out sw sw in out out out c f 8 1 esr l f v v 1 v v when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage char- acteristics of all the ceramics for a given value and size. r 2 20 k w apw 8804 fb gnd v out r 1 80 k w v in v out i l n - fet sw i out c in c out i in esr p - fet i p - fet
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 1 4 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) output capacitor selection (cont.) i lim i l i peak i out i p-fet d i l layout consideration for all switching power supplies, the layout is an impor- tant step in the design; especially at high peak currents and switching frequencies. if the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. the input capacitor should be placed close to the pvdd and gnd. connecting the capacitor and pvdd/gnd with short and wide trace without any via holes for good input voltage filtering. the distance between vin/gnd to capacitor less than 2mm respectively is recommended. 2. to minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the lx pin to minimize the noise coupling into other circuits. 3. the output capacitor should be place closed to lx and gnd. 4. since the feedback pin and network is a high imped- ance circuit the feedback network should be routed away from the inductor. the feedback pin and feed- back network should be shielded with a ground plane or trace to minimize noise coupling into this circuit. 5. a star ground connection or ground plane minimizes ground shifts and noise is recommended. lx v out v d d c in l 1 c out via to vout gnd r 2 r 1 a p w 8 8 0 4 l a y o u t c o n s i d e r a t i o n t d f n 3 x 3 - 1 0 s o p - 8 p c in c out r 2 r 1 l 1 v d d lx gnd v out via to vout
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 1 5 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) a p w 8 8 0 4 r e c o m m e n d e d f o o t p r i n t 5 . 3 1 . 8 1 . 25 0 . 6 1 2 3 4 8 7 6 5 2 . 9 5 3 . 45 unit : mm ground plane for thermalpad thermalvia diameter 12 mil x 5 0 . 75 0 . 5 tdfn 3 x 3 - 10 2 . 7 0 0 . 275 1 . 75 0 . 3 unit : mm
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 1 6 p a c k a g e i n f o r m a t i o n s o p - 8 p thermal pad d d1 e 2 e 1 e e b h x 4 5 o c see view a a 2 a a 1 view a l 0 . 2 5 gauge plane seating plane q note : 1. followed from jedec ms-012 ba. 2. dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. dimension "e" does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 10 mil per side. 0.020 0.010 0.020 0.050 0.006 0.063 max. 0.40 l 0 0 o c e e h e1 0.25 d c b 0.17 0.31 0.016 1.27 8 o c 0 o c 8 o c 0.50 1.27 bsc 0.51 0.25 0.050 bsc 0.010 0.012 0.007 millimeters min. s y m b o l a1 a2 a 0.00 1.25 sop-8p max. 0.15 1.60 min. 0.000 0.049 inches d1 2.50 0.098 2.00 0.079 e2 3.50 3.00 0.138 0.118 4.80 5.00 0.189 0.197 3.80 4.00 0.150 0.157 5.80 6.20 0.228 0.244
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 1 7 p a c k a g e i n f o r m a t i o n t d f n 3 x 3 - 1 0 d e pin 1 a a1 a3 b pin 1 corner d2 e 2 l e 0.70 0.069 0.028 0.002 0.50 bsc 0.020 bsc 0.20 0.008 k 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122 s y m b o l min. max. 0.80 0.00 0.18 0.30 2.20 2.70 0.05 1.40 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tdfn3x3-10 0.30 0.50 1.75 0.008 ref min. max. inches 0.031 0.000 0.007 0.012 0.087 0.106 0.055 0.012 0.020 note : 1. followed from jedec mo-229 veed-5.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 1 8 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 sop - 8p 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0.4 0 6.40 ? 0.20 5.20 ? 0.20 2.10 ? 0.20 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 12.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 12.0 ? 0.30 1.75 ? 0.10 5.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tdfn3x3 - 10 4.0 ? 0.10 8.0 ? 0.10 2.0 ? 0.05 1.5+0.1 0 - 0.00 1.5 min. 0.6+0.00 - 0.40 3.30 ? 0.20 3.30 ? 0.20 1.30 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d d e v i c e s p e r u n i t package type unit quantity sop - 8p tape & reel 2500 tdfn3x3 - 10 tape & reel 3000
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 1 9 t a p i n g d i r e c t i o n i n f o r m a t i o n s o p - 8 p t d f n 3 x 3 - 1 0 user direction of feed user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 2 0 c l a s s i f i c a t i o n p r o f i l e c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - d e c . , 2 0 1 2 a p w 8 8 0 4 w w w . a n p e c . c o m . t w 2 1 c l a s s i f i c a t i o n r e f l o w p r o f i l e s ( c o n t . ) table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ 125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a115 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e l i a b i l i t y t e s t p r o g r a m c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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