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1/22 september 2004 this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. VIPER53EDIP viper53esp off line primary switch rev. 1 table 1. typical output power capability note : above power capabilities are given under adequate thermal conditions switching frequency up to 300 khz current mode control with adjustable current limitation soft start and shut down control automatic burst mode in stand-by condition (?blue angel? compliant) undervoltage lockout with hysteresis integrated startup current source overtemperature protection overload and short-circuit control overvoltage protection description the viper53e combines in the same package an enhanced current mode pwm controller with a high voltage mdmesh power mosfet. figure 1. package typical applications cover off line power supplies with a secondary power capability ranging up to 30w in wide range input voltage or 50w in single european voltage range and dip-8 package, with the following benefits: ? overload and short circuit controlled by feedback monitoring and delayed device reset. ? efficient standby mode by enhanced pulse skipping. integrated startup current source disabled during the normal operation to reduce the input power. table 2. order codes type european (195 - 265 vac) us / wide range (85 - 265 vac) VIPER53EDIP 50w 30w viper53esp 65w 40w 1 10 powerso-10 ? dip-8 package tube tape and reel dip-8 VIPER53EDIP - powerso-10 ? viper53esp viper53esp13tr preliminary data
VIPER53EDIP / viper53esp 2/22 figure 2. block diagram table 3. absolute maximum ratings note: 1. in order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1 k ? should be inserted in series with the tovl pin. symbol parameter value unit v ds continuous drain source voltage (t j =25 ... 125 c) (see note 1) -0.3 ... 620 v i d continuous drain current internally limited a v dd supply voltage 0 ... 19 v v osc osc input voltage range 0 ... v dd v i comp i tovl comp and tovl input current range (see note 1) -2 ... 2 ma v esd electrostatic discharge: machine model (r=0 ? ; c=200pf) charged device model 200 1.5 v kv t j junction operating temperature internally limited c t c case operating temperature -40 to 150 c t stg storage temperature -55 to 150 c ff oscillator 150/400ns blanking 1v overtemp. detector 8.4/ 11.5v vdd osc drain comp source pwm latch on/off blanking time selection pwm comparat or current amplifier s r1 r2 r3 r4 r5 q overload comparat or 18v 125k 0.5v standby comparat or overvolt age comparat or uvlo comparat or h comp 0.5v 4.4v 4.5v tovl 8v 4v vcc i comp
3/22 VIPER53EDIP / viper53esp figure 3. configuration diagram (top view) table 4. pin function figure 4. current and voltage conventions name function v dd power supply of the control circuits. also provides the charging current of the external capacitor during startup. the functions of this pin are managed by three threshold voltages: - v ddon : voltage value at which the device starts switching (typically 11.5 v). - v ddoff : voltage value at which the device stops switching (typically 8.4 v). - v ddovp : triggering voltage of the overvoltage protection (trimmed to 18 v). source power mosfet source and circuit ground reference. drain power mosfet drain. also used by the internal high voltage current source during the start-up phase, for charging the external v dd capacitor. comp input of the current mode structure. allows the setting of the dynamic characteristic of the converter through an external passive network. useful voltage range extends from 0.5 v to 4.5 v. the power mosfet is always off below 0.5 v, and the overload protection is triggered if the voltage exceeds 4.4v. this action is delayed by the timing capacitor connected to the tovl pin. tovl allows the connection of an external capacitor for delaying the overload protection, which is triggered by a voltage on the comp pin higher than 4.4 v. osc allows the setting of the switching frequency through an external rt-ct network. 1 2 3 4 5 10 9 8 7 6 vdd tovl nc nc nc osc comp nc nc source drain source tovl comp vdd nc drain source 1 5 4 8 7 6 2 3 osc dip-8 powerso-10 ? i dd v dd i osc v osc i tovl v tovl i comp v comp i d v ds vdd osc drain source comp tovl control
VIPER53EDIP / viper53esp 4/22 table 5. thermal data note: 2. when mounted on a standard single-sided fr4 board with 50mm 2 of cu (at least 35 m thick) connected to the drain pin. note: 3. when mounted on a standard single-sided fr4 board with 50mm 2 of cu (at least 35 m thick) connected to the device tab. electrical characteristics (t j =25 c, v dd =13v, unless otherwise specified) table 6. power section note: 4. on clamped inductive load note: 5. this parameter can be used to compute the energy dissipated at turn on e ton according to the initial drain to source voltage v dson and the following formula: table 7. oscillator section symbol parameter max value unit r thj-case dip-8 20 c/w r thj-amb dip-8 (see note 4) 80 c/w r thj-case powerso-10 ? 2 c/w r thj-amb powerso-10 ? (see note 4) 60 c/w symbol parameter test conditions min. typ. max. unit bv dss drain-source voltage i d =1ma; v comp =0v 620 v i dss off state drain current v ds =500v; v comp =0v; t j =125 c 150 a r ds(on) static drain-source on state resistance i d =1a; v comp =4.5v; v tovl =0v t j =25 c t j =100 c 0.9 1 1.7 ? ? t fv fall time i d =0.2a; v in =300v (see figure 5 and note 4) 100 ns t rv rise time i d =1a; v in =300v (see figure 5 and note 4) 50 ns c oss drain capacitance v ds =25v 170 pf c eon effective output capacitance 200v < v dson < 400v (see note 4) 60 pf e ton 1 2 -- -c eon 300 2 v dson 300 ------------------- ?? ?? 1.5 ??? = symbol parameter test conditions min. typ. max. unit f osc1 oscillator frequency initial accuracy r t =8k ? ; c t =2.2nf (see figure 9) 95 100 105 khz f osc2 oscillator frequency total variation r t =8k ? ; c t =2.2nf (see figure 10) v dd =v ddon ... v ddovp ; t j =0 ... 100 c 93 100 107 khz v oschi oscillator peak voltage 9 v v osclo oscillator valley voltage 4 v
5/22 VIPER53EDIP / viper53esp electrical characteristics (t j =25 c, v dd =13v, unless otherwise specified) table 8. supply section table 9. pwm comparator section note: 6. in order to insure a correct stability of the error amplifier, a capacitor of 10nf (minimum value: 8nf) should always be present on the comp pin. symbol parameter test conditions min. typ. max. unit v dsstart drain voltage starting threshold v dd =5v; i dd =0ma 34 50 v i ddch1 startup charging current v dd =0 ... 5v; v ds =100v (see figure 6) -12 ma i ddch2 startup charging current v dd =10v; v ds =100v (see figure 6) -2 ma i ddchoff startup charging current in thermal shutdown v dd =5v; v ds =100v (see figure 8) t j > t sd - t hyst 0ma i dd0 operating supply current not switching f sw =0khz; v comp =0v 811ma i dd1 operating supply current switching f sw =100khz 9ma v ddoff v dd undervoltage shutdown threshold (see figure 6) 7.5 8.4 9.3 v v ddon v dd startup threshold (see figure 6) 10.2 11.5 12.8 v v ddhyst v dd threshold hysteresis (see figure 6) 2.6 3.1 v v ddovp v dd overvoltage shutdown threshold (see figure 8) 17 18 19 v symbol parameter test conditions min. typ. max. unit h comp ? v comp / ? i dpeak v comp =1 ... 4 v (see figure 8) di d /dt=0 1.7 2 2.3 v/a v compos v comp offset di d /dt=0 (see figure 8) 0.5 v i dlim peak drain current limitation i comp =0ma; v tovl =0v (see figure 8) di d /dt=0 1.7 2 2.3 a i dmax drain current capability v comp =v compovl ; v tovl =0v di d /dt=0 (see figure 8) 1.6 1.9 2.3 a t d current sense delay to turn-off i d =1a 250 ns v compbl v comp blanking time change threshold (see figure 7) 1 v t b1 blanking time v comp < v compbl (see figure 7) 300 400 500 ns t b2 blanking time v comp > v compbl (see figure 7) 100 150 200 ns t onmin1 minimum on time v comp < v compbl 450 600 750 ns t onmin2 minimum on time v comp > v compbl 250 350 450 ns v compoff v comp shutdown threshold (see figure 8) 0.5 v v comphi v comp high level i comp =0ma (see note 5) 4.5 v i comp comp pull up current v comp =2.5v 0.6 ma
VIPER53EDIP / viper53esp 6/22 electrical characteristics (t j =25 c, v dd =13v, unless otherwise specified) table 10. overload protection section note: 7. v compovl is always lower than v comphi . table 11. overtemperature protection section symbol parameter test conditions min. typ. max. unit v compovl v comp overload threshold i tovl =0ma (see figure 4 and note 6) 4.35 v v diffovl v comphi to v compovl voltage difference v dd =v ddoff ... v ddovp ; i tovl =0ma (see figure 4 and note 6) 50 150 250 mv v ovlth v tovl overload threshold (see figure 4) 4 v t ovl overload delay c ovl =100nf (see figure 4) 8ms symbol parameter test conditions min. typ. max. unit t sd thermal shutdown temperature (see fig. 8) 140 160 c t hyst thermal shutdown hysteresis (see fig. 8) 40 c
7/22 VIPER53EDIP / viper53esp figure 5. rise and fall time figure 6. startup vdd current figure 7. blanking time figure 8. overload event i d v ds 90% 10% t fv t rv t t 300v cld c< VIPER53EDIP / viper53esp 8/22 figure 9: thermal shutdown figure 10: shut down action figure 11: overvoltage event figure 12: comp pin gain and offset t t v dd v comp t t j v ddon t sd t sd -t hyst automatic startup t t i d v comp t v osc v compoff v oschi v osclo abnormal operation t t v ds v comp t v dd v ddovp switching not switching normal operation v comp i dpeak v compos v comphi slope = 1 / h comp i dlim v compovl i dmax
9/22 VIPER53EDIP / viper53esp figure 13: oscillator schematic and settings the switching frequency settings shown on the graphic here below is valid within the following boundaries: r t 2k ? > f sw 300khz < 320 ? source osc vdd pwm section ct rt vcc 1 10 100 10 300 100 frequency (khz) r t (k ? ) 1nf 2.2nf 4.7nf 10nf 22nf
VIPER53EDIP / viper53esp 10/22 figure 14: typical frequency variation vs. junction temperature figure 15: typical current limitation vs. junction temperature -20 0 20 40 60 80 100 120 0.96 0.98 1 1.02 1.04 normalised frequency temperature ( c) -20 0 20 40 60 80 100 120 0.96 0.98 1 1.02 1.04 normalised idlim temperature ( c)
11/22 VIPER53EDIP / viper53esp figure 16: off line power supply with optocoupler feedback secondary feedback configuration example the secondary feedback is implemented through an optocoupler driven by a programmable zener of the tl431 type as shown on figure 11. the optocoupler is connected in parallel with the compensation network on the comp pin which delivers a constant biasing current of 0.6 ma to the optotransistor. this current doesn ? t depend on the compensation voltage, and so it doesn ? t depend on the output load either. the gain of the optocoupler ensures consequently a constant biasing of the tl431 device (u3) which is in charge of secondary regulation. if the optocoupler gain is sufficiently low, no additional components are required to ensure a minimum current biasing of u3. also, the low biasing current value avoid any ageing of the optocoupler. the constant current biasing can be used to simplify the secondary circuit: instead of a tl431, a simple zener and resistance network in series with the optocoupler diode can insure a good secondary regulation. as the current flowing in this branch remains constant for the same reason as above, typical load regulation of 1% can be achieved from zero to full output current with this simple configuration. since the dynamic characteristics of the converter are set on the secondary side through components associated to u3, the compensation network has only a role of gain stabilization for the optocoupler, and its value can be freely chosen. r5 can be set to a fixed value of 2.2 k ? , offering the possibility of using c7 as a soft start capacitor: when starting up the converter, the viper53e device delivers a constant current of 0.6 ma on the comp pin, creating a constant voltage of 1.3 v in r5 and a rising slope across c7. this voltage shape together with the operating range of 0.5 v to 4.5 v provides a soft startup of the converter. the rising speed of the output voltage can be set through the value of c7. c4 and c6 values must be adjusted accordingly in order to ensure a correct startup. r5 r3 r4 d3 d1 c1 t1 c2 f1 r1 d2 c7 c5 c4 c6 t2 d4 c8 c10 l1 c9 r2 c3 ac in dc out u2 u3 c11 r6 r7 r8 vdd osc drain source comp tovl control c12 10nf r9 1k
VIPER53EDIP / viper53esp 12/22 current mode topology the viper53e implements the conventional current mode control method for regulating the output voltage. this kind of feedback includes two nested regulation loops: the inner loop controls the peak primary current cycle by cycle. when the power mosfet output transistor is on, the inductor current (primary side of the transformer) is monitored with a sensefet technique and converted into a voltage v s . when v s reaches v comp , the power switch is turned off. this structure is completely integrated as shown on the block diagram of page 2, with the current amplifier, the pwm comparator, the blanking time function and the pwm latch. the following formula gives the peak current in the power mosfet according to the compensation voltage: the outer loop defines the level at which the inner loop regulates peak current in the power switch. for this purpose, v comp is driven by the output of the regulation loop (a tl431 through an optocoupler in secondary feedback configuration, see figure 11) and sets accordingly the peak drain current for each switching cycle. as the inner loop regulates the peak primary current in the primary side of the transformer, all input voltage changes are compensated for before impacting the output voltage. this results in an improved line regulation, instantaneous correction to line changes and better stability for the voltage regulation loop. current mode topology also provides a good converter startup control. as the compensation voltage can be controlled to increase slowly during the startup phase, the peak primary current will follow this soft voltage slope to provide a smooth output voltage rise, without any overshoot. the simpler voltage mode structure which only controls the duty cycle, leads generally to high currents at startup with the risk of transformer saturation. an integrated blanking filter inhibits the pwm comparator output for a short time after the integrated power mosfet is switched on. this function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side transformer capacitance or secondary side rectifier reverse recovery time when working in continuous mode. standby mode the device implements a special feature to address the low load condition. the corresponding function described hereafter consists of reducing the switching frequency by going into burst mode, with the following benefits: ? it reduces the switching losses, thus providing low consumption on the mains lines. the device is compliant with ? blue angel ? and other similar standards, requiring less than 0.5 w of input power when in standby. ? it allows the regulation of the output voltage, even if the load corresponds to a duty cycle that the device is not able to generate because of the internal blanking time, and associated minimum turn on. for this purpose, a comparator monitores the comp pin voltage, and maintains the pwm latch and the power mosfet in the off state as long as v comp remains below 0.5 v (see block diagram on page 2). if the output load requires a duty cycle below the one defined by the minimum turn on of the device, the regulation loop drives the comp voltage until it reaches this 0.5 v threshold (v compoff ). the power mosfet can be completely off for some cycles, and resumes normal operation as soon as v comp is higher than 0.5 v. the output voltage is regulated in burst mode. the corresponding ripple is not higher than the nominal one at full load. in addition, the minimum turn on time which defines the frontier between normal operation and burst mode changes according to v comp value. below 1 v (v compbl ), the blanking time increases to 400 ns, whereas it is 150 ns for higher voltages (see figure 7). the minimum turn on times resulting from these values are respectively 600 ns and 350 ns, when taking into account internal propagation time. this brutal change induces an hysteresis between normal operation and burst mode as shown on figure 12. i dpeak v comp v compos ? h comp --------------------------------------------------------- - = figure 17: standby mode implementation v comp v compsd v compbl v compoff 600ns 350ns f sw p in f swnom f swstby p stby p rst minimum 1 3 2 1 2 3 ton turn on
13/22 VIPER53EDIP / viper53esp when the output power decreases, the system reaches point 2 where v comp equals v compbl . the minimum turn on time passes immediately from 350 ns to 600 ns, exceeding the effective turn on time that should be needed at such output power level. therefore the regulation loop will quickly drive v comp to v compoff (point 3) in order to pass into burst mode and to control the output voltage. the corresponding hysteresis can be seen on the switching frequency which passes from f swnom which is the normal switching frequency set by the components connected to the osc pin, to f swstby . note that this frequency is actually an equivalent number of switching pulses per second, rather than a fixed switching frequency, as the device is working in burst mode. as long as the power remains below p rst the output of the regulation loop remains stuck at v compsd and the converter works in burst mode. its ? density ? increases (i.e. the number of missing cycles decreases) as the power approaches p rst , and resumes finally normal operation at point 1. the hysteresis cannot be seen on the switching frequency, but the comp pin voltage which passes brutally at that power level from point 3 to point 1. the power points value p rst and p stby are defined by the following formulas: where ip(v compbl ) is the peak power mosfet current corresponding to a compensation voltage of v compbl (1v), that is to say about 250 ma. note that the power point p stby where the converter is going into burst mode doesn ? t depend on the input voltage. the standby frequency f swstb y is given by: the ratio between the nominal switching frequency and the standby one can be as high as 4, depending on the lp value and input voltage. high voltage startup current source an integrated high voltage current source provides a bias current from the drain pin during the startup phase. this current is partially absorbed by internal control circuits in standby mode with reduced consumption and also supplies the external capacitor connected to the vdd pin. as soon as the voltage on this pin reaches the high voltage threshold v ddon of the uvlo logic, the device turns into active mode and starts switching. the startup current generator is switched off, and the converter should normally provide the needed current on the vdd pin through the auxiliary winding of the transformer, as shown on figure 11. the external capacitor c vdd on the vdd pin must be sized according to the time needed by the converter to startup, when the device starts switching. this time tss depends on many parameters, among which transformer design, output capacitors, soft start feature and compensation network implemented on the comp pin and the secondary feedback circuit. the following formula can be used for defining the minimum capacitor needed: figure 13 shows a typical startup event. v dd starts from 0 v with a charging current i ddch1 at about 9 ma. when about v ddoff is reached, the charging current is reduced down to i ddch2 which is about 0.6 ma. this lower current leads to a slope change on the v dd rise. the device starts switching for a v dd equal to v ddon , and the auxiliary winding delivers some energy to the v dd capacitor after the startup time tss. the charging current change at v ddoff allows a fast complete startup time tsu, and maintains a low restart duty cycle. this is especially useful for short circuits and overloads conditions, as described in the following section. p rst 1 2 -- -f swnom tb 1 td + () 2 v in 2 1 lp ------ - ?? ?? = p stby 1 2 -- -f swnom ip 2 v compbl () lp ?? ? = f swstby p stby p rst ------------------- -f swnom ? = c vdd i dd1 tss ? v ddhyst -------------------------- > figure 18: startup waveforms i dd i dd1 tss i ddch2 i ddch1 t t v ddsd v ddst v ddreg v dd tsu
VIPER53EDIP / viper53esp 14/22 short-circuit and overload protection a v compovl threshold of about 4.4 v has been implemented on the comp pin. when v comp goes above this level, the capacitor connected on the tovl pin begins to charge. when reaching typically 4 v (v ovlth ), the internal mosfet driver is disabled and the device stops switching. this state is latched thanks to the regulation loop which maintains the comp pin voltage above the v compovl threshold. since the vdd pin doesn ? t receive any more energy from the auxiliary winding, its voltage drops down until it reaches vddoff and the device is reset, recharging the vdd capacitor for a new restart cycle. note that if vcomp drops down below the v compovl threshold for any reason during the vdd drop, the device resumes switching immediately. the device enters an endless restart sequence if the overload or short circuit condition is maintained. the restart duty cycle d rst is defined as the time ratio for which the device tries to restart, thus delivering its full power capability to the output. in order to keep the whole converter in a safe state during this event, d rst must be kept as low as possible, without compromising the real start up of the converter. a typical value of about 10 % is generally sufficient. for this purpose, both vdd and tovl capacitors can be used to satisfy the following conditions: refer to the previous startup section for the definition of tss, and c vdd must also be checked against the limit given in this section. the maximum value of the two calculus will be adopted. all this behavior can be observed on figure 4. in figure 8 the value of the drain current id for v comp =v compovl is shown. the corresponding parameter i dmax is the drain current to take into account for design purpose. since i dmax represents the maximum value for which the overload protection is not triggered, it defines the power capability of the power supply. regulation loop stability the complete converter open loop transfer function can be built from both power cell and regulation loop transfer functions. a theoretical example can be seen in figure 16 for a discontinuous mode flyback loaded by a simple resistor, regulated from secondary side through an optocoupler. a typical schematic corresponding to this situation can be seen on figure 11. the transfer function of the power cell is represented as g(s) in figure 16. it exhibits a pole which depends on the output load and on the output capacitor value. as the load of a converter may change, two curves are shown for two different values of output resistance value, r l1 and r l2 . a zero at higher frequency values also appears, due to the output capacitor esr. note that the overall transfer function doesn ? t depend on the input voltage, thanks to the current mode control. c ovl 12.5 10 6 ? tss ?? > vdd 810 4 1 d rst ---------------- 1 ? ?? ?? c ovl i ddch2 ? v ddhyst ------------------------------------------- ?? ? > figure 19: typical regulation loop vdd osc drain source comp tovl control r1 c1 r3 r2 c2 vout r4 tl431
15/22 VIPER53EDIP / viper53esp a typical regulation loop is shown on figure 14 and has a fixed behavior represented by f(s) on figure 16. a double zero due to the r 1 -c 1 network on the comp pin and to the integrator built around the tl431 and r 2 -c 2 is set at the same value as the maximum load r l2 pole. the total transfer function is shown as f(s).g(s) at the bottom of figure 16. for maximum load (plain line), the load pole begins exactly where the zeros of the comp pin and the tl431 stop, and this results in a first order decreasing slope until it reaches the zero of the output capacitor esr. the point where the complete transfer function has a unity gain is known as the regulation bandwidth and has a double interest: ? the higher it is the faster will be the reaction to an eventual load change, and the smaller will be the output voltage change. ? the phase shift in the complete system at this point has to be less than 135 to ensure a good stability. generally, a first order gives 90 of phase shift, and 180 for a second order. in figure 16, the unity gain is reached in a first order slope, so the stability is ensured. the dynamic load regulation is improved by increasing the regulation bandwidth, but some limitations have to be respected: as the transfer function above the zero due the capacitor esr is not reliable (the esr itself is not well specified, and other parasitic effects may take place), the bandwidth should always be lower than the minimum of f c and esr zero. as the highest bandwidth is obtained with the highest output power (plain line with r l2 load in figure 16), the above criteria will be checked for this condition and allows to define the value of r 4 , if r1 is set fixed (2.2 k ? , for instance). the following formula can be derived: with: and: go is the current transfer ratio of the optocoupler. the lowest load gives another condition for stability: the frequency f bw1 must not encounter the third order slope generated by the load pole, the r1-c1 network on the comp pin and the r2- c2 network at the level of the tl431 on secondary side. this condition can be met by adjusting both c 1 and c2 values: with: the above formula gives a minimum value for c 1 . it can be then increased to provide a natural soft start function as this capacitor is charged by the error amplifier current capacity i comp at start-up. special recommendations a capacitor of 10 nf (minimum value: 8 nf) should always be connected to the comp pin to insure a correct stability of the internal current source. this is represented on figure 11. in order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1 k ? should be inserted in series with the tovl pin, as shown on figure 11. note that this resistance doesn ? t impact the overload delay, as its value is negligeable in front of the internal pull up resistance (about 125 k ? ). r 4 p max p out2 ------------------- - g o r 1 ? f bw2 r l2 c out ?? ------------------------------------------------------ - ? = p out2 v out 2 r l2 ----------------- = p max 1 2 -- -l p i lim 2 f sw ?? ? = c 1 r l1 c out ? 6.3 g o r 4 -------- r 1 2 ?? --------------------------------- p out1 p max ------------------- - ? > c 2 r l1 c out ? 6.3 g o r 4 -------- r 1 r 2 ??? -------------------------------------------- p out1 p max ------------------- - ? > p out1 v out 2 r l1 ----------------- =
VIPER53EDIP / viper53esp 16/22 software implementation all the above considerations and some others are included in a design software which provides all the needed components around the viper device for a specified output configuration. this software is available in download on the st internet site. figure 20: complete converter transfer function g( s ) f f c f f f( s ) f( s ).g( s ) 1 r l1 c out ?? ---------------------------------------- - 1 r l2 c out ?? ---------------------------------------- - 1 2 esr c out ?? ? ------------------------------------------------ - f bw 2 f bw 1 1 1 1 3.2 p max p out2 ------------------- - ? 3.2 p max p out1 ------------------- - ? g o r 1 r 4 ------ - ? 1 2 r comp c comp ?? ? ---------------------------------------------------------------- -
17/22 VIPER53EDIP / viper53esp package mechanical table 12. plastic dip-8 mechanical data figure 21. plastic dip-8 package dimensions symbol millimeters min typ max a 5.33 a1 0.38 a2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 d 9.02 9.27 10.16 e 7.62 7.87 8.26 e1 6.10 6.35 7.11 e2.54 ea 7.62 eb 10.92 l 2.92 3.30 3.81 package weight gr. 470 p001
VIPER53EDIP / viper53esp 18/22 package mechanical table 13. powerso-10? mechanical data note: (*) muar only poa p013p figure 22. powerso-10? package dimensions symbol millimeters min typ max a 3.35 3.65 a (*) 3.4 3.6 a1 0.00 0.10 b 0.40 0.60 b (*) 0.37 0.53 c 0.35 0.55 c (*) 0.23 0.32 d 9.40 9.60 d1 7.40 7.60 e 9.30 9.50 e2 7.20 7.60 e2 (*) 7.30 7.50 e4 5.90 6.10 e4 (*) 5.90 6.30 e1.27 f 1.25 1.35 f (*) 1.20 1.40 h 13.80 14.40 h (*) 13.85 14.35 h0.50 l 1.20 1.80 l (*) 0.80 1.10 a0 o 8 o (*) 2 o 8 o detail "a" plane seating l a1 f a1 h a d d1 = = = = e4 0.10 a c a b b detail "a" seating plane e2 10 1 eb he 0.25 p095a
19/22 VIPER53EDIP / viper53esp figure 23. plastic dip-8 tube shipment (no suffix) all dimensions are in mm. base q.ty 20 bulk q.ty 1000 tube length ( 0.5) 532 a 8.4 b 11.2 c ( 0.1) 0.8 a b c
VIPER53EDIP / viper53esp 20/22 figure 24. powerso-10 ? suggested pad layout and tube shipment (no suffix) figure 25. tape and reel shipment (suffix ?13tr?) 6. 30 10.8 - 11 14.6 - 14.9 9.5 1 2 3 4 5 1.27 0.67 - 0.73 0. 54 - 0. 6 10 9 8 7 6 b a c c a b muar casablanca all dimensions are in mm. base q.ty bulk q.ty tube length ( 0.5) a b c ( 0.1) casablanca 50 1000 532 10.4 16.4 0.8 muar 50 1000 532 4.9 17.2 0.8 reel dimensions all dimensions are in mm. base q.ty 600 bulk q.ty 600 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
21/22 VIPER53EDIP / viper53esp revision history table 14. revision history date revision description of changes 31-aug-2004 1 - first issue
VIPER53EDIP / viper53esp 22/22 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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