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L6372 octal industrial input interface product preview input status monitoring by means of current levels detection externally programmable upper current level input open line detection input protection by means of inter- nal diodes clamping to ground and supply voltage digital filtering of noise on each channel allows implementation with mini- mum power dissipation of 8 current sinking inputs according to the iec standard data transfer from parallel in to serial out description the L6372 is especially designed for use as a line receiver in industrial control systems based on the 24v/6ma signal levels (iec1131, 24vdc, type 2). 8 input lines can be connected to the de- vice. up to 8 input lines can be connected to each de- vice. several devices can be linked to monitor more than 8 lines. this is advanced information on a new product now in development or undergoing evaluation. details are subject to change without notice. september 1994 functional diagram ordering numbers: L6372dp (powerdip16+2+2) L6372fp (so16+2+2) multipower bcd technology so 16+2+2 powerdip 16+2+2 1/15
pin connection absolute maximum ratings symbol pin parameter value unit v s 14 supply voltage (t w 10ms) 40 v v ilog 9 logic input voltage (dc) -0.3 to 7 v 10 (see channel protection) i ilog 11, 12 logic input forced current, per pin 1ma i i 1, 2, 3, 4, 17, 18, 19, 20 channel input current (t w 1ms) (see channel protection) 2a v line - i channel input voltage (see channel protection) -0.3 to v s +0.3 v i out 13 output current 10 to -20 ma v out output voltage -3 to 5 v i set 7, 8 setting pins forced current 1ma v set setting pins forced voltage - 0.3 to 5 v t op ambient temperature operating range - 25 to 85 c t j junction temperature operating range (see overtemperature protection) - 25 to 125 c t st storage temperature range - 55 to 150 c note: esd immunity for pins 1,2,3,4,17,18,19 and 20 is guaranteed up to 1200v (human body modelnegative spike versus v s ) L6372 2/15
electrical characteristics (t j = -25 to 125 c; v s = 24v; unless otherwise specified.) dc operation symbol pin parameter test condition min. typ. max. unit v s 14 supply voltage (operative) 12 24 35 v v sh 14 power-on upper threshold v s variable 9.8 10.4 11 v v s hys 14 power-on hysteresis 400 800 1600 mv i s 14 supply current v s = 12 to 35v t j = -25 c all inputs i i = 1ma, v s = 24v 12 ma v s = 12 to 35v t j =25 c all inputs i i = 1ma, v s = 24v 10.5 ma v s = 12 to 35v t j = 125 c all inputs i i = 1ma, v s = 24v 9 ma v oh 13 output voltage high i o =0;v s = 12 to 35v 4.8 5.2 5.5 v i o = 3ma; v s = 12 to 35v 3.5 v i oh 13 output source current v o = 2v; v s =12to35v 4 ma v ol 13 output voltage low i o = 4ma; v s = 12 to 35v 0.4 v v s = 24v; t j= 25 c 0.15 v i ol 13 output sink current v o = 5v; v s =12to35v 5 ma v s = 24v; t j= 25 c12ma v th+ (*) 9 to 12 positive going input threshold v s = 12 to 35v 1 1.3 1.6 v v th- (*) 9 to 12 negative going input threshold v s = 12 to 35v 0.85 1.1 1.4 v hy in (*) 9 to 12 input hysteresis v s = 12 to 35v 0.1 0.2 0.4 v i lin 9 to 12 input leak current v s = 12 to 35v; v in =-0.2 to 5.2v -100 100 m a i 1 1to4, 17 to 20 limited input current v i= 0.5 to 1.1v 0.375 0.550 0.750 ma i 2 1to4, 17 to 20 limited input current r ref = 12k w; v in = 2.4 to 30v i 2 appr. = k 2 ? 1.26v/r ref for r ref = 11 to 30k w 6.1 6.8 7.48 ma v reg 1to4, 17 to 20 regulated input voltage i i = 0.750 to 2ma 1.0 1.2 1.6 v i i = 2 to 6.1ma 1.0 1.2 2.4 v v 11 (*) 1 to 4, 17 to 20 comparator 1 low threshold 0.4 0.7 v v 1h (*) 1 to 4, 17 to 20 comparator 1 high threshold 0.9 1.0 v h c1 (*) 1 to 4, 17 to 20 comparator 1 hysteresis 0.1 0.2 0.4 v v 2l 1to4, 17 to 20 comparator 2 low threshold 1.6 2.0 v v 2h 1to4, 17 to 20 comparator 2 high threshold 2.2 2.4 v h c2 1to4, 17 to 20 comparator 2 hysteresis 0.1 0.2 0.4 v (*) guaranteed by design, not tested. L6372 3/15
electrical characteristics (t j = -25 to 125 c; unless otherwise specified.) ac operation symbol parameter test condition min. typ. max. unit f osc (*) oscillator frequency c = 1.2nf; r ref = 12k w; 8.8 10 11.2 khz i chg (*) current charging r ref = 12k w 40 50 60 v hosc upper switching threshold 3.2 3.7 v v losc lower switching threshold, 1 1.5 v t sv time serial valid time from 0.85v on pin p/s to the first rising edge of the external clock 0.8 m s t so time serial out time from negative edge on pin p/s to activation of the output buffer of d out with the content of the eighth flip/flop 0.35 m s t ckh high level clock duration 300 ns t ckl low level clock duration 300 ns f clock clock frequency 1.5 mhz t r clock rise time 500 ns t f clock fall time 500 ns t su set up time for d in before the clock rising edge 200 ns t hold hold time for d in after the rising edge of the clock 0ns t delay delay time of d out after the rising edge of the clock 15 45 150 ns t pdin internal delay, d in to the d input of the first of the eight flip/flops 50 90 200 ns (*) f osc and i chg vary inversely to r ref , for r ref from 11k w to 30k w. m a L6372 4/15
thermal characteristics r th j-pin powerdip . the thermal resistance is re- ferred to the thermal path from the dissi- pating region on the top surface of the sili- con chip, to the points along the four central pins of the package, at a distance of 1.5 mm away from the stand-offs. so . similarly, the reference point is the knee on the four central pins, where the pins are upwardly bent and the soldering joint with the pcb footprint can be made. r th j-amb 1 if a dissipating surface, thick at least 35 m m and with a surface similar or bigger than the one shown, is created making use of the printed circuit. such heatsinking sur- face is considered on the bottom side of an horizontal pcb (worst case). r th j-amb 2 if the power dissipating pins (the four cen- tral ones), as well as the others, have a minimum thermal connection with the ex- ternal world (very thin strips only) so that the dissipation takes place through still air and through the pcb itself. it is the same situation of point above, without any heatsinking surface created on purpose on the board. additional data for the powerdip package can be found in: application note 9030: thermal characteristics of the power dip 20, 24 packages soldered on 1,2,3 oz. copper pcb thermal data symbol parameter dip 20 so 20 unit r th j-pin thermal resistance junction to pin 12 17 c/w r th j-amb 1 thermal resistance junction to ambient (see thermal characteristics) 40 65 c/w r th j-amb 2 thermal resistance junction to ambient (see thermal characteristics) 50 80 c/w figure 1: printed heatsink L6372 5/15
external line characteristics the input characteristics of each of the eight channels of the L6372 do not implement directly the input characteristics required by the oiec1131, 24vdc, type 2o, because the iec specification requires that the line receiver uses at least a certain amount of power, that is, for eight inputs, more than the maximum power that a silicon ic in a package of reasonable dimen- sions can dissipate. the solution adopted includes one or two external resistors per every line receiver implemented. one resistor is sufficient if no visual indication of the line status is required. if a led is included, two resistors are sufficient, and in addition the channel input protections of the L6372 also pro- tect the led. different input characteristic; of the line receiver can be implemented according to the choice of the values of -r 1 (one per input) -r 2 (if used, one per input) -r ref (one per ic). different input characteristics may be chosen to match the constraints of: - complying with the mask allowed for the in- put characteristics by the iec recommen- dation (see figure 4); - not exceeding the maximum allowed power dissipation per line input (depending on the equipment construction and characteristic); - not exceeding the maximum allowed power dissipation per channel input in the ic (de- pending upon the type of ic package dip or so its heatsinking characteristics through the pcb, and the maximum ambi- ent temperature around it). a) is the simplest possible case: no visual in- dication of the line status is implemented; the system dissipation is the minimum pos- sible, but the dissipation in the ic channel is higher than in the cases b) and c). b) assumes that v s can be kept at 12v, and made sink the excess line current from the channel protection diodes when the input lines are at their high level; the channel dissipation can be kept to a minimum. c) allows a very low power dissipation, with the led and v s anywhere in the allowed range. in all cases the iec mask is re- spected because the detection of the tran- sition from olow level receivedo to ohigh level receivedo, operated by the thresholds v 2l and v 2h (see figure 5), takes place when the line voltage is inside the area from 5 to 11 v allowed by the iec recom- mendation. figure 2: external channel circuits r re f r 1 r 2 vs case a 12 k w 2% 1.1k w 5% e 12 to 35v case b 15 k w 2% 1.0k w 5% 11.6 to 12v case c 18 k w 2% 1.2k w 5% 12 to 35v 2.0k w 5% 680 w 5% L6372 6/15
figure 3 a) c) b) L6372 7/15
the masks in figure3 for the cases a), b), c) plot, in a i/v diagram (horizontally the line input current and vertically the line input voltage), the resulting line input characteristics. they appear as three curves for each diagram, starting from the origin and running close to each other. one shows the case where all tolerances combine to generate the typical case, and the other two to generate the opposite extreme characteristics. in the plots the boundaries of the regions recommended by the oiec 1131 24vdc, type 2o for the different in- put decoding functions to take place, are shown. other choices for r 1 ,r 2 and r ref are of course possible, and case by case the set of values shall be different, according to the different design con- straint of the application. in the above paragraph it has been assumed that the leds are of the green or yellow types (higher forward drop than the more common red ones). channel protection at the input of each channel, two diodes clamp the voltage to v s and to ground. they have been designed and sized in order to: - exhibit a low forward voltage drop when pulses of inrushing current up to 2a are forced, v f typical of 2v @ 2a (2a corresponds to a voltage of 2kv if a resistor of 1k w is put externally in series to each channel input); - avoid interference of noise pulses on the ad- jacent channels (a 1a pulse lasting up to 100 m s won't be felt in the adjacent channels); - avoid interference with the overall chip opera- tion due to parasitic elements in the inte- grated circuit structure (very low leakage to the chip substrate during forward conduction, and no parasitic transistors with the other dif- fused structures close by in the chip). the series resistance r 1 combines with the two protection diodes at each channel input, to imple- ment an effective protection from any line distur- bance. input channel on each of its 8 inputs the L6372 continuously monitors, by means of two comparators, whether: - it is possible to sink the high level current (equal to or greater than the level pro- grammed by an external resistor r ref , called i 2 and typically set at 6.8 ma ); or - if at least it is possible to sink a current equal to, or greater than the low level current (fixed inside the ic, called i 1 and having a typical value of 550 m a). in the following tables the conditions of power dis- sipation for the three cases are given. for the calculation of the dissipated power, the extreme case when all channel are working with maximum current, maximum line voltage and maximum supply voltage to the ic (unless other- wise specified) has been considered. min. typ. max. unit i line-i @v line-i = 11v 6.12 6.80 7.48 ma i line-i @v line-i = 30v 6.12 6.80 7.48 ma p diss on chip @ v line-i = 30v 1.45 1.56 1.65 w p diss on board @ v line-i = 30v 1.79 1.96 2.11 w a) min. typ. max. unit i line-i @v line-i = 11v 6.04 6.47 6.92 ma i line-i @v line-i = 30v 15.50 16.39 17.35 ma p diss on chip @ v line-i = 30v 686 725 764 mw p diss on board @ v line-i = 30v 4.07 4.28 4.51 w c) min. typ. max. unit i line-i @v line-i = 11v 6.03 6.60 7.19 ma i line-i @v line-i = 30v 16.40 17.22 18.10 ma p diss on chip @ v line-i = 30v 634 698 760 mw p diss on board @ v line-i = 30v 3.39 3.59 3.81 w b) (v s = 12v) L6372 8/15
if not even the low level current i 1 can be sunk, then the signal is interpreted as o input discon- nected o. around i 1 the input characteristic is a constant current line, and the voltage varies rap- idly. a voltage comparator is sensing the input, and is triggered at levels of v 1l (typically 0.7v) and v 1h (typically 0.9v). the distance between the two thresholds (hysteresis) is provided to give immu- nity against the noise that may affect the input signal. if an intermediate level is detected, sinking a cur- rent between i 1 and i 2 , the signal is interpreted as oline connected, with a low level signal receivedo. again, an internal voltage comparator is used, with two thresholds separated by an hysteresis for noise immunity (v 2l , typically 2v and v 2h , typi- cally 2.2v). if a level clearly corresponding to the current i 2 is detected, then the signal is inter- preted as o line connected, with a high level sig- nal received o. data/diagnostic the signal on pin 12, dt/dg, decides whether the information on the signals level or the information on the status of the lines is transferred to the digi- tal section of the device. a high level on this pin means that data are to be transferred to the inputs of the digital filters; a low level means that the diagnostics are requested instead. table 1: dt/dg selection: input to the digital filter input current (input voltage vi) below low level (v i L6372 9/15
frequency generation - internal if the local oscillator is used, the pin osc will be connected to a capacitor c, grounded on the other side. the oscillation is achieved by an internal cur- rent generator, that repeatedly charges and discharges the capacitor c between two volt- age levels (v hosc and v losc , typically 3.5v and 1.5v). the current has the same absolute value (i chg ) both during the charge and dis- charge phase. i chg is obtained mirroring the current that flows through r ref (1.26v/r ref ),with a coeffi- cient of 0.457, so that, for instance, if r ref is 12k w ,i chg is typically 50 m a. the frequency can be calculated as: f osc = i chg 2 ? c ? ( v hosc - v losc ) for instance, if r re f = 12k w and c = 1.2nf, f osc is about 10khz. the method to determine f osc indicated here above gives the value to be expected with the highest probability. all the positive causes of deviation in the chip, including v s and t j , will not, in practice, combine and create a devia- tion, from such calculated f osc value, in ex- cess of 12%. - external if an external signal is to be used, it will be fed directly into the osc pin, without any ca- pacitor for oscillation purposes. the internal impedance of the generator of such signal must be low enough to override i chg , and the voltage swing must exceed the upper (v hosc ) and lower (v iosc ) thresholds. in order to have a margin, add 20% to the i chg value calcu- lated with the formula i chg = ( 0.457 ? 1.26v ) r ref and use for v losc and v hosc the extreme values given in the data sheet. filter operation each filter is a synchronous state machine, with 8 significant states, clocked by the oscillator fre- quency divided by 8. in 4 states (0xx) the output is 0, in the other 4 states (1xx) the output is 1. at the chip start-up (power-on reset) or in case of overtemperature the fundamental 0 state is forced ( it corresponds to the reset of the filter state). when the normal operation of the chip is allowed, the input to the filter generates the following tran- sition table: figure 5: input channel characteristics L6372 10/15
present state filter output input next state 000 0 0 000 000 0 1 001 001 0 0 000 001 0 1 010 010 0 0 000 010 0 1 011 011 0 0 000 011 0 1 100 100 1 0 101 100 1 1 100 101 1 0 110 101 1 1 100 110 1 0 111 110 1 1 100 111 1 0 000 111 1 1 100 it can be seen, for instance, that pulses of the in- put, with a polarity opposite to the output and last- ing for less than four clock periods, are com- pletely filtered out. if instead the input exhibits a change of level that lasts long enough for four clock edges to sample it, then the output of the filter, after the four clock periods, follows the change of level at the input. if an input signal with changes that do not occur more often that every 32 periods of the main os- cillation is considered, it can be seen that such fil- ter introduces a delay of the input transitions that is randomly variable from 24 to 32 periods of the main oscillation. in the case of input transitions that occur closer to each other than 24 periods of the oscillator, the resulting pulse is considered an unwanted noise pulse and is consequentlyeliminated by the filter. an input pulse lasting between 24 and 32 periods could either be cancelled or acknowledged by the filter, with the delay said above, according to the relative phase of such pulse with respect to the square wave (clock/8) that clocks the filter. device output to extract the information from the L6372 (line le vels or line statuses according to the dt/dg pin) the external processor activates the following se- quence: 1)the level on pin p/s (parallel active high / se- rial active low) is brought from its normal high level to a low logical level. the parallel jam inputs to the 8 flip-flops of the shift register are disabled. the last datum available is kept in each cell. the output of the first cell of the shift register is made available on the output pin dout. when the L6372 is in parallel mode, dout is kept at its low level, irrespectively of the out- put of the shift register. the signals on the L6372 inputs clk and din are made available on the relevant internal inputs to the shift register. 2)the external processor can now start clocking the shift register. at every rising edge of the signal on the clk pin, the data are shifted one step forward. in a typical case, several L6372 are chained to- gether. the clock signal is common. the dout of the first is connected to the din of the second, and so on, so that the external proc- essor can, with a single shift operation, read the data of all the devices chained together, from the output dout of the last in the chain. reset an internal reset signal is generated any time an anomalous condition is detected, and used to block the device operation. such reset signal is generated when one (or both) of the following conditions is detected: - undervoltage - overtemperature it inhibits the serial output, resets the shift register and the digital filters, but has no effect on the creation of the reference voltages of the internal comparators, nor on the continuous operation of the oscillator. the reset disappears one or two clock pulses af- ter the overtemperature or undervoltage condition has disappeared. undervoltage detection the supply voltage is expected to range from 12v to 30v, even if its reference value is considered to be 24v. in this range the L6372 operates correctly. below 12v the overall system has to be considered not reliable. consequently the supply voltage is moni- tored continuously and a signal, called uv, is in- ternally generated and used. the signal is oono as long as the supply voltage does not reach the upper internal threshold of the v s comparator (called v sh and typically found at 10.4v).the uv disappears above v sh . once the uv has been removed, the supply volt- age must decrease below the lower threshold (called v sl , and typically set at 10.2v) before it is turned on again. the hysteresis of approximately 800mv is pro- vided to prevent intermittent operation of the de- vice at low supply voltages that may have a su- perimposed ripple around the average value. L6372 11/15
overtemperature if the chip temperature exceeds t h (measured in a central position in the chip) the chip deactivates itself, because an internal signal, called ot, forces the reset signal. to reduce the device power dissipation to a minimum, the ot signal turns-off the internal current generators of the eight channels and the internal oscillator opera- tions. normal condition (ot low) is resumed as soon as (typically after some seconds) the chip temperature monitored goes back below t i . the different thresholds t h and t l, with hysteretic behavior, assure that no intermittent conditions can be generated. typical values for t h and t l , are 170 o c and 150 o c. figure 8: timing figure 9: typical application L6372 12/15
powerdip20 package mechanical data dim. mm inch min. typ. max. min. typ. max. a1 0.51 0.020 b 0.85 1.40 0.033 0.055 b 0.50 0.020 b1 0.38 0.50 0.015 0.020 d 24.80 0.976 e 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 f 7.10 0.280 i 5.10 0.201 l 3.30 0.130 z 1.27 0.050 L6372 13/15
so20 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 12.6 13.0 0.496 0.512 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.4 7.6 0.291 0.299 l 0.5 1.27 0.020 0.050 m 0.75 0.030 s 8 (max.) L6372 14/15
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications men- tioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. L6372 15/15

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