View ICS94211AF_7250366.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated circuit systems, inc. ics94211 0441e?11/17/04 pin configuration recommended application: 440bx/via apollo pro133/ ali 1631 style chipset. output features: 2 - cpus @2.5v 1 - ioapic @ 2.5v 13 - sdram @ 3.3v 6 - pci @3.3v, 1 - 48mhz, @3.3v 1 - 24mhz @ 3.3v 2 - ref @3.3v, 14.318mhz. features: programmable ouput frequency. programmable ouput rise/fall time. programmable pciclk, pciclk_f, sdram skew. real time system reset output spread spectrum for emi control typically by 7db to 8db, with programmable spread percentage. watchdog timer technology to reset system if over-clocking causes malfunction. uses external 14.318mhz crystal. fs pins for frequency select key specifications: cpu ? cpu: <175ps sdram - sdram: <500ps pci ? pci: <500ps cpu(early)-pci: min=1.0ns, typ=2.0ns, max=4.0ns programmable system frequency generator for p ii / iii ? block diagram 48-pin 300mil ssop * internal pull-up resistor of 120k to vdd ** internal pull-down resistor of 120k to gnd functionality 3 s f2 s f1 s f0 s f u p c ) z h m ( k l c i c p ) z h m ( 0000 0 0 . 0 80 0 . 0 4 000 1 0 0 . 5 70 5 . 7 3 00 10 1 3 . 3 85 6 . 1 4 00 11 2 8 . 6 61 4 . 3 3 0100 0 0 . 3 0 13 3 . 4 3 0101 1 0 . 2 1 14 3 . 7 3 0110 1 0 . 8 61 0 . 4 3 0 111 3 2 . 0 0 11 4 . 3 3 1000 0 0 . 0 2 10 0 . 0 4 10 0 1 9 9 . 4 1 13 3 . 8 3 10 10 9 9 . 9 0 16 6 . 6 3 10 1 1 0 0 . 5 0 10 0 . 5 3 1100 0 0 . 0 4 10 0 . 5 3 110 1 0 0 . 0 5 10 5 . 7 3 1110 0 0 . 4 2 10 0 . 1 3 1111 9 9 . 2 3 15 2 . 3 3 pci_stop# pll2 pll1 spread spectrum 48mhz 24mhz ioapic cpuclk (1:0) reset# sdram (12:0) pciclk (4:0) pciclk_f x1 x2 buffer in xtal osc pci clock divder stop s data sclk fs(3:0) mode control logic config. reg. /2 ref(1:0) 2 2 13 5 4 vddref *pci_stop/ref0 gnd x1 x2 vddpci *mode/pciclk_f **fs3/pciclk0 gnd pciclk1 pciclk2 pciclk3 pciclk4 vddpci buffer_in gnd sdram12_f sdram11 vddsdr sdram10 sdram9 gnd sdata sclk vddlapic ioapic ref1/fs2* gnd cpuclk0 cpuclk1 vddlcpu reset# sdram0 gnd sdram1 sdram2 vddsdr sdram3 sdram4 gnd sdram5 sdram6 vddsdr sdram7 sdram8 vdd48 48mhz/fs0* 24mhz/fs1* ics94211 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2 ics94211 0441e?11/17/04 general description pin configuration the ics94211 is a single chip clock solution for desktop designs using the bx/apollo pro133/ali 1631 style chipset. it provides all necessary clock signals for such a system. the ics94211 belongs to ics new generation of programmable system clock generators. it employs serial programming i 2 c interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/ enabling individual clocks. this device also has ics propriety 'watchdog timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking. notes: 1: internal pull-up resistor of 120k to 3.3v on indicated inputs 2: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic hi to vdd or gnd for logic low. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1f e r d d vr w pv 3 . 3 l a n i m o n , y l p p u s r e w o p l a t x , f e r 2 0 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 # p o t s _ i c p 1 n i e l i b o m n i ( w o l t u p n i n e h w , l e v e l 0 c i g o l t a s k c o l c ) 4 : 0 ( k l c i c p s t l a h ) 0 = e d o m , e d o m , 2 2 , 6 1 , 9 , 3 5 4 , 9 3 , 3 3 d n gr w pd n u o r g 41 xn i k c a b d e e f d n a ) f p 6 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 52 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 6 3 ( p a c 4 1 , 6i c p d d vr w pv 3 . 3 l a n i m o n , ) 4 : 0 ( k l c i c p d n a f _ k l c i c p r o f y l p p u s 7 f _ k l c i c pt u o r e w o p r o f # p o t s _ i c p y b d e t c e f f a t o n k c o l c i c p g n i n n u r e e r f . t n e m e g a n a m e d o m 2 , 1 n i d e h c t a l . e d o m e l i b o m = 0 , e d o m p o t k s e d = 1 , n i p t c e l e s n o i t c n u f 7 n i p . t u p n i 8 3 s fn id n g o t n w o d - l l u p l a n r e t n i . t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 0 k l c i c pt u o w e k s s n 8 4 - 1 h t i w s k c o l c u p c o t s u o n o r e h c n y s . s t u p t u o k c o l c i c p ) y l r a e u p c ( 0 1 , 1 1 , 2 1 , 3 1) 1 : 4 ( k l c i c pt u o w e k s s n 8 4 - 1 h t i w s k c o l c u p c o t s u o n o r e h c n y s . s t u p t u o k c o l c i c p ) y l r a e u p c ( 5 1n i r e f f u bn i. s t u p t u o m a r d s r o f s r e f f u b t u o n a f o t t u p n i , 8 2 , 1 2 , 0 2 , 8 1 , 7 1 , 5 3 , 4 3 , 2 3 , 1 3 , 9 2 0 4 , 8 3 , 7 3 ) 0 : 2 1 ( m a r d st u o n i p n i r e f f u b m o r f s t u p t u o r e f f u b t u o n a f , s t u p t u o k c o l c m a r d s ) t e s p i h c y b d e l l o r t n o c ( 6 3 , 0 3 , 9 1r d s d d vr w p. v 3 . 3 l a n i m o n , e r o c l l p u p c d n a ) 2 1 : 0 ( m a r d s r o f y l p p u s 3 2a t a d so / ii r o f t u p n i a t a d 2 t u p n i t n a r e l o t v 5 , t u p n i l a i r e s c 4 2k l c sn ii f o t u p n i k c o l c 2 t u p n i t n a r e l o t v 5 , t u p n i c 5 2 z h m 4 2t u ok c o l c t u p t u o z h m 4 2 1 s f 2 , 1 n i. t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 6 2 z h m 8 4t u ok c o l c t u p t u o z h m 8 4 0 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 7 28 4 d d vr w p. e r o c l l p d e x i f d n a s r e f f u b t u p t u o z h m 8 4 & 4 2 r o f r e w o p 1 4t e s e rt u o r o e g n a h c o i t a r y c n e u q e r f r o f l a n g i s t e s e r m e t s y s e m i t l a e r . w o l e v i t c a s i l a n g i s s i h t . t u o e m i t r e m m i t g o d h c t a w 2 4u p c l d d vr w pl a n i m o n v 5 . 2 , s k c o l c u p c r o f y l p p u s 3 41 k l c u p ct u ow o l = # p o t s _ u p c f i w o l . 2 l d d v y b d e r e w o p , s t u p t u o k c o l c u p c 4 40 k l c u p ct u o# p o t s _ u p c e h t y b d e t c e f f a t o n . k c o l c u p c g n i n n u r e e r f 6 4 1 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 2 s f 2 , 1 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 7 4c i p a o it u oc i p a o i. l d d v y b d e r e w o p z h m 8 1 3 . 4 1 . t u p t u o k c o l c 8 4c i p a l d d vr w p. v 5 . 2 . s t u p t u o c i p a o i e h t r o f n i p r e w o p
3 ics94211 0441e?11/17/04 general i 2 c serial interface information for the ics94211 how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending byte 0 through byte 20 (see note) ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends byte 0 through byte 8 (default) ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8). ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit controller (host) ics (slave/receiver) start bit address d2 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack byte 18 ack byte 19 ack byte 20 ack stop bit how to write: *see notes on the following page . controller (host) ics (slave/receiver) start bit address d3 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack if 7 h has been written to b6 byte 7 ack if 12 h has been written to b6 byte18 ack if 13 h has been written to b6 byte 19 ack if 14 h has been written to b6 byte 20 ack stop bit how to read:
4 ics94211 0441e?11/17/04 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. readback will support standard smbus controller protocol. the number of bytes to readback is defined by writing to byte 8. 2. when writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. if for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. 3. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 4. the input is operating at 3.3v logic levels. 5. the data byte format is 8 bit bytes. 6. to simplify the clock generator i 2 c interface, the protocol is set to use only block-writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 7. at power-on, all registers are set to a default condition, as shown. notes: brief i 2 c registers description for ics94211 programmable system frequency generator register name byte description pwd default functionality & frequency select register 0 output frequency, hardware / i 2 c frequency select, spread spectrum & output enable control register. see individual byte description output control registers 1-6 active / inactive output control registers/latch inputs read back. see individual byte description vendor id & revision id registers 7 byte 11 bit[7:4] is ics vendor id - 1001. other bits in this register designate device revision id of this part. see individual byte description byte count read back register 8 writing to this register will configure byte count and how many byte will be read back. do not write 00 h to this byte. 08 h watchdog timer count register 9 writing to this register will configure the number of seconds for the watchdog timer to reset. 10 h watchdog control registers 10 bit [6:0] watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. 000,0000 vco control selection bit 10 bit [7] this bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. 0 vco frequency control registers 11-12 these registers control the dividers ratio into the phase detector and thus control the vco output frequency. depended on hardware/byte 0 configuration spread spectrum control registers 13-14 these registers control the spread percentage amount. depended on hardware/byte 0 configuration group skews control registers 15-16 increment or decrement the group skew amount as compared to the initial skew. see individual byte description output rise/fall time select registers 17-20 these registers will control the output rise and fall time. see individual byte description
5 ics94211 0441e?11/17/04 byte 0: functionality and frequency select register (default=0) notes: 1. default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. t i b n o i t p i r c s e d d w p t i b ) 4 : 7 , 2 ( 2 t i b 7 t i b6 t i b5 t i b4 t i b f e r / o c v r e d i v i d o c v z h m k l c u p c z h m k l c i c p z h m 1 e t o n 3 s f2 s f1 s f0 s f 00000 0 4 / 7 4 41 0 . 0 6 10 0 . 0 80 0 . 0 4 0000 1 2 4 / 0 4 40 0 . 0 5 10 0 . 5 70 5 . 7 3 00010 4 4 / 2 1 51 6 . 6 6 11 3 . 3 85 6 . 1 4 00011 2 4 / 2 9 34 6 . 3 3 12 8 . 6 61 4 . 3 3 00 100 1 3 / 6 4 40 0 . 6 0 20 0 . 3 0 13 3 . 4 3 00 10 1 1 3 / 5 8 41 0 . 4 2 21 0 . 2 1 14 3 . 7 3 00 110 4 5 / 3 1 52 0 . 6 3 11 0 . 8 61 0 . 4 3 00 111 7 3 / 8 1 55 4 . 0 0 23 2 . 0 0 11 4 . 3 3 01000 1 2 / 2 5 30 0 . 0 4 20 0 . 0 2 10 0 . 0 4 01001 2 3 / 4 1 59 9 . 9 2 29 9 . 4 1 13 3 . 8 3 01010 3 3 / 7 0 58 9 . 9 1 29 9 . 9 0 16 6 . 6 3 01011 3 3 / 4 8 40 0 . 0 1 20 0 . 5 0 10 0 . 5 3 01100 8 1 / 2 5 30 0 . 0 8 20 0 . 0 4 10 0 . 5 3 01101 1 2 / 0 4 40 0 . 0 0 30 0 . 0 5 10 5 . 7 3 01110 5 2 / 3 3 49 9 . 7 4 20 0 . 4 2 10 0 . 1 3 01111 6 2 / 3 8 49 9 . 5 6 29 9 . 2 3 15 2 . 3 3 10 00 0 1 2 / 6 9 30 0 . 0 7 20 0 . 5 3 15 7 . 3 3 10 00 1 9 1 / 5 4 39 9 . 9 5 29 9 . 9 2 10 5 . 2 3 10 0 10 5 2 / 0 4 40 0 . 2 5 20 0 . 6 2 10 5 . 1 3 10 0 1 1 9 2 / 8 7 40 0 . 6 3 20 0 . 8 1 13 3 . 9 3 10 10 0 0 3 / 6 8 45 9 . 1 3 28 9 . 5 1 16 6 . 8 3 10 10 1 7 3 / 1 9 41 0 . 0 9 10 0 . 5 97 6 . 1 3 10 110 5 3 / 0 4 40 0 . 0 8 10 0 . 0 90 0 . 0 3 10 11 1 9 3 / 3 6 48 9 . 9 6 11 0 . 5 84 3 . 8 2 11000 6 1 / 1 7 30 0 . 2 3 30 0 . 6 6 10 5 . 1 4 1100 1 0 2 / 7 4 41 0 . 0 2 31 0 . 0 6 10 0 . 0 4 11010 0 2 / 3 3 49 9 . 9 0 39 9 . 4 5 15 7 . 8 3 11011 5 1 / 0 1 31 9 . 5 9 25 9 . 7 4 19 9 . 6 3 11100 3 2 / 9 6 47 9 . 1 9 28 9 . 5 4 10 5 . 6 3 1110 1 8 1 / 2 6 35 9 . 7 8 28 9 . 3 4 19 9 . 5 3 11110 4 2 / 6 7 48 9 . 3 8 29 9 . 1 4 10 5 . 5 3 11111 8 1 / 7 4 32 0 . 6 7 21 0 . 8 3 10 5 . 4 3 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 d a e r p s r e t n e c % 5 3 . 0 e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
6 ics94211 0441e?11/17/04 byte 1: cpu, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x # 2 s f d e h c t a l 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b0 41 0 m a r d s 2 t i b-1 ) d e v r e s e r ( 1 t i b3 41 1 k l c u p c 0 t i b4 41 0 k l c u p c byte 2: pci, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b71 f _ k l c i c p 5 t i b-1 ) d e v r e s e r ( 4 t i b3 11 4 k l c i c p 3 t i b2 11 3 k l c i c p 2 t i b1 11 2 k l c i c p 1 t i b0 11 1 k l c i c p 0 t i b81 0 k l c i c p notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched frequency selects (fs#) will be inverted logic load of the input frequency select pin conditions. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b-x # 1 s f d e h c t a l 2 t i b-1 ) d e v r e s e r ( 1 t i b-x # 3 s f d e h c t a l 0 t i b-1 ) d e v r e s e r ( byte 4: reserved , active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b7 41 c i p a o i 3 t i b-1 ) d e v r e s e r ( 2 t i b-1 ) d e v r e s e r ( 1 t i b6 41 1 f e r 0 t i b210 f e r byte 5: peripheral , active/inactive register (1= enable, 0 = disable) byte 3: sdram, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) e t o n ( d e v r e s e r 6 t i b-0 ) e t o n ( d e v r e s e r 5 t i b-0 ) e t o n ( d e v r e s e r 4 t i b-0 ) e t o n ( d e v r e s e r 3 t i b-0 ) e t o n ( d e v r e s e r 2 t i b-1 ) e t o n ( d e v r e s e r 1 t i b-1 ) e t o n ( d e v r e s e r 0 t i b-0 ) e t o n ( d e v r e s e r byte 6: peripheral , active/inactive register (1= enable, 0 = disable) note: this is an unused register writing to this register will not affect device performance or functinality. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-x # 0 s f d e h c t a l 5 t i b6 21 z h m 8 4 4 t i b5 21 z h m 4 2 3 t i b-1 ) d e v r e s e r ( 2 t i b , 1 2 , 7 1 8 1 , 0 2 1) 2 1 : 9 ( m a r d s 1 t i b , 2 3 , 8 2 , 9 2 , 1 3 1) 8 : 5 ( m a r d s 0 t i b , 8 3 , 4 3 5 3 , 7 3 1) 4 : 1 ( m a r d s
7 ics94211 0441e?11/17/04 byte 7: vendor id and revision id register byte 8: byte count and read back register notes: 1. pwd = power on default t i bd w pn o i t p i r c s e d 7 t i b0 d e v r e s e r 6 t i b0 d e v r e s e r 5 t i b0 d e v r e s e r 4 t i b0 d e v r e s e r 3 t i b1 d e v r e s e r 2 t i b0 d e v r e s e r 1 t i b0 d e v r e s e r 0 t i b0 d e v r e s e r t i bd w pn o i t p i r c s e d 7 t i b0 d i r o d n e v 6 t i b0 d i r o d n e v 5 t i b1 d i r o d n e v 4 t i bx d i n o i s i v e r 3 t i bx d i n o i s i v e r 2 t i bx d i n o i s i v e r 1 t i bx d i n o i s i v e r 0 t i bx d i n o i s i v e r byte 11: vco frequency control register note: the decimal representation of these 7 bits (byte 11 [6:0]) + 2 is equal to the ref divider value . t i bd w pn o i t p i r c s e d 7 t i bx 0 t i b r e d i v i d o c v 6 t i bx 6 t i b r e d i v i d f e r 5 t i bx 5 t i b r e d i v i d f e r 4 t i bx 4 t i b r e d i v i d f e r 3 t i bx 3 t i b r e d i v i d f e r 2 t i bx 2 t i b r e d i v i d f e r 1 t i bx 1 t i b r e d i v i d f e r 0 t i bx 0 t i b r e d i v i d f e r byte 12: vco frequency control register note: the decimal representation of these 9 bits (byte 12 bit [7:0] & byte 11 bit [7] ) + 8 is equal to the vco divider value. for example if vco divider value of 36 is desired, user need to program 36 - 8 = 28, namely, 0, 00011100 into byte 12 bit & byte 11 bit 7. t i bd w pn o i t p i r c s e d 7 t i bx 8 t i b r e d i v i d o c v 6 t i bx 7 t i b r e d i v i d o c v 5 t i bx 6 t i b r e d i v i d o c v 4 t i bx 5 t i b r e d i v i d o c v 3 t i bx 4 t i b r e d i v i d o c v 2 t i bx 3 t i b r e d i v i d o c v 1 t i bx 2 t i b r e d i v i d o c v 0 t i bx 1 t i b r e d i v i d o c v byte 10: watchdog timer count register t i bd w pn o i t p i r c s e d 7 t i b0 e s e h t f o n o i t a t n e s e r p e r l a m i c e d e h t s m 1 r o s m 0 9 2 o t d n o p s e r r o c s t i b 8 e r o f e b t i a w l l i w r e m i t g o d h c t a w e h t e h t t e s e r d n a e d o m m r a l a o t s e o g t i t l u a f e d . g n i t t e s e f a s e h t o t y c n e u q e r f 6 . 4 = s m 0 9 2 x 6 1 s i p u r e w o p t a . s d n o c e s 6 t i b0 5 t i b0 4 t i b1 3 t i b0 2 t i b0 1 t i b0 0 t i b0 note: fs values in bit [0:4] will correspond to byte 0 fs values. default safe frequency is same as 00000 entry in byte0. byte 9: vco control selection bit & watchdog timer control register t i bd w pn o i t p i r c s e d 7 t i b0 q e r f 5 1 & 4 1 b = 1 / q e r f 0 b / w h = 0 6 t i b0 e l b a n e = 1 / e l b a s i d = 0 e l b a n e d w 5 t i b0 m r a l a = 1 / l a m r o n = 0 s u t a t s d w 4 t i b0 2 t i b 0 e t y b , y c n e u q e r f e f a s d w 3 t i b0 3 s f , y c n e u q e r f e f a s d w 2 t i b0 2 s f , y c n e u q e r f e f a s d w 1 t i b0 1 s f , y c n e u q e r f e f a s d w 0 t i b0 0 s f , y c n e u q e r f e f a s d w
8 ics94211 0441e?11/17/04 byte 13: spread sectrum control register byte 14: spread sectrum control register note: please utilize software utility provided by ics application engineering to configure spread spectrum. incorrect spread percentage may cause system failure. t i bd w pn o i t p i r c s e d 7 t i bx 7 t i b m u r t c e p s d a e r p s 6 t i bx 6 t i b m u r t c e p s d a e r p s 5 t i bx 5 t i b m u r t c e p s d a e r p s 4 t i bx 4 t i b m u r t c e p s d a e r p s 3 t i bx 3 t i b m u r t c e p s d a e r p s 2 t i bx 2 t i b m u r t c e p s d a e r p s 1 t i bx 1 t i b m u r t c e p s d a e r p s 0 t i bx 0 t i b m u r t c e p s d a e r p s t i bd w pn o i t p i r c s e d 7 t i bx d e v r e s e r 6 t i bx d e v r e s e r 5 t i bx d e v r e s e r 4 t i bx 2 1 t i b m u r t c e p s d a e r p s 3 t i bx 1 1 t i b m u r t c e p s d a e r p s 2 t i bx 0 1 t i b m u r t c e p s d a e r p s 1 t i bx 9 i b m u r t c e p s d a e r p s 0 t i bx 8 t i b m u r t c e p s d a e r p s note: please utilize software utility provided by ics application engineering to configure spread spectrum. incorrect spread percentage may cause system failure. byte 15: output skew control byte 16: output skew control t i bd w pn o i t p i r c s e d 7 t i b l o r t n o c w e k s f _ k l c i c p 6 t i b 5 t i b l o r t n o c w e k s } 4 : 0 [ k l c i c p 4 t i b 3 t i b l o r t n o c w e k s f _ m a r d s 2 t i b 1 t i b l o r t n o c w e k s } 7 : 0 [ m a r d s 0 t i b t i bd w pn o i t p i r c s e d 7 t i b l o r t n o c w e k s ] 1 1 : 8 [ m a r d s 6 t i b 5 t i bx d e v r e s e r 4 t i bx d e v r e s e r 3 t i bx d e v r e s e r 2 t i bx d e v r e s e r 1 t i bx d e v r e s e r 0 t i bx d e v r e s e r byte 17: output rise/fall time select register byte 18: output rise/fall time select register t i bd w pn o i t p i r c s e d 7 t i b l o r t n o c e t a r w e l s : f _ k l c u p c 6 t i b 5 t i b l o r t n o c e t a r w e l s : 1 k l c u p c 4 t i b 3 t i b l o r t n o c e t a r w e l s ] 1 1 : 0 [ m a r d s 2 t i b 1 t i b l o r t n o c e t a r w e l s : f _ m a r d s 0 t i b t i bd w pn o i t p i r c s e d 7 t i b l o r t n o c e t a r w e l s : ] 4 : 0 { i c p 6 t i b 5 t i b l o r t n o c e t a r w e l s f _ i c p 4 t i b 3 t i b l o r t n o c e t a r w e l s : z h m 8 4 2 t i b 1 t i b l o r t n o c e t a r w e l s : z h m 4 2 0 t i b notes: 1. pwd = power on default 2. the power on default for byte 13-20 depends on the harware (latch inputs fs[0:4]) or i 2 c (byte 0 bit [1:7]) setting. be sure to read back and re-write the values of these 8 registers when vco frequency change is desired for the first pass.
9 ics94211 0441e?11/17/04 vco programming constrains vco frequency ...................... 150mhz to 500mhz vco divider range ................ 8 to 519 ref divider range ................. 2 to 129 phase detector stability .......... 0.3536 to 1.4142 useful formula vco frequency = 14.31818 x vco/ref divider value phase detector stabiliy = 14.038 x (vco divider value) -0.5 note: 1. user needs to ensure step 3 & 7 is carried out. systems with wrong spread percentage and/or group to group skew relation programmed into bytes 13-16 could be unstable. step 3 & 7 assure the correct spread and skew relationship. 2. if vco, ref divider values or phase detector stability are out of range, the device may fail to function correctly. 3. follow min and max vco frequency range provided. internal pll could be unstable if vco frequency is too fast or too slow. use 14.31818mhz x vco/ref divider values to calculate the vco frequency (mhz). 4. ics recommends users, to utilize the software utility provided by ics application engineering to program the vco frequency. 5. spread percent needs to be calculated based on vco frequency, spread modulation frequency and spreadamount desired. see application note for software support. to program the vco frequency for over-clocking. 0. before trying to program our clock manually, consider using ics provided software utilities for easy programming. 1. select the frequency you want to over-clock from with the desire gear ratio (i.e. cpu:sdram:3v66:pci ratio) by writing to byte 0, or using initial hardware power up frequency. 2. write 0001, 1001 (19 h ) to byte 8 for readback of 21 bytes (byte 0-20). 3. read back byte 11-20 and copy values in these registers. 4. re-initialize the write sequence. 5. write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired vco & ref divider values. 6. write to byte 13 to 20 with the values you copy from step 3. this maintains the output spread, skew and slew rate. 7. the above procedure is only needed when changing the vco for the 1st pass. if vco frequency needed to be changed again, user only needs to write to byte 11 and 12 unless the system is to reboot. t i bd w pn o i t p i r c s e d 7 t i bx d e v r e s e r 6 t i bx d e v r e s e r 5 t i bx d e v r e s e r 4 t i bx d e v r e s e r 3 t i bx d e v r e s e r 2 t i bx d e v r e s e r 1 t i bx d e v r e s e r 0 t i bx d e v r e s e r byte 19: reserved register note: byte 19 and 20 are reserved registers, these are unused registers writing to these registers will not affect device performance or functinality. t i bd w pn o i t p i r c s e d 7 t i bx d e v r e s e r 6 t i bx d e v r e s e r 5 t i bx d e v r e s e r 4 t i bx d e v r e s e r 3 t i bx d e v r e s e r 2 t i bx d e v r e s e r 1 t i bx d e v r e s e r 0 t i bx d e v r e s e r byte 20: reserved register
10 ics94211 0441e?11/17/04 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd -5 5 ma i il1 v in = 0 v; inputs with no pull-up resistors -5 i il2 v in = 0 v; inputs with pull-up resistors -200 c l = max cap loads; cpu=66-133 mhz , sdram=100 mhz 124 350 cpu=133 mhz, sdram=133 mhz 135 500 i dd2. 5op c l = max cap loads; 18 70 powerdown current i dd3.3pd c l = 0 pf; input address to vdd or gnd 600 ma input frequency f i v dd = 3.3 v 14.318 mhz pin inductance l p in 7nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target frequency 3 ms settling time 1 t s from 1st crossing to 1% target frequency 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target frequency 3 ms t pzh ,t pzl output enable delay (all outputs) 1 10 ns t phz ,t pl z output disable delay (all outputs) 1 10 ns skew 1 tcpu-pci v t = 1.5v; vtl=1.25v 2.45 4 ns 1 guaranteed by design, not 100% tested in production. delay 1 input capacitance 1 input low current ma i dd3. 3op operating supply current ma
11 ics94211 0441e?11/17/04 electrical characteristics - cpu t a = 0 - 70c;vdd = 3.3v; v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance 1 r dsp2b vo=v d d *(0.5) 13.5 15 45 ? output impedance 1 r dsn2b vo=v d d *(0.5) 13.5 16.5 45 ? output high voltage v oh2b i oh = -1 ma 2 2.48 v output low voltage v ol2b i ol = 1 ma 0.04 0.4 v v oh@min = 1 v -60 -27 v oh@max = 2.375v -27 -7 v ol@min = 1.2 v 27 63 v ol@max =0.3v 20 30 rise time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1.2 1.6 ns fall time 1 t f2b v oh = 2.0 v, v ol = 0.4 v 0.4 0.9 1.6 ns duty cycle 1 d t2b v t = 1.25 v 45 46.9 55 % skew 1 t sk2b v t = 1.25 v 12.7 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = 1.25 v, cpu 66, sdram 100 150 250 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current i oh2b output low current i ol2b electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%, c l = 40 pf for pci0-1, c l = 10 - 30 pf for other pcis (unless otherwise st a parameter symbol conditions min typ max units output impedance 1 r dsp1 vo=v d d *(0.5) 12 55 ? output impedance 1 r dsn1 vo=v d d *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh@min = 1 v -33 v oh@max = 3.135v -33 v ol@min = 1.95 v 30 v ol@max =0.4v 38 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v, 0.5 1.5 2 ns fall time 1 t f1 v ol = 2.4 v, v oh = 0.4 v, pci0-3 0.5 1.5 2 ns duty cycle 1 d t1 v t = 1.5 v 45 52.5 55 % skew 1 t sk1 v t = 1.5 v 49 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 200 500 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current i oh1 output low current i ol1
12 ics94211 0441e?11/17/04 electrical characteristics - ioapic t a = 0 - 70c; vdd = 3.3v; v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance 1 r dsp4b vo=v d d *(0.5) 9 3 ? output impedance 1 r dsn4b vo=v d d *(0.5) 9 30 ? output high voltage v oh4b i oh = -5.5 ma 2 v output low voltage v ol4b i ol = 9 ma 0.4 v v oh@min = 1.4 v -21 v oh@max = 2.5v -36 v ol@min = 1.0 v 36 v ol@max =0.2v 31 rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 0.4 0.7 1.6 ns fall time 1 t f4b v oh = 2.0 v, v ol = 0.4 v 0.4 1.1 1.6 ns duty cycle 1 d t4b v t = 1.25 v 45 53.7 55 % 1 guaranteed by design, not 100% tested in production. ma ma output high current i oh4b output low current i ol4b electrical characteristics - sdram t a = 0 - 70c; v dd = 3.3 v +/-5%, c l = 20 - 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance 1 r dsp3 vo=v d d *(0.5) 10 24 ? output impedance 1 r dsn3 vo=v d d *(0.5) 10 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v v oh@min = 2 v -46 v oh@max = 3.135v -54 v ol@min = 1 v 54 v ol@max =0.4v 53 rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.4 0.8 1.6 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 0.4 0.8 1.6 ns duty cycle 1 d t3 v t = 1.5 v 45 51.7 55 % skew 1 t sk3 v t = 1.5 v 166 250 ps propagation delay tprop v t = 1.5 v 3.15ns 1 guaranteed by design, not 100% tested in production. output high current i oh3 ma output low current i ol3 ma
13 ics94211 0441e?11/17/04 electrical characteristics - ref, 24_48mhz, 48mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp5 v o = v d d *(0.5) 20 60 ? output impedance 1 r dsn5 v o = v d d *(0.5) 20 60 ? output high voltage v oh5 i oh = -1 ma 2.4 v output low voltage v ol5 i ol = 1 ma 0.4 v v oh @ min = 1.0 v -23 v oh @ max = 3.135 v -29 v ol @ min = 1.95 v 29 v ol @ max = 0.4 v 27 rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 0.4 2 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 0.4 2 4 ns duty cycle 1 d t5 v t = 1.5 v 455355% v t = 1.5 v, fixed clocks 200 500 v t = 1.5 v, ref clocks 1032 1250 1 guaranteed by design, not 100% tested in production. jitter, cycle-to-cycle 1 t jcyc-cyc5 ps output high current i oh5 ma output low current i ol5 ma 0441c?10/09/03 0441c?10/09/03
14 ics94211 0441e?11/17/04 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics94211 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power- on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
15 ics94211 0441e?11/17/04 pci_stop# timing diagram pci_stop# is an asynchronous input to the ics94211 . it is used to turn off the pciclk clocks for low power operation. pci_stop# is synchronized by the ics94211 internally. the minimum that the pciclk clocks are enabled (pci_stop# high pulse) is at least 10 pciclk clocks. pciclk clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics94211 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics94211. 3. all other clocks continue to run undisturbed. 4. cpu_stop# is shown in a high (true) state.
16 ics94211 0441e?11/17/04 ordering information ics94211 y f-t designation for tape and reel packaging package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics, av = standard device example: ics xxxx y f - t index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l min max min max a2.412.80.095.110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c0.130.25.005.010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h0.380.64.015.025 l0.501.02.020.040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.635 basic 0.025 basic ref erence do c.: jedec pub licat io n 9 5, m o-118 variations see variations see variations n d mm. d (inch)
document search | package search | parametric search | cross reference search | green & rohs | calculators | thermal data | reliability & quality | military global sites email | print contact idt | investors | press search entire site home > products > timing solutions > pc-notebook-server clocks > clock synthesizer by chipset vendor > desktop chipsets > 94211 a dd to m y idt [ ? ] 94211 (desktop chipsets) description 440bx/via apollo pro133/ ali 1631 style chipset. market group pc clock additional info the ics94211 is a single chip clock solution for desktop designs us ing the bx/apollo pro133/ali 1631 style chipset. it provides all necessary clock signals for such a system. the ics94 211 belongs to ics new generation of program mable system clock gener ators. it employs serial programming i2c interface as a vehicle for changing output func tions, changing output frequency, conf iguring output strength, c onfiguring output to output skew, changing spread spectrum am ount, changing group divider ratio and dis/ enabling individual clocks. this device also has ics propriety 'watchdog timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking. ? programmable ouput frequency. ? programmable ou put rise/fall time. ? programmable pciclk, pciclk_f, sdram skew. ? real time sys tem reset output ? spread spectrum for emi cont rol typically by 7db to 8db, with programmable spread percentage. ? watchdog timer t echnology to reset system if over-clocking causes malfunction. ? uses exte rnal 14.318mhz crystal. ? fs pins for frequency select you may also like... related orderable parts attributes 94211af 94211aflf 94211aflft 94211aft voltage 3.3 v (pv48) 3.3 v (pvg48) 3.3 v (pvg48) 3.3 v (pv48) package ssop 48 ssop 48 ssop 48 ssop 48 speed na na na na temperature c c c c status active active active active sample yes yes no no minimum order quantity 90 90 1000 1000 factory order increment 30 30 1000 1000 related documents type title size revision date datasheet 94211 datasheet 165 kb 11/08/2006 pa g e 1 of 2 08-jun-2007 mhtml:file://c:\94211.mh t
node: www.idt.com home | site map | about idt | press room | investor relations | trademark | privacy policy | careers | register | contact us use of this website signifies your agreement to the acceptable use and privacy policy . copyright 1997-2007 integrated device technology, inc. all rights reserved. pa g e 2 of 2 08-jun-2007 mhtml:file://c:\94211.mh t

▲Up To Search▲

Price & Availability of ICS94211AF

	To Download ICS94211AF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .