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| 1.2 a programmable device power supply with integrated 16 - bit level setting dacs data sheet ad5560 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one techn ology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2008 - 2012 analog devices, inc. all rights reserved. features programmable device power supply (dps) fv, mi, mv, fnmv f uncti ons 5 i nternal current ra nges (on - chip r sense ) 5 a , 25 a, 250 a, 2.5 ma, 25 ma 2 external high current ranges (ext ernal r sense ) extforce1 : 1.2 a max imum extforce2 : 500 ma maxi mum integrated programmable levels all 16- bit dacs: force dac, comparator dacs, clamp dacs, offset dac , osd dac, dgs dac p rogrammable kelvin clamp and alarm offset and gain cor rection registers on - c hip ramp m ode on f orce dac for power supply s lewing progra mmable slew ra te feature, 1 v/s to 0.3 v/s dutgnd kelvin sense and alarm 25 v fv span with asymmetrical operation within ? 22 v /+25 v on - chip comparators gangable for higher current guard amplifier system pmu connections current clamps die temperature se nsor and shutdown feature on - c hip diode thermal a rray diagnostic register allows access to internal nodes open - drain alarm flags (temperature, current clamp, kelvin alarm ) spi - / microwire - /dsp - compatible in terface 64- l ead (10 mm 10 mm) tqfp with exposed p ad (on top ) 72- ball (8 mm 8 mm) flip - chip bga applications automa tic test equipment (ate) device power supply general description the ad5560 is a high performance, highly integrated device power supply consisting of programmable force voltages and mea sure ranges . this part includes the required dac levels to set the programmable inputs for the drive amplifier , as well as clamping and comparator circuitry. offset and gain correction is included on - chip for dac functions. a number of program - mable measu r e current ranges are available: five internal fixed r anges a nd two external customer - selectable ranges (extforc e1 and extforce2) that can supply currents up to 1.2 a and 500 ma, respectively. the voltage range possible at this high current level is limit ed by headroom and the maximum power dissipation. current ranges in excess of 1.2 a or at high current and high voltage combinations can be achieved by paralleling or ganging multiple dps devices. open - drain alarm outputs are provided in the event of ove rcurrent, overtemperature, or kelvin alarm on either the sense or dutgnd line . the dps functions are controlled via a simple 3 - wire serial interface compatible with spi, qspi?, microwire?, and dsp interface standards running at clock speeds of up to 50 mh z.
ad5560 data sheet rev. d | page 2 of 68 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 3 functional block diagram .............................................................. 4 specifications ..................................................................................... 5 timing characteristics .............................................................. 13 timing diagrams ........................................................................ 13 absolute maximum ratings .......................................................... 15 esd caution ................................................................................ 15 pin configurations and function descripti ons ......................... 16 typical performance characteristics ........................................... 20 terminology .................................................................................... 28 theory of operation ...................................................................... 29 force amplifier ........................................................................... 29 dac refer ence voltage (vref) ............................................... 29 open - sense detect (osd) alarm and clamp ....................... 29 device under test ground (dutgnd) ................................. 29 gpo .............................................................................................. 30 comparators ................................................................................ 30 current clamps .......................................................................... 30 short - circuit protection ............................................................ 30 guard amplifier ......................................................................... 30 compensation capacitors ......................................................... 30 current range selection ............................................................ 31 high current ranges ................................................................. 31 ideal sequence for gang mode ................................................. 32 compensation for gang mod e ................................................. 32 system force/sense switches .................................................... 32 die temperature sensor and thermal shutdown .................. 33 measure output (measout) ................................................. 33 v mid voltage ................................................................................ 33 force amplifier stability ............................................................ 36 poles and zeros in a typical system ........................................ 37 minimizing the number of external compensation components ................................................................................ 37 extra poles and zeros in the ad5560 ...................................... 37 compensation strategies ........................................................... 38 optimizing performance for a known capacitor using autocompensation mode .......................................................... 38 adjusting the autocompensation mode ................................. 39 dealing with para llel load capacitors .................................... 39 dac levels .................................................................................. 39 force and comparator dacs ................................................... 39 clamp dacs ............................................................................... 39 osd dac .................................................................................... 40 dutgnd dac .......................................................................... 40 offset dac .................................................................................. 40 offset and gain registers .......................................................... 40 reference selection .................................................................... 41 choosing av dd /av ss power supply rails ............................... 41 choosing hcav ss x and hc av dd x supply rails ................... 41 power dissipation ....................................................................... 41 package composition and maximum ver tical force ............ 42 slew rate control ....................................................................... 42 serial interface ................................................................................ 44 spi interface ................................................................................ 44 spi write mode .......................................................................... 44 sdo output ................................................................................ 44 reset function ......................................................................... 44 busy function ........................................................................... 44 load function .......................................................................... 44 register update rates ................................................................ 45 control registers ............................................................................ 46 dps and dac addressing ........................................................ 46 readback mode .......................................................................... 57 dac readback ............................................................................ 57 power - on default ...................................................................... 57 using the hcav dd x a n d h c av ss x supplies .......................... 59 power supply sequencing ......................................................... 59 required external components ............................................... 60 power supply decoupling ......................................................... 61 applications information .............................................................. 62 thermal considerations ............................................................ 62 temperature contour map on the top of the package ......... 63 outline dimensions ....................................................................... 64 ordering guide .......................................................................... 65 data sheet ad5560 rev. d | page 3 of 68 revisi on history 8 /12 rev. c to rev. d added 72 - ball flip - chip bga (throughout) ............................... 1 added figure 7 and table 5 (renumbered seuentially) .......... 18 added applications information section .................................... 62 updated outline dimensions ........................................................ 6 4 change s to ordering guide ........................................................... 6 5 10 /10 rev. b to rev. c changes to force output voltage parameter and load transient response parameter, table 1 ............................................................ 5 changes to figure 52 ...................................................................... 29 changes to table 9 .......................................................................... 32 9 /09 rev. a to rev. b changes to table 1, measure current and measure voltage parameters .......................................................................................... 6 changes to die temperature sensor and thermal shutdown section ............................................................................ 31 changes to table 10 and table 11 ................................................. 32 changes to table 18, bit 15 ............................................................ 45 changes to table 23, bits15:12 ................................................... 50 changes to table 25 ........................................................................ 54 12/08 rev. 0 to rev. a changes to figure 1 .......................................................................... 4 changes to table 1 ............................................................................ 4 changes to table 2 .......................................................................... 13 changes to table 3 .......................................................................... 15 changes to open - sense detect (osd) alarm and clamp ....... 27 changes to figure 53 ...................................................................... 30 change to gm maximum rating, table 13 .................................. 34 changes to table 19 ........................................................................ 46 changes to bit 7, bit 8 functions, table 21 ................................. 48 changes to power supply decoupling section ........................... 59 11/08 revision 0: initial version ad5560 data sheet rev. d | page 4 of 68 functional block dia gram r z : 500? to 1.6m? r p : 200? to 1m? 100k? 25k? 6k? gpo reset a v ss a v dd hw_inh/load dgnd clalm tm p alm vref dv cc refgnd agnd clen/ load 8pf rclk kelalm sw16 guard am p 1 reg c reg m reg 16 16 16 16 1 16-bit clamp control dac offset clh 2 reg 1 reg c reg m reg 16 16 16 16 1 16-bit dac offset offset clh 2 reg 16 16 16 16 16-bit dac offset cph 2 reg 16 16 8 8 16-bit dac osd dac dgs dac ad5560 offset diagnostic b diagnostic a dutgnd sense tsense mux and gain 1/0.2 cpl sw3 sw2 sw1 a b 2 reg 1 reg c reg m reg 16 16 16 16 16 1 16-bit dac fin r3 2 reg ram p reg mux g m 16-bit clh dac clh offset dac r4 r1 agnd s/w inh thermal shutdown r2 1 reg c reg m reg 16 16 16 1 reg c reg m reg ksense vsense isense cpoh/ cpo cpo l measout power-on reset die temp sensor and thermal shutdown open sense detect sw7 sw13 sw14 sw15 sw17 sw18 serial spi interface sclk sync sdi bus y sdo ? ? ? ? + + ? + ? + + + 10 or 20 1 agnd v sense i sense dac mid code vo lt age t o center i range loca l feedback extforce1 extforce2 vref vref a c b a c b 16 16 alarm block ksense dutgnd sense guard dutgnd sense and alarm sw5a 40 a/v 80 a/v 400 a/v 1000 a/v inhibit slew rate control hc a v dd 1x c c0 c c1 c c2 c c3 hc a v dd 2x sense extforce1 up to 1.2a up to 500ma extforce2 sl a ve_in master_out c f0 t o c f4 c f0 t o c f4 dut 07779-001 extmeasih1 sys_sense sys_force sw8 sw9 extmeasih2 extmeasi l ext r sense 1 ext r sense 2 dutgnd guard/ sys_dutgnd sw6 sw5b sw 1 1 10k ? hc a v ss 1x hc a v ss 2x 100k? 20k? 2k? 200? 20? 2.5ma 250 a 25 a 5a 25ma r sense force sw4 figure 1. data sheet ad5560 rev. d | page 5 of 68 specifications hcav dd x ( av ss + 33 v ), hcav dd x av dd , hcav ss x av ss , av dd 8 v, av ss ?5 v, |av dd ? av ss | 16 v and 33 v, dv cc = 2.3 v to 5.5 v , v ref = 5 v, g ain (m), o ffset (c) , and dac o ffset registers are at default values ; agnd = dgnd = 0 v ; t j = 25c to 90c, maxim um specifications , u nless otherwise noted. fsv is full - scale voltage, fsvr is full - scale voltage range , fsc is full - scale current, fscr is full - scale current range. table 1 . parameter min typ max unit test conditions/comments forc e voltage force output voltage 1 extforce1 av ss + 2.25 av dd ? 2.25 v allow 500 mv for external r sense voltage drop. hcav ss 1x + 1.75 hcav ss 1x ? 1.75 v allow 500 mv for external r sense voltage drop. hcav ss 1x + 1.25 hcav dd 1x ? 1.25 v allow 500 mv for external r sense voltage drop. reduced headroom/footroom, c lamps must be enabled. 2 extforce2 av ss + 2.25 av dd ? 2.25 v allow 500 mv for external r sense voltage drop hcav ss 2x + 1.75 hcav dd 2x ? 1.75 v allow 500 mv for external r sense voltage drop hcav ss 2x + 1.25 hcav dd 2x ? 1.25 v allow 500 mv for external r sense voltage drop. reduced headroom/footroom, clamps must be enabled. 2 force av ss + 2.75 av dd ? 2.75 v internal current ranges, includes 500 mv for internal r sense voltage drop headroom/footroom 1 ?2.75 +2.75 v internal current ranges to av dd /av ss , includes 500 mv for internal r sense voltage drop. headroom/footroom 1 ?2.25 +2.25 v external current ranges, extforce1/ extforce2 to hcav dd x and hcav ss x supplies; includes 500 mv for external r sense voltage drop. force output voltage span ?22 +25 v may be a skewed range but within headroom requirements and maximum power dissipation for current range. forced voltage linearity error ?2 +2 mv forced voltage offset error ?50 +50 mv uncalibrated, use c register to calibrate, meas - ured at midscale. forced voltage offset error tempco 1 27 v/c standard deviation = 23 v/c. forced voltage gain error ?25 +25 mv u ncalibrated, use m register to calibrate. forced voltage gain error tempco 1 4 ppm/c standard deviation = 3 ppm/c. short - circuit current limit 3 clamps off. extforce1 ?3.5 2. 7 +3.5 a positive and negative dc short - circuit current. extforce2 ?1.25 0.9 +1.25 a positive and negative dc short - circuit current. force ?75 50 +75 ma 25 ma range, positive and negative dc short - circuit current. ?20 10 +20 ma all other ranges, p ositive and negative dc short - circuit current. active c fx buffer ?64 +64 ma dc load regulation 1 ?1 +1 mv extforce1 range, 1 a load current change. ?0.4 +0.4 mv extforce2 range, 0.5 a load current change. load transient response 1 70 mv 1.2 a load step into 100 f dut capacitance (10 m esr), autocompensation mode. 140 mv 1.2 a load step into 30 f dut capacitance (10 m esr), autocompensation mode. nsd 1 350 nv/hz measured at 1 khz, at output of force. measure current ranges sense resistors are trimmed to within 1%, nominal 500 mv v rsense . internal sense resistors 1 100 k 5 a current ra nge. 20 k 25 a current range. 2 k 250 a current range. 200 2.5 ma current range. 20 25 ma current range. ad5560 data sheet rev. d | page 6 of 68 parameter min typ max unit test conditions/comments measure current ranges specified current ranges with v ref = 5 v and mi gain = 20, or with v ref = 2.5 v and mi gain = 5. 5 a set using internal sense resistor. 25 a set using internal sense resistor. 250 a set using internal sense resistor. 2.5 ma set using internal sense resistor. 25 ma set using internal sense resistor. 500 ma ext force2, set by user with external sense resistor, limited by headroom requirements and maximum power dissipation. 120 0 ma extforce1, set by user with external sense resistor, limited by headroom requirements and maximum power dissipation. measure cu rrent all offset dac/supply combinations settings, all gain settings are measure current = (i dut r sense mi gain), unless otherwise noted. differential input voltage range 1 ?0.64 +0.64 v maximum voltage across r sense , mi gain = 20. ?0.7 +0.7 v maximum voltage across r sense , mi gain = 10. output voltage span 1 25 v measure current block alone (internal node). offset error ?1 +1 % fsc at 0 a, mi gain = 20, measout gain = 1. offset error tempco 1 ?1 ppm of fsc/c standard deviation = 13 ppm/c. offset error ?1.5 +1.5 % fsc at 0 a, mi gain = 10, measout gain = 1. offset error tempco 1 ?1 ppm of f sc/c standard deviation = 13 ppm/c. offset error ?1.5 +1.5 % fsc at 0 a, mi gain = 20, measout gain = 0.2. offset error tempco 1 3 ppm of fsc/c standard deviation = 13 ppm/c. offset error ?3 +3 % fsc at 0 a, mi gain = 10, measout gain = 0.2. offset error tempco 1 8 ppm of fsc/c standard deviation = 15 ppm/c. gain error ?2 +2 % fsc internal current ranges, all gain settings. gain error 1 ?1 +1 % fsc external current ranges, excluding r sense . gain error tempco 1 20 ppm/c standard deviation = 5 ppm/c. measout gain = 1 all supply conditions. linearity error ?0.01 +0.01 % fscr mi gain = 20 a nd 10. measout gain = 0.2 nominal supply (16.5 v, 0x8000 offset dac). linearity error ?0.06 +0.06 % fscr mi gain = 20. linearity error ?0.05 +0.05 % fscr mi gain = 10. measout gain = 0.2 low supply (?25 v/+8 v, 0xd4eb offset dac). linearity error ?0.125 +0.125 % fscr mi gain = 20. linearity error ?0.175 +0.175 % fscr mi gain = 10. measout gain = 0.2 high supply (?5 v/+28 v, 0xd1d offset dac). linearity error ?0.0875 +0.0875 % fscr mi gain = 20. linearity error ?0.1 +0.1 % fscr m i gain = 10. common - mode error ?0.005 +0.005 %fsvr/v % of fs change at measure output per volts change in dut voltage. nsd 1 900 nv/hz mi gain = 20, measout gain = 1, measured at measout @ 1 khz, inputs grounded. 550 nv/hz mi gain = 10, measout gain = 1, measured at measout @ 1 khz, inputs grounded. 170 nv/hz mi gain = 20, measout gain = 0.2, measured at measout @ 1 khz, inputs grounded. 110 nv/hz mi gain = 10, measout gain = 0.2, measured at measout @ 1 khz, inputs grounded. measure voltage measout gain 1 and measout gain 0.2. measure voltage range 1 av ss + 2.75 av dd ? 2.75 v all voltage ranges. gain error ?0.1 +0.1 % fs gain error tempco 1 3 ppm/c standard deviation = 2 ppm/c. measout gain = 1 linearity error ?2 +2 mv offset error ?12 +12 mv offset error tempco 1 2 v/c standard deviation = 12 v/c. nsd 1 100 nv/hz @ 1 khz, at measout, inputs grounded. data sheet ad5560 rev. d | page 7 of 68 parameter min typ max unit test conditions/comments measout gain = 0.2 linearity error ?5.5 +5.5 mv referred to mv input, nominal supply (16.5 v, 0x8000 offset dac). ?9 +24 mv referred to mv input, low supply (?25 v/+8 v, 0xd4eb offset dac). ?4 +13 mv referred to mv input, high supply (?5 v/+28 v, 0xd1d offset dac). offset error ?30 +20 mv referred to mv output. offset error tempco 1 10 v/c standard deviation = 12 v/c, ref erred to mv output. nsd 1 50 nv/hz @ 1 khz, at measout, inputs grounded. combined leakage includes sys_sense, sys_force, extforce1, extforce2, extmeasih1, extmeasih2, extmeasil, force, and sense; measured with pd = 1, sw - inh = 0 (power up and tristate). leakage current ?37.5 +37.5 na ?30 +30 na t j = 25c to 70c. leakage current tempco 1 0.1 0.4 na/c sense input leakage cur rent ?2.5 +2.5 na measured with pd = 1, sw - inh = 0 (power - up and tristate). leakage current tempco 1 0.0 1 na/c pin capacitance 1 10 pf e xtmeasih1, extmeasih2, extmeasil leakage current ?2.5 +2.5 na measured with pd = 1, sw - inh = 0 (power - up and tristate). leakage current tempco 1 0.0 1 na/c pin capacitanc e 1 5 pf force output, force maximum current drive 1 ?30 +30 ma leakage current ?10 +10 na measured with pd = 1, sw - inh = 0 (power - up and tristate). leakage current tempco 1 0.0 3 na/c pin capacitance 1 120 pf extforce1 outputs maximum current drive 1 ?1200 +1200 ma set with external sense resistor, limited by headroom and power dissipation. leakage current ?7.5 +7.5 na measured with pd = 1, sw - inh = 0 (power - up and tristate). leakage current tempco 1 0.0 3 0.06 na/c pin capacitance 1 275 pf extforce2 outputs maximum current drive 1 ?500 +500 ma set with external sense resistor, limited by headroom and power d issipation. leakage current ?5 +5 na measured with pd = 1, sw - inh = 0 (power - up and tristate). leakage current tempco 1 0.0 2 0.05 na/c pin capacitance 1 100 pf sys_sense voltage range av ss av dd v leakage current ?2.5 +2.5 na sys_sense high - z, force amplifier inhibited. leakage current tempco 1 0.0 05 0.025 na/c path on resistance 280 av dd = 16.5 v, av ss = ?16.5 v. pin capacitance 1 5 pf ad5560 data sheet rev. d | page 8 of 68 parameter min typ max unit test conditions/comments sys_force voltage range av ss av dd v current carrying capability 1 ?25 +25 ma leakage current ?2.5 +2.5 na sys_f orce high - z, force amplifier inhibited. leakage current tempco 1 0.00 5 0.025 na/c path on resistance 35 av dd = 16.5 v, av ss = ?16.5 v. pin capacitance 1 5 pf sys_dutgnd voltage range av ss av dd v path on resistance 300 400 av dd = 16.5 v, av ss = ?16.5 v. current clamp clamp accuracy programmed clamp value programmed clamp value + 10 % of fs mi gain = 20, with clamp separation of 2 v, and 1 v separation from agnd/0 a. programmed clamp value programmed clamp value + 20 % of fs mi gain = 10, with clamp separation of 2 v, and 1 v separation from agnd/0 a. vcll to vclh 1 2 v 10% of fscr (mi gain = 20), 20% of fscr (mi gain = 10), restriction to prevent both clamps activating together. vcll to 0 a 1 1 v 5% of fscr (mi gain = 20), 10% of fscr (mi gain = 10), restriction to avoid impinging on fv before programmed level. vclh to 0 a 1 1 v 5% of fscr (mi gain 20), 10% of fscr (mi gain = 10), restriction to avoid impinging on fv before programmed level. clamp activation response time 1 20 100 s measured from busy going low to visible clamping. clamp recovery 1 2 5 s measured from busy going low to visible recovery. alarm delay 1 50 s time for clalm to flag. force amplifer slew rate 1 1 v/s fastest slew rate, controlled via serial interface. 0.312 v/s slowest slew rate, controlled via serial interface. maximum stable load capacitance 1 160 f voltage overshoot/undershoot 1 5 % of programmed value (1 v). settling time (force amplifer) compensation register 1 = 0x4880 (229 nf to 380 nf, esr 74 to 140 m) to within 10 mv of programmed value. fv (1200 ma extforce1 range) 1 16 25 s 3.7 v step, r dut = 2.4 , c dut = 0.22 f, full dc load. fv (900 ma extforce1 range) 1 18 30 s 8 v step, r dut = 8.8 , c dut = 0.22 f, full dc load. fv (500 ma extforce2 range) 1 34 53 s 15 v step, r dut = 30 , c dut = 0.22 f, full dc load. fv (300 ma extforce2 range) 1 25 50 s 10 v step, r dut = 33.3 , c dut = 0.22 f, full dc load. fv (25 ma range) 1 , 3 125 180 s 20 v step, r dut = 800 , c dut = 0.22 f, full dc load. fv (2.5 ma range) 1 , 3 300 500 s 1 0 v step, r dut = 4 k, c dut = 0.22 f, full dc load. fv (250 a range) 1 , 3 300 500 s 10 v step, r dut = 40 k, c dut = 0.22 f, full dc load. fv (25 a range) 1 , 3 400 600 s 10 v step, r dut = 400 k, c dut = 0.22 f, full dc load. fv (5 a range) 1 , 3 20 40 s 1 v step, r dut = 200 k, c dut = 0.22 f, full dc load. compensation register 1 = 0x8880 (1.7 f to 2.9 f, esr 74 to 140 m) fv (180 ma extforce1 range) 1 16 25 s 3 v step, c dut = 2.2 f, full dc load. fv (100 ma extforce2 range) 1 60 80 s 8 v step, c dut = 2.2 f, full dc load. compensation register 1 = 0xb880 (7.9f to 13 f, esr 74 to 140 m) fv (180 ma extforce1 range) 1 55 70 s 3 v step, c dut = 10 f, full dc load. fv (100 ma extforce2 range) 1 210 260 s 8 v step, c dut = 10 f, full dc load. compensation register 1 = 0xc880 (13 f to 22 f, esr 74 to 140 m) fv (180 ma extforce1 range) 1 65 80 s 3 v step, c dut = 20 f, full dc load. fv (100 ma extforce2 range) 1 310 370 s 8 v step, c dut = 20 f, full dc load. data sheet ad5560 rev. d | page 9 of 68 parameter min typ max unit test conditions/comments settling time (fv, measure current) compensation register 1 = 0x4880 (229 nf to 380 nf, esr 74 to 140 m) to within 10 mv of programmed value. mi (1200 ma extforce1 range) 1 30 40 s 3.7 v step, r dut = 2.4 , c dut = 0.22 f, full dc load. mi (900 ma extforce1 range) 1 32 42 s 8 v step, r dut = 8.8 , c dut = 0.22 f, full dc load. mi (500 ma extforce2 range) 1 69 95 s 15 v step, r dut = 30 , c dut = 0.22 f, full dc load. mi (300 ma extforce2 range) 1 70 100 s 10 v step, r dut = 33.3 , c dut = 0.22 f, full dc load. mi (25 ma range) 1 , 3 650 s 20 v step, r dut = 800 , c dut = 0.22 f, full dc load. mi (2.5 ma range) 1 , 3 6400 s 10 v step, r dut = 4 k, c dut = 0.22 f, full dc load. mi buffer alone 1 10 15 s 0.5 v step using measout high - z to within 10 mv of final value. settling time (fv, measure voltage) compensation register 1 = 0x4880 (229 nf to 380 nf, esr 7 4 to 140 m) to within 10 mv of programmed value. mv (1200 ma range) 1 16 s 3.7 v step, r dut = 2.4 , c dut = 0.22 f, full dc load. mv (900 ma range) 1 20 s 8 v step, r dut = 8.8 , c dut = 0.22 f, full dc load. mv (500 ma range) 1 34 s 15 v step, r dut = 30 , c dut = 0.22 f, full dc load. mv (300 ma range) 1 25 s 10 v step, r dut = 33.3 , c dut = 0.22 f , full dc load. mv (25 ma range) 1 , 3 125 180 s 20 v step, r dut = 800 , c dut = 0.22 f, full dc load. mv (2.5 ma range) 1 , 3 300 500 s 10 v step, r dut = 4 k, c dut = 0.22 f, full dc load. mv (250 a range) 1 , 3 300 500 s 10 v step, r dut = 40 k, c dut = 0.22 f, full dc load. mv buff er alone 1 2 5 s 10 v step using measout high - z to within 10 mv of final value. settling time (fv) safe mode to within 100 mv of programmed value. fv (1200 ma extforce1 range 1 25 s 3.7 v step, r dut = 3.1 , c dut = 0.22 f, full dc load. fv (180 ma extforce1 range) 1 303 s 3 v step, r dut = 16 , c dut = 0. 22 f to 20 f, full dc load. fv (100 ma extforce2 range) 1 660 s 8 v step, r dut = 33.3 , c dut = 0. 22 f to 20 f, full dc load. fv (25 ma range) 1 , 3 760 1000 s 2 0 v step, r dut = 400 , c dut = 0.22 f, full dc load. switching transients ra nge change transient 1 0.5 % of fv c dut = 10 f, changing from higher to adjacent lower ranges (except extforce1 to extforce2). 20 mv c dut = 10 f, changing from lower (5 a) to higher range (extforce1). 0.5 % o f fv c dut = 100 f, changing between all ranges. dac specifications force/comparator/offset dacs resolution 16 bits voltage output span ?22 +25 v v ref = 5 v, minimum and maximum values set by offset dac. differential nonlinearity 1 ?1 +1 lsb guaranteed monotonic. offset dac gain error ?20 +20 mv clamp dac cll < clh. resolution 16 bits voltage output span ?22 +25 v v ref = 5 v, minimum and maximum values set by offset dac. differentia l nonlinearity 1 ?1 +1 lsb guaranteed monotonic. osd dac resolution 16 bits voltage output span 0.62 5 v v ref = 5 v. differential nonlinearity 1 ? 2 +2 lsb dgs dac resolution 16 bits voltage output span 0 5 v v ref = 5 v. differential nonlinearity 1 ?2 +2 lsb ad5560 data sheet rev. d | page 10 of 68 parameter min typ max unit test conditions/comments comparator dac dynamic output voltage settling time 1 3.5 6 s 1 v cha nge to 1 lsb. slew rate 1 1 v/s digital - to - analog glitch energy 1 10 nv - s glitch impulse peak amplitude 1 40 mv reference input vref dc input impedance 1 m typically 100 m . vref input current ?10 +10 a per input; typically 30 na. vref range 1 2 5 v comparator measured directly at comparator; does not include measure block errors. error ?7 +7 mv uncalibra ted. voltage comparator with respect to the measured voltage. propagation delay 1 0.25 s error 1 ?12 +12 mv uncalibrated. current comparator propagation delay 1 0.25 1 s error 1 ?1.5 +1.5 % of programmed current range, uncalibrated. measure output, measout measure output voltage span 1 ?12.81 +12.81 v m easout gain = 1, v ref = 5 v, offset dac = 0x8000. measure output voltage span 1 ?6.405 +6.405 v measout gain = 1, v ref = 2.5 v. measure output voltage span 1 0 5.125 v measout gain = 0.2, v ref = 5 v, offset dac = 0x8000. measure output voltage span 1 0 2.56 v measout gain = 0.2, v ref = 2.5 v. measure pin output impedance 115 output leakage current ?100 +100 na when hw_in h is low. output capacitance 1 5 pf short - circuit current 1 ?10 +10 ma open - sense detect/clamp/alarm measurement accuracy ?200 +200 mv clamp accuracy 600 900 mv a larm delay 1 50 s dutgnd voltage range 1 ?1 +1 v pull - up current +50 +70 a pull - up for purpose of detecting open circuit on dutgnd, can be disabled. leakage current ?1 +1 a when pull - up disabled, dgs dac = 0x3333 (1 v with v ref = 5 v). if dutgnd voltage is far away from one of comparator thresholds, more leakage may be present. trip point accuracy ?30 +10 mv alarm delay 1 50 s guard amplifier voltage range 1 av ss + 2.25 av dd ? 2.25 v voltage span 1 25 v output offset ?10 +10 mv short - circuit current 1 ?20 +2 0 ma load capacitance 1 100 nf output impedance 100 alarm delay 1 200 s if it moves 100 mv away from input level. die temperature sensor accuracy 1 ?10 +10 % relative to a temperature change. output voltage at 25c 1.54 v output scale factor 1 4.7 mv/c output voltage range 1 1 2 v data sheet ad5560 rev. d | page 11 of 68 parameter min typ max unit test conditions/comments spi interface log ic logic inputs input high voltage, v ih 1.7/2.0 v (2.3 v to 2.7 v)/(2.7 v to 5.5 v) jedec - compliant input levels. input low voltage, v il 0.7/0.8 v (2.3 v to 2.7 v)/(2.7 v to 5.5 v) jedec - compliant input levels. input current, i inh , i inl ?1 +1 a input capacitance, c in 1 10 pf cmos logic outputs sdo, cpol, cpoh, gpo, cpo. output high voltage, v oh dv cc ? 0.4 v output low voltage, v ol 0.4 v i ol = 500 a. tristate leakage current ?1 + 1 a sdo, cpol, cpoh, cpo. output capacitance 1 10 10 10 pf sdo, cpol, cpoh, cpo. open - drain logic outputs busy , tmpalm , clalm , kelalm . outp ut low voltage, v ol 0.4 v i ol = 500 a, c l = 50 pf, r pullup = 1 k. output capacitance 1 10 pf power supplies hcav dd 1x 4 28 v |hcav dd x C hcav ss x| < 33 v, hcav ss x av ss , hcav dd x av dd . hcav ss 1x ?25 ?5 v hcav dd 2x 4 28 v |hcav dd x C hcav ss x| < 33 v, hcav ss x av ss , hcav dd x av dd . hcav ss 2x ?25 ?5 v av dd 8 28 v |av dd C av ss | < 33 v. av ss ?25 ?5 v dv cc 2.3 5.5 v ai dd 4 30 ma all ranges. ai ss 4 ?30 ma al l ranges. di cc 3 ma ai dd 4 27 ma channel inhibited/tristate, hw_inh or sw - inh low. ai ss 4 ?27 ma channel inhibited/tristate, hw_inh or sw - inh low. hcav dd x and hcav ss x supply currents shown are excluding load currents; however, for power budget calculations, the supply currents here are consumed by the load. hcai dd 1 20 ma when enabled, excludin g load conditions. hcai dd 1 0.5 ma when disabled. hcai ss 1 ?20 ma when enabled, excluding load condition. hcai ss 1 ?0.5 ma when disabled. hcai dd 2 15 ma when enabled, excluding load conditions. hcai dd 2 0.25 ma when disabled. hcai ss 2 ?15 ma when enabled, excluding load conditions. hcai ss 2 ?0.25 ma when disabled. power - down currents supply currents on power - up or during a power - down condition. hcaidd 250 a hcaiss ?250 a hcaidd 250 a hcaiss ?250 a aidd 5 ma aiss ?5 ma dicc 3 ma maximum power dissipati on extforce1 10 w extforce2 5 w power - up overshoot 1 5 % of programmed value. ad5560 data sheet rev. d | page 12 of 68 parameter min typ max unit test conditions/comments power supply sensitivity 1 dc to 1 khz. forced voltage/av dd ?65 db ?30 db at 1 00 khz. forced voltage/av ss ?65 db ?25 db at 100 khz. forced voltage/hcav dd x ?90 db ?60 db at 100 khz. forced voltage/hcav ss x ?90 db ?62 db at 100 khz. measured current/av dd ?50 db ?25 db at 100 khz. measured current/av ss ?43 d b ?20 db at 100 khz. measured current/hcav dd x ?90 db ?60 db at 100 khz. measured current/hcav ss x ?90 db ?60 db at 100 khz. measured voltage/av dd ?65 db ?30 db at 100 khz. measured voltage/av ss ?65 db ?25 db at 100 khz. measured v oltage/hcav dd x ?90 db ?60 db at 100 khz. measured voltage/hcav ss x ?90 db ?65 db at 100 khz. forced voltage/dv cc ?80 db ?46 db at 100 khz. measured current/dv cc ?80 db ?36 db at 100 khz. measured voltage/dv cc ?80 db ?46 db at 100 khz. 1 guaranteed by design and characterization, not subject to production test . 2 programmable clamps must be enabled if taking advantage of reduced headroom/footroom. 3 clamps disabled. 4 not including internal pull - up current between avdd/ avss and hcavddx/hcavssx pins. data sheet ad5560 rev. d | page 13 of 68 timing characteristi cs hcav dd x av ss + 33 v, hcav ss x av ss , av dd 8 v, av ss ? 5 v, |av dd ? av ss | 16 v and 33 v, v ref = 5 v (t j = 25c to 90c, maximum specifi cations, unless otherwise noted ) . table 2 . spi interface parameter 1 , 2 , 3 dv cc = 2.3 v to 2.7 v dv cc = 2.7 v to 3.3 v dv cc = 4.5 v to 5.5 v unit description t update 600 600 600 ns max channel u pdate cycle time t 1 2 5 20 20 ns min sclk cycle time ; 60/40 duty cycle t 2 1 0 8 8 ns min sclk high time t 3 10 8 8 ns min sclk low time t 4 10 10 10 ns min sync falling edg e to sclk falling edge setup time t 5 15 15 15 ns min minimum sync high time t 6 5 5 5 ns min 24 th sclk falling e dge to sync rising edge t 7 5 5 5 ns min data setup time t 8 4.5 4.5 4.5 ns min data hold time t 9 4 40 35 30 ns max sync rising edge to busy falling edge t 10 1.5 1.5 1.5 s max busy pulse width low for dac x 1 write 280 280 280 ns max busy pulse width low for other register write t 11 25 20 10 ns min reset pulse width low t 12 400 400 400 s max reset time indi cated by busy l ow t 13 250 250 250 ns min minimum sync high time in readback mode t 14 5 , 6 45 35 25 ns max sclk rising ed ge to sdo v alid t 15 30 30 30 ns max sync rising ed ge to sdo high -z load t iming t 16 20 20 20 ns min load pulse width low t 1 7 150 150 150 ns min busy rising edge to force output r esponse time t 1 8 0 0 0 ns min busy rising edge to load falling edge t 19 150 150 150 ns min load rising edge to force output response time 150 150 150 ns min load rising edge to current range response 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t f = 2 ns (10% to 90% of d v cc ) and timed from a voltage level of 1.2 v. 3 see figure 4 an d figure 5 . 4 this is measured with the load circuit shown in figure 2 . 5 this is measured with the load circuit shown in figure 3 . 6 longer sclk cycle time is required for cor rect operation of readback mode; consult timing diagrams and timing specifications. timing diagrams to output pin dv cc r load 2.2k? c load 50pf v ol 07779-002 figure 2. load circuit for open drain 07779-003 v oh (min ) ? v ol (max) 2 200a i ol 200a i ol to output pin c load 50pf figure 3. load circuit for cmos ad5560 data sheet rev. d | page 14 of 68 s y n c s clk s d i bu s y r e se t 1 2 t 3 t 2 2 4 t 4 t 6 t 1 t 7 t 8 t 9 db 2 3 db 0 t 10 t 11 t 12 bu s y t 5 1 l o a d a c t i v e durin g bu s y. 2 l o a d a c t i v e a ft e r bu s y. 3 load function is available via clen or hw_inh as determined by dps register 2. l o a d 1,3 force extforce1 extforce2 1 force extforce1 extforce2 2,3 l o a d 2,3 t 16 t 17 t 18 t 16 t 19 07779-004 figure 4. spi write timing sclk sync sdi sdo 24 48 d0b db23 db0 db0 input word specifies register to be read nop condition selected register data clocked out t 13 t 14 t 15 db23 db23 07779-005 figure 5. spi read timing data sheet ad5560 rev. d | page 15 of 68 absolute maximum rat ings table 3 . parameter rating av dd to av ss 34 v av dd to agnd ? 0.3 v to + 34 v av ss to agnd ? 34 v to + 0.3 v hcav dd x to hcav ss x 34 v hcav dd x to agnd ? 0.3 v to + 34 v hcav ss x to agnd ?34 v to + 0.3 v hcav dd x to av ss ? 0.3 v to av ss + 34 v hcav dd x to av dd ? 0.3 v to av dd + 0.3 v hcav ss x to av ss + 0.3 v to av ss ? 0.3 v d v cc to dgnd ?0.3 v to +7 v agnd to dgnd ?0.3 v to +0.3 v refgnd to a gnd ?0.3 v to +0.3 v digital inputs to dgnd ?0.3 v to dv cc + 0.3 v analog inputs to agnd av ss ? 0.3 v to av dd + 0.3 v extforce1 and extforce2 to agnd 1 av dd ? 28 v storage temperature ?65c to +125c operatin g junction temperature 25c to 90c reflow profile j - std 20 (jedec) junction temperature 150c max power dissipation 10 w max (extforce1 stage) 5 w max (extforce2 stage) esd hbm 1500 v ficdm 500 v 1 when an extforce1 or extforce2 stage is enab led and the supply differ - ential |av dd ? av ss | > 28 v, take care to ensure that these pins are not directly shorted to av ss voltage at any time because this can cause damage to the device. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. th is is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may a ffect device reliability. esd caution ad5560 data sheet rev. d | page 16 of 68 pin configuration s and function descrip tions nc c f4 c f3 c f2 c f1 c f0 dutgnd sense extmeasil guard/sys_dutgnd agnd av ss av dd extmeasih1 extmeasih2 av dd extforce1a hcav ss 1a hcav ss 2a extforce2a hcav dd 2a hcav dd 1b extforce1b hcav ss 1b hcav ss 2b extforce2b hcav dd 2b hcav dd 1c extforce1c hc_v ss 1c gpo hcav dd 1a pin 1 notes 1. nc = no connec t . 2. exposed pad on top of package. exposed pad is internally connected to most negative point, av ss . ad5560 t op view (not to scale) 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 37 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 47 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 07779-006 busy cpol sdo dv cc dgnd sclk sdi cpoh/cpo clen/load rclk tmpalm kelalm clalm reset hw_inh/load sync measout av dd c c3 c c0 c c1 c c2 slave_in av ss sys_force sys_sense agnd vref refgnd av ss force master_out exposed pad on top figure 6. tqfp _ ep pin configuration table 4 . tqfp _ ep pin function descriptions pin no. mnemonic description 1 clalm clamp alarm output . o pen - drain output, active low ; this pin can be programmed to be either latched or unlatched. 2 kelalm kelvin alarm pin for sense and dutgnd, open - drain active low . this pin c an be programmed to be either latched or unlatched. 3 tmpalm temperature alarm flag. o pen - drain output, active low ; t his pin can be programmed to be either latched or unlatched. 4 cpoh/ cpo comparator high output (cpoh) or window comparator outp ut (cpo ) . 5 cpol comparator low output . 6 busy open - drain active low outpu t . this pin indicat es the status of the calibration engine for the dac channels. 7 sdo serial data out put . this pin is u sed for reading back dac and dps register information for diagnostic purposes. 8 dv cc digital supply voltage . 9 dgnd digital ground reference point. 10 sclk clock input , active falling edge. 11 sdi serial data input . 12 sync frame sync, active low. 13 rclk ramp clock logic input. if t he ramp function is used, a clock signal of 833 khz maximum s hould be applied to this input to drive the ramp circuitry. tie rclk low if it is unused. 14 reset logic input . this pin is used to reset all internal nodes on the device to th eir power - on reset value. 15 clen/ load clamp enable. this input allows the user to enable or disable the c lamp circuitry. this pin can be configured as a load function to allow synchronization of multiple devices. eithe r clen or hw _ inh can be chosen as load input ( see the system control register , address 0x1 ). 16 hw _ inh / load hardware inhibit input to disable force amp lifier. this pin can be configur ed a s a load function to allow synchronization of multiple devices. either clen or hw_inh can be chosen as a load input ( see the system control register , address 0x1 ). 17 refgnd accurate ground referen ce for applied voltage referenc e. data sheet ad5560 rev. d | page 17 of 68 pin no. mnemonic description 18 vref reference input for dac channels , input range 2 v to 5 v . 19, 44 agnd analog ground. 20, 30, 45 av ss negative analog supply voltage . these pin s suppl y dacs and other high voltage circuitr y , such as m easure b loc ks. 21, 33, 46 av dd positive analog supply voltage. th e s e pin s supply dacs and other high voltage circuitry , such as m easure blocks . 22 measout multiplexed dut voltage sense, dut current sense, kel vin sense , or temperature output; refer to agnd . 23 c c3 compensation capacitor input 3 . 24 c c0 compensation capacitor input 0 . 25 c c1 compensation capacitor input 1 . 26 c c2 compensation capacitor input 2 . 27 slave_ in slave input when ganging multiple dps devices . 28 master_ out master output when ganging multiple dps devices . 29 sys_sense external sense signal output. 31 sys_force external force signal input. 32 force output force pin for internal current ranges. 34 nc no connect. 35 c f4 feedforward capacitor 4 . 36 c f3 feedforward capacitor 3 . 37 c f2 feedforward capacitor 2 . 38 c f1 feedforward capacitor 1 . 39 c f0 feedforward capacitor 0 . 40 dutgnd device under test ground. 41 sense input sense line. 42 extmeasil low side measure current line for external high current ranges. 43 guard /sys_dutgn d guard amplifier output pin or system d evice u nder t est g round p in. see the dps register 2 in table 19 for addressing details. 47 extmeasih1 input high measure lin e for external high current range 1 . 48 extmeasih2 input hig h measure line for external high current range 2 . 49, 55, 61 hcav dd 1 a, hcav dd 1b, hcav dd 1c high current posi tive analog supply voltage, for extforce1 range . 50, 56, 62 extforce1 a, extforce1b, extforce1c output force . this pin is used for high current ra nge 1, up to a max imum of 1.2 a . 51, 57, 63 hcav ss 1 a, hcav ss 1b, hcav ss 1c high current nega tive analog supply voltage, for extforce1 range . 52, 58 hcav ss 2 a, hcav ss 2b high current negative analog supply voltage, for extforce2 range . 53, 59 extforce2 a, extforce 2 b output force . this pin is used for high current range 2, up to a max imum of 500 ma . 54, 60 hcav dd 2 a, hcav dd 2b high current positive analog supply voltage, for extforce2 range . 64 gpo extra logic output bit . ideal for external function s such as switching out a decoupling capacitor at dut. 65 ep the exposed pad is internally connected to av ss . ad5560 data sheet rev. d | page 18 of 68 9 8 7 6 5 4 3 2 1 extforce1a extforce1a extforce2a extforce1b extforce1b extforce2b extforce1c extforce1c gpo hcav dd 1a hcav ss 1a hcav dd 2a hcav dd 1b hcav ss 1b hcav dd 2b hcav dd 1c hcav ss 1c clalm hcav dd 1a hcav ss 1a hcav ss 2a hcav dd 1b hcav ss 1b hcav ss 2b hcav dd 1c hcav ss 1c kelalm av dd extmeasih1 extmeasih2 cpol cpoh/cpo tmpalm av ss agnd guard/ sys_dutgnd dv cc sdo busy dutgnd extmeasil sense sdi sclk dgnd c f0 c f2 sys_force sys_sense c c0 av ss reset rclk sync c f1 c f3 slave_in master_out c c1 measout av dd vref clen/ load c f4 av dd force c c2 c c3 av ss agnd refgnd hw_inh/ load 3 3 array is void of balls a b c d e f g h j 07779-062 figure 7. f lip - chip bga pin configuration, bottom side (bga balls are visible ) table 5 . flip - ch ip bga pin function descriptions pin no. mnemonic description a1 gpo extra logic output bit. ideal for external functions such as switching out a decoupling capacitor at dut. a2 , a3 extforce1c output force. th ese pin s are used for high current range 1, u p to a maximum of 1.2 a. a4 extforce2b output force. this pin is used for high current range 2, up to a maximum of 500 ma. a5, a6 extforce1b output force. th ese pin s are used for high current range 1, up to a maximum of 1.2 a. a7 extforce2a outpu t fo rce. this pin is used for high current range 2, up to a maximum of 500 ma. a8, a9 extforce1a output force. th ese pin s are used for high current range 1, up to a maximum of 1.2 a. b1 clalm clamp alarm output. open - drain output, active low; this pin can be programmed to be either latched or unlatched. b2 , c2 hca v ss 1c high current negative analog supply voltage for extforce1 range. b3 , c3 hca v dd 1c high current positive analog supply voltage for extforce1 range. b4 hca v dd 2b high current positive analog supply voltage for extforce2 range. b5 , c5 hca v ss 1b high current negative analog supply voltage for extforce1 range. b6 , c6 hca v dd 1b high current positive analog supply voltage for extforce1 range. b7 hca v dd 2a high current po sitive anal og supply voltage for extforce2 range. b8 , c8 hca v ss 1a high current negative analog supply voltage for extforce1 range. b9 , c9 hca v dd 1a high current positive analog supply voltage for extforce1 range. c1 kelalm kelvin alarm pin for sen se and dutgnd, open - drain active low. this pin can be programmed to be either latched or unlatched. c4 hca v ss 2b high current negative analog supply voltage for extforce2 range. c7 hca v ss 2a high current negative analog supply voltage for extforce2 range. data sheet ad5560 rev. d | page 19 of 68 pin no. mnemonic description d1 tmpalm temperature alarm flag. open - drain output, active low; this pin can be programmed to be either latched or unlatched. d2 cpoh/cpo comparator high output (cpoh) or window comparator output (cpo). d3 cpol comparator low output. d7 extmeasih2 input high measure line for external high current range 2. d8 extmeasih1 input high measure line for external high current range 1. d9 , h3 , j8 av dd positive analog supply voltage. these pins supply dacs and other high voltage circuitry, su ch as measure blocks. e1 busy open - drain active low output. this pin indicates the status of the calibration engine for the dac channels. e2 sdo serial data output. this pin is used for reading back dac and dps register information for diagnostic purposes. e3 dv cc digital supply voltage. e7 guard/sys_dutgnd guard amplifier output pin or system device under test ground pin. see the dps register 2 in table 19 for addressing details. e8 agnd analog ground . e9 , g4 , j4 av ss negative analog supply voltage. these pins supply dacs and other high voltage circuitry, such as measure blocks. f1 dgnd digital ground reference point. f2 sclk clock input, active falling edge. f3 sdi serial data input. f7 sense in put sense line. f8 extmeasil low side measure current line for external high current ranges. f9 dutgnd device under test ground. g1 sync frame sync, active low. g2 rclk ramp clock logic input. if the ramp function is used, a clock sig nal of 833 khz maximum should be applied to this input to drive the ramp circuitry. tie rclk low if it is unused. g3 reset logic input. this pin is used to reset all internal nodes on the device to their power - on reset value. g5 c c0 com pensation capacitor input 0. g6 sys_sense external sense signal output. g7 sys_force external force signal input. g8 c f2 feedforward capacitor 2. g9 c f0 feedforward capacitor 0. h1 clen/ load clamp enable. this input allows the user t o enable or disable the clamp circuitry. this pin can be configured as a load function to allow synchronization of multiple devices. either clen or hw_inh can be chosen as load input (see the system con trol register, address 0x1). h2 vref reference input for dac channels, input range is 2 v to 5 v. h4 measout multiplexed dut voltage sense, dut current sense, kelvin sense, or temperature output; refer to agnd. h5 c c1 compensation capacitor input 1. h6 master_out master output when ganging multiple dps devices . h7 slave_in slave input when ganging multiple dps devices. h8 c f3 feedforward capacitor 3. h9 c f1 feedforward capacitor 1. j1 hw_inh / load hardware inhibit input to disable force amplifier. this pin can be configured as a load function to allow synchronization of multiple devices. either clen or hw_inh can be chosen as a load input (see the system control register, address 0x1). j2 refgnd accurate ground reference for applied voltage reference. j3 agnd analog ground. j5 c c3 compensation capacitor input 3. j6 c c2 compensation capacitor input 2. j7 force output force pin for internal current ranges. j9 c f4 feedforward capacitor 4. ad5560 data sheet rev. d | page 20 of 68 typical performance characteristics 07779-026 code linearity (mv) ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 0 10,000 20,000 30,000 40,000 50,000 60,000 figure 8. force voltage linearity vs. code, v ref = 5 v, no load 07779-027 code mv linearity error (mv) 10,000 0 20,000 2.0 1.5 0.5 0 ?0.5 ?1.0 1.0 ?1.5 ?2.0 30,000 40,000 50,000 60,000 t j = 2 5 c a v dd = 16.25v a v ss = ?16.25v v ref = 5v measout gain = 1 measout gain = 0.2 figure 9. measure voltage linearity vs. code (measout gain = 1, measout gain = 0.2, nominal supplies) measout gain = 1 07779-033 code mv linearity (mv) ?2 ?1 0 1 2 3 4 5 0 10,000 20,000 30,000 40,000 50,000 60,000 t j = 25 c av dd = 28v av ss = ?5v v ref = 5v offset dac = 0xd1d measout gain = 0.2 figure 10 . measure voltage linearity vs. code (measout gain = 1, measout gain = 0.2, positive skew supply) ?4 ?2 0 2 4 6 8 10 12 measout gain = 1 measout gain = 0.2 07779-034 code mv linearity (mv) 0 10,000 20,000 30,000 40,000 50,000 60,000 t j = 25 c av dd = 8v av ss = ?25v v ref = 5v offset dac = 0 xd4eb figure 11 . measure voltage linearity vs. code (meas out gain 1, measout gain = 0.2, negative skew supply) 07779-035 code 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 low supplies high supplies high: av dd = 28v, av ss = ?5v, offset dac = 0xd1d low: av dd = 5v, av ss = ?25v offset dac = 0xd4eb nom: av dd /av ss = 16.25v, offset dac = 0x8000 v ref = 5v nominal supplies linearity (%) ?0.0100 0.0100 ?0.0075 ?0.0050 ?0.0025 0.0025 0 0.0050 0.0075 figure 12 . measure current linearity vs. code (measout gain = 1, mi gain = 20) , t j = 25c 07779-036 code mi linearity (%) 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 ?0.010 ?0.005 0.005 0 0.010 high supplies nominal supplies high: av dd = 28v, av ss = ?5v, offset dac = 0xd1d low: av dd = 5v, av ss = ?25v offset dac = 0xd4eb nom: av dd /av ss = 16.25v, offset dac = 0x8000 v ref = 5v low supplies figure 13 . measure current linearity vs. code ( measo ut gain = 1, mi gain = 10) data sheet ad5560 rev. d | page 21 of 68 07779-037 code 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 high supplies nominal supplies high: av dd = 28v, av ss = ?5v, offset dac = 0xd1d low: av dd = 5v, av ss = ?25v offset dac = 0xd4eb nom: av dd /av ss = 16.25v, offset dac = 0x8000 v ref = 5v 25ma range low supplies linearity (%) ?0.0500 0.0500 ?0.0375 ?0.0250 ?0.0125 0.0125 0 0.0250 0.0375 figure 14 . measure current linearity vs. code ( measout gain = 0.2, mi gain = 20) 07779-038 code 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 high supplies high: av dd = 28v, av ss = ?5v, offset dac = 0xd1d low : av dd = 5v, av ss = ?25v offset dac = 0xd4eb nom : av dd /av ss = 16.25v, offset dac = 0x8000 v ref = 5v 25ma range low supplies nominal supplies linearity (%) ?0.100 0.100 ?0.075 ?0.050 ?0.025 0.025 0 0.050 0.075 figure 15 . measure current linearity vs. code ( measout gain = 0.2, mi gain = 10) 07779-039 code linearity (%) 0 10,000 20,000 30,000 40,000 50,000 60,000 ?0.0100 0.0100 ?0.0075 ?0.0050 ?0.0025 0.0025 0 0.0050 0.0075 av dd = +16.25v av ss = ?16.25v v ref = 5v offset dac = 0x8000 mi gain = 20 measout gain = 1 25ma range 25 a range 2.5ma fi gure 16 . measure current linearity vs. i range ( measout gain = 1, mi gain = 20) 07779-040 code linearity (%) 0 10,000 20,000 30,000 40,000 50,000 60,000 ?0.0500 0.0500 ?0.0375 ?0.0250 ?0.0125 0.0125 0 0.0250 0.0375 av dd = +16.25v av ss = ?16.25v v ref = 5v offset dac = 0x8000 mi gain = 20 measout gain = 0.2 25ma range 25 a range 2.5ma figure 17 . measure current linearity vs. i range ( measout gain = 0.2, mi gain = 20) 07779-030 stress voltage (v) leakage current (na) t j = 25 c ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 ?10 5 0 5 10 extforce1a extforce2b force extforce1b extmeasih1 sense extforce1c extmeasih2 sys_force extforce2a extmeasil sys_sense combined leakage figure 18 . leakage current vs. stress voltage (force and c ombined leakage ) 0 1 2 3 4 5 6 7 07779-031 leakage current (na) extforce1a extforce2b force extforce1b extmeasih1 sense extforce1c extmeasih2 sys_force extforce2a extmeasil sys_sense combined leakage v stress = 9v 25 35 45 55 65 75 85 95 temperature ( c) figure 19 . leakage current vs. temperature (force and combined leakage) , v stress = 9 v ad5560 data sheet rev. d | page 22 of 68 07779-032 stress voltage (v) leakage current (na) t j = 25c ?0.20 ?0.15 ?0.10 ?0.05 0.05 0 0.10 0.15 ?10 5 0 5 10 extforce1a extforce2b extforce1b extmeasih1 sense extforce1c extmeasih2 sys_force extforce2a extmeasil sys_sense figure 20. leakage current vs. stress voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 extforce1a extforce2b extforce1b extmeasih1 sense extforce1c extmeasih2 sys_force extforce2a extmeasil sys_sense 25 35 45 55 65 75 85 95 07779-061 temperature (c) leakage current (na) v stress =9v figure 21. leakage current vs. temperature, v stress = 9 v ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 25 35 45 55 65 75 85 07779-047 temperature (c) offset error (%) high high 0.2 nominal low nominal 0.2 low 0.2 high: av dd = 28v, av ss = ?5v, offset dac = 0xd1d low : av dd = 5v, av ss = ?25v offset dac = 0xd4eb nom : av dd /av ss = 16.25v, offset dac = 0x8000 v ref = 5v low0.2/high0.2/nom0.2 mean for measout gain = 0.2 figure 22. mi offset error vs. temperature, mi gain = 20, measout gain = 1 and 0.2 ?0.12 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 25 35 45 55 65 75 85 07779-48 temperature (c) gain error (%) high nominal low figure 23. mi positive gain error vs. temperature, mi gain = 20, measout gain = 1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 25 35 45 55 65 75 85 07779-043 temperature (c) positive gain error (mv) negative gain error (mv) av dd = 16.25v av ss = ?16.25v v ref = 5v offset dac = 0x8000 figure 24. fv gain error vs. temperature 20.0 20.5 21.0 21.5 22.0 22.5 23.0 25 35 45 55 65 75 85 07779-041 temperature (c) offset error (mv) figure 25. fv offset error vs. temperature data sheet ad5560 rev. d | page 23 of 68 ?0.007 ?0.006 ?0.005 ?0.004 ?0.003 ?0.002 ?0.001 0 25 35 45 55 65 75 85 07779-045 temperature ( c) gain error (%) high nominal low figure 26 . mv gain error v s. temperatur e, measout gain = 1 25 35 45 55 65 75 85 low high 07779-042 temperature ( c) offset error (mv) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 nominal figure 27 . mv offset error vs . temperature , measout gain = 1 0 0.005 0.010 0.015 0.020 0.025 0.030 25 35 45 55 65 75 85 07779-046 temperature ( c) gain error (%) high nominal low figure 28 . mv gain error vs . temperature , measout gain = 0.2 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 25 35 45 55 65 75 85 07779-044 temperature ( c) offset error (mv) high nominal low figure 29 . m v o ffset error vs . temperature , measout gain = 0.2 07779-015 ch1 50mv ch3 5v m200 s a ch3 1.5v 1 3 t 10.4% ch1 p-p 27mv ch1 are a 10.92 vs b w b w force sync figure 30 . range change 2.5 ma to 25 ma, safe mode, 2.5 ma i load , 10 f load 07779-016 ch1 50mv ch3 5v m200 s a ch3 1.5v 1 3 t 10.4% ch1 p-p 16mv ch1 are a ?5.336 vs b w b w force sync figure 31 . range change 25 ma to 2.5 ma, safe mode, 2.5 ma i load , 10 f load ad5560 data sheet rev. d | page 24 of 68 07779-017 ch1 50mv ch3 5v m200 s a ch3 1.5v 1 3 t 10.4% ch1 p-p 159mv ch1 are a 14.31 vs b w b w force sync figure 32 . range change 25 ma to extforce2 , safe mode, 25 ma i load , 10 f load 07779-018 ch1 50mv ch3 5v m200 s a ch3 1.5v 1 3 t 10.4% ch1 p-p 36mv ch1 are a ?9.738 vs force sync figure 33 . range change extforce2 to 25 ma, safe mode, 25 ma i load , 10 f load 07779-019 peak-to-peak (mv) 0 50 100 150 200 250 300 350 safe mode auto comp safe mode auto comp safe mode auto comp ext range 1 ext range 2 25ma range 10 f load 30 f load 100 f load figure 34 . kick/droop response vs . i range , compensation , and c load , , 10% to 90% to 10% i load change 07779-020 ch1 100mv ch2 5v m40 s a ch2 1.6v 1 2 t 120.4 s ch1 p-p 84mv b w trigger force figure 35 . autoc omp e nsation mode 90% to 10% i load change , extforce2 range , 10 f load 07779-021 ch1 100mv ch2 5v m40 s a ch2 4v 1 2 t 120.4 s ch1 p-p 86mv b w trigger force figure 36 . autoc omp ensation mode 10% to 90% i load change, extforce2 range , 10 f load 07779-022 ch1 100mv ch2 5v m40 s a ch2 1.6v 1 2 t 120.4 s ch1 p-p 172mv b w trigger force figure 37 . safe mode 80% to 10%, extforce2 r ange, 10 f load data sheet ad5560 rev. d | page 25 of 68 ch2 5v 07779-023 ch1 100mv m40 s a ch2 4.6v 1 2 t 120.4 s ch1 p-p 174mv b w trigger force figure 38 . safe mode 10% to 90%, extforce2 range, 10 f load 07779-024 forced temperature ( c) measout voltage (v) 1.4 1.5 1.6 1.7 1.8 1.9 2.0 25 35 45 55 65 75 85 av dd = +16.5v av ss = ?16.5v figure 39 . measout tsense temperature sensor vs. temperature ( multiple devices) 07779-054 ch1 5v ch3 5v m400 s a ch3 2.9v 1 2 3 4 t 10.2% b w ch2 2v ch4 10v t a = 25 c av dd = +16.25v av ss = ?16.25v v ref = 5v offset dac = 0x8000 i range /i load = 250 a 0 to 10v step r load = 40k ? c load = 220nf autocomp mode 0x4880 measout gain 1, mi gain 20 force measout ? mi busy figure 40 . transient response fvmi mode , 25 0 a range , autocompensation mode 07779-055 ch1 5v ch3 5v m20 s a ch3 2.9v 1 2 3 4 t 1.4% b w ch2 2v ch4 10v t a = 25 c av dd = +16.25v av ss = ?16.25v v ref = 5v offset dac = 0x8000 i range /i load = 25ma 0 to 10v step r load = 40k ? c load = 220nf autocomp mode 0x4480 measout gain 1, mi gain 20 force measout ? mi busy figure 41 . transient response fvmi mode , 25 ma range , autocomp ensation m ode 07779-056 ch1 5v ch3 5v m100 s a ch3 2.9v 1 2 3 4 t 7.2% b w ch2 2v ch4 10v t a = 25 c av dd = +16.25v av ss = ?16.25v v ref = 5v offset dac = 0x8000 i range /i load = 250 a 0 to 10v step r load = 40k ? c load = 220nf safe mode measout gain 1, mi gain 20 force measout ? mi busy figure 42 . transient response fvmi mode , 25ma range, safe mode 07779-057 ch1 5v ch3 5v m4s a ch3 2.9v 1 2 3 4 t 3% b w ch2 1v ch4 10v t a = 25 c av dd = +16.25v av ss = ?16.25v v ref = 5v offset dac = 0x8000 i range /i load = extforce1/1.2a 0 to 3.7v step c load = 10 f ceramic autocomp mode 0x9680 measout gain 1, mi gain 20 force measout ? mi busy figure 43 . transient response fvmi mode , extforce1 range , autocompensation mode ad5560 data sheet rev. d | page 26 of 68 07779-058 ch1 5v ch3 5v m20 s a ch3 2.9v 1 2 4 t 4.6% b w ch2 1v ch4 10v t a = 25 c av dd = +16.25v av ss = ?16.25v v ref = 5v offset dac = 0x8000 i range /i load = extforce1/1.2a 0 to 3.7v step c load = 10 f ceramic safe mode measout gain 1, mi gain 20 3 force measout ? mi busy figure 44 . transient response fvmi mode , extforce1 range , safe mode 07779-059 ch1 5v ch3 5v m10 s a ch3 2.9v 1 2 3 4 t 9.8% b w ch2 2v ch4 10v t a = 25 c av dd = +16.25v av ss = ?16.25v v ref = 5v offset dac = 0x8000 i range /i load = extforce2/ 300ma 0 to 10v step c load = 220nf autocomp mode 0x4880 measout gain 1, mi gain 20 force measout ? mi busy figure 45 . transient response fvmi mode, extforce2 range , autocompensation mode 3 07779-060 ch1 5v ch3 5v m100 s a ch3 2.9v 1 2 4 t 9.8% b w force ch2 2v ch4 10v t a = 25 c av dd = +16.25v av ss = ?16.25v v ref = 5v offset dac = 0x8000 i range /i load = extforce2/300ma 0 to 10v step c load = 220nf safe mode measout gain 1, mi gain 20 measout ? mi busy figure 46 . transient response fvmi mode, extforce2 range , safe mode 07779-025 nsd (nv/ hz) 0 100 200 300 400 500 600 700 800 900 1000 part h1 part h2 part h3 gain = 00 gain = 10 gain = 00 gain = 10 gain = 00 gain = 01 gain = 10 gain = 11 fvmn fvmv fnmv fvmi figure 47 . nsd vs . amplifier stage and gain setting at 1 khz ?100 ?80 ?60 ?40 ?20 20 0 10 100 1k 10k 100k 1m 10m 07779-049 frequency (hz) acpsrr (db) dv cc = +5.25v, av dd = +16.5v, av ss = ?16.5v foh mv: gain 0 mv: gain 1 mv: gain 2 mv: gain 3 mi: gain 0 mi:gain 1 mi: gain 2 mi: gain 3 figure 48 . acpsrr of av dd vs . frequency ?100 ?120 ?140 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m 07779-050 frequency (hz) acpsrr (db) dv cc = +5.25v, av dd = +16.5v, av ss = ?16.5v foh mv: gain 0 mv: gain 1 mv: gain 2 mv: gain 3 mi: gain 0 mi:gain 1 mi: gain 2 mi: gain 3 figure 49 . acpsrr of av ss vs . f requency data sheet ad5560 rev. d | page 27 of 68 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m 07779-051 frequency (hz) acpsrr (db) mv: gain 0 foh mi: gain 0 dv cc = +5.25v, av dd = +16.5v, av ss = ?16.5v figure 50 . acpsrr of dv cc vs . frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m 07779-052 frequency (hz) acpsrr (db) mi: gain 0 foh dv cc = +5.25v, av dd = +16.5v, av ss = ?16.5v mv: gain 0 figure 51 . acpsrr o f hcav dd x vs . f requency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m 07779-053 frequency (hz) acpsrr (db) mi: gain 0 dv cc = +5.25v, av dd = +16.5v, av ss = ?16.5v foh mv: gain 0 figure 52 . acpsrr of hcav ss x vs . f requency 0 200 400 600 800 1000 1200 1400 1600 0.001 0.01 0.1 1 10 i clamp v alue ( ma) r load ( ?) cable l = 0h, clamp at 800ma cable l = 1h, clamp at 800ma cable l = 2h, clamp at 800ma cable l = 0h, clamp at 1.2a cable l = 2h, clamp at 1.2a cable l = 0.2h, clamp at 1.2a cable l = 1h, clamp at 1.2a cable l = 0.2h, clamp at 800ma cable l = 0h, clamp at 400ma cable l = 0.2h, clamp at 400ma cable l = 1h, clamp at 400ma cable l = 2h, clamp at 400ma cable l = 0h, clamp at 100ma cable l = 0.2h, clamp at 100ma cable l = 1h, clamp at 100ma cable l = 2h, clamp at 100ma 07779-063 figure 53 . i clamp value vs. r load C cal at 1ohm ad5560 data sheet rev. d | page 28 of 68 terminology offset error offset error is a measure of the difference between t he actual voltage and the ideal voltage at midscale or at zero current expressed in m illivolts (mv) or percentage of full - scale range ( % fsr ) . gain error gain error is the difference between full - scale error and zero - scale error. it is expressed in percenta ge of full - scale range ( % fsr) . gain error = full - scale error ? zero - scale error where: full - scale error is the difference between the actual voltage and the ideal voltage at full scale. zero - scale error is the difference between the actual voltage and the ideal voltage at zero scale. linearity error linearity error , or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the full - scale range. it is measured after adjusting for offset error and gain error and is expressed in m illivolts (mv) . common - mode (cm) error cm error is the error at the output of the amplifier due to the common - mode input voltage. it is expressed in percentage of full - scale voltage range per volt (% fsvr/v ) . clamp limit clamp limit is a measure of where the clamps begin to function fully and limit the clamped voltage or current. leakage current leakage c urrent is the current measured at an output pin when the circuit connected to that pin is in high impedance state. slew rate the slew rate is the rate of change of t he output voltage expre ssed in volts per micro s econd (v/s) . differential nonlinearity (dnl) dnl is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified dnl of 1 lsb maximum ensures monotonicity. output voltage settling time output voltage settli ng time is the amount of time it takes for the output of a dac to settle to a specified level for a full - scale input change. digital -to - analog glitch energy digital - to - analog glitch energy is the amount of energy that is injected into the analog output at the major code transition. it is specified as the area of the glitch in nanovolts per second ( nv - s ec ) . it is measured by toggling the dac register data between 0x7fff and 0x8000 . ac power supply rejection ratio ( acpsrr ) acpsrr is a measure of the parts a bility to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.2 v p - p. the ratio of the amplitude of the signal on the output to the am plitude of the modulation is the acpsrr . it is expressed in decibels (db) . v stress v stress is the stress voltage applied to each pin during leakage testing. data sheet ad5560 rev. d | page 29 of 68 theory of operation the ad5560 is a single - channel , device power supply for use in semiconduct or automatic test equipment. a ll the dac levels required to operate the device are available on chip . this device contains programmable modes to force a pin vol - tage and measure the corresponding current (fvmi ) covering a wide current measure range of up to 1.2 a . a voltage sense amplifier allows measurement of the dut voltage. measured current or voltage is available on the measout pin. force amplifier the f orce amplifier is a unity gain amplifier forcing voltage directly to the device under test (dut ). this high bandwidth amplifier allow s suppression of load transient induced glitching on the am plifier output. headroom and footroom requireme nts for t he amplifier are 2.25 v and an additional 500 mv dro pped across the selected sense resistor with full - sc ale current flowing. the amplifier is designed to drive high currents up to 1.2 a with the capability of ganging together outputs of multiple ad5560 devices for currents in excess of 1.2 a. the force amplifier can be compensated to ensure stability when driving dut capacitances of up to 160 f. the device is capable of supplying transient currents in excess of 1.2 a when powering a dut with a large decoupling capacitor. a c lamp enable pin (clen) allows disabling of the c lamp circuitry to allow the ampl ifier to quickly charge this large capacitance. an extra control bit (gpo) is available to switch out dut decoupling when making low current measurements. hw_ inh function a hardware inhibit pin ( hw_inh / l oad ) allows disabling of the force amplifier, making the output high impedance. this function is also availab le through the serial interface ( see the sw - inh bit in the dps register 1 , address 0x2) . this pin can also be configured as a load function to allow multiple devices to be synchronized. note that either clen or hw_inh can be chosen as a load function. dac reference voltag e ( vref ) one analog reference input , vref, supplies all dac level s with the neces sary reference voltage to generate the required dc levels. open - sense detect (osd) alarm and clamp the open - se nse detect (osd) circuitry protects the dut from overvoltage when the force and sense lines of the f orce amplifier beco ming disconnected from each other. this block performs three functions related to the force and sense lines . ? it c lamps the sense line to within a programmable threshold level (plus a v be ) of the force line , where the programmable threshold is set by the osd dac voltage level . this limits the maximum or minimum voltage that can appear on the force pin ; it c an be driven no higher than [v( f in dac) + t hreshold + v be ] and no lower than [v( f in dac) ? t hreshold ? v be ] . ? it t r iggers an alarm on kelalm if the force line goes mo re than the threshold voltage away (osd dac level) from the sense line. ? it t ranslates the v( f orce ? s ense ) voltage to a level relative to agnd so that it can b e measured through the measout pin. the o pen - sense detect level is programmable over the range 0.62 v to 5 v (16 - b it osd dac plus one diode drop). the 5 v osd dac can be access ed through the serial interface ( see the dac register addressing portion of table 24) . there is a 10 k? resistor that can be connected between the force and sense pins by use of sw11. this 10 k? resistor is intended to maintain a force/sense connection when a dut is not in place. it is not intended to be connected when measurements are being made because this defeats the purpose of the osd circuit in identifying an open circuit between force and sense . in addition, the sense path has a 2.5 k? resistor in series; there - fore, if the 10 k? switch is closed, errors may become apparent when in high current rang es. device u nder test g round (dutgnd) dutgnd is the ground level of the dut. dutgnd kelvin sense kelalm flags when the voltage at the dutgnd pin moves too far away from the agnd line (>1 v default setting of the dgs dac ). this alarm tri gger is programmable via the serial interface. th e threshold for the alarm function is program - mable using the dutgnd sense dac (dgs dac) (s ee table 24). the dutgnd pin has a 50 a pull - up resistor that allows the alarm function to detect whether dutgnd is open. setting the disable dutalm bit high (register 0x6, bit 10) disables the 50 a pull - up resistor and also disables the alarm feature. the alarm feature c an also be set to latched or unlatched (register 0x6, bit 11) . kelvin alarm ( kelalm ) the open - drain active low kelvin alarm pin flags the user when an open occurs in either the s ense or dutgnd line ; it can be programmed to be either latch ed or unlatched ( r egister 0x6 , bit 13, bit 11, bit 7 ) . the delay in the alarm flag is 50 s. ad5560 data sheet rev. d | page 30 of 68 gpo the gpo pin can be used as an extra control bit for external switching functions, such as for switching out dut decoupling when making low current measurements. the gpo pin is also internally connected to an array of thermal diodes scattered acr oss the ad5560. the d iagnostic register (address 0x7) details the addressing and location of the diodes. these can be used for diagnostic purposes to determine the thermal gradients across the die and across a board containing many ad5560 devices. when sel ected, the anode of these diodes is connected to gpo and the cathode to agnd. the ad5560 evaluation board uses the on semiconductor ? adt7461 temperature sensor for the purpose of analyzing the temperature at different points across the die. comparators the dut measured value is monitored by two comparators (cpol, cpoh) . these comparators give the advantage of speed for go - no - go testing. table 6 . comparator output function test condition cpol cpoh ( v dut or i dut ) > cph 0 ( v dut or i dut ) < cph 1 ( v dut or i dut ) > cpl 1 ( v dut or i dut ) < cpl 0 cph > ( v dut or i dut ) > cpl 1 1 to minimize the number of comparator output lines routed back to the controller, it is possible to change the comparator function to a window comparator that o utput s on one single pin , cpo. this pin is shared with cpoh and , when configured through the serial interface , it provides information on whether the measured dut current or voltage is inside or outside the window set by the cpl and cph dac levels (see table 24) . table 7 . comparator output function in cpo mode test condition cpo output (v dut or i dut ) > cpl and < cph 1 (v dut or i dut ) < cpl or > cph 0 current clamps high and low current clamps are inc luded on chip. these protec t the dut in the event of a short circuit. the clh and cll levels are set by the 16 - b it dac levels. t he clamp works to limit the current supplied by the force amplifier to within the set levels. the clamp circuitry compares the voltage across the sense resistor (multiplied by an i n - amp gain of 10 or 20) to compare to the programmed clamp limit and activates the clamp circuit if either the high level or low level is exceeded, thus ensuring that the dut current can never exceed the prog rammed clamp limit + 10% of full - scale current. if a clamp level is exceeded, this is flagged via the latched open - drain clalm pin , and the resulting alarm information can be read back via the spi interface. the clamp levels shou ld not be set to the same level; instead , they should be set a minimum of 2 v apart (irrespective of the mi gain setting). this equates to 1 0% of fscr (mi gain = 20) (20% of fscr, mi g ain of 10) apart . they should also be 1 v away from the 0 a level. the cl amp register limits the cll clamp to the range 0x0000 to 0x7fff ; any code in excess of this is seen as 0x7fff . s imilarly, the clh clamp register s are limited to the range 0x8000 to 0xfff f (see table 24) . clamp alarm function ( clalm ) the clalm open - drain output flags the user when a clamp limit has been hit ; it can be programmed to be either latched or unlatched. clamp enable f unction (clen / load ) pin 15 ( clen ) allows the u ser to disable the c lamping function w hen powering a device with large dut capacitance, thus allowing increased current drive to the device and , therefore , speeding up the charging time of the load capacitance. clen is active high. thi s pin can also be con figured as load to allow multiple dev ices to be synchronized. note that either clen or hw _ inh can be chosen as a load function. short - circuit protection the ad5 560 force amplifier stage has built - in sho rt - circuit protection per stage as noted in the specifications section . when the current clamps are disabled, the user must minimize the duration of time that the device is left in a short - circuit condition (for all current ra nges). g uard a mplifier a g uard amplifier allows the user to force the shield of the coaxial cable to be driven to the same forced voltage at the dut, ensuring minimal voltage drops across the cable to minimize errors from cable insulation leakage. the gua rd amplifier also has an alarm function that flag s the open - drain kelalm pin when the g uard output is shorted. the delay in the alarm flag is 200 s. the g uard amplifier output (guard /sys_dutgnd , pin 43 ) can also be configured to function as a sys_dutgnd pin; to do this, the guard a mplifier must be tristated via software ( see dps register 2, table 19 ). compensation capacit ors the force amplifier is capable of driving dut capacitances up to 160 f. four extern al compensation capacitor (c c x ) inputs are provided to ensure stability into the maximum load capacit - ance while ensuring that settling t ime is optimized. in addition, five c f x capacitor inputs are provided to switch across the sense d ata sheet ad5560 rev. d | page 31 of 68 resistors to further o ptimize stability and settling time perform - ance. the ad5560 has thr ee compensation modes: s afe mode, a utocomp ensation mode , and m anual compensation mode, all of which are described in more detail in the force amplifier stability section . the range of suggested compensation capacitors allows optimum performance for any capacitive load from 0 pf to 160 f using one of the modes previously listed. although there are four compensation input pins and five feed - forward capacitor i nputs pins, all capacitor inputs may be used only if the user intend s to drive large variations of dut load capacitances. if the dut load capacitance is known and does not change for all combinations of voltage rang es and test conditions, then it i s possib le only one set of c c x and c f x capacitors may be required. table 8 . suggested compensation capacitor selection capacitor value c c0 100 pf c c1 100 pf c c2 330 pf c c3 3.3 nf c f0 4.7 nf c f1 22 nf c f2 100 nf c f 3 470 nf c f4 2.2 f the voltage range for the c c x and c f x pins is the same as the voltage range expected on force ; therefore , choice of capa - citors should take this into account. c f x cap acitor s can have 10% tolerance ; this extra variation directly affect s settling times , especially when measur ing current in the low current ranges. selection of c c x should be at 5% tolerance. c urrent range s election integrated thin film resistors minimize external components and allow easy selection of current ranges from 5 a to 25 ma . using external current sense resistors, two higher current ranges are possible : extforce1 can drive currents up to 1.2 a, while extforce2 is designed to drive currents up to 500 ma. the voltage drop across the selected sense resist or is 500 mv when f ull - scale current is flowing through it. the measure current amplifier has two gain settings, 10 and 20. the two gain settings allow users to achieve the quoted/ specified current ranges with large or small voltage swings. the gain of 20 setting is inten ded for use with a 5 v reference , and the gain of 10 setting is for use with a 2.5 v reference. both combinations ensure the specified current ranges. other vref/gain setting combinations should only be used to achieve smaller current ranges. attempting t o achieve greater current ranges than the specified ranges is outside the intended operation of the ad5560. the maximum guaranteed voltage across r sense is 0.64 v (gain of 20) or 0.7 v (gain of 10) . high current ranges for c urrents in excess of 1200 ma, a gang mode is available whe reby multiple devices are ganged together for higher cur rents. there are two methods of g anging channels together ; these are discussed in the following two sections . master and slaves in force voltage (fv) mode all devices are placed in force voltage ( fv ) mode. one device acts as the master device and the other devices act as slaves. by connecting in this manner, any device can be configured as the master. here, the master _ out pin of the m aster device is connected to t he output of the force a mplifier , and it feeds the inputs of eac h s lave force amplifier (via the slave _ in pin ). all devices are con nected externally to the dut. for current to be shared equally, there must be good matching between each of the paths to the dut. settings for dps register 2 are m aster = 0x0000 , s lave = 0x0 4 00 . clamps should be disabled in the s lave devices. extmeasil sense master dps extmeasih1 sw5-a fin dac 1 sw5-a sw16 r sense local feedback sw5-b sw6 master out extforce1 extforce2 slave in r sense r sense dut dutgnd extmeasil sense slave dps 1 extmeasih1 sw5-a fin dac 1 20 or w 20 or w 20 or w sw5-a sw16 local feedback sw5-b sw6 master out extforce1 extforce2 slave in extmeasil sense slave dps 2 extmeasih1 sw5-a fin dac i sense amp v sense amp i sense amp v sense amp i sense amp v sense amp 1 sw5-a sw16 local feedback sw5-b sw6 master out extforce1 extforce2 slave in 07779-007 figure 54 . simplified block diagram of high current ganging mode ad5560 data sheet rev. d | page 32 of 68 master in fv mode, slaves in force current ( fi ) m ode t he master device is placed into fv mode , and all slave devices into force current ( fi ) mode. the measured current of the master device (master _ out) is applied to the in put of all slave devices (slave_ in) , and th e slaves act as followers . a ll channels work to share the current equally among all devices in the gang. because the slaves forc e current, matching the dut paths is not s o critical. settings for dps register 2 are m aster = 0x0200 , s lave = 0x0600 . clamps should be disabled in the s lave devices. extmeasil master dps extmeasih1 sw5-a fin dac measout buffer and gain i sense amp sense sw5-a sw16 sw5-b sw6 master out extforce1 extforce2 slave in extmeasil slave dps 1 extmeasih1 sw5-a fin dac measout buffer and gain i sense amp sense sw5-a sw16 sw5-b sw6 master out extforce1 extforce2 slave in extmeasil slave dps 2 extmeasih1 sw5-a fin dac measout buffer and gain i sense amp sense sw5-a sw16 sw5-b sw6 master out extforce1 extforce2 slave in dut dutgnd 20 20 20 07779-008 r sense r sense r sense figure 55 . simplified block diagram of gang mode, using an fv/fi combination t he extforce1 , extforce2 , or 25 ma ranges can be used for the gang mode. therefore , it is possible to gang devices to get a high voltage/high curren t combination, or a low voltage/high current combination. for example, ganging five 25 v/25 ma devices using the 25 ma range achieve s a 25 v/625 ma range, wh ereas five 15 v/200 ma devices using the extforce2 path can achieve a 15 v/1 a range. similarly, g anging four 3.5 v/1.2 a devices using the extforce1 path result s in a 3.5 v/4.8 a dps. ideal sequence for gang mo de use the following steps to bring devices into and out of gang m ode : 1. choose the master device and force 0 v out put , corres - ponding to zero current. 2. select s lave dps 1 and place it in slave mode (keep s laves in h i gh - z mode via sw - inh or hw_inh until ready to gang) . 3. s elect to gang in either current or voltage mode. 4. repeat step 2 and step 3 one at a time thr ough the chain of slaves . 5. l oad the required voltage to the m aster device . t he other devices copy either voltage or current as programmed. t o remove devices from the gang, the master device should be programmed to force 0 v out again . the procedure for re moving devices should be the reverse of step 1 through step 5 . note that this may not always be possible in practice ; therefore , it is also possible to gang and ungang while driving a load . j ust ensure that the slave devices are in h i gh - z mode while confi - guring them into the required range and gang setting . g ang mode extends only to the 25 ma range and the two high curr ent ranges, extforce1 and extforce2 . t herefore , whe re an accurate measurement is required at a low current, the user should remove slaves from the gang to move to the appropriate lower current range to make the measurement. similarly, slaves can be brought back into the gang if needed . compensation for gan g mode when ganging, the slave devices should be set to the fastest response. when sl ave s are in fi mode, the ad5560 force amp lifier over - rides other compensation settings to enforce c f x = 0, r z = 0 , and g m x 1. this is done internally to the f orce amplifier ; therefore , readback will not show that the signals inside the force amplifier ac tually change . system force/sense s witches system force/sense switches allow easy connection of a central or system parametric measurement unit ( pmu ) for calibration or a dditional measurement purposes. the s ystem device under test ground (s ys _dutgnd) switc h is shared with the guard /sys_dutgnd pin ( pin 43) . see the dps register 2 in table 19 for addressing details. d ata sheet ad5560 rev. d | page 33 of 68 die temperature sens or a nd thermal shutdown there are three types of temperature sensors in the ad5560. ? the fi rst is a temperature sensor available on the measo ut pin and expressed in voltage terms. nominally at 25c, this sensor reads 1.54 v . i t has a temp erature co efficient of 4.7 mv/c. this sensor is active during power - down mode. die temp = ( vmeasout (tsense ) ? 1.54)/0.0047 + 25c based on typical temperature sensor output voltage at 25c and output scaling factor. ? the second type of temperature sensor is related to the thermal shutdown feature in the device. here , there are sensors located in the middle of the enabled power stage, which are used to trip the thermal shutdown. the thermal shutdown feature sense s only the power stages , and the power stage that it senses is determined by the active stage. if ranges of < 25 ma are selected , the extforce1 sensor is m onitored . the extforce1 power stage itself is made up of three identical stages, but the thermal shutdown is activated by only one stage ( extforce 1b). similarly , the extforce2 stage is made up of two identical output stages, but the thermal shutdown can be activated b y only one stage ( extforce 2 a ). the thermal shutdown circuit monitors these sensors and , in the event of the die tem p erature exceeding the program - mable threshold temperature (100c , 110c, 120c, 130c (default)), the device protects itself by inhibiting the force a mplifier stage, clearing sw - inh in dps register 1 and flagging t he over temperature event via the open - drain tmpalm pin, which can be programmed to be either latched or unlatched. these temperature sensors can be read via the measout pin by selecting them in the d iagnostic register ( table 23, vptat lo w and vptat h i gh ) . they are expressed in voltage and to scale to temperature . t hey must be referred to the vtsd reference voltage levels ( see table 23) also available on measout. this set of sensors is not active in power - down mode. die temp _y = { ( v ptat _ x ? vtsd _ low )/[( vtsd _h i gh ? vtsd _lo w )/( temp_high C temp_low )] } + temp_low w here : x , y are (high, npn) and (low, pnp). temp _ low = ?273c. temp _ high = +130c. ? the third set of temp erature sensors is an array of thermal diodes scattered across the die. these d iodes allow the user to evaluate the temperature of different parts of the die and are of great use to determine the temperature gradients across the die and the temperature of the accurate portions of the die when the device is dissipating high power. for further details on the thermal array and locations, see the d iagnostic r egister section in table 23. these diodes can be muxed out onto the gpo pin. the diagnostic register (address 0x7) details the addressing and location of the diodes. these can be used for diagnostic purposes to determine the thermal gradients across the die and across a board containing many ad5560 devices. when selected, the anode of each diode is connected to gpo and the cathode to agnd. the ad5560 eva luation board uses the on semiconductor adt7461 temperature sensor for the purpose of analyzing the temperature at different points across the die. note that , when a t hermal shutdown occurs, as the f orce a mp lifier is inhibited or tristated, user interventi on is required to re activate the device. it is necessary to c lear the temperature alarm flag by issuing a read command of register addre ss 0x44 ( alarm status and c lear alarm status register , table 25) , and then issu ing a new write to the dps r egister 1 ( sw - inh = 1) to re enable the force amplifier. see also the thermal consider ations section. measure output (meas out) the measured dut voltage, current (voltage representation of dut current), k sense , or die temperature is available on measout with respect to agnd. the default measout range is the forced voltage range for voltage measure and current measure (nominally 12.81 v, depending on reference voltage and offset dac) and include s over range to allow for system error correction. the serial interface allows the user to select another measout range of ( 1.025 vref ) to agnd; this range is suitable for use with an adc with a sm aller input range . to allow for system error correction, there is additional gain for the force function . i f this overrange is used as intended, the output range on measout scale s accordingly. the measout line can be tri stated via the serial interface. when using low supply voltages, ensure that there is suf ficient headroom and footroom for the required force voltage range. v mid voltage the midcode voltage ( v mid ) is used in the measure current amplifier block to center the current ranges at about 0 a. this is required to ensure that the quoted current range s can be achieved when using offset dac settings other than the default. v mid corresponds to 0x8000 or the dac midcode value, that is, the middle of the voltage range set by the offset dac setting (see table 15 and figure 56) . v mid = 5.125 vref (32,768/2 16 ) ? (5.125 vref ( offset_dac_code /2 16 )) o r v mid = 5.125 vref ((32,768 ? offset dac )/2 16 ) ad5560 data sheet rev. d | page 34 of 68 v min is another inportant voltage level that is used in other parts of the circuit. when using a measout gain of 0.2, the v min level is used to scale the volta ge range ; therefore, when choosing supply rails, it is very important to ensure that there is sufficient footroom so that the v min level is not impinged on (the high voltage dac amplifiers used here require approximately 2 v footroom to av ss ). see the choosing av dd /av ss power supply rails section for more information . v min = ?5.125 vref ( offset _ dac _ code /2 16 ) table 9 . measout output ranges measout function gain1 = 0, measout gain = 1 transfer function output voltage range 1 offset dac = 0x0 offset dac = 0x8000 offset dac = 0xe000 m easure v olta ge (mv) v dut 0 v to 25.62 v 12 . 81 v ?22.42 v to +3.2 v measure current (mi) gain0 = 0 mi gain = 20 (i dut r sense 20) + v mid 0 v to 25.62 v 12.81 v ?22.42 v to +3.2 v gain0 = 1 mi gain = 10 (i dut r sense 10) + v mid 0 v to 12.81 v (v ref = 2.5 v) 6.4 v (v ref = 2.5 v) ?11.2 v to +1.6 v (v ref = 2.5 v) 1 vref = 5 v, unless otherwise noted. table 10. measout function gain1 = 1, measout gain = 0.2 transfer function output voltage range 1 , 2 measure voltage (mv) mv = 0.2 (v dut ? v min ) 0 v to 5.12 v (2.56 v cent ered around 2.56 v) (includes overrange) measure current (mi) gain0 = 0 m i gain = 20 (i dut r sense 20 0.2) + 0.5125 vref 0 v to 5.12 v (2.56 v centered around 2.56 v) (includes overrange) gain0 = 1 m i gain = 10 (i dut r sense 10 0.2) + 0.5 125 vref 1.28 v to 3.84 v (1.28 v, centered around 2.56 v) 0 v to 2.56 v (1.28 v, centered around 1.28 v) (v ref = 2.5 v) 1 vref = 5 v, unless otherwise noted. 2 the offset dac setting has no effect on the output voltage range. table 11. p ossible adcs and adc drivers f or use w ith ad5560 1 part no. resolution sample rate ch ann els ain range 2 interface adc driver multiplexer 3 package ad7685 16 250 ksps 1 0 to vref serial, spi ada4841 -x adg704, adg708 m s o p, lfcsp ad7686 16 500 ksps 1 0 to vref serial, spi ada4841 -x adg704, adg708 m s o p, lfcsp ad7693 16 500 ksps 1 ? vref to +vref serial, spi ada4841 - x, ada4941 -1 adg1404, adg1408, adg1204 m s o p, lfcsp ad7610 16 250 ksps 1 bipolar 10 v, bipolar 5 v, unipolar 10 v, unipolar 5 v serial, parallel ad8021 ad1404, adg1408, adg120 4 lfcsp, lqfp ad7655 16 1 msps 4 0 v to 5 v serial , spi ada4841 -x/ ad8021 lqfp, lfcsp 1 subset of the possibl e ad cs , adc drivers , and multiplexers suitable for use with the ad5560. visit http://www.analog.com for more options. 2 do not allow the measout output range to exceed the ain range of the adc . 3 for the purposes of sh aring adcs among multipl e dps channels, note that the multiplexer is not absolutely necessary because the ad5560 measout path has a tristate mode. d ata sheet ad5560 rev. d | page 35 of 68 att att 5r r 1k? 5r mi mv att att tri dac att 1k? 5r r osd dac in measure voltage measure current measout 5r notes 1. att: attenuation for external measout 0.20 for output voltage range 0v to 5.125v (with overrange) (vref = 5v). tri: tristate mode mv: measure voltage mi: measure current mi_gain: measure i gain selection mi_x10 mi_x20 internal measi high i sense amp r 10r r 10r 2r 2r - sense dutgnd v sense amp 5r 5r 5r 5r vref refgnd vmid = (vtop ? vbot)/2 vbot low voltage offset dac hv dac amp v min v mid v os = (1 + 2/8.25) (offset dac voltage) 8.25r 8.25r mi_gain vtop internal measi low 2r 2r 8.25r 2r 07779-009 figure 56 . mi, mv, and measout block showing gain settings and offset dac influence ad5560 data sheet rev. d | page 36 of 68 force amplifier stability there are three modes for configuring the force amplifier: safe mode, autocompensation mode, and manual compensation mode. manual compensation mode has high est priority, followed by safe mode, then autocompensation mode. safe mode selected through compensation register 1 (see table 20), this mode guarantees stability of the force amplifier under all conditions. where the load is unknown, this mode is useful but results in a slow response. this is the power-on default of the ad5560. autocompensation mode using this mode, the user inputs the c r and esr values, and the ad5560 decides the most appropriate compensation scheme for these load conditions. the compensation chosen is for an optimum tradeoff between ac response and stability. manual compensation mode this mode allows access to all of the internal programmable parameters to configure poles/ze ros, which affect the dynamic performance of the loop. thes e variables are outlined in table 12 and table 13. figure 57 shows more details of the force amplifier block. table 12. external variables name description min max c r dut capacitance with contributing esr 10 nf 160 f r c esr in series with c r 1 m 10 c d dut capacitance with negligible esr 100 pf 10 nf r d loading resistance at the dut ~2 infinity i r current range 5 a 1.2 a table 13. internal variables name description min max r z resistor in series with c c0 , which contributes a zero. 500 1.6 m r p resistor to 8 pf to contribute an additional pole 200 1 m c c0 :c c3 capacitors to ensure unconditional stability 100 pf 100 nf c f0 :c f4 capacitors to optimize ac performance into different c r , c d 4.7 nf 10 f g mx transconductance of force amplifier input stage 40 a/v 900 a/v dutgnd force sense v sense ? ? + + 1 c f0 4.7nf r z : 500 ? to 1.6m ? c f1 22nf c f2 100nf c f3 470nf c f4 2.2f r sense 2 r sense 1 ad5560 force voltage loop extforce1 extforce2 100k ? 25k ? 20 ? 200? 2k ? 20k? 100k ? 6k? 100pf 100pf 330pf 3.3nf c c0 c c1 c c2 c c3 force dac g m r p : 200 ? to 1m ? 8pf agnd + ? + ? c d c r r d r c 07779-010 figure 57. block diagram of a force amplifier loop d ata sheet ad5560 rev. d | page 37 of 68 poles and zeros in a typical system typical closed loop systems have one dominant pole in the feedback path, providing ? 20 db/decade gain roll off and 90 of phase shift so that the gain decreases to 0 db where there is a conservative 90 of phase margin. the ad5560 has compensation options to help cope wit h the various load conditions that a dps is presented with. m inimizing t he number of e xternal c ompensation c omponents note that , depending on the range of load conditions, not all external capacitors are required. c fx p ins t here are five external c fx pin s. all five pins are used in the autoc omp ensation mode to choose a suitable capacitor , depending on the load being driven. to reduce component count, it is possible to connect just one capacitor, for instance, c f2 to the c f2 , c f1 , and c f0 pins . there fore , when any of the small est three external cap acitor s are selected, the same p hysic al capacitor is used because it i s connected to all three pins. a disadvantage here is that the larger c f2 capacitor sh ould be bigger than optimal and may increase settling ti me of the whole circuit (particularly the measure current). c cx p ins to make the ad5560 stable with any unknown capacitor from 0 pf to 160 f, all four c c x capacitors are required. however, if the range of load is from 0 pf to 20 f, then c c 3 can be omitted . s imilarly, if the load range is from 0 pf to 2.2 f, then c c 2 and c c 3 c an be omitted. only c c0 is required in autocompensation mode. n ote that safe mode , w hich makes the device stable in any load from 0 pf to 160 f , simply switches in all of the four c cx capacitors. stability into 160 f is assured only if all four capacitors are present ; otherwise, the maximum capacitor for stability is reduced to 20 f, 2.2 f , or 220 nf , depending on ho w many capacitors are missing. extra poles and zero s in the ad5560 the effect of c c x c c 0 is switched o n at all times. c c 3 , c c 2 , and c c 1 can be con - nected in addition to c c 0 to slow down the f orce a mp lifier loop. in the 500 ma ran ge looking into a small load capacitor , with only c c 0 connected, the ac gain vs . phase response results in ~ 90 of phase m argin and a unity gain bandwidt h ( ugb ) of ~ 400 khz. the effect of c fx the output of the ad5560 passes through a sense resistor to the dut. coupled with the load capacitor, this sense resistor can act as a low - pass filter that adds phase shift and decreases phase margin (particularly in the low current ranges where the sense resistors are large). placing a capacitor in parallel with this sense resistor provides an ac feedforward path to the dut. therefore, at high frequen - cies, the dut is driven through the c fx capacitor rather t han through the sense resistor. note that each c f x output has an output impeda nce of about 3 . t his is very small compared to the sense resistors of the low current ranges but not so for the highest current ranges. there fore, the c fx capacitors are most effective in the low curren t ranges but are of lesser benefit in higher current ranges. as sh own in the force amp lifier diagram (see figure 57) , there is a pole at 1/( r sense [c fx + c r ] ) and a zero at 1/[ r sense c f x ]. therefore, the output impedance of each c fx output, at around 1 , limits the improvement availa ble by using the c f x capaci - tors. for a large load capacitance, there is still a pole at ? 1/[1 c r ] above which the phase improvement is lost. if there is also a cable resistance to the dut, or if c f x has significant esr, this should be added to the 1 to calculate the pole frequency. if c f x is chosen to be bigger than the load capacitance, it can dominate the settling time and slow down the settling of the whole circuit. also, it directly affects the time taken to measure a current ( r sense c f x ) . the effect of r z when the load capacitance is known, r z can be used to optim - ize the response of the ad5560. because the c fx buffers have some output impedance of about 1 , there is likely to be some a dditional resistance to the dut. t here can still be an output pole associated with this resistance and the load capacitance, c r , 1/ [r 0 c r ] ( where r 0 = the series/parallel combination of the sense resistor, the c fx output im pedance, the c f x capacitor esr , and the cable to dut ) . this is particularly significan t for larger load capacitances in any current range. by p rogram ming a zero into the loop response by setting r z (in series with c c 0 ), it is possible to cancel this pole. above the frequency 1/[c c 0 r z ], the series resistance and capacitance begin to look resistive rather than capacitive , and the 90 phase shift and 20 db/decade contributed by c c0 no longer appl y . note that , to c ancel the load pole with the r z zero , the lo ad pole must be known to exist. adding a zero to cancel a pole that does not exist causes an oscillation (perhaps the expected load capacitor is not present). also, it is recommended to avoid creating a zero frequency lower than the pole frequency ; instead , allow the zero frequency to be 2 or 3 higher than the calculated pole frequency. the effect of r p r p can be used to ensure circuit stability when a poor load capacitor with significant esr is present. above the frequency, 1/[c r r c ], the dut begins t o look resistive. the esr of the dut capacitor, r c , contrib utes a zero at this frequency. t he load cap acitor , c r , is counted on to stabilize the system when the user has cancelled the load pole with the r z zero . just as the absence of c r under these circum stances can cause oscillations, the presence of esr r c while nonzero r z is used can cause ad5560 data sheet rev. d | page 38 of 68 stability problems. this is most likely to be the case when there are both a large c r and large r c . the r p resistor is intended to solve this problem. again, it is p rudent not to cancel exact pole/zero cancellation with r z and instead allow the zero to be 2 to 3 the frequency of the pole. it is best to be very conservative when using r z to cancel the load pole . c hoos e a high zero frequency to avoid flat spots in th e gain curve that extend bandwidth , and be conservative when choosing r p to create a pole. aim to place the r z zero at 5 the exact cancellation frequency and the r p pole at around 2 the exact cancellation frequency. the best solution here is to avoid thi s complexity by using a high quality capacitor with low esr. compensation strateg ies ensuring stability into an unknown capacitor u p to a maximum value if the ad5560 has to be stable in a range of load capacitance from no load capacitance to an upper limi t, then select manual com pensation mode and , in compensation register 2 , set the parameters according to the maximum load capacitance listed in table 14. table 14 . suggested compensation settings for l oad capa - citance range of unknown value to some maximum value capacitor g m [1:0] r p [ 2:0] r z [2:0] c c [3:1] c f[2:0] min max 0 0.22 f 2 0 0 000 2 0 2.2 f 2 0 0 001 3 0 10 f 2 0 0 010 4 0 20 f 2 0 0 011 4 0 160 f 2 0 0 111 4 table 14 assumes that the c c x and c f x capacitor values are those suggested in table 8 . making a circuit stable over a range of load capacitances for no load capacitance or greater means that the circuit is over - c ompensated for small load capacitances , under compensated for hi gh load capacitances, or both. the previous choice settings, along with the suggested capacitor values , is a compromise between both. by compromising phase margin into the largest load capacito rs, the system bandwidth can be increased , which means better performance under load current transient condi - tions. the disadvantage is that there is more overshoot during a large dac step. to reduce this at the expense of settling time, it may be desirabl e to temporarily switch a capacitor range 5 or 10 larger before making a large dac step. optimizing p erformance for a k nown c apacitor u sing a utocompensation m ode the a uto co mp ensation mode decides what values of g m x , c cx c f x , r z , and r p should be chosen for good performance in a particular capacitor. both the capacitance and its esr need to be kn own. to avoid creating an oscillator, the capacitance shoul d not be over estimated and the esr should not be under esti - mated. use the following steps to dete rmine compensation settings when u s ing the m anual compensation register (this algorithm is what the auto co mpensation method is based upon): 1. use c r ( the load capacitance with a series esr ) and r c ( the esr of that load capacitance ) as inputs . 2. assume that c r has not been overestimated and that r c has not been underestimated. (although, when the esr r c is shown to have a frequency dependence , the lowest r c that occurs near the resonant frequency is probably a better guide. however, do not underestimate this esr). a. c c 0 is the suggested 100 pf . b. c fx c apacitor values are as suggested , and they extend up to 2.2 f (c f4 ) . for faster settling into small capacitive loads , include smaller c f x values such as c f3 and c f2 . if a capacitor is not included, then short the correspo nding c f x pin to one that is. c. there is approximately 1 of parasitic resistance, r c , from the ad5560 to the dut (for example, the cable) ; r c = 1 . 3. select g m[1:0] = 2, c c [3:1] = 000. thi s makes the input stage of the f orce amp lifier ; have g m x = 300 a/v ; deselect the c ompensation c apacitors , c c 1 , c c 2 , c c 3 , so that only c c 0 is active. 4. choose a c f [2:0] value from 0 to 4 to select the largest c f x capacitor that is smaller than c r . 5. if c r < 100 nf, then set r z[ 2:0] = 0, r p [2:0] = 0. this e nd s the algorithm. 6. calculate r 0 , the resistive impedance to the dut, using the following steps: a. calculate r s , the sense resistor , from the selected current range using r s = 0.5 v/i rang e . b. calculate r f , the output impedance , through the c f x capacitor, by using r f = 1.2 + ( esr of c fx cap acitor ) c. calculate r fm , a modified version of r f , which takes account of frequency dependent peaking , through the c f x buffers i nto a large capacitive load, by using r fm = r f /(1 + [2 ( c fx /2.2 f)]) that is, r fm is up to 3 smaller than r f , when the selected c fx capacitor is large compared to 2.2 f. then calculate r 0 = r c + ( r s ||r fm ) where r c takes its value from the assumptions in s tep 2. 7. if r c > (r 0 /5), then the esr is large enough to make the dut look resistive. choose r z [2:0] = 0, r p [2:0] = 0. this ends the algorithm 8. calculate the unity gain frequency ( fug ) , the ide al unity gain frequency of the f orce amp lifier , from fug = g m x /2c c 0 . using the previously sugge sted values ( g m[1:0] = 2 gives g m x = 300 a/v and c c0 = 100 pf) , fug calcul ates to 480 khz. 9. calculate f p , the load pole frequency , using f p = 1/(2r 0 c c 0 ). d ata sheet ad5560 rev. d | page 39 of 68 10. calculate f z , the esr zero frequency , using f z = 1/(2rccr). 11. if f p > fug, the load pole is above the bandwidth of the ad5560 . ignore it with r z [2:0] = 0, r p [2:0] = 0. this en ds the algorithm 12. if r c < (r 0 /25), then the esr is negligible. a ttempt to cancel the load pole with r z zero . choose an ideal zero frequency of 2 f p for some safety margin and then choose the r z [2:0] value that gives the closest fr equency on a logarithmic scale. this ends the algorithm 13. otherwise, this is a troublesome window in which a load pole and a load zero cant be ignore d . use the following steps: ? to can c el the load pole at f p , choose an ideal zero frequency of 6 f p (this is more conservative than the 2 f p suggested earlier, but there is more that can go wrong with miscalculation). then choose the r z [2:0] value that gives the closest zero to this ideal frequency of 6 f p on a logarithmic scale. ? to cancel the esr zero at f z , choose an ideal p ole frequency of 2 f z . ? then choose the r p [2:0] value that gives the closest pole to this ideal frequency of 2 f z on a logarithmic scale. this ends the algorithm adju sting the autoc omp ensation mode the a uto c omp ensation algorithm assumes that there is 1 of resistance (r c ) from the ad5560 to the dut. if a particular application has resistance that differs greatly from this, then it is likely that the autocompensation algorithm is non optimal. if using the autocompensation algorithm as a star t ing point, consider that overstating the c r capacitance and understating the esr r c is l ikely to give a faster response but could cause oscillations. understating c r and overstating r c is more likely to slow things down and reduce phase margin but not create an osci llator. i t is often advisable to err on the side of simplicity. rather than insert a pole and zero at similar frequencies, it may be better to add none at all. set r p [2:0] = r z [2:0] = 0 to push them beyond the ad5560 bandwidth. dealing with parallel l oad c ap acitor s in the event that the load capacitance consists of two parallel capacitors with different esrs, it is highly likely that the overall complex impedance at the unity gain bandwidth is dominated by the larger capacitor and its esr. assuming that t he smaller capacitor does not exist normally is a safer simplifying assump - tion. a mo re complex alternative is to calculate the overall imped ance at the expected unity gain bandwidth and use this to calculate an equivalent series c r and r c that have the same complex impedance at that particular frequency. dac levels this device contains all the dedicated dac levels necessary for operation: a 16- b it dac for the force amplifier, two 16- bit dacs for the clamp high and low levels, two 16- bit dacs for the com parat or high and low levels, a 16 - bit dac to set a programmable open sense volt age , and a 16- bit o ffset dac to bias or offset a number of dacs on chip (force, cll, clh, cpl, cph) . force and comparator dacs the architecture of the main force amplifier dac consists of a 16 - bit r - 2r dac, wh ereas the comparator dacs are resistor - string dacs followed by an output buffer amplifier. this resistor - string architecture guarantees dac monotonicity. the 16 - bit binary digital code loaded to the dac register determin es at what node on the string the voltage is tapped off before being fed to the output amplifier. the comparator dac is sim ilarly arranged. the f orce and c omparator dacs have a 25.62 v span , including over range to enable offset and gain errors to be cal ibrated out. the transfer function for these 16- bit dacs is dutgnd code dac offset vref code dac vref v out + ? ? ? ? ? ? ? ? ? ? ? ? ? = 16 16 2 _ _ 125 . 5 2 125 . 5 w here dac code is x 2 (see the offset and gain r egisters section ) . clamp dacs the architecture of the c lamp dac consists of a 16 - bit resisto r - strin g dac followed by an output buffer amplifier. this resisto r - string architecture guarantees dac monotonicity. the 16 - bit binary digital code loaded to the dac register determines at what node on the string the voltage is tapped off before being fed t o the output amplifier. the c lamp dacs have a 25.62 v span , in cluding over range , to enable offset and gain errors to be calibrated out. ad5560 data sheet rev. d | page 40 of 68 the transfer fu nction for these 16 - bit dacs is dutgnd code dac offset v code dac v vcll vclh ref ref + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 16 16 2 _ _ 125 . 5 2 125 . 5 , the transfer function for the clamp current va lue is gain amp mi r code dac v iclh icll sense ref _ _ 2 32768 125 . 5 , 16 ? ? ? ? ? ? ? ? ? = w here: r sense is the sense resistor . mi_amp_gain is the g ain of the mi amp ( either 10 or 20 ) . osd dac the osd dac is a 16 - bit dac function, again a resistor string dac guaranteeing monotonicity. the 16 - bit binary digital co de loaded to the dac register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. the osd function is used to program the voltage difference needed between the force and sense lines before the alarm cir cuit flags an error. the osd dac has a range of 0.62 v to 5 v. the transfer function is as follows: ? ? ? ? ? ? = 16 2 code dac vref v out (1) the offset dac does not affect the osd dac output range. dutgnd dac similarly, the dutgnd dac (dgs) is a 16 - bit dac and uses a resistor string dac to guarantee monotonicity. the 16 - bit binary digital code loaded to the dac register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. this function is used to program the voltage difference needed between the dutgnd and agnd lines before the alarm circuit flags an error. the dutgnd dac has a range of 0 v to 5 v. the transfer function for this 16 - bit dac is shown in equation 1. the offset dac does not affect the osd dac output rang e. offset dac in addition to the offset and gain trim, there is also a 16 - b it offset dac that offsets the output of each dac on chip. there - fore, depending on headroom available, the input to the f orce a mplifier can be arranged either symmetrical ly or asy mm etrical ly abo ut dutgnd but always within a voltage span of 25 v. so me extra gain is included to allow for system error correction using the m (gain) and c (offset) registers. the usable voltage range is ? 22 v to + 25 v. full scale loaded to the o ffset dac does not give a useful output voltage range because the output amplifiers are limi ted by available footroom. table 15 shows the effect of the o ffset dac on other dacs in th e device ( clamp, comparator, and fo rce dacs). table 15 . offset dac relationship with other dacs , v ref = 5 v offset dac code dac code 1 dac output voltage range 0 0 0.00 0 32, 768 12.81 0 65, 535 25.62 32, 768 0 ? 12.81 32, 76 8 32, 768 0.00 32, 768 65, 535 12.81 57, 344 0 ? 22.42 57, 344 32, 768 ? 9.61 57, 344 65, 535 3.20 65, 355 footroom l imitations 1 dac code shown for 16 - bit force dac. offset and gain r egisters each dac level contains independent offset and gain control registers that allow the user to digitally trim offset and gain. these registers give the user the ability to calibrate out errors in the complete signal chain ( including the dac ) using the internal m and c registers, which hold the correction fa ctors. the digital input transfer function for the dacs can be represented as x2 = [ x1 ( m + 1)/ 2 n ] + ( c C 2 n C 1 ) where: x2 is the data - word loaded to the resistor string dac. x1 is the 16 - bit data - word written to the dac input register. m is the code in the gain register (default code = 2 16 C 1) . n is the dac resolution ( n = 16) . c is the code in the offset register (default code = 2 15 ) . offset and gain registers for the force amplifier dac the force amplifier input (f in ) dac level contains independent o ffset and gain control registers that allow the user to digitally trim offset and gain. there is one set of registers for the force voltage range: x1, m, and c. offset and gain registers for the comparator dacs the c omparator dac levels contain independent offset and gain control registers that allow the user to digitally trim offset a nd gain. there are seven sets of registers consisting of a c ombi - nation of x1, m , and c , one set each for the five internal force current ranges and one set each for the two e xternal high current ranges. offset and gain registers for the clamp dacs the cl amp dac levels contain independent offset and gain control registers that allow the user to digitally trim offset and gain. o ne set of registers covers the v sense range, the five internal force current ranges , and the two external high current ranges. both clamp dac x1 registers and the ir associated o ffset and gain registers are 16 bit . d ata sheet ad5560 rev. d | page 41 of 68 reference selection the voltage applied to the vref pin determines the output voltage range and span applied to the force amplifier, clamp , and comparator inputs and the current ranges. this device can be used with a reference input ranging from 2 v to 5 v. however, for most applications , a reference input of 5 v is ab l e to meet all voltage ra nge requirements. the dac amplifier gain is 5 .125 , which gives a dac output span of 25 .625 v. the dacs have gain and offset registers that can be used to calibrate out system errors. in addition, the gain register can be used to reduce the dac output rang e to the desired force voltage range. using a 5 v reference and setting the m (gain) register to one - fourth scale or 0x4000 gives an output voltage span of 6.25 v. because the f orc e dac has 18 bits of resolution even with only one - fourth of the output vol tage span, it is still possible to achieve 16 - bit resolution in this 6.25 v range. the measure current amplifier has two gain settings, 10 and 20. the two gain settings all ow users to achieve the quoted/ speci - fied current ranges with large or small voltag e swings. the 20 gain setting is intended for use with a 5 v reference , and the 10 gain setting is for use with a 2.5 v reference. both combinations ensure the specified current ranges. other vref/gain setting combinations should be used only to achieve sm aller current ranges. see table 27 for suggested references for use with the ad5560. choosing av dd /av ss power supply rails as noted in the specifications section, the minimum supply variation acr oss the part is |av dd ? av ss | 16 v and 33 v, av dd 8 v, and av ss ? 5 v . for the ad5560 circuits to operate correctly, the supply rails must take into account not only the force vol t age range but also the internal dac minimum volt age level, as well as headroom /footroom . t he dac amplifier gains vref by 5.125, and the offset dac centers that range about some chosen point. because the dac minimum voltage (v min ) is used in other parts of the circuit (measout gain of 0.2), it is important that av ss be chosen based on the follow ing: av ss ?5.125 ( vref ( offset_dac_code /2 16 )) ? av ss _h eadroom ? v dutgnd ? ( r cable i load ) where: av ss _h eadroom is the 2.75 v headroom (includes the r sense voltage drop). v dutgnd is the voltage range anticipated at dutgnd. r cable is the cable/path resistance . i load is the maximum load current. when choosing av dd , remember to take into account the specified current ranges. t he m easure c urrent block has either a gain of 20 or 10 and must have sufficient headroom/ footroom to operate correctly. as the nominal , v rsense is 0.5 v for the full - scale specified current flowing for all ranges. if this is gai ned by 20, the measure current a mplifier output (internal node) voltage range is 10 v with full - scale current and the default o ffset dac setting . the m easure cu rrent block needs 2.25 v footroom/headroom for correct operation in addition to the 0.5 v v rsense . for simplicity, when v ref = 5 v, minimum |a v dd ? av ss | = 31.125 v (vref 5.125 + headroom + footroom) ; otherwis e , there can be unanticipated e ffects res ult ing from headroom / footroom issues. this does not take into account cable loss or dutgnd contributions. simil arly, when v ref = 2.5 v, minimum |a v dd ? av ss | = 18.3 v and , when v ref = 2 v, minimum |av dd ? av ss | = 16 v . the ad5560 is designed to settle f ast into large capacitive loads ; therefore, when slewing, the device draws 2 to 3 the current range from the av dd /av ss supplies. w hen supply rails are chosen , they should be capable of supplying each dps channel with sufficient current to slew. choosing hc av ss x and hcav dd x supply rails selection of hcav ss x and hcav dd x supplies is determined by the extforce1 and extforce2 output ranges. the supply rails chosen must take into account headroom and footroom, dutgnd voltage range, cable loss, supply tolerance , and v rsense . i f diodes are used in series with the hcav ss x and hcav dd x supplies pins (shown in figure 59) , the diode voltage drop should also be factored into the supply rail calculation. the ad5560 is designed to settle fa st into large capacitive loads in h igh current ranges ; therefore, when slewing, the device dra w s 2 to 3 the current range from the hcav ss x and hcav dd x supplies. w hen choosing supply rails, ensure that they are capable of supplying each dps channel wi th s ufficient current to slew. all output stages of the ad5560 are symmetrical; they can source and sink the rated current. s upply design/bypassing should account for this. power dissipation the max im u m power dissipation allowed in the extforce1 stage is 10 w, wh ereas in the extforce2 stage , it is 5 w. take c are to ensure that the device is adequately cooled to remove the heat. the quiescent current is ~ 0.8 w with an internal current range enabled and ~ 1 w with external current ranges, extforce1 or extforce2 , enabled. th is device is specified for performance up to 90c junction temperature (t j ) . ad5560 data sheet rev. d | page 42 of 68 package composition and max imum vertical force the exposed pad and leads of the tqfp package have a 100% tin finish. the exposed paddle is connected internally to av s s . the simulated maximum allowable force for a single lead is 0.18 lbs ; total allowable force for the package is 11.5 lbs. the quoted maximum force may cause permanent lead bending . other package failure (die, mo ld, board) may occur first at lower forces. slew rate control there are two methods of achieving different slew rates using the ad5560. one method is using the programmable slew rate feature that gives eight programmable rates. the second method is using the ramp feature and an external clock. pro grammable slew rate eight programmable modes of s lew r ates are available to choose from through the serial interface, enabling the user to choose different rates t o power up the dut. the different slew rates are achieved by variation in the internal compen sation of the f orce dac output amplifier. the slew rates available are 1.000 v/ s, 0.875 v/ s , 0.750 v/ s , 0.625 v/ s , 0.5 v/ s , 0.4375 v/ s, 0.35 v s , and 0.313 v/ s . ramp function included in the ad5560 is a ramp function that enables the user to apply a rising or falling voltage ramp to the dut. the user supplies a clock, rclk, to control the timing. this function is controlled via the serial interface and requires programming of a number of registers to determine the end value, the ramp size , and the c lock divider register to determine the update rate. the contents of the fin dac x 1 register are the ramp start value. the user must load the end code register and the step size register. the sign is now generated from the difference between the fin dac x 1 register and the end code ; then the step size value is added to or subtracted from fin dac x 1, calibrated and stored. the user must supply a clock to the rclk pin to load the new code to the dac. the output settle s in 1.2 s for a step of 10 mv with c dut in the lowest range of <0.2 f. while the output is settling, the next step is calculated to be ready for the next ramp clock . t he calibration engine is used here ; therefore, there is a calibration delay of 1. 2 s . the ramp timing is co ntrolled in two wa ys: by a user - supplied clock ( rclk ) and by a clock divider register . t his gives the user much flexibility over the frequency of the ramp steps. the ramp typically starts after (2 c lock d ivider + 2) clocks, although there can be a 1 clock delay due to th e asynchronous nature of rclk. the external clock can be a maximum of 833 khz when using clock divider = 1. faster rclk speeds can be used, but the fastest ramp rate is linked into the dac calibration engine. for slower ramp rates, an even slower rclk can be used. the step sizes are in multiples of 16 lsbs. i f the code previous to the end code is not a multiple of this step size, the last step is smaller. if the ramp function must be interrupted at any stage during the ramp, write the i nterrupt r amp comman d. the fin dac x1 stop s ramping at the current value and return s to normal operation. the fastest ramp rate is 0.775 v/ s (for a 5 v reference and an 833 k hz c lock using a 2032 lsb step size and divider = 1). the slowest ramp rate is 24 v/ s (for a 5 v r eference and an 833 khz c lock using a 16 lsb step size and divider = 255). even slower ramps can be achieved with slower sclk. the ramp continue s until any of the following occur s: ? it reaches the end code. ? an interrupt ramp is received from the user. ? if any enabled alarm triggers , t he ramp stop s to allow the user to service the activated alarm. while the device is in ramp mode, the only command that the inte rface accept s is an interrupt ramp . no other commands sho uld be wri tten to th e device while rampin g because they are ignor ed. d ata sheet ad5560 rev. d | page 43 of 68 no write new fin 1 dac v alue upd a te dac code? no yes no change ram p st art? new ram p yes change ste p size? select ram p size program clock divider change clock division? yes no yes no yes yes no write ram p end code ram p mode enable ram p calcul a te next dac code load dac do not load dac. re t ain previous v alue termin a te ram p ram p complete? interrupt ramp? alarm? return t o norma l mode 07779-0 1 1 figure 58 . flow chart for ramp function ad5560 data sheet rev. d | page 44 of 68 serial interface the ad5560 contains an spi - compatible interface operating at clock frequencies of up to 50 mhz. to minimize both the power cons umption of th e device and on - chip digital noise, the inter face powers up fully only when the device is being written to, that is, on the falling edge of sync . spi interface the serial interface is 2.5 v lvttl - compatible when operating from a 2.3 v to 3.6 v dv cc supply . it is controlled by the following four pins: ? sync (f rame synchronization input ) ? sdi (serial data input pin) ? sclk (c lock s data in and out of the device) ? sdo (s erial da ta output pin for data readback) spi write mode the ad5560 allows writing of data via the serial interface to every register directly accessible to the serial interface, which is all registers except the dac registers. the serial word is 24 bits long. the serial interface works with both a continuous and a burst (gated) serial clock. serial data appl ied to sdi is clocked into the ad5560 by clock pulses applie d to sclk. the first falling edge of sync starts the write cycle. at least 24 falling clock edges must be applied to sclk to clock i n 24 bits of data before sync is taken high again. the input register addressed is updated on the rising edge of sync . fo r another serial transfer to take place, sync must be taken low again. sdo outpu t the sdo output in the ad5560 is a weak/slow output driver. if using readback or the daisy - chain function, the frequency of sclk must be reduced so that sdo can operat e properly. the sclk frequency is dependent on the dv cc supply voltage used; see table 2 for details and the following example: max imum sclk = 12 mhz , then dv cc = 2.3 v to 2.7 v maximum sclk = 15 mhz, then dv cc = 2.7 v to 3.3 v maximum sclk = 20 mhz, then dv cc = 4.5 v to 5.5 v reset function reset is a level - sensitive input. bringing the reset line low resets the contents of all internal registers to their power - on reset state. the falling edge of reset initiates the reset process; busy goes low for the duration, returning high when the reset process is complete. this sequence takes 300 s max imum . do not write to the serial interface w hile busy is low handling a reset co mmand . when busy returns high, normal operation resumes , and the status of the reset pin is ignored until it goes low again. busy function busy is a digital open - drain output that ind icates the status of the ad5560. all writes drive the busy output low for some period of time ; however , e vents that use the calibration engine , such as all dac x 1 writes , drive it lower for a longer period of time while the calculations a re completed . for the dacs, the value of the internal data ( x 2) loaded to the dac data register is calculated each time the user writes new data to the corresponding x 1 r egister. during the calculation of x 2 , the busy output goes low a nd x2 writes are pipelined ; therefore , x2 writes can still be presented to the device while busy is still low ( see the register update rates section ). the dac outputs update immediately after busy goes high. writes to other registers must be handled differently and should either watch the busy pin or be timed. w hile busy is low, the user can continue wr iting new data to any control register , m register , o r c register but should not complete the writing process ( sync returning high) until the busy signal has returned high . busy also goes low during power - on reset , as well as when a low level is detected on the reset pin. busy writes to the s ystem control register, compensation register , alarm register , and diagnostic register ; m or c registers do not involve the calibration engine, th us speeding up writing to the devi ce. load function th e ad5560 device contains a function with which updates to mu ltiple devices can be synchronized using the load function. there is not a dedicated pin available for this f unction; however, either the cl en or hw_inh pin can be used as a load input (selection is made in the system control register , address 0x1 , bits[ 8 :7 ] ). when selected as the load function, the pin no longer operate s in it s previou s function (power - on default for each of these pins is a cl en or hw_inh function). the load function controls the following registers: ? 0x8 fin dac x2 register ? 0xd cll dac x2 register ? 0x10 clh dac x2 register ? 0x4 compe nsation register 1 ? 0x5 compensation register2 ? 0x2 dps register1 (only current ranges, bits [13: 11] ) there is, however, a n alternate method for updating and using the clen and hw_inh pins in their normal function. data sheet ad5560 rev. d | page 45 of 68 if bits[ 8 :7] of the syste m control register (address 0x1) are high, then the clen and hw_inh operate as normal, and the update wait s until busy goes high (this way multiple channels can still be synchronized by simply tying busy pins together ) . register update rate s as mentioned previously , the value of the x 2 register is calculated each time the user writes new data to the corresponding x 1 register. the calculation is performed by a three stage proc ess. the first two stages t ake 6 00 ns e ach , and the third stage takes 3 0 0 ns. when the write to one of the x 1 registers is complete , the calculation process begins . t he user is free to write to another register provided that the write operation does n o t finish until the first stage calculation is com plete, that is, 6 00 ns after the completion of the first write operation. ad5560 data sheet rev. d | page 46 of 68 control registers dps and dac addressi ng the serial word assignment consists of 24 b its , as shown in table 16. all write - to regist ers can be read back. there are some read - only registers (address 0x43 and address 0x44). dac x2 register s are not available for readback . a no operation (nop) command performs no function within the device. this code may be useful when performing a readb ack function where a change of dac or dps register is not required. table 16 . serial word assignment b23 [b22:b16] [b15:b0] r/ w address bits data bits table 17 . read or write register ad dressing address register default data bits, msb first 0x0 nop 0x0000 nop command; performs no operation . 0x1 system control register 0x0000 bit name function 15 14 tmp[1:0] thermal shutdown bits . tmp1, tmp0 allow the user to program the thermal sh ut down temperature of operation . tmp action 0 shutdown at a t j of 130c (power - on default) 1 shutdown at a t j of 120c 2 shutdown at a t j of 110c 3 shutdown at a t j of 100c 13 12 g ain [1:0] measout output range. the measout range defaults to the voltage force span for v oltage and current measurements ( this is 12.81 v ) , which includes some overrange to allow for error correction. the measout range can be reduced by using the gain bits. this allows for use of asymmetrical sup plies or for use of a smaller input range adc. measout gain settings do not translate the low voltage temperature sensor signal ( tsense ) . gain measout gain mi gain 0 1 20 1 1 10 2 0.2 20 3 0.2 10 to allow for syste m error correction, there is an additional gain of 0.125 for the force function if this error correction is used as intended ; then the output range on measout scales accordingly (s ee table 9 ) . 11 fingnd writing a 1 to fin gnd switches the positive input of the force amplifier to gnd; when 0, the input of the force amplifier is connected to the output of the force dac. 10 cpo write a 1 to the cpo bit to enable a simple window comparator function. in this mode, only one comparator output is avail able (cpoh/cpo). this provides two bits of information . t he compared value is either inside or outside the window and enables the user to bring only one line back to the controller per dps device. 9 pd this bit powers down the force amplifier block. note that the amplifier must be powered up but inhibited ( sw - inh or hw_inh ) , to meet leakage specifications. a 0 powers this block down (default). 8 7 load updates to registers listed in the following load f unction column do not occur until the active load pin is brought low (or in the case of load 3, until busy goes high). load load function 0 default operation, clen and hw_inh function normally . 1 the cl en pin is a load input . 2 the hw_inh pin is a load i nput . 3 the device senses the busy open - drain pin and doesn't update until that goes high. no load hardware pin. cl en and hw_inh function normally. 6:0 unused set to 0 . data sheet ad5560 rev. d | page 47 of 68 table 18. dps register 1 address default data bits, msb first 0x2 0x0000 bit name function 15 sw - inh this bit enables the force amplifier when high and disable s the amplifier when low. this bit is and d with the hw_ inh hardware inhibit pin. 14 reserved reserved, set to 0 . 13 i[2:0] current range addressing . these bits allow selection of the required current range. 12 11 i action 0 5 a current range . 1 25 a current range . 2 250 a current range . 3 2.5 ma current range . 4 25 ma current range . 5 external range 2 . 6 external range 1 . 7 reserved . 10 cmp[1:0] comparator f unction. cmp1 acts as a comparator output enable, wh ereas cmp0 selects between a compa ring dut current or voltage; by default , the comparators are high - z on power - on. 9 cmp action 0 comparator outputs high - z . 1 comparator outputs high - z . 2 compare dut current . 3 compare dut voltage . 8 me[3:0] bits me[3:0] allow se lection of the required measure mode, allowing the measout line to be disabled; connect to the temperature sensor or enable it for measurement. me3 is measout enable/disable; when high, measout is enabled, and me[2:0] can be used to preselect the measuring parameter. where a number of measout lines are connected together and passed to a common adc, this function can allow for much faster measurement time between channels because the slew time of the measurement buffer is reduced. for details on diagnostic f unctions, see address 0x7, the diagnostic register. 7 6 5 me[2:0] action 0 measout high - z . 1 connect measout to i sense . 2 connect measout to v sense . 3 connect measout to k sense . 4 connect measout to tsense . 5 connect measout to dutgnd sense . 6 connect measout to diagnostic functions: diag a (see address 0x7) . 7 connect measout to diagnostic functions : diag b (see address 0x7) . 4 clen clamp enable ; set high to enable the clamp; set low to disable the clamp. this bit is ord with the hardware clen pin. 3:0 unused set to 0 . ad5560 data sheet rev. d | page 48 of 68 table 19. dps register 2 address default data bits, msb first 0x3 0x0000 bit name function 15 sf0 system force and sense line addressing, sf0. bi t sf0 addresses each of the different combinations of switching the system force and sense lines to the force and sense pins at the dut. g uard high - z (bit 7) sfo sys_sense pin sys_force pin guard/ sys_dutgnd pin 0 0 open open guard 0 1 sense force guard 1 0 open open open 1 1 sense force dutgnd 14 13 12 sr[2:0] slew rate control, sr2, sr1, sr0. selects the slew rate for the main dac output amp. sr action 0 1 v/ s 1 0.875 v/s 2 0.75 v/s 3 0.62 v/s 4 0.5 v/s 5 0.43 v/s 6 0.35 v/s 7 0.3125 v/s 11 gpo general purpose output bit. the gpo bit can be used for any function , such as disconnecting the decoupling capacitor to help speed up low current testing. 10 9 slave, gangimode ganging multiple devices increases the current drive available. use these bits to enable selection of the ganging mode and place the device in slave or master mode. in default operation, each devi ce is a master (gang of one ). figure 54 shows how the dev ice is configured in this mode. slave action 0 master: master _ out = internally connect s to active extforce1 / extforce2 output 1 master: master _ out = mast er mi 2 slave fv to extforce1 / extforce2 connected internally to close the fvamp loop 3 slave fi 8 int10k setting this bit high allows the user to connect an internal sense short resistor of 10 k between the force and the sense lines (closes s w 11) . this resistor is actually made up of series 4 k resistor s followed by a 2 k switch and another 4 k resistor. there is a 10 k resistor that can be connected between the force and sense pins by use of sw11. this 10 k resistor is intended to mainta in a force/sense connection when a dut is not in place. it is not intended to be connected when measurements are being made because this defeats the purpose of the osd circuit in identifying an open circuit between force and sense. in addition, the sense p ath has a 2.5 k resistor in series; therefore, if the 10 k switch is closed, errors may become apparent when in high current ranges. 7 guard h igh -z set this bit high to h igh - z the guard a mplifier. this is required if using the guard/ sys_dutgnd pin in the sys_dutgnd function. 6:0 unused set to 0 . data sheet ad5560 rev. d | page 49 of 68 the ad5560 has three compensation modes. the power - on default mode is safemode enabled. this ensures that the device is stable into any load. use compensation register 1 to configure t he device for autocompensation, where the user inputs the cdut and esr bits , and the ad5560 chooses the most appropriate compensation scheme for these load conditions. table 20. compensation register 1 address default data bits, msb first 0x4 0x0000 bit name function 15 14 13 12 cdut[3:0] use these control bits to tell the device how much capacitive load there is so that the device can optimize the compensation used. do not overestimate cdut because this can cause oscillations. underestimating cdut gives suboptimal but stable performance . cdut cdut min cdut max 0 0 nf 50 nf 1 50 nf 83 nf 2 83 nf 138 nf 3 138 nf 229 nf 4 229 nf 380 nf 5 380 nf 630 nf 6 630 nf 1.1 f 7 1.1 f 1.7 f 8 1.7 f 2.9 f 9 2.9 f 4.8 f 10 4.8 f 7.9 f 11 7.9 f 13 f 12 13 f 22 f 13 22 f 36 f 14 36 f 60 f 15 60 f 160 f 11 10 9 8 esr[3:0] use these control bits to tell the device how much esr there is in ser ies with cdut so that the device can optimize the compensation used. do not underestimate esr because this can cause oscillations. overe stimating esr gives suboptimal but stable performance. esr esr min esr max 0 0 m 1 m 1 1 m 1.8 m 2 1.8 m 3.4 m 3 3.4 m 6.3 m 4 6.3 m 12 m 5 12 m 21 m 6 21 m 40 m 7 40 m 74 m 8 74 m 140 m 9 140 m 250 m 10 250 m 460 m 11 460 m 860 m 12 860 m 1500 m 13 1500 m 2900 m 14 2900 m 5400 m 15 6400 m 10, 000 m 7 safemode safemode = 0 overrides values in compensation register 1 to make the force amplifier stable under most load conditions. this mode i s useful if it i s unknown what the dps is driving, but it does result in an extremely slow respo nse. the d efault operation on power - on or reset is safemode . safemode settings are always g m[1:0] = 2, r p [2:0] = 0, r z [2:0] = 0, c c [3:1] = 111, c f [2:0] = 5 , and c c 0 = 1 . s et this bit high to enable auto compensation. 6:0 reserved set to 0 . ad5560 data sheet rev. d | page 50 of 68 table 21. compensation register 2 address default data bits, msb first 0x5 0x0110 bit name function 15 ma nual c ompensation the ad5560 can be manually configured to compensate the force a mplifier into a wide range of load conditions. when this bit is high, manu al compensation mode is active , and it overrides the settings of compensation register 1. readback wh en in manual compensation mode returns the compensation settings loaded to the force amplifier and loaded to this register. similarly, when in autocompensation m ode, readback of this register address returns the compensation settings of the force amplifier . however, readback of this register address when in safe mode does not reflect safemode settings. safemode settings are g m[1:0] = 2, r p [2:0] = 0 , r z [2:0] = 0, c c [3:1 ] = 111, c f [2:0] = 5 , and c c 0 = 1. 14 13 12 r z [2:0 ] set the value of r z to add a zero at the following frequencies. this calculation assumes that c c0 = 100 pf . r z r z x ( ) f z (hz) 0 1 500 3.2 m 1 1.6 k 1 m 2 5 k 320 k 3 16 k 100 k 4 50 k 32 k 5 160 k 10 k 6 500 k 3.2 k 7 1.6 m 1 k 11 10 9 r p [2:0] set the value of r p to add an additional p ole. there is an internal 8 pf capacitor to provide an rc filter, creating a pole at on e of the following frequencies. r p [2:0] r p () f p (hz) 0 1 200 100 m 1 675 29 m 2 2280 8.7 m 3 7700 2.6 m 4 26 k 760 k 5 88 k 220 k 6 296 k 67 k 7 1 m 20 k 8 7 g m[1:0] set the transconductance of the force amp lifiers input stage. the gain bandwidth (gbw) of the force voltage loop is equal to g m x /c c0 . the following values assume c c0 = 100 pf. g m x g m x (a/v) gbw (hz) 0 40 64 k 1 80 130 k 2 1 300 48 0 k (default) 3 9 00 1. 3 m 6 5 4 c f[2:0] these bits determine which feedforward capacitor c fx is switched in. c f x action 0 none 1 c f0 2 c f1 3 c f2 4 c f3 5 1 c f4 6 none 7 none 3 c c 3 connect c c 3 in series with 100 k 1 2 c c 2 connect c c 2 in series with 25 k 1 1 c c 1 connect c c 1 in series with 6 k 1 0 reserved 0 1 this item corresponds to a safemode setting ( safemode is the power - on d efault setting). data sheet ad5560 rev. d | page 51 of 68 register 0x6 allows the user to enable or disable any of the alarm flags that are not required. if disabled, that particular alarm no longer flags on the app ropriate open - drain pin; however, the alarm status is still available in both of the alarm status registers (address 0x43 and address 0x44). table 22 . alarm setup register address default data bits, msb first 0x6 0x0000 bit name function 15 latched tmpalm set this latch ed bit high to program the open - drain tmpalm alarm pin as a latched output; leave low for an unlatched alarm pin (default). 14 disable tmpalm set this bit high to disable the open - drain tmpalm alarm pin; leave low to leave enabled (default). 13 latched osalm set this latched bit high to program the osalm as a latched alarm on the open - drain kelalm pin; leave low for an unlatched alarm pin (default). 12 disable osalm set this bit high to disable the osalm alarm function flagging the open - drain kelalm pin; leave low to remain enab led (default). the disable grdalm , dutalm , and osalm alarm function s share one open - drain kelalm alarm pin. these bits allow user s to choose if they wish to have all or selected inform ation flagged to the a larm pin. 11 latched dutalm set this latched bit high to program the dutalm as a latched alarm on the open - drain kelalm pin; leave low for an unlatched alarm pin (default). 1 0 disable dutalm set this bit high to disable the dutalm alarm function fla gging the open - drain kelalm pin. leave low to leave enabled (default). the disable grdalm , dut alm , and osalm alarm function s share one open drain kelalm alarm pin. these bits allow user s to choose if they wish to have all or any information flagged to the a larm pin. the dutgnd pin has a 50 a pull - up to allow for detection of an error in the dutgnd path. setting this bit high also disables the 50 a pull - up. 9 latched clalm set this latched bit high to program the open - drain clalm clamp alarm pin as a latched output; leave low for an unlatched alarm pin (default). 8 disable clalm set this bit high to disable the open drain clalm alarm pin; leave low to leave enabled (default). 7 latched grdalm set this latched bit high to program the grdalm as a latched alarm on the open - drain kelalm pin; l eave low for an unlatched alarm pin (default). 6 disable grdalm set this bit high to disable the grdalm a larm function flagging the open - drain kelalm pin; leave low to leave enabled (default). the disable grdalm , dutalm and osalm alarm function s share one open - drain kelalm alarm pin. these bits allow user s to choose if they wish to have all or any information flagged to the kelalm alarm pin. 5:0 unused set to 0 . ad5560 data sheet rev. d | page 52 of 68 table 23 . diagnostic register address default data bits, msb first 0x7 0x0000 bit name function 15 14 13 12 diag s elect[3:0] diag select selects the set of diagnostic signals that can be made available on measout. first, use measout addressing (dps register 1) to select either the diag a or the diag b node to b e made available on measout. diag select selected measure block diag a diag b 0:3 disabled disabled disabled 4 force amplifier disabled disabled 5 extforce1a extforce2a 6 finp finm 7 output 2.5 ma output 25 ma 8 measu re block vptat low vptat high 9 vtsd low (ref v for ?273c ) vtsd high (r ef v for +130c ) 10 mi vmid code 11 mv vmin code 12 dac block force dac vos dac 13 cll dac clh dac 14 cpl dac cph dac 15 osd dac dgs dac vptat low/vptat high are temperature sensor devices in the middle of the enabled power stage , which gives a voltage level that can be mapped back to the vtsd low and vtsd high reference points to get a temperature value. these sensors are used in the thermal shutdown feature. see the die temperature sensor a nd thermal shutdown section. vmid c ode is the midscale voltage of the dacs ; the offset dac has a direct effect on this voltage level. vmin c ode is the zero - scale voltage of the dacs ; again the offset dac has a direct eff ect. 11 10 9 8 7 tsense s elect[3:0] the following codes allow selection of one of three sets of eight thermal diodes. the d+ of the selected thermal diode is available on the gpo pin ; the d? is on the agnd. thes e thermal diodes are located across the d ie, in the cool p arts and in the power stages. d iodes [ 16:23 ] are located in the force amplifier npns (power output devices for supplying current). similarly, d iodes [ 24:31 ] are located in the force amplifier pnp devices (output devices for sinking current ). tsense select selected thermal block connected sensor 0:7 n/a normal gpo operation no sensor connected 8 cool block cool end of high current drivers, hot side of digital block 9 25 ma output stage 10 hottest part of sensitive measurement circuitry and cool part of force amplifier 11 coolest end of force amplifier block 12 coolest end of dacs 13 beside tsense available on measout 14 hottest part of dacs 15 cool side of digital block 16 force am plifier pnps 1a - 1 17 1a - 2 18 2a (similar location to vptat low for extforce2 range) 19 1b - 1 (similar location to vptat low for extforce1 range) 20 1b - 2 21 2b 22 1c - 1 23 1c - 2 data sheet ad5560 rev. d | page 53 of 68 address default data bits, msb first 0x7 0x0000 bit name function 24 force amplifier npns 1 a- 1 25 1a - 2 26 2a (similar location to vptat high for extforce2 range) 27 1b- 1 (similar location to vptat high for extforce1 range) 28 1b - 2 29 2b 30 1c - 1 31 1c - 2 6 5 test force amp[1:0] these register bits allo w disabling of stages of the force amplifier. th ey can be used to ensure connectivity in each parallel stage. the enabled stage depends also on which current range is selected. current range test force amplifier enabled stage extforce1 0 all sta ges extforce1 1 extforce1c extforce1 2 extforce1b extforce1 3 extforce1a extforce2 0 all stages extforce2 1 reserved extforce2 2 extforce2b extforce2 3 extforce2a 4:0 reserved set to 0 . ad5560 data sheet rev. d | page 54 of 68 table 24. other registers address register default data bits, msb first 0x8 fin dac x1 0x8000 x 1 dac register; d15 to d0, msb first . 0x9 fin dac m 0xffff m register; d15 to d0, msb first . 0xa fin dac c 0x8000 c register; d15 to d0, msb first . 0xb o ffset d ac x 0x8000 d15 to d0 . 0xc osd dac x 0x1fff d15 to d0 . 0xd cll dac x1 0x0000 d15 to d0 ; t he low clamp level can only be negative; the msb is always 0 to ensure this . 0xe cll dac m 0xffff d15 to d0 . 0xf cll dac c 0x8000 d15 to d0 . 0x10 clh dac x1 0xfff f d15 to d0; th e high clamp level can only be positive; the msb is always 1 to ensure this . 0x11 clh dac m 0xffff d15 to d0 . 0x12 clh dac c 0x8000 d15 to d0 . 0x13 cpl dac x1 5 a r ange 0x0000 d15 to d0 . 0x14 cpl dac m 5 a range 0xffff d15 to d0 . 0x15 cpl dac c 5 a range 0x8000 d15 to d0 . 0x16 cpl dac x1 25 a range 0x0000 d15 to d0 . 0x17 cpl dac m 25 a range 0xffff d15 to d0 . 0x18 cpl dac c 25 a range 0x800 0 d15 to d0 . 0x19 cpl dac x1 250 a range 0x0000 d15 to d0 . 0x1a cpl dac m 250 a range 0xffff d15 to d0 . 0x1b cpl dac c 250 a range 0x8000 d15 to d0 . 0x1c cpl dac x1 2.5 ma range 0x0000 d15 to d0 . 0x1d cpl dac m 2.5 ma range 0xffff d15 to d0 . 0x1e cpl dac c 2.5 ma range 0x8000 d15 to d0 . 0x1f cpl dac x1 25 ma range 0x0000 d15 to d0 . 0x20 cpl dac m 25 ma range 0xffff d15 to d0 . 0x21 cpl dac c 25 ma range 0x8000 d15 to d0 . 0x22 cpl dac x1 ext r ange 2 0x0000 d15 to d0 . 0x23 cpl dac m ext r ange 2 0 xffff d15 to d0 . 0x24 cpl dac c ext r ange 2 0x8000 d15 to d0 . 0x25 cpl dac x1 ext r ange 1 0x0000 d15 to d0 . 0x26 cpl dac m ext r ange 1 0xffff d15 to d0 . 0x27 cpl dac c ext r ange 1 0x8000 d15 to d0 . 0x28 cph dac x 1 5 a range 0xffff d15 to d0 . 0x29 cph dac m 5 a range 0xffff d15 to d0 . 0x2a cph dac c 5 a range 0x8000 d15 to d0 . 0x2b cph dac x1 25 a range 0xffff d15 to d0 . 0x2c cph dac m 25 ma range 0xffff d15 to d0 . 0x2d cph dac c 25 a range 0x80 00 d15 to d0 . 0x2e cph dac x1 250 a range 0xffff d15 to d0 . 0x2f cph dac m 250 a range 0xffff d15 to d0 . 0x30 cph dac c 250 a range 0x8000 d15 to d0 . 0x31 cph dac x1 2.5 ma range 0x0000 d15 to d0 . 0x32 cph dac m 2.5 ma range 0xffff d15 to d0 . 0x33 cph dac c 2.5 ma range 0x8000 d15 to d0 . 0x34 cph dac x1 25 ma range 0xffff d15 to d0 . 0x35 cph dac m 25 ma range 0xffff d15 to d0 . 0x36 cph dac c 25 ma range 0x8000 d15 to d0 . 0x37 cph dac x1 ext r ange 2 0xffff d15 to d0 . 0x38 cph dac m ext ra nge 2 0xffff d15 to d0 . 0x39 cph dac c ext r ange 2 0x8000 d15 to d0 . 0x3a cph dac x1 ext r ange 1 0xffff d15 to d0 . 0x3b cph dac m ext r ange 1 0xffff d15 to d0 . data sheet ad5560 rev. d | page 55 of 68 address register default data bits, msb first 0x3c cph dac c ext r ange 1 0x8000 d15 to d0 . 0x3d dgs dac 0x3333 d15 to d0 dutgnd sense dac , 0 v to 5 v range . 0x3e ramp end code 0x0000 d15 to d0 ; this is the ramp end code. the ramp start code is the code that is in the fin dac register . 0x3f ramp step size 0x0001 0000 0000 d6 to d0 . d6:d0 set the ramp step size in increments of 16 lsb per code, with a 5 v reference, 16 lsb = 6.1 mv . for example, 000 0000 = 16 lsbs (6.1 mv) step 000 0001 = 16 lsbs (6.1 mv) step 111 1111 = 2032 lsbs (775 mv) step . 0x40 rclk divider 0x0001 0000 0000 d7 to d0 . d7:d0 set the rclk d ivider . 0000 0000 = 1 0000 0001 = 1 0000 0010 = 2 0000 0011 = 3 1111 1111 = 255 0x41 enable ramp 0x0000 0xffff to enable . 0x42 interrupt ramp 0x0000 0x0000 to interrupt . ad5560 data sheet rev. d | page 56 of 68 table 25. alarm status and clear alarm status register address register defaul t data bits, msb first 0x43 alarm status 0x0000 this register is a read - only register providing information on the status of the alarm functions and the comparator outputs. bit name function 15 ltmpalm latched temperature alarm bit ; if low, this bit indicates that an alarm event has occurred . 14 tmpalm unlatched alarm bit; if low, these bit indicates that an alarm event is still present . 13 losalm latched open - sense alarm bit ; if low, indicates that an alarm event has occurred . 12 osalm unlatched open - sense a larm bit; if low, indicates that an alarm event is still present . 11 ldutalm la tched dutgnd kelvin sense alarm ; if low, indicates that an alarm event has occurred . 10 dutalm unlatched dutgnd kelvin sense alarm ; if low, indicates that an alarm event is still present . 9 lclalm latched c lamp alarm ; if low, indicates that an alarm event has occurred . 8 clalm unlatched c lamp alarm ; if low, indicates that an alarm event is still present . 7 lgrdalm latched g uard alarm ; if low, indicates that an alarm event has occurred . 6 grdalm unlatched g uard alarm ; if low, indicates that an alarm event is still present . 5 cpol comparator output low condition a s per the comparator output pin . 4 cpoh comparator output high condition a s per the comparator output pin . 3:0 unused must be zeros . 0x 44 alarm status and clear alarm 0x0000 this register is a read - only register providing information on the status of the alarm functions and the comparator outputs. reading this register also automatically clears any latched alarm pins or bits. bit nam e function 15 ltmpalm latched temperature alarm bit ; if low, this bit indicates that an alarm event has occurred . 14 tmpalm unlatched alarm bit ; if low, these bit indicates that an alarm event is still present . 13 losalm latched open - sense alarm bit ; if low, indicates that an alarm event has occurred . 12 osalm unlatched open - sense alarm bit ; if low, indicates that an alarm event is still present . 11 ld utalm latched dutgnd kelvin sense alarm ; if low, indicates that an alarm event has occurred . 10 dutalm u nlatched dutgnd kelvin sense alarm ; if low, indicates that an alarm event is still present . 9 lclalm latc hed clamp alarm ; if low, indicates that an alarm event has occurred . 8 clalm unlatched clamp alarm ; if low, indicates that an alarm event is still present . 7 lgrdalm latched guard alarm ; if low, indicates that an alarm event has occurred . 6 grdalm unlatched guard alarm ; if low, indicates that an alarm event is still present . 5 cpol comparator output low condition as per the comparator output pin . 4 cpoh comparator output high conditio n as per the comparator output pin . 3:0 unused must be zeros . 0x45 cp l dac x1 0x 0000 d15 to d0 . 0x46 cpl dac m 0xffff d15 to d0 . 0x47 cpl dac c 0x8000 d15 to d0 . 0x48 cph dac x1 0x ffff d15 to d0 . 0x49 cph dac m 0xffff d15 to d0 . 0x4a cph dac c 0x 8000 d15 to d0 . 0x4b to 0x7f reserved reserved . data sheet ad5560 rev. d | page 57 of 68 readback mode the ad5560 allows data readback via the serial interface from every register directly accessible to the serial interface, which is all registers except the dac register (x2 calibrated regi ster). t o read back contents of a register, it is necessary to write a 1 to the r / w bit , address the appropriate register , and fill the data bits with all zeros. after the write command has been written, data from the selected register i s loaded to the internal shift register and is available on the sdo pin during the next spi operation. address 0x43 and address 0x44 are the only registers that are read only . the read function gives the user details of the a larm s tatus and the comparator output result. alarm flags on latched a larm pins (pin 1, pin 2, pin 3 ) and bit s are cleared after a read command of register 0x44 (alarm status and clear alarm register (see table 25) ) . sclk frequency for readback do es not operate at the full speed of the spi interface. see the timing characteristics section for further details. dac readback the dac x1, dac m , and dac c registers are available to read back via the serial interface. access to th e calibrated x 2 register is not available. power - on default du ring power - on, the power - on state machine resets all inte rnal re gisters to their default values , and busy goes low. a rising edge on busy indicates that the power - on event is complete and that the interface is enabled. the reset pin has no function in the power - on event. during power - on, all dac x 1 registers corresponding to 0 v are cleared ; the calibration register d efault corresponds to m at full scale and to c at zero scale. the default condition s of the dps and the system control registers are as shown in the relevant tables ( see table 17 through table 26) . during a reset function , all registers are reset to the power - on default. ad5560 data sheet rev. d | page 58 of 68 table 26. ad5560 truth table of switches 1 reg bit name bit sw1 sw2 sw3 sw4 sw7 sw13 sw14 sw15 sw5 sw6 sw8 sw9 sw11 sw16 system control register gain 0, gain1 x x x x x x x x x x x x x x fingnd 0 b x x x x x x x x x x x x x 1 a x x x x x x x x x x x x x cpo x x x x x x x x x x x x x x pd 2 , 3 x x x x x x x x x x x x x on dps register 1 sw - inh 2 0 4 x c x x x x x x x x x x x x 1 5 x a x x x x x x x x x x x x i2, i1, i0 000 x x x on on off off off x x x x x x 001 x x x on on off off off x x x x x x 010 x x x on on off off off x x x x x x 011 x x x on on off off off x x x x x x 100 x x x on on off off off x x x x x x 101 x x x off off off on on x x x x x x 110 x x x off off on off on x x x x x x cmp1, cmp0 00 x x x x x x x x x x x x x x 01 x x x x x x x x x x x x x x 10 x x a x x x x x x x x x x x 11 x x b x x x x x x x x x x x me3, me2, me1, me0 000 x x x x x x x x x x x x x off 001 x x x x x x x x x x x x x on 010 x x x x x x x x x x x x x on 011 x x x x x x x x x x x x x on 100 x x x x x x x x x x x x x on 101 x x x x x x x x x x x x x on 110 x x x x x x x x x x x x x on 111 x x x x x x x x x x x x x on dps register 2 sf0 0 x x x x x x x x x x off off x x 1 x x x x x x x x x x on on x x slave, gangimode 00 6 b a x x x x x x a off x x x x 01 7 b a x x x x x x b off x x x x 10 8 c c x x x x x x off on x x x x 11 9 c b x x x x x x off on x x x x int10k 0 x x x x x x x x x x x x off x 1 x x x x x x x x x x x x on x hardware pins hw_inh 2 x c x x x x x x x x x x x x clen x x x x x x x x x x x x x x 1 x = dont care; the s witch is unaffected by the particular bit condition. 2 active low. 3 power - down mode; used for low power consumption. 4 force amplifier outputs tristate, low leakage mode; feedback made around amplifie r. 5 fv mode. 6 master: master_ out = internally connects to active extforce1 / extforce2 /25 ma output . 7 master: master_ out = master mi . 8 slave fv: extforce1 / extforce2 /25 ma connected internally to close the fvamp loop . 9 slave fi . data sheet ad5560 rev. d | page 59 of 68 using the hcav dd x and hcav ss x supplies the first set of power supplies, av dd and av ss , provide power to the dac levels and associated circuitry. t hey also supply the force amplifier stage for the low current ranges (ranges using internal sense resistors up to 25 ma max imum ). the second set of power supplies, hcav ss 1 and hcav dd 1 , are intended to be used to minimize power consumption in the ad5560 device for the extforce1 range (up to 1.2 a). s imilarly, the hcav ss 2 and hcav dd 2 supplies are used for the extforce2 range (up to 500 ma). these supplies must be less than or equal to the av dd and av ss supplies. when driving high currents at low voltages, power can be greatly minimized by ensuring that the supplies are at the lowest voltages. therefore, hcav ss x and hcav dd x can be switched externally to different power rails as required by the set voltage range. however, the design of the high current output stage means that these supplies always have to be at a hig her vo ltage t han the forced voltage , irrespective of the current range being used. therefore, depending on the level of supply switching, external diodes may be required in series with each of the hcav dd x and hcav ss x supplies , as shown in figure 59 . there are internal pull - up resistors between the supplies (see figure 59) . using diode s here allows a more flexible use of supplies and can minimize the amount of supply switching required. in the exam ple, the av dd and av ss supplies can support the high vo ltage needs, wh ereas the hcav dd x and hcav ss x supplies su pport the low voltage, higher current ranges. diode selection should take into account the current carrying requirements. supply selection for hcav dd x and hcav ss x supplies must allow for this extra voltage drop. power supply sequenc ing when th e supplies are connected to the ad5560 , it is importa nt that the agnd and dgnd pins be connected to the relevant ground plane before the positive or negative supplies are applied . in most applications, this is not an issue because the ground pins for the power supplies are connected to the ground pins of the ad5560 via ground planes. the av dd and av ss supplies must be applied to the device either before or at the same time as the hca v dd x and hcav ss x supplies, as indicated in table 3 . there are no known supply sequences surrounding the dv cc supply, although it is recommended that it be applied as indicated by the absolute maximum r atings (see table 3 ) . ad5560 33k? 1200ma range 500ma range force dut range 0v to +25v output range 0v to +25v internal r sense 0.5v at full current internal range select (5a, 25a, 250a, 2.5ma, 25ma) extforce1 dut range ?2v to +3v extforce2 dut range 0v to +6v allow 0.5v for ext r sense output range ?2.5v to +3.5v 2. highest current range 1. low current, high voltage 3. midcurrent range output range ?0.2v to +6.5v allow 0.5v for ext r sense + 10f + 0.1f 10f 0.1f hcav dd 2 = +9v hcav ss 2 = ?5v hcav dd 1 = +6v hcav ss 1 = ?5v + + + 10f + 0.1f 10f 0.1f + + av dd = +28v av ss = ?5v + 10f + 0.1f dv cc = 3v/5v + 0.1f 10f 0.1f + + 33k? 100k? 100k? 07779-012 figure 59 . example of using the extra supply rails within the ad5560 to achieve multiple voltage/current ranges ad5560 data sheet rev. d | page 60 of 68 required e xternal c omponents the minimum required external co mponents are shown in the block diagram in figure 60 . decoupling is very dependent on the type of supplies used, the board layout , and the noise in the system. it is possible that less decoupling may be required as a result. a lthough there are four compensation input pins and five feedforward capacit or input pins, all capacitor inputs may be used only if the user intend s to drive large variations of dut load capacitances. if the dut load capacitance is known and doesnt change for all combinations of voltage ranges and test conditions, then it i s possible only one set of c c x and c f x is required. shared adc adc v ref av ss av dd vref dv cc kelalm clalm dv cc or other digital supply tmpalm reset r pullup dv cc or other digital supply r pullup measout c c0 c c1 c c2 c c3 extforce1 extforce2 cf4 cf3 cf2 cf1 dut 07779-013 extmeashi1 sense extmeashi2 r sense 2 r sense 1 extmeasil dutgnd force + 10f + 0.1f 10f 0.1f hcav dd2 hcav ss2 ref hcav dd1 hcav ss1 shared reference + + + 10f + 0.1f 10f 0.1f + + av dd av ss + 10f + 0.1f dv cc + 0.1f 10f 0.1f + + + 0.1f cf0 adc driver figure 60 . external components required for use with the dps table 27 . reference s suggested for use with the ad5560 1 part no. voltage (v) initial accuracy % ref out t empco (ppm/c max ) a/b grade ref output current (ma) supply voltage range (v) package adr431 2.5 0.04 10/3 30 4.5 to 18 msop, soic adr435 5 0.04 10/3 30 7 to 18 msop, soic adr441 2.5 0.04 10/3 10 3 to 18 msop, soic adr445 5 0.04 10/3 10 5.5 to 18 msop, soic 1 subset of the possible references su itable for use with the ad 5560. see www.analog.com/references for more options. data sheet ad5560 rev. d | page 61 of 68 power supply decoupling in any circuit where accuracy is important, careful consid - eration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5560 is mo unted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5560 is in a system where multiple devices require an agnd - to - dgnd connection, the connection should be made at one point on ly. the star ground point should be established as close as possible to the device. t he dgnd connection in the ad5560 should be treated as agnd and returned to the agn d plane . for more detail on decoupling for mixed signal applications, refer to analog devices tutorial mt 031 . for supplies with multiple pins (av ss , av dd , d v cc ) , it is recommended to tie these pins together and to decouple each supply once. the ad5560 should have ample supply decoupling of 10 f in parallel with 0.1 f on each supply located as close to the part as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and effective seri es inductance (es l ), such as the common ceramic capaci - tors that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. digital lines running unde r the device should be avoided because thes e couple noise onto the device. the analog ground plane should be allowed to run under the ad5560 to avoid noise coupling . the power supply lines of the ad5560 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching digital signals should be shielded with digital ground to avoid radiating no ise to other parts of the board and should never be run near the reference inputs. it is essential to minimize noise on all vref lines. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through out the board. as is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. also note that the exposed paddle of the ad5560 is internally connected to the negative supply av ss . ad5560 data sheet rev. d | page 62 of 68 applications informa tion thermal consider ations table 28. thermal resistance for tqfp_ep 1 cooling airflow (lfpm) ja 2 jc (uniform) 3 jc (local) 4 ideal tim 6 jc (local) w/tim 6 jcp w/tim 5 unit no heat sink 0 39 n / a c/w 200 37.2 c/w 500 35.7 c/w heat sink 7 0 12.2 n / a c/w 200 11.1 1.0 2.8 4.91 c/w 500 9.5 c/w cold plate 8 n/a n/a 1.0 2.8 4.91 7.5 c/w 1 all numbers are simulated and assume a jedec 4 - layer test board. 2 ja is the thermal resistance from hottest junction to ambient air. 3 jc (uniform) is the thermal resistance from junction to the package top, assuming total power i s uniformly distributed. 4 jc (local) is the thermal resistance from junction to the center of package top, assuming total power = 8.5 w (1 w uniformly distributed, 7.5 w in power stages local heating) . 5 jcp is the thermal resistance from hottest juncti on to infinite cold plate with consideration of thermal interface material (tim). 6 ideal tim is assuming top of package in perfect contact with an infinite cold plate. w/tim is assuming tim is 0.5 mm thick , with thermal conductivity of 2.56 w/m/k. 7 heat sink with a rated performance of ca ~5.3 c/w under forced convection, gives ~t j = 111c at 5 00 lfm. thermal performance of the package depends on the heat sink and environmental conditions. 8 attached in finite cold plate should be 26 c to maintain t j < 9 0 c , giv en total power = 8.5 w . thermal performance of the package depends on the heat sink and environmental conditions . 9 to estimate junction temperature, the following equations can be used: t j = t a mb + ja power t j = t cold plat e + j cp power t j = t top + jc power table 29. thermal resistance for flip chip bga 1 cooling airflow (lfpm) ja 2 jc (uniform) 3 jc (local) 4 ideal tim 6 jc (local) w/tim 6 jcp 5 w/tim unit no heat sink 0 40.8 n / a c/w 200 38.1 c/w 500 36 c /w heat sink 8 0 18 n / a c/w 200 11.8 0.05 1.6 4.6 c/w 500 9 c/w cold plate 9 n/a n/a 0.05 1.6 4.6 6.5 c/w 1 all numbers are simulated and assume a jedec 4 - layer test board. 2 ja is the thermal resistance from hottest junction to ambient air. 3 jc (unifor m) i s the thermal resistance from junction to the package top, assuming total power is uniformly distributed. 4 jc (loca l) is the thermal resistance from junction to the center of package top, assuming total power = 8.5 w (1 w uniformly dis tributed, 7.5 w in power stages local heating) . 5 jcp is the thermal resistance from hottest junction to infinite cold plate with consideration of thermal interface material (tim). 6 ideal tim is assuming top of package in perfect contact with an infi nite cold plate. w/tim is assuming tim is 0.4 mm thick , with thermal conductivity of 3.57 w/m/k. 7 heat sink with a rated performance of ca ~4.9 c/w under forced convection, gives ~t j = 112 c at 5 00 lfm. thermal performance of the package depends on the h eat sink and environmental conditions. 8 attached in finite cold plate should be 30 c to maintain t j < 9 0 c , given total power = 8.5 w . thermal performance of the package depends on the heat sink and environmental conditions . 9 to estimate junction temper ature, the following equations can be used: t j = t a mb + ja power t j = t cold plat e + j cp power t j = t top + j c power data sheet ad5560 rev. d | page 63 of 68 temperature contour map on the t op of the p ackage tqfp_ep package due to localized heating, temperature at the top surface of the package has steep gradient. thus, the jc value i s highly dependent on where the case temperature is measured. figure 61 shows the top of the die temperature contour map for the tqfp_ep. bga package due to localized heating, temperature at the top surface of the package has steep gradient. thus , the jc value i s highly dependent on where the case temperature is measured. figure 62 shows the top of the die temperature contour map for the flip chip b ga. 07779-064 figure 61 . temperature contour map for 64- l ea d tqfp_ep 07779-065 figure 62 . temperature contour map for the flip chip bga ad5560 data sheet rev. d | page 64 of 68 outline dimensions compliant to jedec standards ms-026-acd-hu 10-19-2011-c 49 64 17 1 16 32 33 48 0.50 bsc lead pitch 12.20 12.00 sq 11.80 10.20 10.00 sq 9.80 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 7 3.5 0 0.15 0.05 0.08 coplanarity view a rotated 90 ccw 1.05 1.00 0.95 0.20 0.09 view a 1.20 max seating plane 0.75 0.60 0.45 1.00 ref 0.27 0.22 0.17 bottom view (pins up) 49 64 1 17 16 32 33 48 0.675 0.872 7.85 bsc 7.85 bsc 5.95 bsc 5.95 bsc top view (pins down) exposed pad figure 63. 64-lead thin quad flat package, exposed pad [tqfp_ep] (sv-64-3) dimensions shown in millimeters * compliant to jedec standards mo-225 with exception to package height. a b c d e f g 1 32 456789 bottom view h j detail a top view detail a 6.865 ref 5.720 ref 0.40 ref (die offset) 04-19-2012-b 8.10 8.00 sq 7.90 * 1.20 1.08 1.00 0.36 ref seating plane 0.39 0.34 0.29 0.81 0.76 0.71 0.50 0.45 0.40 ball diameter coplanarity 0.12 6.40 bsc sq 0.80 bsc 0.80 ref a1 ball corner a1 ball corner figure 64. 72-ball chip scale package ball grid array [csp_bga] (bc-72-2) dimensions shown in millimeters data sheet ad5560 rev. d | page 65 of 68 ordering guide model 1 temperature range 2 package description package option ad5560jsvuz t j = 25c to +90 o c 64- lead thin quad flat pack with exposed pad (tqfp_ep) sv -64-3 ad5560jsvuz - reel t j = 25c to +90 o c 64- lead thin quad flat pack with exposed pad (tqfp_ep) sv -64-3 ad5560jbcz t j = 25c to +90 o c 72- ball chip scale package ball grid array (csp - bga) bc -72-2 ad5560jbcz - reel t j = 25c to +90 o c 72- ball chip scale package ball grid array (csp - bga) bc -72-2 eval - ad5560ebuz evaluation kit 1 z = rohs compliant part. 2 t j = junction temperature. ad5560 data sheet rev. d | page 66 of 68 notes data sheet ad5560 rev. d | page 67 of 68 notes ad5560 data sheet rev. d | page 68 of 68 notes ? 2008 - 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07779 - 0- 8/12(d) |
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