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seite 1 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe specification customer : module no.: WG12232A-NGA-N approved by: ( for customer use only ) sales by approved by checked by prepared by issued date: contents 1.module classification information 2.precautions in use of lcd modules 3.general specification 4.absolute maximum ratings 5.electrical characteristics 6.optical characteristics 7.interface description free datasheet http:///
seite 2 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe 8.contour drawing & block diagram 9.function description 10.commands description 11.timing characteristics 12.quality assurance 13.relability 1.module classification information w g 1 2 2 3 2 a n g a n brand winstar display corporation display type hcharacter type, ggraphic type display font 122 x 32 dot model serials no. backlight type nwithout backlight bel, blue green del, green wel, white fccfl, white yled, yellow green aled, amber rled, red oled, orange gled, green lcd mode btn positive, gray tfstn negative ntn negative, gstn positive, gray ystn positive, yellow green mstn negative, blue ffstn positive lcd polarize type/ temperature range/ view direction areflective, n.t, 6:00 dreflective, n.t, 12:00 greflective, w. t, 6:00 jreflective, w. t, 12:00 btransflective, n.t,6:00 etransflective, n.t.12:00 htransflective, w.t,6:00 ktransflective, w.t,12:00 ctransmissive, n.t,6:00 ftransmissive, n.t,12:00 itransmissive, w. t, 6:00 ltransmissive, w.t,12:00 special code n : without negative voltage free datasheet http:///
seite 3 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe 2.precautions in use of lcd modules (1)avoid applying excessive shocks to the module or making any alterations or modifications to it. (2)dont make extra holes on the printed circuit bo ard, modify its shape or change the components of lcd module. (3)dont disassemble the lcm. (4)dont operate it above the absolute maximum rati ng. (5)dont drop, bend or twist lcm. (6)soldering: only to the i/o terminals. (7)storage: please storage in antistatic electrici ty container and clean environment. 3.general specification item dimension unit number of characters 122 x 32 dot module dimension 84.0 x 44.0 x 10.2(max) mm view area 60.0 x 18.0 mm active area 53.64 x 15.64 mm dot size 0.4 x 0.45 mm dot pitch 0.44 x 0.49 mm lcd type stn, positive, reflective , gray duty 1/32 view direction 6 oclock backlight type n/a 4.absolute maximum ratings free datasheet http:///
seite 4 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe item symbol min typ max unit operating temperature t op 0 +50 storage temperature t st 10 +60 input voltage v i 0 v dd v supply voltage for logic v dd 0 6.7 v supply voltage for lcd v dd v lcd 0 10 v supply voltage for lcd vee 5 v 5.electrical characteristics item symbol condition min typ max unit supply voltage for logic v dd v ss 4.75 5.0 5.25 v supply voltage for lcd v dd v 0 ta=0 ta=25 ta=+50 4.3 4.6 4.9 v v v input high volt. v ih 0.7v dd v dd v input low volt. v il 0 0.3v dd v output high volt. v oh 2.4 v output low volt. v ol 0.4 v supply current i dd 1.0 ma 6.optical characteristics item symbol condition min typ max unit (v) cr 2 R 10 105 deg view angle (h) cr 2 R 30 30 deg contrast ratio cr 3 response time t rise 100 150 ms free datasheet http:///
seite 5 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe t fall 100 150 ms definition of operation voltage (vop) defin ition of response time ( tr , tf ) driving voltage(v) intensity cr max 100 vop selected wave nonselected wave [positive type] cr = lon / loff intensity 90 100 tr 10 tf nonselected conition nonselected conition selected conition [positive type] conditions : operating voltage : vop viewing angle( ) : 0 0 frame frequency : 64 hz driving waveform : 1/n dut y , 1/a bias definition of viewing angle(cr 2) R RR R f = 180 = 90 = 0 = 270 b r l 7.interface description pin no. symbol level description 1 v ss 0v ground 2 v dd 5v power supply for logic 3 vo (variable) operating voltage for lcd 4 a0 h/l h : data l : instruction 5 cs1 h/l chip select signal for ic1 ( left 61*32 d ots ) active h 6 cs2 h/l chip select signal for ic2 ( right 61*32 dots ) active h 7 nc nc 8 nc nc free datasheet http:///
seite 6 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe 9 r/w h/l h : read ; l : write 10 db0 h/l data bus 11 db1 h/l data bus 12 db2 h/l data bus 13 db3 h/l data bus 14 db4 h/l data bus 15 db5 h/l data bus 16 db6 h/l data bus 17 db7 h/l data bus 18 res h/l h -> l: the lcm be reset 19 nc 20 nc 8.contour drawing &block diagram free datasheet http:///
seite 7 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe 9.function description block diagram free datasheet http:///
seite 8 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe this 12232 dots lcd module built in two sed 152 0 lsi controller. mpu interface the sed 1520 controller transfers data via 8bit bi direcional data buses (do to d7), it can fit any mpu if it corresponds to sed 1520 read and writ e timing characteristics. data transfer the sed1520 driver uses the a0, e and r/w signals t o transfer data between the system mpu and internal registers, the combinations used are g iven in the table below. a0 r/w function 1 1 read display data 1 0 write display data 0 1 read status 0 0 write to internal register (command) busy flag when the busy flag is logical 1, the sed1520 series is executing its internal operations. any command other than status read is rejected during t his time. the busy flag is output at pin d7 by the status read command. if an appropriate cycl e time (t cyc ) is given, this flag needs not be checked at the beginning of each command and, th erefore, the mpu processing capacity can greatly be enhanced. display start line and line count registers the contents of this register form a pointer to a l ine of data in display data ram corresponding to the first line of the display (com 0), and are set by the display start line command. column address counter the column address counter is a 7bit presentable c ounter that supplies the column address for d is pla y s ta rt line re gis te r l ine c ounte r d is pla y d a ta r a m ( d d r a m ) d is pla y da ta la tc h m pu inte rfa c e c olume a ddr e s s re gis te r c olume a ddr e s s c ounte r t o l c d pa ne l l c d drive c irc uit d 0 ~ d 7 r /w r e s a 0 , c s 1 , c s2 free datasheet http:///
seite 9 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe mpu access to the display data ram. see figure 1. the counter is incremented by one every time the driver receives a read or write disp lay data command. addresses above 50h are invalid, and the counter will not increment pas t this value. the contents of the column address counter are set with the set column address command. display data ram the display data ram stores the lcd display data, o n a 1bit per pixel basis. the relationship between display data, display address and the display is shown in figure 1 . page register the page register is a 2bit register that supplies the page address for mpu access to the display data ram. see figure 1. the contents of t he page register are set by the set page register command. free datasheet http:///
seite 10 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe figure 1. display data ram address the 122*32 dots display area is consisted 2 61*32,t he interface pin cs1 enable the left 61*32 ,cs2 enable the right 61*32 dots. page address data d0 d1 d2 d3 d4 d5 d6 d7 d2 d7 d4 d6 d5 d3 d1 d0 d2 d7 d4 d6 d5 d3 d1 d0 d2 d7 d4 d6 d5 d3 d1 d0 d1,d2= 0,0 0,1 1,0 1,1 c o l o u m a d d r e s s a d c d 0 = 0 d 0 = 1 s e g p i n 0 0 h 1 2 3 4 5 6 7 0 1 h 0 2 h 0 3 h 0 4 h 0 5 h 0 6 h line address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh com 0 common output com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 16 com 17 com 18 com 19 com 20 com 21 com 22 com 23 com 24 com 25 com 26 com 27 com 28 com 29 com 30 com 31 4 f h 4 e h 4 d h 4 f h 4 e h 4 d h 4 c h 4 b h 4 a h 4 9 h 0 2 h 0 1 h 0 0 h 8 0 7 9 7 8 6 1 6 0 5 9 3 c h 3 b h 3 a h sed1521 sed1520 free datasheet http:///
seite 11 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe 10.commands descriptions summary code command a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 function display on/off 0 1 0 1 0 1 0 1 1 1 0/1 turns display on or off. 1:on, 0:off display start line 0 1 0 1 1 0 display start address (0 to 31) specifies ram line corresponding to top line of display. set page address 0 1 0 1 0 1 1 1 0 page (0 to 3) sets display ram page in page address register. set column (segment) address 0 1 0 0 column address (0 to 79) sets display ram column address in column address register. read status 0 0 1 busy adc on/off reset 0 0 0 0 reads the following status: busy 1:busy 0:ready adc 1:cw output 0:ccw output on/off 1:display off 0: display on reset 1:being reset 0:normal write display data 1 1 0 write data writes data from data bus into display r am. read display data 1 0 1 read data reads data from display ram into data bus . select adc 0 1 0 1 0 1 0 0 0 0 0/1 0:cw output, 1:ccw output statis drive on/off 0 1 0 1 0 1 0 0 1 0 0/1 selects static driving operation. 1:static drive, 0:normal driving select duty 0 1 0 1 0 1 0 1 0 0 0/1 selects lcd duty cycle 1:1/32, 0:1/16 readmodifywrite 0 1 0 1 1 1 0 0 0 0 0 readmodifywrite on end 0 1 0 1 1 1 0 1 1 1 0 readmodifywrite off reset 0 1 0 1 1 1 0 0 0 1 0 software reset table 1 table 1 is the command table. the sed 1520 series identifies a data bus using a combination of a0 and r/w (rd or wr) signals. as the mpu trans lates a command in the internal timing only (independent from the external clock), its speed is very high. the busy check is usually not required. display on/off this command turns the display on and off. d=1: display on d=0: display off display start line this command specifies the line address shown in fi gure 1 and indicates the display line that corresponds to com0. the display area begins at th e specified line address and continues in aeh, afh a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 0 1 1 1 d free datasheet http:///
seite 12 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe b8h to bbh the line address increment direction. this area ha ving the number of lines of the specified display duty is displayed. if the line address is changed dynamically by this command, the vertical smooth scrolling and paging can be used. this command loads display start line register. see figure 1. set page address this command specifies the page address that corres ponds to the low address of the display data ram when it is accessed by the mpu. any bit o f the display data ram can be accessed when its page address and column address a re specified. the display status is not changed even when the page address is changed. this command loads the page address register. c0h to dfh a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 0 a 4 a 3 a 2 a 1 a 0 a 4 a 3 a 2 a 1 a 0 line address 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 31 a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 1 1 0 a 1 a 0 free datasheet http:///
seite 13 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe see figure 1 set column address this command specifies a column address of the disp lay data ram. when the display data ram is accessed by the mpu continuously, the column address is incremented by 1 each time it is accessed from the set address. therefore, th e mpu can access to data continuously. the column address stops to be incremented at addre ss 80, and the page address is not changed continuously. this command loads the column address register. a 6 a 5 a 4 a 3 a 2 a 1 a 0 column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 79 read status a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 busy adc on/off reset 0 0 0 0 reading the command i/o register (a0=0) yields syst em status information. the busy bit indicates whether the driver will acce pt a command or not. ? busy=1: the driver is currently executing a command or is resetting. no new command will be accepted. busy=0: the driver will accept a new command. the adc bit indicates the way column addresses are assigned to segment drivers. ? adc=1: normal. column address nsegment driver n. adc=0: inverted. column address 79usegment driver u. the on/off bit indicates the current status of the display. ? it is the inverse of the polarity of the display on /off command. 00h to 4fh a 1 a 0 page 0 0 0 0 1 1 1 0 2 1 1 3 a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 free datasheet http:///
seite 14 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe aoh a1h a4h a5h on/off=1: display off on/off=0: display on the reset bit indicates whether the driver is execu ting a hardware or software reset or if it ? is in normal operating mode. reset=1: currently executing reset command. reset=0: normal operation write display data writes 8bits of data into the display data ram, at a location specified by the contents of the column address and page address registers and then increments the colu mn address register by one. read display data read 8bits of data from the data i/o latch, update s the contents of the i/o latch with display data from the display data ram location specified b y the contents of the column address and page address registers and then increments the colu mn address register. after loading a new address into the column address register one dummy read is required before valid data is obtained. select adc this command selects the relationship between displ ay data ram column addresses and segment drivers. d=1: seg0column address 4fh,.(inverted) d=0: segocolumn address 00h,.(normal) this command is provided to reduce restrictions on the placement of driver ics and routing of traces during printed circuit board design. see fi gure 1 for a table of segments and column addresses for the two values of d. static drive on/off a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 write data a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 read data a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 0 0 0 0 d a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 0 0 1 0 d free datasheet http:///
seite 15 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe a8h a9h e0h forces display on and all common outputs to be sele cted. d=1: static drive on d=0: static drive off select duty this command sets the duty cycle of the lcd drive, pleas e set d=1, lcd duty cycle is 1/32 duty. read-modify-write this command defeats column address register autoi ncrement after data reads. the current contents of the column address register are saved. this mode remains active until an end command is received. operation sequence during cursor display ? when the end command is entered, the column address is returned to the one used during input of readmodifywrite command. this function can reduce the load of mpu when data change is repeated at a specific display area (such as cursor blinking). * any command other than data read or write can be used in the readmodifywrite mode. however, the column address set command cannot be u sed. a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 0 1 0 0 d a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 1 0 0 0 0 0 free datasheet http:///
seite 16 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe display start line register line counter display data ram ( dd ram ) display data latch mpu interface colume address register colume address counter to lcd panel lcd drive circuit d0 ~ d7 r/w res a0 , cs1 , cs2 end no. defect judgment criterion partition 1 spots a)clear size: d mm acceptable qty in active area d 0.1 disregard Q 0.1 seite 17 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe eeh e2h this command cancels readmodifywrite mode and res tores the contents of the column address register to their value prior to the receipt of the readmodifywrite command. p a g e a d d r e s s d a t a d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 2 d 7 d 4 d 6 d 5 d 3 d 1 d 0 d 2 d 7 d 4 d 6 d 5 d 3 d 1 d 0 d 2 d 7 d 4 d 6 d 5 d 3 d 1 d 0 d 1 , d 2 = 0 , 0 0 , 1 1 , 0 1 , 1 c o l o u m a d d r e s s a d c d 0 = 0 d 0 = 1 s e g p i n 0 0 h 1 2 3 4 5 6 7 0 1 h 0 2 h 0 3 h 0 4 h 0 5 h 0 6 h l i n e a d d r e s s 0 0 h 0 1 h 0 2 h 0 3 h 0 4 h 0 5 h 0 6 h 0 7 h 0 8 h 0 9 h 0 a h 0 b h 0 c h 0 d h 0 e h 0 f h 1 0 h 1 1 h 1 2 h 1 3 h 1 4 h 1 5 h 1 6 h 1 7 h 1 8 h 1 9 h 1 a h 1 b h 1 c h 1 d h 1 e h 1 f h c o m 0 c o m m o n o u t p u t c o m 1 c o m 2 c o m 3 c o m 4 c o m 5 c o m 6 c o m 7 c o m 8 c o m 9 c o m 1 0 c o m 1 1 c o m 1 2 c o m 1 3 c o m 1 4 c o m 1 5 c o m 1 6 c o m 1 7 c o m 1 8 c o m 1 9 c o m 2 0 c o m 2 1 c o m 2 2 c o m 2 3 c o m 2 4 c o m 2 5 c o m 2 6 c o m 2 7 c o m 2 8 c o m 2 9 c o m 3 0 c o m 3 1 4 f h 4 e h 4 d h 4 f h 4 e h 4 d h 4 c h 4 b h 4 a h 4 9 h 0 2 h 0 1 h 0 0 h 8 0 7 9 7 8 6 1 6 0 5 9 3 c h 3 b h 3 a h s e d 1 5 2 1 s e d 1 5 2 0 reset this command clears ? the display start line register. ? and set page address register to 3 page. it does not affect the contents of the display data ram. when the power supply is turned on, a reset signal is entered in the res pin. the reset command cannot be used instead of this reset signal . 11.timing characteristics mpu bus read/write ii (68family mpu) a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 1 0 1 1 1 0 a 0 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 1 0 0 0 1 0 free datasheet http:///
seite 18 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe ta=20 to 75 deg. c, v dd =5v10 unless stated otherwise rating parameter symbol condition min. max. unit signal system cycle time t cyc6 1000 ns address setup time t aw6 20 ns address hold time t ah6 10 ns a0,r/w t acc6 t oh6 dh6 t ew t t f r t t cyc6 t aw6 ds6 t ah6 t cs1,cs2 r/w a0 d0 to d7 (write) (read) d0 to d7 free datasheet http:///
seite 19 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe data setup time t ds6 80 ns data hold time t dh6 10 ns output disable time t oh6 10 60 ns access time t acc6 cl=100pf 90 ns d0 to d7 enable read 100 ns pulsewidth write t ew 80 ns cs rise and fall time tr, tf 15 ns (v dd =2.7 to 4.5 v, ta=20 to +75 ) rating parameter symbol condition min. max. unit signal system cycle time t cyc6 2000 ns address setup time t aw6 40 ns address hold time t ah6 20 ns a0,r/w data setup time t ds6 160 ns data hold time t dh6 20 ns output disable time t oh6 20 120 ns access time t acc6 cl=100pf 180 ns d0 to d7 enable read 200 ns pulsewidth write t ew 160 ns cs rise annd fall time tr, tf 15 ns 12. quality assurance screen cosmetic criteria 13.reliability content of reliability test free datasheet http:///
seite 20 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe environmental test test item content of test test condition applicable standard high temperature storage endurance test applying the high storage temperatur e for a long time. 60 200hrs low temperature storage endurance test applying the high storage temperatur e for a long time. -10 200hrs high temperature operation endurance test applying the electric stress (voltag e & current) and the thermal stress to the element for a long time. 50 200hrs low temperature operation endurance test applying the electric stress under l ow temperature for a long time. 0 200hrs high temperature/ humidity storage endurance test applying the high temperature and hi gh humidity storage for a long time. 60 ,90%rh 96hrs high temperature/ humidity operation endurance test applying the electric stress (voltag e & current) and temperature / humidity stress to t he element for a long time. 50 ,90%rh 96hrs temperature cycle endurance test applying the low and high temperatur e cycle. -10 25 60 30min 5min 30min 1 cycle -10 / 60 10 cycles free datasheet http:///
seite 21 ? anzseiten \*arabisch e` e` e` e` ! x?oRe x?oRe x?oRe x?oRe ***su pply voltage for logic system=5v. supply voltage fo r lcd system =operating voltage at 25 free datasheet http:///

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