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ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 66 tsop-ii and 60 ball fbga with pb-free (rohs compliant) ddr sdram registered module 184pin registered module based on 512mb c-die with 72-bit ecc information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sa msung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, me dical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmen tal procurement to which special terms or provisions may apply. * samsung electronics reserves the right to ch ange products or specification without notice.
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 table of contents 1.0 ordering information...... ................ ................. ................ ................ ................. ............... ............ 4 2.0 operating frequencies..... ................. ................ ................ ................. ................ ............... .......... 4 3.0 feature............. ................ ................ .............. .............. .............. ............... .............. ........... ........... 4 4.0 pin configuration (front side/back side) ..... ................ ................ ................. .............. ............. 5 5.0 pin description .......... ................. ................ ................ ................. ................ ................ ................ 5 6.0 functional block diagram ........... ................ ................. .............. .............. .............. ............. ....... 6 6.1 512mb, 64m x 72 ecc module (m312l6523cus) ................ ................ ................. ................ ............. 6 6.2 1gb, 128m x 72 ecc module (m312l2923cus) ................. ................ ................. ................ ............. 7 6.3 1gb, 128m x 72 ecc module (m312l2920cus) ................. ................ ................. ................ ............. 8 6.4 2gb, 256m x 72 ecc module (m312l5628cu0) ............... ................. ................ ................. ............... 9 6.5 512mb, 64m x 72 ecc module (m312l6523cz3)................................................................................. ........... 10 6.6 1gb, 128m x 72 ecc module (m312l2923cz3) ............... ................. ................ ................. ............. 11 6.7 1gb, 128m x 72 ecc module (m312l2920cz3) .................................................................................. ............ 12 6.8 2gb, 256m x 72 ecc module (m312l5720cz3) .................................................................................. ............ 13 7.0 absolute maximum ratings........... ................. ................ .............. .............. .............. ............. ... 14 8.0 power & dc operating conditions (sstl_2 in/out) ......... .............. .............. .............. ........... 14 9.0 ddr sdram idd spec table . ................ ................. ................ ................. ................ ................ .. 15 9.1 m312l6523cus [ (64m x 8) * 9 , 512mb module ] ................... ................. .............. .............. ........... 15 9.2 m312l2923cus [ (64m x 8) * 18 , 1gb module ] ............... ................. ................ ................. ............. 15 9.3 m312l2920cus [ (128m x 4) * 18 , 1gb module ] . ................ ................. ................ ................ ............ .............. 16 9.4 m312l5628cu0 [ (st.256m x 4) * 18 , 2gb module ] ................ ................. .............. .............. ........... 16 9.5 m312l6523cz3 [ (64m x 8) * 9 , 512mb module ]............................................................................. ............... 17 9.6 m312l2923cz3 [ (64m x 8) * 18 , 1gb module ] ............... ................. ................ ................. ............. 17 9.7 m312l2920cz3 [ (128m x 4) * 18 , 1gb module ] ................. ................ ................. ................ ........... 18 9.8 m312l5720cz3 [ (128m x 4) * 36, 2gb module ] ............... ................. ................ ................. ............. 18 10.0 ac operating conditions.... ................ ................. ................ ................. ................ ............. ..... 19 11.0 input/output capacitance .......... ................ ................. .............. .............. .............. ............. ..... 19 12.0 ac timming parameters & specificat ions ................ ................ ................. ................ ........... 20 13.0 system characteristics for ddr sdram ........... .............. .............. .............. .............. ........... 21 14.0 component notes......... ................ ................. ................ ................ ................. ................ ......... 22 15.0 system notes ........... ................. ................ ................ ................. ................ ................. ............. 23 16.0 command truth table.................. .............. .............. .............. ............... .............. .............. ...... 24 17.0 physical dimensions...... ................. ................ ................ ................. ................ ............... ........ 25 17.1 64m x 72 (m312l6523cus) ................ ................ ................ ................. .............. .............. ........... 25 17.2 128m x 72 (m312l2923cus), (m312l2920cus) ................ ................ ................. ................ ........... 26 17.3 st.256m x 72 (m312l5628cu0) ............... ................. .............. .............. .............. .............. ........... 27 17.4 64m x 72 (m312l6523cz3) ................ ................ ................ ................. .............. .............. ........... 28 17.5 128m x 72 (m312l2923cz3), (m312l2920cz3) ................. ................ ................. ................ ........... 29 17.6 256m x 72 (m312l5720cz3) ................. ................ ................. .............. .............. .............. ........... 30
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 revision history revision month year history 1.0 february 2005 - first release. 1.1 april 2005 - added notice. 1.2 june 2005 - changed master format 1.3 january 2006 - changed fbga rdimm part numbers 1.4 march 2006 - added notes for part numbers and updated system characteristics
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 cc(ddr400@cl=3) b3(ddr333@cl=2.5) a2(ddr266@cl=2) b0(ddr266@cl=2.5) speed @cl2 - 133mhz 133mhz 100mhz speed @cl2.5 166mhz 166mhz 133mhz 133mhz speed @cl3 200mhz - - - cl-trcd-trp 3-3-3 2.5-3-3 2-3-3 2.5-3-3 184pin registered dimm base d on 512mb c-die (x4, x8) ? vdd : 2.5v 0.2v, vddq : 2.5v 0.2v for ddr266, 333 ? vdd : 2.6v 0.1v, vddq : 2.6v 0.1v for ddr400 ? double-data-rate architecture; tw o data transfers per clock cycle ? bidirectional data strobe [dq] (x4,x8) & [l(u)dqs] (x16) ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs transition with ck transition ? programmable read latency : ddr266(2, 2. 5 clock), ddr333(2.5 clock), ddr400(3 clock) ? programmable burst length (2, 4, 8) ? programmable burst type (sequential & interleave) ? edge aligned data output, center aligned data input ? auto & self refresh, 7.8us re fresh interval(8k/64ms refresh) ? serial presence detect with eeprom ? sstl_2 interface ? 66pin tsop ii and 60 ball fbga pb-free package ? rohs compliant 1.0 ordering information 2.0 operating frequencies note : ?u? of part number(11th digit) stand for lead-free tsop products. note : ?z? of part number(11th digit) stand for lead-free fbga products. note : ?3? of part number(12th digi t) stand for dummy pad pcb products. part number density organization component composition height m312l6523cus-ca2/b0 512mb 64m x 72 64mx8( k4h510838c) * 9ea 1,200mil m312l2923cus-ca2/b0 1gb 128m x 72 64mx8( k4h510838c) * 18ea 1,200mil m312l2920cus-ca2/b0 1gb 128m x 72 128mx4( k4h510438c) * 18ea 1,200mil M312L5628CU0-CA2/b0 2gb 256m x 72 st.256mx4( k4h1g0638c) * 18ea 1,200mil m312l6523cz3-ccc/b3 512mb 64mx72 64mx8( k4h510838c) * 9ea 1,125mil m312l2923cz3-ccc/b3 1gb 128m x 72 64mx8( k4h510838c) * 18ea 1,125mil m312l2920cz3-ccc/b3 1gb 128m x 72 128mx4( k4h510438c) * 18ea 1,125mil m312l5720cz3-ccc/b3 2gb 256m x 72 128mx4( k4h510438c) * 36ea 1,200mil 3.0 feature
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 note : 1. * : these pins are not used in this module. 2. pins 111, 158 are nc for 1row module & used for 2row module. 3. pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : dm (x8 base module) or dqs (x4 base module). pin front pin front pin front pin back pin back pin back 1 vref 32 a5 62 vddq 93 vss 124 vss 154 ras 2 dq0 33 dq24 63 we 94 dq4 125 a6 155 dq45 3 vss 34 vss 64 dq41 95 dq5 126 dq28 156 vddq 4 dq1 35 dq25 65 cas 96 vddq 127 dq29 157 cs0 5 dqs0 36 dqs3 66 vss 97 dm0/dqs9 128 vddq 158 cs1 6 dq2 37 a4 67 dqs5 98 dq6 129 dm3/dqs12 159 dm5/dqs14 7 vdd 38 vdd 68 dq42 99 dq7 130 a3 160 vss 8 dq3 39 dq26 69 dq43 100 vss 131 dq30 161 dq46 9 nc 40 dq27 70 vdd 101 nc 132 vss 162 dq47 10 reset 41 a2 71 *cs2 102 nc 133 dq31 163 *cs3 11 vss 42 vss 72 dq48 103 nc 134 cb4 164 vddq 12 dq8 43 a1 73 dq49 104 vddq 135 cb5 165 dq52 13 dq9 44 cb0 74 vss 105 dq12 136 vddq 166 dq53 14 dqs1 45 cb1 75 *ck2 106 dq13 137 ck0 167 *a13 15 vddq 46 vdd 76 *ck2 107 dm1/dqs10 138 ck0 168 vdd 16 *ck1 47 dqs8 77 vddq 108 vdd 139 vss 169 dm6/dqs15 17 *ck1 48 a0 78 dqs6 109 dq14 140 dm8/dqs17 170 dq54 18 vss 49 cb2 79 dq50 110 dq15 141 a10 171 dq55 19 dq10 50 vss 80 dq51 111 cke1 142 cb6 172 vddq 20 dq11 51 cb3 81 vss 112 vddq 143 vddq 173 nc 21 cke0 52 ba1 82 vddid 113 *ba2 144 cb7 174 dq60 22 vddq key 83 dq56 114 dq20 key 175 dq61 23 dq16 53 dq32 84 dq57 115 a12 145 vss 176 vss 24 dq17 54 vddq 85 vdd 116 vss 146 dq36 177 dm7/dqs16 25 dqs2 55 dq33 86 dqs7 117 dq21 147 dq37 178 dq62 26 vss 56 dqs4 87 dq58 118 a11 148 vdd 179 dq63 27 a9 57 dq34 88 dq59 119 dm2/dqs11 149 dm4/dqs13 180 vddq 28 dq18 58 vss 89 vss 120 vdd 150 dq38 181 sa0 29 a7 59 ba0 90 nc 121 dq22 151 dq39 182 sa1 30 vddq 60 dq35 91 sda 122 a8 152 vss 183 sa2 31 dq19 61 dq40 92 scl 123 dq23 153 dq44 184 vddspd note : vddid defines relationship of vdd and vddq , and the default status of it is open (vdd=vddq) pin name function pin name function a0 ~ a12 address input (multiplexed) dm0 ~ dm8 data - in mask ba0 ~ ba1a bank select address vdd power supply (2.5v for ddr266/333, 2.6v for ddr400) dq0 ~ dq63 data input/output vddq power supply for dqs (2.5v for ddr266/333, 2.6v for ddr400) dqs0 ~ dqs17 data strobe input/output vss ground ck0,ck0 ~ ck2, ck2 clock input vref power supply for reference cke0, cke1(for double banks) clock enable input vddspd serial eeprom power/supply ( 2.3v to 3.6v ) cs0 , cs1 (for double banks) chip select input sda serial data i/o ras row address strobe scl serial clock cas column address strobe sa0 ~ 2 address in eeprom we write enable vddid vdd, vddq level detection cb0 ~ cb7 check bit(data-in/data-out) nc no connection 5.0 pin description 4.0 pin configuration (f ront side/back side)
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 (populated as 1 bank of x8 ddr sdram module) v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 vref v ddspd spd d0 - d8 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp rcs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 7 i/o 5 i/o 2 i/o 0 i/o 6 i/o 4 i/o 3 i/o 1 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 i/o 6 i/o 5 i/o 3 i/o 1 i/o 7 i/o 4 i/o 2 i/o 0 i/o 0 i/o 2 i/o 5 i/o 6 i/o 1 i/o 3 i/o 4 i/o 7 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 i/o 7 i/o 4 i/o 2 i/o 0 i/o 6 i/o 5 i/o 3 i/o 1 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 i/o 6 i/o 4 i/o 2 i/o 0 i/o 7 i/o 5 i/o 3 i/o 1 dqs8 dm8 dm/ cs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 d8 i/o 5 i/o 4 i/o 2 i/o 0 i/o 7 i/o 6 i/o 3 i/o 1 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. pll* ck0,ck0 pck ras cas cke0 ba0-ba1 a0-a12 r e g i s t e r cs0 pck reset rcs0 rba0 - rba1 ra0 - ra12 rras rcas rcke0 rwe ba0 -ba1 : sdrams dq0 - d8 a0 -a12 : sdrams d0 - d8 ras : sdrams d0 - d8 cas : sdrams d0 - d8 cke : sdrams d0 - d8 we : sdrams d0 - d8 we * wire per clock loading table/wiring diagrams 6.1 512mb, 64m x 72 e cc module (m312l6523cus) 6.0 functional block diagram
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 rcs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 7 i/o 5 i/o 2 i/o 0 i/o 6 i/o 4 i/o 3 i/o 1 i/o 7 i/o 5 i/o 2 i/o 0 i/o 6 i/o 4 i/o 3 i/o 1 i/o 6 i/o 5 i/o 3 i/o 1 i/o 7 i/o 4 i/o 2 i/o 0 i/o 7 i/o 5 i/o 2 i/o 1 i/o 6 i/o 4 i/o 3 i/o 0 i/o 7 i/o 5 i/o 2 i/o 0 i/o 6 i/o 4 i/o 3 i/o 1 i/o 7 i/o 4 i/o 2 i/o 0 i/o 6 i/o 5 i/o 3 i/o 1 i/o 7 i/o 5 i/o 2 i/o 0 i/o 6 i/o 4 i/o 3 i/o 1 i/o 6 i/o 4 i/o 2 i/o 0 i/o 7 i/o 5 i/o 3 i/o 1 dm/ cs dqs d9 dm/ cs dqs d10 dm/ cs dqs d11 dm/ cs dqs d12 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 dm/ cs dqs d13 dm/ cs dqs d14 dm/ cs dqs d15 dm/ cs dqs d16 rcs 1 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 i/o 1 i/o 2 i/o 4 i/o 6 i/o 0 i/o 3 i/o 5 i/o 7 i/o 0 i/o 2 i/o 5 i/o 6 i/o 1 i/o 3 i/o 4 i/o 7 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 i/o 0 i/o 3 i/o 5 i/o 7 i/o 1 i/o 2 i/o 4 i/o 6 i/o 0 i/o 2 i/o 5 i/o 7 i/o 1 i/o 3 i/o 4 i/o 6 i/o 1 i/o 3 i/o 5 i/o 7 i/o 0 i/o 2 i/o 4 i/o 6 v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd spd d0 - d17 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp dqs8 dm8 dm/ cs dqs d8 i/o 5 i/o 4 i/o 2 i/o 0 i/o 7 i/o 6 i/o 3 i/o 1 dm/ cs dqs d17 i/o 2 i/o 3 i/o 5 i/o 7 i/o 0 i/o 1 i/o 4 i/o 6 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 pck ras cas cke0 cke1 cs1 ba0-ba1 a0-a12 cs0 we pck reset rcs1 rcs0 rba0 - rba1 ra0 - ra12 rras rcas rcke0 rwe rcke1 ba0 -ba1 : sdrams dq0 - d17 a0 -a12 : sdrams d0 - d17 ras : sdrams d0 - d17 cas : sdrams dq0 - d17 cke : sdrams d0 - d8 cke : sdrams d9 - d17 we : sdrams d0 - d17 r e g i s t e r pll* ck0,ck0 * wire per clock loading table/wiring diagrams notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. (populated as 2 bank of x8 ddr sdram module) 6.2 1gb, 128m x 72 ecc module (m312l2923cus)
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dqs9 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqs16 rcs 0 dqs4 dqs1 dqs5 dqs2 dqs3 dqs15 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dqs8 dqs17 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm resistors: 22 ohms. ras cas cke0 ba0-ba1 a0-a12 s0 rs0 rba0 - rba1 ra0 - ra12 rras rcas rcke0 rwe ba0 -ba1 : sdrams dq0 - d17 a0 -a12 : sdrams d0 - d17 ras : sdrams d0 - d17 cas : sdrams dq0 - d17 cke : sdrams d0 - d17 we : sdrams d0 - d17 r e g i s t e r dqs i/o 3 i/o 2 i/o 1 i/o 0 d8 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d0 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d1 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d2 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d3 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d4 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d5 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d6 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d7 cs dm vss dqs i/o 0 i/o 1 i/o 2 i/o 3 d17 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d9 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d10 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d11 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d12 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d13 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d14 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d15 cs dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d16 cs dm dqs10 reset pck pck we pll* ck0,ck0 * wire per clock loading table/wiring diagrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d17 d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref strap: see note 4 v ddspd spd (dm0) (dm1) (dm2) (dm3) (dm4) (dm5) (dm6) (dm7) (dm8) (populated as 1 bank of x4 ddr sdram module) 6.3 1gb, 128m x 72 e cc module (m312l2920cus)
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm0/dqs9 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm4/dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm7/dqs16 rcs 0 rcs 1 dqs4 dqs1 dqs5 dqs2 dqs3 dm6/dqs15 dqs6 dqs7 dq15 dqs i/o 3 i/o 2 i/o 1 i/o 0 d0 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d1 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d2 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d3 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d4 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d5 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d6 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d7 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d9 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d10 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d11 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d12 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d13 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d14 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d15 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d16 dm dm1/dqs10 v ss dqs i/o 3 i/o 2 i/o 1 i/o 0 d18 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d19 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d20 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d21 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d22 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d23 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d24 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d25 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d27 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d28 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d29 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d30 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d31 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d32 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d33 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d34 dm notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. ra0 - ra12 a0-an: sdrams d0 - d35 ras : sdrams d0 - d35 rcas cas : sdrams d0 - d35 rcke1 cke: sdrams d18 - d35 pck we : sdrams d0 - d35 rcke0 rba0 - rba1 ba0-ban: sdrams d0 - d35 ras cas cke0 cke1 rcs1 cs1 ba0-ba1 a0-a12 r e g i s t e r rras rwe cs0 rcs0 we pck reset cke: sdrams d0 - d17 pll ck0,ck0 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d35 d0 - d35 v dd /v ddq d0 - d35 d0 - d35 vref v ddspd spd cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dqs8 dm8/dqs17 dqs i/o 3 i/o 2 i/o 1 i/o 0 d8 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d17 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d26 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d35 dm cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs (populated as 2 bank of x4 ddr sdram module) 6.4 2gb, 256m x 72 e cc module (m312l5628cu0)
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 2 i/o 4 i/o 7 d0 dm0 i/o 3 i/o 1 i/o 6 i/o 5 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm d1 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm d2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm d3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm d4 dm4 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm d5 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm d6 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm d7 dm7 rcs 0 cs cs cs cs cs cs cs cs dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs dm6 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm d8 cs dqs dqs dqs dqs dqs pck ras cas cke0 ba0-ba1 a0-a12 r e g i s t e r cs0 pck reset rcs0 rba0 - rba1 ra0 - ra12 rras rcas rcke0 rwe ba0 -ba1 : ddr sdrams d0 - d8 a0 -a12 : ddr sdrams d0 - d8 ras : ddr sdrams d0 - d8 cas : ddr sdrams d0 - d8 cke : ddr sdrams d0 - d8 we : ddr sdrams d0 - d8 we pll* ck0,ck0 * wire per clock loading table/wiring diagrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss ddr sdrams d0 - d8 v dd /v ddq ddr sdrams d0 - d8 ddr sdrams d0 - d8 vref v ddspd spd notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. dm2 dqs2 dm3 dqs3 dm8 dqs8 i/o 7 i/o 5 i/o 3 i/o 0 i/o 4 i/o 6 i/o 1 i/o 2 i/o 0 i/o 2 i/o 4 i/o 7 i/o 3 i/o 1 i/o 6 i/o 5 i/o 7 i/o 5 i/o 3 i/o 0 i/o 4 i/o 6 i/o 1 i/o 2 i/o 7 i/o 5 i/o 3 i/o 0 i/o 4 i/o 6 i/o 1 i/o 2 i/o 7 i/o 5 i/o 3 i/o 0 i/o 4 i/o 6 i/o 1 i/o 2 i/o 7 i/o 5 i/o 3 i/o 0 i/o 4 i/o 6 i/o 1 i/o 2 i/o 0 i/o 2 i/o 4 i/o 7 i/o 3 i/o 1 i/o 6 i/o 5 i/o 7 i/o 5 i/o 3 i/o 0 i/o 4 i/o 6 i/o 1 i/o 2 (populated as 1 bank of x8 ddr sdram module) 6.5 512mb, 64m x 72 ecc module (m312l6523cz3)
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 rcs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 dm/ cs dqs d9 dm/ cs dqs d10 dm/ cs dqs d11 dm/ cs dqs d12 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 dm/ cs dqs d13 dm/ cs dqs d14 dm/ cs dqs d15 dm/ cs dqs d16 rcs 1 v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd spd d0 - d17 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp dqs8 dm8 dm/ cs dqs d8 dm/ cs dqs d17 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 pck ras cas cke0 cke1 cs1 ba0-ba1 a0-a12 cs0 we pck reset rcs1 rcs0 rba0 - rba1 ra0 - ra12 rras rcas rcke0 rwe rcke1 ba0 -ba1 : ddr sdram dq0 - d17 a0 -a12 : ddr sdram d0 - d17 ras : ddr sdram d0 - d17 cas : ddr sdram dq0 - d17 cke : ddr sdram d0 - d8 cke : ddr sdram d9 - d17 we : ddr sdram d0 - d17 r e g i s t e r pll* ck0,ck0 * wire per clock loading table/wiring diagrams notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 i/o 7 i/o 6 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 5 i/o 4 i/o 3 i/o 2 (populated as 2 bank of x8 ddr sdram module) 6.6 1gb, 128m x 72 ecc module (m312l2923cz3 )
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dqs9 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqs16 rcs 0 dqs4 dqs1 dqs5 dqs2 dqs3 dqs15 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dqs8 dqs17 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm resistors: 22 ohms. ras cas cke0 ba0-ba1 a0-a12 cs0 rcs0_2 rcs0_1 rba0 - rba1 ra0 - ra12 rras rcas rcke0a rwe rcke0b ba0 -ba1 : ddr sdram dq0 - d17 a0 -a12 :ddr sdram d0 - d17 ras : ddr sdram d0 - d17 cas : ddr sdram dq0 - d17 cke : ddr sdram d0 - d8 cke : ddr sdram d9 - d17 we :ddr sdram d0 - d17 r e g i s t e r dqs i/o 3 i/o 2 i/o 1 i/o 0 d8 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d0 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d1 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d2 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d3 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d4 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d5 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d6 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d7 cs dm vss dqs i/o 0 i/o 1 i/o 2 i/o 3 d9 cs dm dqs d10 cs dm dqs d11 cs dm dqs d12 cs dm dqs10 reset pck pck we pll* ck0,ck0 * wire per clock loading table/wiring diagrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d17 d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd spd (dm0) (dm1) (dm2) (dm3) (dm4) (dm5) (dm6) (dm7) (dm8) i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 dqs d13 cs dm dqs d14 cs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 dqs d15 cs dm dqs d16 cs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 dqs d17 cs dm i/o 0 i/o 1 i/o 2 i/o 3 (populated as 1 bank of x4 ddr sdram module) 6.7 1gb, 128m x 72 e cc module (m312l2920cz3)
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dqs9 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqs16 rcs 0 rcs 1 dqs4 dqs1 dqs5 dqs2 dqs3 dqs15 dqs6 dqs7 dq15 dqs d0 cs dm dqs d1 dm dqs d2 dm dqs d3 dm dqs d4 dm dqs d5 dm dqs d6 dm dqs d7 dm dqs10 v ss dqs i/o 0 i/o 1 i/o 2 i/o 3 d18 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d19 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d20 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d21 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d22 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d23 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d24 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d25 dm notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. ra0 - ra12 a0-a12: ddr sdram d0 - d35 ras : ddr sdram d0 - d35 rcas cas : ddr sdram d0 - d35 rcke1 cke: ddr sdram d18 - d35 pck we : ddr sdram d0 - d35 rcke0 rba0 - rba1 ba0-ba1: ddr sdram d0 - d35 ras cas cke0 cke1 rcs1 cs1 ba0-ba1 a0-a12 r e g i s t e r rras rwe cs0 rcs0 we pck reset cke: ddr sdram d0 - d17 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d35 d0 - d35 v dd /v ddq d0 - d35 d0 - d35 vref v ddspd spd pll* ck0,ck0 * wire per clock loading table/wiring diagrams cb0 cb1 cb2 cb3 dqs8 dqs d8 dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d26 dm cb4 cb5 cb6 cb7 dqs17 (dm0) (dm1) (dm2) (dm3) (dm4) (dm5) (dm6) (dm7) (dm8) cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs dqs d9 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d27 dm cs cs dqs d10 dm dqs d11 dm dqs d12 dm dqs d13 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d28 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d29 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d30 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d31 dm cs cs cs cs cs cs cs cs dqs d14 dm dqs d15 dm dqs d16 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d32 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d33 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d34 dm dqs d17 dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d35 dm cs cs cs cs cs cs cs cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 i/o 3 i/o 2 i/o 1 i/o 0 (populated as 2 bank of x4 ddr sdram module) 6.8 2gb, 256m x 72 e cc module (m312l5720cz3)
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restri cted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could af fect device reliability. parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd, v ddq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.5 * # of component w short circuit current i os 50 ma recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 70 c) note : 1. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of same. peak-t o peak noise on vref may not exceed +/-2% of the dc value. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination re sistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. the ratio of the pullup current to the pulldown current is s pecified for the same temperature and voltage, over the entire t emperature and voltage range, for device drain to source voltages from 0.25v to 1.0v. for a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. the full variation in the ratio of t he maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0. parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v for ddr266/333) v dd 2.3 2.7 v supply voltage(for device with a nominal v dd of 2.6v for ddr400) v dd 2.5 2.7 v i/o supply voltage(for device with a nominal v dd of 2.5v for ddr266/333) v ddq 2.3 2.7 v i/o supply voltage(for device with a nominal v dd of 2.6v for ddr400) v ddq 2.5 2.7 v i/o reference voltage v ref 0.49*vddq 0.51*vddq v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v input logic low voltage v il (dc) -0.3 v ref -0.15 v input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.36 v ddq +0.6 v 3 v-i matching: pullup to pulldown current ratio vi(ratio) 0.71 1.4 - 4 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9ma 8.0 power & dc operating co nditions (sstl_2 in/out) 7.0 absolute maximum ratings
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol a2(ddr266@cl=2) b0(ddr266@cl=2.5) unit notes idd0 1,360 1,360 ma idd1 1,630 1,630 ma idd2p 350 350 ma idd2f 770 770 ma idd2q 530 530 ma idd3p 570 570 ma idd3n 910 910 ma idd4r 1,630 1,630 ma idd4w 1,670 1,670 ma idd5 2,260 2,260 ma idd6 normal 350 350 ma low power 330 330 ma idd7a 3,430 3,430 ma (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol a2(ddr266@cl=2) b0(ddr266@cl=2.5) unit notes idd0 2,010 2,010 ma idd1 2,280 2,280 ma idd2p 540 540 ma idd2f 1,290 1,290 ma idd2q 900 900 ma idd3p 990 990 ma idd3n 1,560 1,560 ma idd4r 2,280 2,280 ma idd4w 2,330 2,330 ma idd5 2,910 2,910 ma idd6 normal 540 540 ma low power 510 510 ma idd7a 4,080 4,080 ma 9.1 m312l6523cus [ (64m x 8) * 9 , 512mb module ] 9.2 m312l2923cus [ (64m x 8) * 18 , 1gb module ] 9.0 ddr sdram idd spec table
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol a2(ddr266@cl=2) b0(ddr266@cl=2.5) unit notes idd0 2,340 2,340 ma idd1 2,880 2,880 ma idd2p 420 420 ma idd2f 1,170 1,170 ma idd2q 780 780 ma idd3p 870 870 ma idd3n 1,440 1,440 ma idd4r 2,880 2,880 ma idd4w 2,970 2,970 ma idd5 4,140 4,140 ma idd6 normal 420 420 ma low power 380 380 ma idd7a 6,480 6,480 ma (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol a2(ddr266@cl=2) b0(ddr266@cl=2.5) unit notes idd0 3,400 3,400 ma idd1 3,940 3,940 ma idd2p 760 760 ma idd2f 1,960 1,960 ma idd2q 1,480 1,480 ma idd3p 1,660 1,660 ma idd3n 2,500 2,500 ma idd4r 3,940 3,940 ma idd4w 4,030 4,030 ma idd5 5,200 5,200 ma idd6 normal 760 760 ma low power 685 685 ma idd7a 7,540 7,540 ma 9.4 m312l5628cu0 [ (st.256m x 4) * 18 , 2gb module ] 9.3 m312l2920cus [ (128m x 4) * 18 , 1gb module ]
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd a nd can be differently measured according to dq loading cap. symbol cc (ddr400@cl=3) b3 (ddr333@cl=2.5) unit notes idd0 1,830 1,700 ma idd1 2,100 1,970 ma idd2p 420 420 ma idd2f 1,020 1,020 ma idd2q 600 600 ma idd3p 780 650 ma idd3n 1,290 1,160 ma idd4r 2,150 2,010 ma idd4w 2,330 2,100 ma idd5 2,730 2,600 ma idd6 normal 420 420 ma low power 410 410 ma idd7a 4,220 3,990 ma (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd a nd can be differently measured according to dq loading cap. symbol cc (ddr400@cl=3) b3 (ddr333@cl=2.5) unit notes idd0 2,500 2,230 ma idd1 2,770 2,500 ma idd2p 590 590 ma idd2f 1,420 1,420 ma idd2q 950 950 ma idd3p 1,310 1,040 ma idd3n 1,960 1,690 ma idd4r 2,810 2,540 ma idd4w 2,990 2,630 ma idd5 3,400 3,130 ma idd6 normal 590 590 ma low power 560 560 ma idd7a 4,880 4,520 ma 9.6 m312l2923cz3 [ (64m x 8) * 18 , 1gb module ] 9.5 m312l6523cz3 [ (64m x 8) * 9 , 512mb module ]
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol cc (ddr400@cl=3) b3 (ddr333@cl=2.5) unit notes idd0 4,240 3,700 ma idd1 4,780 4,240 ma idd2p 810 810 ma idd2f 2,080 2,080 ma idd2q 1,530 1,530 ma idd3p 2,250 1,710 ma idd3n 3,160 2,620 ma idd4r 4,870 4,330 ma idd4w 5,230 4,510 ma idd5 6,040 5,500 ma idd6 normal 810 810 ma low power 740 740 ma idd7a 9,010 8,290 ma (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol cc (ddr400@cl=3) b3 (ddr333@cl=2.5) unit notes idd0 2,910 2,640 ma idd1 3,450 3,180 ma idd2p 470 470 ma idd2f 1,290 1,290 ma idd2q 830 830 ma idd3p 1,190 920 ma idd3n 1,830 1,560 ma idd4r 3,540 3,270 ma idd4w 3,900 3,450 ma idd5 4,710 4,440 ma idd6 normal 470 470 ma low power 430 430 ma idd7a 7,680 7,230 ma 9.8 m312l5720cz3 [ (128m x 4) * 36, 2gb module ] 9.7 m312l2920cz3 [ (128m x 4) * 18 , 1gb module ]
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 output load circuit (sstl_2) output z0=50 ? c load =30pf v ref =0.5*v ddq r t =50 ? v tt =0.5*v ddq (ta= 25 c, f=100mhz) parameter symbol m312l6523cus, m312l2920cus m312l2923cus, m312l5628cu0 unit min max min max input capacitance(a0 ~ a12, ba0 ~ ba1,ras ,cas ,we ) cin1 9 11 9 11 pf input capacitance(cke0) cin2 9 11 9 11 pf input capacitance( cs 0) cin3 9 11 9 11 pf input capacitance( clk0, clk0 ) cin411121112pf input capacitance(dm0~dm8) cin5 10 11 14 16 pf data & dqs input/output capaci tance(dq0~dq63) cout1 10 11 14 16 pf data input/output capacitance (cb0~cb7) cout2 10 11 14 16 pf parameter symbol m312l6523cz3, m312l2920cz3 m312l2923cz3, m312l5720cz3 unit min max min max input capacitance(a0 ~ a12, ba0 ~ ba1,ras ,cas ,we ) cin1 9 11 9 11 pf input capacitance(cke0) cin2 9 11 9 11 pf input capacitance( cs 0) cin3 9 11 9 11 pf input capacitance( clk0, clk0 ) cin411121112pf input capacitance(dm0~dm8) cin5 10 11 13 15 pf data & dqs input/output capaci tance(dq0~dq63) cout1 10 11 13 15 pf data input/output capacitance (cb0~cb7) cout2 10 11 13 15 pf note : 1. vid is the magnitude of the difference between the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track va riations in the dc level of the same. parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dq s and dm signals vih(ac) vref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vdd q-0.2 0.5*vddq+0.2 v 2 11.0 input/output capacitance 10.0 ac operating conditions
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 parameter symbol cc (ddr400@cl=3.0) b3 (ddr333@cl=2.5) a2 (ddr266@cl=2.0) b0 (ddr266@cl=2.5) unit note min max min max min max min max row cycle time trc 55 60 65 65 ns refresh row cycle time trfc 70 72 75 75 ns row active time tras 40 70k 42 70k 45 70k 45 70k ns ras to cas delay trcd 15 18 20 20 ns row precharge time trp 15 18 20 20 ns row active to row active delay trrd 10 12 15 15 ns write recovery time twr 15 15 15 15 ns last data in to read command twtr 2 1 1 1 tck clock cycle time cl=2.0 tck - - 7.5 12 7.5 12 10 12 ns cl=2.5 6126127.5127.512ns cl=3.0 510------ clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ck tdqsck -0.55 +0.55 -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns output data access time from ck/ck tac -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns data strobe edge to ouput data edge tdqsq - 0.4 - 0.45 - 0.5 - 0.5 ns 22 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 0 0 ns 13 dqs-in hold time twpre 0.25 0.25 0.25 0.25 tck dqs falling edge to ck rising-setup time tdss 0.2 0.2 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 0.35 0.35 tck address and control input setup time(fast) tis 0.6 0.75 0.9 0.9 ns 15, 17~19 address and control input hold time(fast) tih 0.6 0.75 0.9 0.9 ns 15, 17~19 address and control input setup time(slow) tis 0.7 0.8 1.0 1.0 ns 16~19 address and control input hold time(slow) tih 0.7 0.8 1.0 1.0 ns 16~19 data-out high impedence time from ck/ck thz -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns 11 data-out low impedence time from ck/ck tlz -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns 11 mode register set cycle time tmrd 10 12 15 15 ns dq & dm setup time to dqs tds 0.4 0.45 0.5 0.5 ns j, k dq & dm hold time to dqs tdh 0.4 0.45 0.5 0.5 ns j, k control & address input pulse width tipw 2.2 2.2 2.2 2.2 ns 18 dq & dm input pulse width tdipw 1.75 1.75 1.75 1.75 ns 18 exit self refresh to non-read command txsnr 75 75 75 75 ns exit self refresh to read command txsrd 200 200 200 200 tck refresh interval time trefi 7.8 7.8 7.8 7.8 us 14 output dqs valid window tqh thp -tqhs - thp -tqhs - thp -tqhs - thp -tqhs -ns21 clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - ns 20, 21 data hold skew factor tqhs 0.5 0.55 0.75 0.75 ns 21 dqs write postamble time twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 12 active to read with auto precharge command trap 15 18 20 20 autoprecharge write recovery + precharge time tdal (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) tck 23 12.0 ac timming param eters & specifications
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 the following specification parame ters are required in systems using ddr333, ddr266 & ddr200 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. table 1 : input slew rate fo r dq, dqs, and dm table 2 : input setup & hold time derating for slew rate table 3 : input/output setup & ho ld time derating for slew rate table 4 : input/output setup & hold de rating for rise/fall delta slew rate table 5 : output slew rate char acteristice (x4, x8 devices only) table 6 : output slew rate characteristice (x16 devices only) table 7 : output slew rate matching ratio characteristics ac characteristics ddr400 ddr333 ddr266 parameter symbol min max min max min max units notes dq/dm/dqs input slew rate measured between vih(dc), vil(dc) and vil(dc), vih(dc) dcslew 0.5 4.0 0.5 4.0 0.5 4.0 v/ns a, l input slew rate ? tis ? tih units notes 0.5 v/ns 0 0 ps i 0.4 v/ns +50 0 ps i 0.3 v/ns +100 0 ps i input slew rate ? tds ? tdh units notes 0.5 v/ns 0 0 ps k 0.4 v/ns +75 +75 ps k 0.3 v/ns +150 +150 ps k delta slew rate ? tds ? tdh units notes +/- 0.0 v/ns 0 0 ps j +/- 0.25 v/ns +50 +50 ps j +/- 0.5 v/ns +100 +100 ps j slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h ac characteristics ddr400 ddr333 ddr266 parameter min max min max min max notes output slew rate matching ratio (pullup to pulldown) 0.67 1.5 0.67 1.5 0.67 1.5 e,l 13.0 system characteri stics for ddr sdram
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electr ical, ac and dc characterist ics, may be conducted at nominal reference/supply voltage l evels, but the related speci- fications and device operation are guaranteed for the full voltage range specified. 3. figure 1 represents the timing reference load used in defini ng the relevant timing parameters of the part. it is not int ended to be either a precise rep- resentation of the typical system environment nor a depiction of the actual load pr esented by a production tester. system desi gners will use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers will correlate to their p roduction test conditions (generally a coaxial transmission line term inated at the tester electronics). 4. ac timing and idd tests may use a vil to vih swing of up to 1.5 v in the test environment, but input timing is still refere nced to vref (or to the cross- ing point for ck/ck), and parameter specifications are guaranteed fo r the specified ac input levels under normal use conditions . the minimum slew rate for the input signals is 1 v/ns in the range between vil(ac) and vih(ac). 5. the ac and dc input level specificati ons are as defined in the sstl_2 standard (i .e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input low (hig h) level. 6. inputs are not recognized as valid until vref stabiliz es. exception: during the peri od before vref stabilizes, cke 0.2vddq is recognized as low. 7. enables on.chip refresh and address counters. 8. idd specifications are tested af ter the device is properly initialized. 9. the ck/ck input reference level (for timing referenced to ck/ck ) is the point at which ck and ck cross; the input reference level for signals other than ck/ck , is vref. 10. the output timing reference voltage level is vtt. 11. thz and tlz transitions occur in the same access time window s as valid data transitions. thes e parameters are not reference d to a specific voltage level but specify when the device output is no longer driving (hz), or begins driving (lz). 12. the maximum limit for this parameter is not a device limit. the device will operate with a gr eater value for this parameter , but sys tem performance (bus turnaround) will degrade accordingly. 13. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this ck edge . a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, dqs will be transitioning from high- z to logic low. if a previous write was in progress, dq s could be high, low, or transitioning from high to low at this time, depending on tdqss. 14. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 15. for command/address input slew rate 1.0 v/ns 16. for command/address input slew rate 0.5 v/ns and < 1.0 v/ns 17. for ck & ck slew rate 1.0 v/ns 18. these parameters guarantee device timing, but they are not necessarily tested on each device. they may be guaranteed by de vice design or tester correlation. 19. slew rate is measured between voh(ac) and vol(ac). 20. min (tcl, tch) refers to the smaller of the actual clock lo w time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tcl and tch).....for example, tcl and tch ar e = 50% of the period, less the half per iod jitter (tjit(hp)) of the clock source, and less the half peri od jitter due to crosstalk (tjit(cro sstalk)) into the clock traces. 21. tqh = thp - tqhs, where: thp = minimum half clock period for any given cycle and is defi ned by clock high or clock low (tch, tcl). tqhs accounts for 1) the pulse duration dis- tortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one tansition followed by the worst case pull-in o f dq on the next transi- tion, both of which are, separately, due to data pin skew and output pattern effects, and p channel to n-channel variation of the output drivers. 22. tdqsq - consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers fo r any given cycle. 23. tdal = (twr/tck) + (trp/tck) for each of the terms above, if not already an integer, round to the next highest integer. example: for ddr266b at cl=2.5 and tck=7.5ns tdal = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tdal = 5 clocks output vddq 50 ? 30pf (vout) figure 1 : timing reference load 14.0 component notes
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 b. pulldown slew rate is measured under the test conditions shown in figure 3. output test point vddq 50 ? figure 3 : pulldown sl ew rate test load c. pullup slew rate is measured between (vddq/2 - 320 mv +/- 250 mv) pulldown slew rate is measured between (vddq/2 + 320 mv +/- 250 mv) pullup and pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only on e output switching. example : for typical slew rate, dq0 is switching for minmum slew rate, all dq bits are switching from either high to low, or low to high. the remaining dq bits remain the same as for previous state. d. evaluation conditions typical : 25 c (t ambient), vddq = 2.5v(for ddr266/33 3) and 2.6v(for ddr400), typical process minimum : 70 c (t ambient), vddq = 2.3v(for ddr266/333) and 2.5v(for ddr400), slow - slow process maximum : 0 c (t ambient), vddq = 2.7v(for ddr266/333) and 2.7v(for ddr400), fast - fast process e. the ratio of pullup slew rate to pulldown slew rate is s pecified for the same temperature and voltage, over the entire tempe rature and voltage range. for a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. verified under typical conditi ons for qualification purposes. g. tsopii package divices only. h. only intended for operation up to 266 mbps per pin. i. a derating factor will be used to increase tis and tih in the case where the input slew rate is below 0.5v/ns as shown in ta ble 2. the input slew rate is based on the lesser of the slew rates detemined by either vih(ac) to vil(ac) or vih(dc) to vi l(dc), similarly for rising trans itions. j. a derating factor will be used to increase tds and tdh in the case where dq, dm, and dqs slew rates differ, as shown in tabl es 3 & 4. input slew rate is based on the larger of ac-ac delta rise, fall rate and dc-dc del ta rise, input slew rate is based on the lesser of the slew rates determined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), similarly for rising transitions. the delta rise/fall ra te is calculated as: {1/(s lew rate1)} - {1/(slew rate2)} for example : if slew rate 1 is 0.5 v/ns and slew rate 2 is 0.4 v/ns, then the delta rise, fall rate is - 0.5ns/v . using the table given, this would result in the need for an increase in tds and tdh of 100 ps. k. table 3 is used to increase tds and tdh in the case where the i/o slew rate is below 0.5 v/ns. the i/o slew rate is based on the lesser on the lesser of the ac - ac slew rate and the dc- dc slew rate. the inut slew rate is based on the lesser of the slew rates deter mined by eith er vih(ac) to vil(ac) or vih(dc) to vil(dc), and similarly for rising transitions. l. dqs, dm, and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal tr ansi tions through the dc region must be monotonic. m. in case of registered dimm, device operation defines power up and power management. 184-pin double data rate (ddr) registered dimms include tw o new features to facilitate controlled power-up and to minimize power consumption during low power mode. one feature is externally controlled via a system-generated reset signal; the second is based on module detection of the input clocks. these enhancements permit the modules to power up wi th sdram outputs in a high-z state (eliminating risk of high current dissipations and/or dotted i/os), and result in the powering-down of module support devices (registers and phase-locked loop) when the memor y is in self- refresh mode. device operation describes this more detailly. a. pullup slew rate is characteristized under the test conditions as shown in figure 2. output test point vssq 50 ? figure 2 : pullup slew rate test load 15.0 system notes:
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 (v=valid, x=don t care, h=logic high, l=logic low) note : 1. op code : operand code. a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2. emrs/ mrs can be issued only at all banks precharge state. a new command can be i ssued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be iss ued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the as sociated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and da ta-in are masked at the both edges (write dm latency is 0). 9. this combination is not defined for any functi on, which means "no operation(nop)" in ddr sdram. command cken-1 cken cs ras cas we ba0,1 a10/ap a0 ~ a9 a11, a12 note register extended mrs h x l l l l op code 1, 2 register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll lh x 3 self refresh entry l 3 exit l h lh hh x 3 hx x x 3 bank active & row addr. h x l l h h v row address (a0~a9, a11,a12) read & column address auto precharge disable hxlhlhv l column address 4 auto precharge enable h 4 write & column address auto precharge disable hxlhllv l column address 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks x h 5 active power down entry h l hx x x x lv vv exit l h x x x x precharge power down mode entry h l hx x x x lh hh exit l h hx x x lv vv dm h x x 8 no operation (nop) : not defined h x hx x x x 9 lh hh 9 16.0 command truth table
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 units : inches (millimeters) tolerances : 0.005(.13) unless ot herwise specified the used device is 64mx8 ddr sdram, tsopii sdram part no : k4h510838c a b reg pll a b 5.25 0.005 5.171 (131.350) (133.350 0.13 ) (30.48 +/-0.15) 1.2 +/-0.06 5.077 (128.950) 0.393 (10.00) (19.80) 0.78 (17.80) 0.7 0.10 m cba r (2.00) 0.0787 (3.00 min) 0.118 min reg 0.157 max 0.050 0.0039 (1.270 0.10) (3.99 max) (4.00) (0.157) 0.050 0.0078 0.006 (0.20 0.15) (1.270) 0.100 0.0079 (2.50 0.2 ) detail b 0.250 (6.350) detail a 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 0.10 m c a 0.1496 (3.00 min) 0.118 min r (2.00) 0.0787 (4.00 0.1 ) 0.1575 0.004 m b 0.100 (2.30) 2.500 +0.1/-0.0 17.1 64m x 72 (m312l6523cus) 17.0 physical dimensions
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 units : inches (millimeters) tolerances : 0.005(.13) unless ot herwise specified the used device is 64mx8, 128mx4 ddrsdram, tsopii sdram part no. : k4h510838c, k4h510438c a b reg pll a b 5.25 0.005 5.171 (131.350) (133.350 0.13 ) 5.077 (128.950) 0.393 (10.00) (19.80) 0.78 (17.80) 0.7 0.10 m cba r (2.00) 0.0787 reg 0.157 max 0.050 0.0039 (1.270 0.10) (3.99 max) (4.00) (0.157) (30.48 +/-0.15) 1.2 +/-0.06 (3.00 min) 0.118 min 0.050 0.0078 0.006 (0.20 0.15) (1.270) 0.100 0.0079 (2.50 0.2 ) detail b 0.250 (6.350) detail a 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 0.10 m c a 0.1496 (3.00 min) 0.118 min r (2.00) 0.0787 (4.00 0.1 ) 0.1575 0.004 m b 0.100 (2.30) 2.500 +0.1/-0.0 17.2 128mx72 (m3 12l2923cus), 128mx7 2 (m312l2920cus)
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 units : inches (millimeters) tolerances : 0.005(.13) unless otherwise specified the used device is st.256mx4 sdram, 66tsopii sdram part no : k4h1g0638c a b pll a b 5.25 0.005 5.171 (131.350) (133.350 0.13 ) 5.077 (128.950) 0.393 (10.00) (19.80) 0.78 (17.80) 0.7 0.10 m cba r (2.00) 0.0787 reg. 0.268 max 0.050 0.0039 (1.270 0.10) (6.81 max) (4.00) (0.157) (30.48 +/-0.15) 1.2 +/-0.06 (3.00 min) 0.118 min 0.100 (2.30) 2.500 +0.1/-0.0 0.050 0.0078 0.006 (0.20 0.15) (1.270) 0.100 0.0079 (2.50 0.2 ) detail b 0.250 (6.350) detail a 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 0.10 m c a 0.1496 (3.00 min) 0.118 min r (2.00) 0.0787 (4.00 0.1 ) 0.1575 0.004 m b 17.3 st.256mx72 (m312l5628cu0)
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 tolerances : 0.005(.13) unless otherwise specified the used device is 64mx8 ddr sdram, fbga ddr sdram part no. : k4h510838c-z***, 133.35 a 128.95 a 2x 3.00 min w1 4x 4.00+/-0.1 v1 64.77 p2 49.53 p3 120.65 p1 19.80 b1 28.575 +/-0.15 b 6.35 a b 10.00 b2 1 92 detail b detail a 3.80 w x1 x2 6.35 x 2.175 4.175 v 1.80 d 1.0 +/-0.05 0.20 +/-0.15 t 2.50 g e 1.27 max 0.178 d1 units : millimeters 2.99 max 12.00 184 93 1.27 +/-0.1 2x dia. 2.50 +0.1/-0.00 n 17.4 64mx72 (m312l6523cz3)
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 tolerances : 0.005(.13) unless otherwise specified the used device is 64mx8, 128mx4 ddr sdram, fbga ddr sdram part no. : k4h510838c-z***, k4h510438c-z*** 133.35 a 128.95 a 2x 3.00 min w1 4x 4.00+/-0.1 v1 64.77 p2 49.53 p3 120.65 p1 19.80 b1 28.575 +/-0.15 b 6.35 a b 10.00 b2 1 92 detail b detail a 3.80 w x1 x2 6.35 x 2.175 4.175 v 1.80 d 1.0 +/-0.05 0.20 +/-0.15 t 2.50 g e 1.27 max 0.178 d1 units : millimeters 184 93 3.99 max 12.00 1.27 +/-0.1 2x dia. 2.50 +0.1/-0.00 n 17.5 128mx72 (m312l2923c z3), (m312l2920cz3)
ddr sdram 512mb, 1gb, 2gb registered dimm rev. 1.4 march 2006 tolerances : 0.005(.13) unless otherwise specified the used device is 128mx4 ddr sdram, fbga ddr sdram part no : k4h510438c-z*** units : millimeters 133.35 a 128.95 a 2x 3.00 min w1 4x 4.00+/-0.1 v1 64.77 p2 49.53 p3 120.65 p1 19.80 b1 30.48 +/-0.15 b 6.35 a b 10.00 b2 1 92 detail b detail a 3.80 w x1 x2 6.35 x 2.175 4.175 v 1.80 d 1.0 +/-0.05 0.20 +/-0.15 t 2.50 +/-0.2 g e 1.27 max 0.178 d1 3.99 max 12.0 10.0 184 93 1.27 +/-0.1 2x dia. 2.50 +0.1/-0.00 n 17.6 256mx72 (m312l5720cz3)

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