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keypad decoder and i/o expansion data sheet adp5589 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by ana log devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent right s of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2011C 2013 analog devices, inc. al l rights reserved. technical support www.analog.com features 16- element fifo for event recording 19 configurable i/os allowing functions such as key pad decoding for matrix up to 11 8 key press/release interrupts key pad lock/unlock g pio functions gpi with selectable interrupt level 100 k ? or 300 k ? pull - u p resistors 300 k ? pull - down resistors gpo with push - pull or open drain dual programmable logic blocks pwm generator internal pwm generation external pwm with internal pwm and function c lock divider reset generator s i 2 c interface with f ast - mode plus (fm+) support up to 1 m hz open - drain interrupt output 24- lead lfcsp 3.5 mm 3.5 mm 25- ball wlcsp 1.99 mm 1.99 mm applications devices requiring keypad entry and i/o expansion capabilities functional block dia gram sda gpi scan and decode uvlo por i 2 c interface oscillator registers key scan and decode logic 1 i/o config int rst logic 2 clk div pwm scl vdd adp5589 gnd reset 1 gen reset 2 gen 09714-001 r0 r3 r1 r2 r4 r7 r5 r6 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 figure 1 . gene ral description the adp5589 is a 19 i/o port expander with built - in keypad matrix decoder, programmable logic, reset generator, and pwm generator. i/o expander ics are used in portable dev ices (phones, remot e controls, and cameras) and non portable applicat ions (healthcare, industrial, and instrumentation) . i/o expanders can be used to increase the number of i/os available to a processor or to reduce the number of i/os required through interface connectors for front panel designs. the adp5589 , which handles all key scanning and decoding , can flag the main processor via an interrupt line when new key events have occurred. in addition, gpi cha nges and logic changes c an be tracked as events via the fifo, eliminating the need to monitor different registers for event changes. the adp5589 is equipped with a fifo to store up to 16 events. events can be read back by the process or via an i 2 c compatible interface. the adp5589 frees up the main processor from having to monitor the keypad, thereby reducing power consumption and/or increasing processor bandwidth for performing other func tions. the programmable logic functions allow common logic requirements to be integrated as part of the gpio expander, saving board area and cost.
adp5589 data sheet rev. b | page 2 of 52 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 quick device overview ................................................................... 7 device enable ................................................................................ 8 device overview .......................................................................... 8 detailed description ........................................................................ 9 event fifo .....................................................................................9 key scan control ...........................................................................9 gpo output ................................................................................ 15 logic blocks ................................................................................ 16 pwm block ................................................................................. 17 clock divider block ................................................................... 17 reset blocks ................................................................................ 17 interrupts ..................................................................................... 18 register interface ............................................................................ 19 register map ................................................................................... 21 detailed register descriptions ................................................. 23 application diagram ...................................................................... 48 outline dimensions ....................................................................... 49 ordering guide .......................................................................... 49 revision history 1/1 3 rev. a to rev. b changes to detailed register descriptions section and table 7 .............................................................................................. 22 changes to table 33 and table 34 ................................................ 29 changes to table 36 ........................................................................ 30 changes to table 37 ........................................................................ 31 changes to table 69 ........................................................................ 41 changes to table 84 ........................................................................ 46 changes to figure 31 ...................................................................... 48 8 /11 revision a : initial version
data sheet adp5589 rev. b | page 3 of 52 specifications vdd = 1.8 v to 3.3 v, t a = ? 40 c to + 85?c , unless otherwise noted. 1 table 1. parameter symbol test conditions /comments min typ max unit supply voltage vdd input voltage range vdd 1. 65 3.6 v underv oltage lockout threshold uvlo vdd uvlo active, vdd f alling 1.2 1.3 v uvlo inactive, vdd rising 1.4 1. 6 v supply current standby current i stnby v dd = 1.65 v 1 4 a v dd = 3.3 v 1 10 a operating current (one key press ) i scan = 10 m s core_freq = 50 khz, scan active, 300 k ? pull - up, vdd = 1.6 5 v 30 40 a i scan = 10 m s core_freq = 50 khz, scan active, 100 k ? pull - up, vdd = 1.65 v 35 45 a i scan = 10 m s core_freq = 50 khz, scan active, 300 k ? pull - up, vdd = 3.3 v 75 85 a i scan = 10 m s core _freq = 50 khz, scan active, 100 k ? pull - up, vd d = 3.3 v 80 90 a pull - up, pull - down resistance pull - up option 1 50 100 150 k? pull - up option 2 150 300 450 k? pull - down 150 300 450 k? input logic level ( rst , scl, sda, r0, r1, r2, r3, r4, r5, r6, r7, c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10) logic low input voltage v il 0 .3 vdd v logic high input voltage v ih 0 .7 vdd v input leakage current (per pin ) v i - leak 0.1 1 a push - pull output logic level (r0, r1, r2, r3, r4, r5, r6, r7, c0, c1, c2, c 3, c4, c5, c6, c7, c8, c9, c10) logic low output voltage 2 v ol sink current = 10 ma 0.4 v logic low output voltage 3 v ol sink current = 10 ma 0.5 v logic high output voltage v oh source current = 5 ma 0 .7 vdd v logic high leakage current (pe r pin ) v oh - leak 0.1 1 a open - drain output logic level ( int , sda) logic low output voltage ( int ) v ol i sink = 10 ma 0.4 v logic low output voltage (sda) v ol i sink = 20 ma 0.4 v logic high leakage current (per pin ) v oh - leak 0.1 1 a logic propagation delay 125 300 ns ff1 hold time 4 0 ns ff1 setup time 4 175 ns ff2 hold time 4 0 ns ff2 set up time 4 175 ns gpio debounce 4 70 s internal oscillator frequency 5 osc freq 900 1000 1100 khz i 2 c timing specifications delay from uvlo/reset ina ctive to i 2 c access 60 s scl clock frequency f scl 0 1000 khz scl high time t high 0.26 s scl low time t low 0.5 s data setup time t su ; dat 50 ns data hold time t hd ; dat 0 s setup time for repeated start t su ; sta 0.26 s
adp5589 data sheet rev. b | page 4 of 52 parameter symbol test conditions /comments min typ max unit hold t ime for start/repeated start t hd ; sta 0.26 s bus free time for stop and start condition t buf 0.5 s setup time for stop condition t su ; sto 0.26 s data valid time t vd; dat 0.45 s data valid acknowledge t vd; ack 0.45 s rise time for s cl and sda t r 120 ns fall time for scl and sda t f 120 ns pulse width of suppressed spike t sp 0 50 ns capacitive load for each bus line c b 6 550 pf 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc ). typical values are at t a = 25c, vdd = 1.8 v. 2 maximum of five gpios active simultaneously. 3 all gpios active simultaneously. 4 guaranteed by design. 5 all timers are referenced from the base oscillator and have the same 10% accuracy. 6 c b is the to tal capacitance of one bus line in picofarads. sda scl sda scl s sr p s first clock cycle ninth clock ninth clock 1/ f sc l 70% 30% 70% 30% 70% 30% 70% 30% 70% 30% 70% 30% 70% 30% t f t f t r t r t high t vd; d a t t su; d a t t su; s t a t hd; d a t t hd; s t a t vd; ack t sp t su; s t o t buf t low t hd; s t a v il = 0.3vdd v ih = 0.7vdd 09714-002 figure 2 . i 2 c interface timing diagram
data sheet adp5589 rev. b | page 5 of 52 absolute maximum rat ings table 2. parameter rating vdd to ground C 0.3 v to 4 v scl , sda , rst , int , r0 , r1 , r2 , r3 , r4 , r5 , r6 , r7 , c0, c1, c2, c3, c4, c5, c6, c7 , c8, c9, c10 to ground C 0.3 v to (vdd + 0.3 v) operating ambient temperature range ? 40 c to +85 c 1 operating junction temperature range ? 40c to +125c storage temperature range ? 65c to +150c soldering conditions jedec j - std -020 1 in applications where high power dissipation and poor thermal resistance are present, the maximum amb ient temperature may have to be derated. maximum ambient temperature (t a(max) ) is dependent on the maximum operating junction temperature (t j(maxop) = 125c), the maximum power dissipation of the device (p d(max) ), and the junction - to - ambient thermal resist ance of the part/package in the application ( ja ), using the following equation: t a(max) = t j(maxop) ? ( ja p d(max) ). stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; fun ctional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. abso lute maximum ratings apply individually only, not in combination. unless otherwise specified, all other voltages are referenced to ground . thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3. thermal resistance ja unit 24- lead lfcsp 43.83 c/w maximum power dissipation 120 mw 25- ball wl csp 43 c/w maximum power dissipation 120 m w esd caution
adp5589 data sheet rev. b | page 6 of 52 pin configuration and fu nction descriptions 09714-003 2 1 3 4 5 6 1 8 1 7 1 6 1 5 1 4 1 3 r 2 r 3 r 4 r 5 n o t e s 1 . t h e e x p o s e d p a d m u s t b e c o n n e c t e d t o g r o u n d . r 6 r 7 c 4 c 5 c 6 c 7 r s t v d d 8 9 1 0 1 1 7 r 0 c 0 c 1 c 2 1 2 c 3 r 1 2 0 1 9 2 1 c 9 c 8 c 1 0 2 2 s d a 2 3 s c l 2 4 i n t adp5589 top view (not to scale) 1 a b c d e 234 balla1 corner vdd sda scl gnd c 10 r0 int rst c0 c9 r2 r1 c1 c2 c8 r4 r3 c3 c4 c7 r5 r6 r7 c5 c6 5 09714-104 top view (ball side down) not to scale figure 3. lfcsp pin configuration figure 4. wlcsp pin configuration table 4. pin function descriptions pin no. (lfcsp) pin no. (wlcsp) mnemonic description 1 e3 r7 gpio 8. this pin functions as row 7 if used as keypad. 2 e2 r6 gpio 7. this pin functions as row 6 if used as keypad. 3 e1 r5 gpio 6. this pin functions as row 5 if used as keypad. 4 d1 r4 gpio 5 (gpio alternate function: reset1). this pin functions as row 4 if used as keypad. 5 d2 r3 gpio 4 (gpio alternate function: lc1, pwm_out, or clk_out. this pin functions as row 3 if used as keypad. 6 c1 r2 gpio 3 (gpio alternate function: lb1). this pi n functions as row 2 if used as a keypad. 7 c2 r1 gpio 2 (gpio alternate function: la1). this pi n functions as row 1 if used as a keypad. 8 b1 r0 gpio 1 (gpio alternate function: ly1). this pi n functions as row 0 if used as a keypad. 9 b4 c0 gpio 9. this pin functions as column 0 if used as keypad. 10 c3 c1 gpio 10. this pin functions as column 1 if used as keypad. 11 c4 c2 gpio 11. this pin functions as column 2 if used as keypad. 12 d3 c3 gpio 12. this pin functions as column 3 if used as keypad. 13 d4 c4 gpio 13 (gpio alternate function: reset2). this pin functions as column 4 if used as keypad. 14 e4 c5 gpio 14. this pin functions as column 5 if used as keypad. 15 e5 c6 gpio 15 (gpio alternate function: lc2, pwm_in, or clk_in). this pin functions as column 6 if used as keypad. 16 d5 c7 gpio 16 (gpio alternate function: lb2). this pi n functions as column 7 if used as keypad. 17 b3 rst input reset signal. 18 a1 vdd supply voltage input. 19 c5 c8 gpio 17 (gpio alternate function: la2). this pi n functions as column 8 if used as keypad. 20 b5 c9 gpio 18 (gpio alternate function: ly2). this pi n functions as column 9 if used as keypad. 21 a5 c10 gpio 19. this pin functions as column 10 if used as keypad. 22 a2 sda i 2 c data input/output. 23 a3 scl i 2 c clock input. 24 b2 int open-drain interrupt output. ep (pad) a4 gnd ground. the exposed pad of the lfcsp pa ckage must be connected to ground.
data sheet adp5589 rev. b | page 7 of 52 quick device overview row 0 sda fifo update uvlo por i 2 c interface i 2 c busy? oscillator registers key scan and decode gpi scan and decode logic 1 i/o configuration int rst row 1 row 2 row 3 row 4 row 5 row 6 row 7 col 1 col 0 col 2 col 3 col 4 col 5 col 6 col 7 col 8 col 10 col 9 (r0) (r1) (r2) (r3) (r4) (r5) (r6) (r7) (c0) (c1) (c2) (c3) (c4) (c5) (c6) (c7) (c8) (c9) (c10) (r0) (r1) (r2) (r3) (r1) (r2) (r3) (r0) (r4) (r5) (r6) (r7) (c0) (c1) (c2) (c3) (c4) (c5) (c6) (r3) (c6) (c7) (c8) (c9) (c6) (c7) (c8) (c9) (c10) gpio 1 la1 gpio 2 gpio 3 gpio 4 gpio 5 gpio 6 gpio 7 gpio 8 gpio 9 gpio 10 gpio 11 gpio 12 gpio 13 gpio 14 gpio 15 gpio 16 gpio 17 gpio 18 gpio 19 lb1 lc1 ly1 la2 lb2 lc2 ly2 logic 2 clk div clk_in clk_out pwm (r3) (c6) pwm_in pwm_out (r4) reset1 (c4) reset2 key event gpi event logic event scl v dd adp5589 gnd r0 r3 r1 r2 r4 r7 r5 r6 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 reset1 gen reset2 gen rst 0 9714-004 figure 5. internal block diagram
adp5589 data sheet rev. b | page 8 of 52 device enable when sufficient voltage is applied to vdd and the rst pin is driven with a logic high level, the adp5589 starts up in standby mode with all settings at default. the user can configure the device via the i 2 c interface. when the rst pin is low, the adp5589 enters a reset state and all setting s return to default. the rst pin features a debounce filter. device overview the adp5589 contains 19 multiconfigurable input/output pins. each pin can be programmed to enable the device to carry out its various functions, as follows: ? keypad matrix decoding (11 - column by 8 - row matrix max imum ) . ? general - purpose i/o expansion (up to 19 inputs/outputs ) . ? pwm generation . ? clock division of externally supplied source . ? dual logic fu nction building blocks (up to three inputs, one output) . ? two reset generators . all 19 input/output pins have an i/o st ructure , as shown in figure 6 . i/o vdd 100k? i/o drive debounce 300k? 300k? 09714-005 figure 6 . i/o structure each i/o can be pulled up with a 100 k ? or 300 k ? resistor or pulled down with a 300 k ? resistor. for logic output drive, each i/o has a 5 ma pmos source and a 10 ma nmos sink for push - pull type output. for open - drain output situations, the 5 ma pmos source is not enabled. for logic in put applications, each i/o can be sampled directly or , alternatively, s ampled through a debounce filter. the i/o structure shown in figure 6 allows for all gpi and gpo functions , as well as pwm and clock divide fun ctions. for key matrix scan and decode, the scanning circuit uses the 100 k ? or 300 k ? resistor for pulling up keypad row pins and the 10 ma nmos sinks for grounding keypad column pins (see the key scan control s ection for details about key decoding). configuration of the device is carrie d out by programming an array of internal registers via the i 2 c interface. feedback of device status and pending interrupts can be flagged to an external processor via the int pin . the ad p5589 is offered with three feature sets . table 5 lists the options that are available for each model of the adp5589 . table 5. available optio ns model s description adp5589acpz - 00-r7 adp5589acbz - 00-r7 all gpio s pulled up ( d efault option) adp5589acpz - 01-r7 adp5589acbz - 01-r7 reset pass - thr ough 1 adp5589acpz - 02-r7 adp5589acbz - 02-r7 pull - d own on special function pins 2 1 reset pass - through implies that the reset1 output (r4) follows the logic level of the reset input pin, rst , after the oscillator has been enabled. 2 special function pins are defined as r0 ( row 0 ) , r3 ( row 3 ) , r4 ( row 4 ) , c4 ( column 4 ) , c6 ( column 6 ) , and c9 ( colu mn 9 ) .
data sheet adp5589 rev. b | page 9 of 52 d etailed d escription e vent fifo it is important to understand the function of the event fifo. the adp5589 features an event fifo that can record as many as 16 eve nts. by default, the fifo primarily records key events, such as key press and key release. however, it is possible to configure the general - purpose input (gpi) and logic activity to generate event information on the fifo as well. an event count, ec[4:0], is composed of five bits and works i n tandem with the fifo so that the user knows how much of the fifo must be read back at any given time. the fifo is composed of 16 eight - bit sections that the user accesses by reading the fifo_x registers. the actual fifo is not in user accessible registe rs until a read occurs. the fifo can be thought of as a first in , first out buffer used to fill register 0x03 to register 0x12. the event fifo is made up of 16 eight - bit registers. in each register, bits[6:0] hold the event identifier, and bit 7 holds the event stat e. with seven bits, 127 different events can be identified. see table 11 for event decoding. event1[7:0] e ve n t 8_ i d e n t i f i e r[6:0] event2[7:0] event3[7:0] event4[7:0] event13[7:0] event14[7:0] event15[7:0] event16[7:0] event5[7:0] event6[7:0] event7[7:0] event8[7:0] event9[7:0] event10[7:0] event11[7:0] event12[7:0] 7 e ve n t 8_ s t a t e fifo update gpi events ec[4:0] ovrflow_int key events logic events 6 5 4 3 2 1 0 09714-006 figure 7 . breakdown of event x [7:0] bits when events are available on the fifo, the user should first read back the event count, ec[4:0], to determine how many events must be read back. events can be read from the top of the fifo only. when an event is read back, all remaining events in the fifo are shifted up one location, and the ec [4:0] count is decremented. key 3 pressed key 3 released gpi 7 active ec = 3 first read key 3 released gpi 7 active ec = 2 second read gpi 7 active ec = 1 third read ec = 0 09714-007 figure 8 . fifo operation the fifo registers (0x03 to 0x12) always point to the top of the fifo (that is, the location of event1[7:0]). if the user tries to read back from any location in a fifo, data is always obtained from the top of that fifo. this ensures that events can only be read back in the order in which they occurred, thus ensuring the integrity of the fifo system. some of the onboard functions of adp5589 can be program - med to generate events on the fifo. a fifo update control block manages updates to the fifo. if an i 2 c transaction is accessing any of the fifo address locations, updates are paused until the i 2 c transaction has completed. a fifo o verflow event occurs when more than 16 events are generated prior to an external processor reading a fifo and clearing it. if an overflow condition occurs, the overflow status bit is set. an interrupt is generated if overflow interrupt is enabled, signalin g to the processor that more than 16 events have occurred. k ey s can c ontrol general the 19 input/output pins can be configured to decode a keypad matrix up to a maximum size of 88 switches (11 8 matrix). smaller matrices can also be configured, freeing u p the unused row and column pins for other i/o functions. the r0 through r7 i/o pins comprise the rows of the keypad matrix . the c0 through c10 i/o pins comprise the columns of the keyp ad matrix. pins used as rows are pulled up via the internal 300 k (or 100 k) resistors. pins used as columns are driven low via the internal nmos current sink.
adp5589 data sheet rev. b | page 10 of 52 key scan control 1 2 3 4 5 6 7 8 9 v d d r0 r1 r2 c2 c0 c1 3 3 keypad matrix 09714-008 figure 9 . simplified key scan block figure 9 shows a simplified representation of the key scan block using three row and three column pins connected to a small 3 3, nine - switch keypad matrix. when the key scanner is idle, the row pins are pulled high and the column pins are driven low. the key scanner operates by checking the row pins to see if they are low. if switch 6 in the matrix is pressed, r1 connects to c2. the key scan circuit senses that one of the row pins is pulled low, and a key scan cycle begins. key scanning involves driving all column pins high, then driving each column p in, one at a time, low and sensing whether a row pin is low or not. all row/column pairs are scanned; therefore, if multiple keys are pressed, they are detected. to prevent glitches or narrow press times being registered as a valid key press, the key scan ner requires the key be pressed for two scan cycles. the key scanner has a wait time between each scan cycle; therefore, the key must be pressed and held for at least this wait time to register as being pressed. if the key is continuously pressed, the key scanner continues to scan, wait, scan, wait, and so forth. if switch 6 is released, the connection between r1 and c2 breaks, and r1 is pulled up high. the key scanner requires that the key be released for two scan cycles because the release of a key is not necessarily in sync with the key scanner, it may take up to two full wait/scan cycles for a key to register as released. when the key is registered as released, and no other keys are pressed, the key scanner returns to idle mode. for the remainder of this document, the press/release status of a key is represented as simply a logic signal in the figures. a logic high level represents the key status as pressed, and a logic low represents released. this eliminates the need to draw individual row/column signal s when describing key events. ke y x ke y released ke y released ke y pressed 09714-009 figure 10 . logic low: released; logic high: pressed figure 11 shows a detailed representation of the key scan block and its associated control and status sig nals. when all row and column pins are used, a matrix of 88 unique keys can be scanned.
data sheet adp5589 rev. b | page 11 of 52 logic event 567891011 4321 16 17 18 19 20 21 22 15141312 27 28 29 30 31 32 33 26252423 38 39 40 41 42 43 44 37363534 49 50 51 52 53 54 55 48474645 60 61 62 63 64 65 66 59585756 71 72 73 74 75 76 77 70696867 82 83 84 85 86 87 88 81807978 fifo update key scan control i/o configuration key event gpi event i 2 c busy? r0 r3r1 r2 r4 r7r5 r6 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 column sink on/off pin_config_a[7:0] pin_config_b[7:0] row sense fifo pin_config_c[2:0] unlock1[7:0] unlock2[7:0] ext_lock_event[7:0] unlock_timer[2:0] int_mask_timer[4:0] lock_en lock_stat event_int ovrflow_int lock_int ec[4:0] reset_trigger_time[2:0] reset1_event_a[7:0] reset1_event_b[7:0] reset1_event_c[7:0] 89 91 96 95 94 90 93 92 reset2_event_a[7:0] reset2_event_b[7:0] reset 1_initiate reset 2_initiate 09714-010 figure 11. detailed key scan block use registers pin_config_a[7:0] (0x49), pin_config_b[7:0] (0x4a), and pin_config_c[2:0] (0x4b) to configure i/os for keypad decoding. the number label on each key switch represents the event identifier that is recorded if that switch is pressed. if all row/column pins are configured, it is possible to observe all 88 key identifiers on the fifo. if a smaller 3 3 matrix is configured, for example, using the c5, c6, and c7 column pins and the r1, r2, and r3 row pins, only the nine event identifiers (17, 18, 19, 28, 29, 30, 39, 40, and 41) can possibly be observed on the fifo, as shown in figure 11. by default, the adp5589 records key presses and releases on the fifo. figure 12 illustrates what happens when a single key is pressed and released. initially, the key scanner is idle. when key 32 is pressed, the scanner begins scanning through all configured row/column pairs. after the scan wait time, the scanner again scans through all configured row/column pairs and detects that key 32 has remained pressed, which sets the event_int interrupt. the event counter, ec[4:0], is incre- mented to 1, event1[7:0] of the fifo is updated with its event identifier set to 32, and its event1_state bit is set to 1, indicating a press. key 32 key 32 press key 32 release key scan event_int ec[4:0] fifo 1 2 1 0 0 0 32 32 0 0 09714-011 figure 12. press and release event the key scanner continues the scan/wait cycles while the key remains pressed. if the scanner detects that the key has been released for two consecutive scan cycles, the event counter ec[4:0] is incremented to 2, and event2[7:0] of the fifo is updated with its event identifier set to 32. its event2_state bit is set to 0, indicating a release. the key scanner goes back to idle mode because no other keys are pressed. the event_int interrupt can be triggered by both press and release key events. as shown in figure 13, if key 32 is pressed, event_int is asserted, ec[4:0] is updated, and the fifo is updated. during the time that the key is still pressed, it is possible for the fifo to be read, the event counter decremented to 0, and event_int cleared. when the key is finally released, event_int is asserted, the event counter incremented, and the fifo updated with the release event information.
adp5589 data sheet rev. b | page 12 of 52 key 32 key 32 press key 32 release key scan event_int event_int cleared ec[4:0] fifo fifo read 0 0 0 0 0 0 0 0 fifo 1 0 0 0 32 0 0 0 fifo 101 0 0 0 0 32 0 0 0 09714-012 figure 13. asserting the event_int interrupt key pad extension as shown in figure 11, the keypad can be extended if each row is connected directly to ground by a switch. if the switch placed between r0 and ground is pressed, the whole row is grounded. when the key scanner completes scanning, it normally detects key 1 to key 11 as being pressed; however, this unique condi- tion is decoded by the adp5589 , and key event 89 is assigned to it. up to eight more key event assignments are possible, allowing the keypad size to extend up to 96. however, if one of the extended keys is pressed, none of the keys on that row is detectable. activation of a ground key causes all other keys sharing that row to be undetectable. ghosting ghosting is an occurrence where, given certain key press com- binations on a keypad matrix, a false positive reading of an additional key is detected. ghosting is created when three or more keys are pressed simultaneously on multiple rows or columns (see figure 14). key combinations that form a right angle on the keypad matrix can cause ghosting. the solution to ghosting is to select a keypad matrix layout that takes into account three key combinations that are most likely to be pressed together. multiple keys pressed across one row or across one column do not cause ghosting. staggering keys so that they do not share a column also avoids ghosting. the most common practice is to place keys that are likely to be pressed together in the same row or column. some examples of keys that are likely to be pressed together are as follows: ? the navigation keys in combination with select. ? the navigation keys in combination with the space bar. ? the reset combination keys, such as ctrl + alt + del. col0 row0 row1 row2 row3 press ghost press press col1 col2 09714-013 figure 14. col0-row3 is a ghost key due to short between row0, col0, col2 and row3 during key press fifo lock/unlock the adp5589 features a lock mode, whereby events are pre- vented from updating the fifo or the event counter or from generating event_int interrupts until an unlock event is detected. the lock feature is enabled by setting the lock_en (0x37[0]) bit or, alternatively, by a user programmable key or gpi event (set via ext_lock_event[7:0], address 0x35). if the lock feature is enabled by the lock_en bit, the lock_stat (0x02[5]) bit is set. if the lock feature is enabled by an external event, then the lock_stat bit is set, and a lock_int interrupt is generated. unlock events are programmed via the unlock1[7:0] (0x33) and unlock2[7:0] (0x34) registers. bits[6:0] comprise the even number. bit 7 determines the active/inactive event (see the unlock1 register 0x33 (table 59) and the unlock2 register 0x34 (table 60). if the user chooses to use only one unlock event, only the unlock1[7:0] register should be programmed. unlock events can be key press events (event 1 to event 88). key release events are ignored when the keypad is locked and should not be used as unlock events. gpis configured to generate fifo updates can also be used as unlock events (event 97 to event 115, either active or inactive). if either unlockx register is programmed with value 127 (event 127), this means that any allowable event (key or gpi) is the unlock event. for example, if unlock1[6:0] is programmed with 17, and unlock2[6:0] is programmed with 127, the unlock sequence is key 17 press followed by any other allowable event. if the first unlock event is detected, partial unlock has occurred. if the next event after the first unlock event is not the second unlock event, then a full lock state is entered again. if the next event after the first unlock event is the second unlock event, then lock_stat is cleared, and a lock_int interrupt is generated. the user can at any stage clear lock_en. this clears the lock_stat bit but does not cause a lock_int interrupt to be generated.
data sheet adp5589 rev. b | page 13 of 52 when full unlock is achieved, fifo and event count updates resume. note that if a key press is used as the second unlock event, the release of that key is captured on the fifo after unlocking is completed. the adp5589 features an unlock timer, unlock_timer[2:0] (0x3 6 [ 2 :0]) . when e nabled, after the first unlock event occurs, the unlock timer begins counting , and the second unlock event must occur before the unlock timer expires. if the unlock timer expires, the first unlo ck event must occur again to re start the unlock process. figure 15 shows a simple state diagram of the unlocking process. no first unlock event? unlock timer enabled? second unlock event required? start unlock timer unlock timer expired? unlock yes no yes second unlock event? no yes yes locked no no yes yes lock_stat = 0 lock_stat = 1 lock_stat = 1 event detected? yes no event detected? yes no event detected? no 09714-014 figure 15 . state diagram of unlocking process when lock mode is enabled, no e vent _int interrupts can be generated until the unl ock events occur. the adp5589 f eatures an interrupt mask timer, int_mask_ timer[4:0] (0x36[7: 3 ]) . when this timer and lock mode are enabled, a s ingle e vent _int is generated if any key is pressed or any gpi (pr ogrammed to update the fifo) is active. when the e vent _int is generated, the mask tim er begins counting. no additional e vent _int interrupts are generated until the mask timer expires and a new key is pressed or any gpi (programmed to update the fifo) is a ctive, unless the unlock events occur, in which case, normal operation is resumed. allowing a single event _int interrupt is useful to al ert the processor to turn on its screen and display an unlock message to the user. blanking out additional key presses e nsures that the processor is not unnecessarily interrupted until the u nlock events occur. figure 16 shows the unlock sequence when the interrupt mask timer is enabled.
adp5589 data sheet rev. b | page 14 of 52 no first unlock event? unlock timer enabled? second unlock event required? start unlock timer unlock timer expired? unlock yes yes yes no no no yes second unlock event? no yes yes locked no no yes yes lock_stat = 0 lock_stat = 1 lock_stat = 1 event detected? yes no event detected? yes no event detected? mask timer enabled? mask timer enabled? mask timer expired? set event_int = 1 start mask timer no yes yes no no mask timer expired? set event_int = 1 start mask timer mask timer enabled? yes yes no no mask timer expired? set event_int = 1 start mask timer 09714-015 figure 16 . unl ock sequence
data sheet adp5589 rev. b | page 15 of 52 gpi input each of the 19 i/o lines can be configured as a general-purpose logic input line. figure 17 shows a detailed representation of the gpi scan and detect block and all its associated control and status signals. pin_config_a[7:0] pin_config_b[7:0] pin_config_c[2:0] unlock1[7:0] unlock2[7:0] ext_lock_event[7:0] unlock_timer[2:0] int_mask_timer[4:0] lock_en gpi_int gpi scan control gpio 1 gpio 2 gpio 3 gpio 4 gpio 5 gpio 6 gpio 7 gpio 8 gpio 9 gpio 10 gpio 11 gpio 12 gpio 13 gpio 14 gpio 15 gpio 16 gpio 17 gpio 18 gpio 19 (r0) (r1) (r2) (r3) (r4) (r5) (r6) (r7) (c0) (c1) (c2) (c3) (c4) (c5) (c6) (c7) (c8) (c9) (c10) gpi event i 2 c busy? key event ovrflow_int logic event gpi_int_level_a[7:0] gpi_int_level_b[7:0] gpi_int_level_c[2:0] gpi_interrupt_en_a[7:0] gpio_direction_a[7:0] gpi_status_a[7:0] gpi_status_b[7:0] gpi_status_c[2:0] gpi_int_stat_a[7:0] lck_trk_gpi lock_stat lock_int gpi_event_en_a[7:0] gpio_direction_b[7:0] gpio_direction_c[2:0] gpi_interrupt_en_b[7:0] gpi_interrupt_en_c[2:0] gpi_event_en_b[7:0] gpi_event_en_c[2:0] event_int gpi_int_stat_b[7:0] gpi_int_stat_c[2:0] reset_trigger_time[2:0] reset1_event_a[7:0] reset1_event_b[7:0] reset1_event_c[7:0] reset2_event_a[7:0] reset2_event_b[7:0] fifo update fifo ec[4:0] 09714-016 figure 17. gpi scan and detect block the current input state of each gpi can be read back using the gpi_status_x registers. each gpi can be programmed to generate an interrupt via the gpi_interrupt_en_x registers. the interrupt status is stored in the gpi_int_stat_x registers. gpi interrupts can be programmed to trigger on inputs being high or on inputs being low via the gpi_int_level_x registers. if any of the gpi interrupts is triggered, the master gpi_int interrupt is also triggered. figure 18 demonstrates a single gpi and how it affects its corresponding status and interrupt status bits. cleared by read gpi 6 gpi_status_a[5] g pi_interrupt_en_a[5] gpi_int_stat_a[5] gpi_int gpi_int_level_a[5] cleared by write ?1? 09714-017 figure 18. single gpi example gpis can be programmed to generate fifo events via the gpi_event_en_x registers. gpis in this mode do not gener- ate gpi_int interrupts and instead generate event_int interrupts. figure 19 shows several gpi lines and their effects on the fifo and event count, ec[4:0]. gpi 2 gpi scan event_int ec[4:0] 16 gpi 2 active gpi 14 gpi 6 234 5 gpi 6 active gpi 14 active gpi 14 inactive gpi 6 active gpi 2 active fifo 1 1 1 0 0 0 101 101 105 105 113 113 09714-018 figure 19. multiple gpi lines example the gpi scanner is idle until it detects a level transition. it scans the gpi inputs and updates accordingly. it then returns to idle immediately; it does not scan/wait, like the key scanner. as such, the gpi scanner can detect narrow pulses once they get past the 50 s input debounce filter. gpis (programmed for fifo updating) can be used as keypad unlock events via the unlockx registers (see the fifo lock/unlock section). the lck_trk_gpi bit can be used to allow gpis (programmed for fifo updating) to be tracked when the keypad is locked. gpo output each of the 19 i/o lines can be configured as a general-purpose output (gpo) line. figure 6 shows a detailed diagram of the i/o structure. see the detailed register descriptions section for gpo configuration and usage.
adp5589 data sheet rev. b | page 16 of 52 logic blocks several of the adp5589 i/o lines can be used as inputs and outputs for implementing some common logi c functions. the r1, r2, and r3 i/o pins can be used as inputs, and the r0 i/o pin can be used as an output for logic block 1. the c8, c7, and c6 i/o pins can be used as inputs, and the c9 i/o pin can be used as an output, for logic block 2. it is also po ssible to cascade the output of logic block 1 as an alternate input for logic block 2 (ly1 is used instead of la2). the outputs from the logic blocks can be configured to generate interrupts. they can also be configured to generate events on the fifo. the lck_trk_logic (0x4d[4]) bit can be used to allow logic events (programmed for fifo updating) to be tracked when the keypad is locked. figure 21 and figure 22 show detailed diagrams of the internal make - up of each logic block, illustrating the possible logic functions that can be implemented. gpi event i 2 c busy? key event logic event (r1) la1 lc1 lb1 la1_inv logic event/int generator d clr q set lb1_inv lc1_inv ff1_set ff1_clr r3_extend_cfg[1:0] logic1_sel[2:0] ly1_inv la2_inv lb2_inv lc2_inv ff2_set ff2_clr c6_extend_cfg logic2_sel[2:0] ly2_inv (r2) (r3) (c8) la2 lc2 lb2 (c7) (c6) logic block1 logic block2 ly1 (r0) ly2 (c9) logic1_int logic2_int logic1_int_level fifo update logic2_int_level logic1_event_en logic2_event_en ovrflow_int event_int lck_trk_logic reset_trigger_time[2:0] reset1_event_a[7:0] reset1_event_b[7:0] reset1_event_c[7:0] reset2_event_a[7:0] reset2_event_b[7:0] fifo ec[4:0] d clr q set 09714-019 figure 20 . logic blocks overview la1_inv mux 000 001 sel[2:0] out 010 011 100 101 110 111 sel out 0 1 gnd and1 or1 xor1 ff1 in_la1 in_lb1 in_lc1 la1 la1 la1 in_la1 sel out 0 1 and1 in_la1 in_lb1 in_lc1 r3_extend_cfg[1:0] = 01 logic1_sel[2:0] ly1_inv sel out 0 1 ly1 ly1 ly1 lb1_inv sel out 0 1 lb1 lb1 lb1 in_lb1 lc1_inv sel out 0 1 lc1 lc1 lc1 in_lc1 ff1_set ff1_clr sel out 0 1 or1 in_la1 in_lb1 in_lc1 and and or or sel out 0 1 xor1 in_la1 in_lb1 in_lc1 in_la1 in_lb1 in_lc1 xor xor d clr q set 0 1 sel out 09714-020 ff1 figure 21 . logic block 1
data sheet adp5589 rev. b | page 17 of 52 la2_inv mux 000 001 sel[2:0] out 010 011 100 101 110 111 sel out 0 1 gnd and2 or2 xor2 ff2 in_la2 in_lb2 in_lc2 (ly1) la2 (ly1) la2 (in_ly1) in_la2 sel out 0 1 and2 (in_ly1) in_la2 in_lb2 in_lc2 c6_extend_cfg = 1 logic2_sel ly1_cascade la2 ly1 sel out 0 1 ly2_inv sel out 0 1 ly2 ly2 ly2 lb2_inv sel out 0 1 lb2 lb2 lb2 in_lb2 lc2_inv sel out 0 1 lc2 lc2 lc2 in_lc2 ff2_set ff2_clr sel out 0 1 or2 (in_ly1) in_la2 in_lb2 in_lc2 and and or or sel out 0 1 xor2 ff2 (in_ly1) in_la2 in_lb2 in_lc2 in_la2 in_lb2 in_lc2 xor xor d clr q set 0 1 sel out 09714-021 figure 22 . logic block 2 (r3) pwm_out (c6) pwm_in off time[15:0] pwm_en pwm_in_and pwm_offt_low_byte[7:0] pwm_mode pwm_offt_high_byte[7:0] pwm_ont_low_byte[7:0] pwm_ont_high_byte[7:0] on time[15:0] pwm generator sel out 0 1 09714-022 and figure 23 . pwm block diagram pwm b lock the adp5589 features a pwm generator whose output can be configured to drive out on i/o pin r3. pwm on/off times are programmed via four 8 - bit registers. newly programmed values are not latched until the final byte , pwm_ont_high_byte ( address 0x41 , bits[7:0] ), is written to (see figure 23 ) . the highest frequency obtain able from the pwm is performed by setting the least significant bit (lsb) of both the on and off bit patterns, resulting in a 500 khz signal with a 50% duty cycle. each lsb respresents 1 s of on or off time. the pwm block provides support for continuous p wm mode as well as a one - shot mode (see tabl e 74 ). additionally, an external signal can be anded with the internal pwm signal. this option can be selected by writing a 1 to pwm_in_and, pwm_cfg[2]. the input to the external and i s the c 6 i/o pin. c 6 should be set to gpi (gpio15) . note that the debounce for c 6 will result in a delay of the anding, and can be controlled using register gpi_15_deb_dis ( address 0x28, bit[6]) . newly programmed values are not latched until the final byt e, pwm_ont_high_byte ( address 0x 41 , bits[7:0]), is written. c lock d ivider b lock the adp5589 features a clock divider block that divides down the frequency of an externally supplied source via i/o pin c6. the o utput of the divider is driven out on i/o pin r3. clk_in (r3) clk_out (c6) clk_div_en clk_div[4:0] clk_inv clk divider sel out 0 1 09714-023 figure 24 . clock divider block r eset b lock s the adp5589 features two reset block s that can generate reset condition s if certain even ts are detected at the same time . up to three reset trigger events can be programmed for reset1 . up to two reset trigger eve nts can be programmed for reset 2. the event scan control block s monitor whether these events are present for the duration of reset_t rigger _time[2:0] (0x3d[4:2]) . if they are, reset - initiate signal s are sent to the reset genera tor block s . the generated reset signal pulse width is programmable.
adp5589 data sheet rev. b | page 18 of 52 reset_pulse_width[1:0] reset_trigger_time[2:0] reset1_event_a[7:0] reset1_event_b[7:0] reset1_event_c[7:0] k ey s ca n c on t r o l rst_passthru_en rst (r4) reset1 g p i s ca n c on t r o l log i c b l o c k c on t r o l reset2_event_a[7:0] reset2_event_b[7:0] (c4) reset2 reset1_ initiate reset2_ initiate reset gen 2 reset gen 1 09714-024 figure 25 . reset blocks the reset 1 s ignal uses i/o pin r4 as its o utput . a pass - through mode allows the main rst pin to be output on the r 4 pin also . the reset2 signal uses i/o pin c4 as its output . the reset generation signal s are useful in situations where the system processor has locked up and the system is unresponsive to input events. the user can press one of the reset event combina - tion s and initiate a system - wide reset. this alleviates the need for removing the battery from the system and performing a hard reset. it is not recommended to u se the immediate trigger time (see the details of the reset_cfg register, 0x3d, in table 69) because this setting may cause false triggering. interrupts the int pin can be asserted low if any of the internal interrupt sources is active. the user can select which internal interrupts interact with the external interrupt pin in register int_en ( address 0x4e , bits[7:0]) (refer to table 86 ). allows the user to choose whether the external interrupt pin remains asserted, or deasserts for 50 s, then reasserts, in the case that there are multiple internal interrupts asserted, and one is cleared (refer to table 85). event_int event_ien int drive int int_cfg gpi_int gpi_ien logic1_int logic2_int logic1_ien logic2_ien ovrflow_int ovrflow_ien lock_int lock_ien 09714-025 figure 26 . asserting int low
data sheet adp5589 rev. b | page 19 of 52 register interface register access of the adp5589 is acquired via its i 2 c-compatible serial interface. the interface can support clock frequencies of up to 1 mhz. if the user is accessing the fifo or key event counter (kec), fifo/kec updates are paused. if the clock frequency is very low, events may not be recorded in a timely manner. fifo or kec updates can happen up to 23 s after an interrupt is asserted because of the number of i 2 c cycles required to perform an i 2 c read or write. this delay should not present an issue to the user. figure 27 shows a typical write sequence for programming an internal register. the cycle begins with a start condition, followed by the hard coded 7-bit device address, which for the adp5589 is 0x34, followed by the r/ w bit set to 0 for a write cycle. the adp5589 acknowledges the address byte by pulling the data line low. the address of the register to which data is to be written is sent next. the adp5589 acknowledges the register pointer byte by pulling the data line low. the data byte to be written is sent next. the adp5589 acknowledges the data byte by pulling the data line low. a stop condition completes the sequence. figure 28 shows a typical multibyte write sequence for program- ming internal registers. the cycle begins with a start condition followed by the 7-bit device address (0x34), followed by the r/ w bit set to 0 for a write cycle. the adp5589 acknowledges the address byte by pulling the data line low. the address of the register to which data is to be written is sent next. the adp5589 acknowledges the register pointer byte by pulling the data line low. the data byte to be written is sent next. the adp5589 acknowledges the data byte by pulling the data line low. the pointer address is then incremented to write the next data byte, until it finishes writing the n data byte. the adp5589 pulls the data line low after every byte, and a stop condition completes the sequence. figure 29 shows a typical byte read sequence for reading internal registers. the cycle begins with a start condition followed by the 7-bit device address (0x34), followed by the r/ w bit set to 0 for a write cycle. the adp5589 acknowledges the address byte by pulling the data line low. the address of the register from which data is to be read is sent next. the adp5589 acknowledges the register pointer byte by pulling the data line low. a start condi- tion is repeated, followed by the 7-bit device address (0x34), followed by the r/ w bit set to 1 for a read cycle. the adp5589 acknowledges the address byte by pulling the data line low. the 8-bit data is then read. the host pulls the data line high (no acknowledge), and a stop cond ition completes the sequence. start 0 = writ e 7-bit device address adp5589 ack 8-bit register pointer 8-bit write data 00 0 0 adp5589 ack adp5589 ack stop 09714-026 figure 27. i 2 c single-byte write sequence start 0 = writ e 7-bit device address adp5589 ack 8-bit register pointer write byte 1 write byte 2 write byte n 00 0 0 0 0 0 adp5589 ack adp5589 ack adp5589 ack adp5589 ack adp5589 ack stop 09714-028 figure 28. i 2 c multibyte write sequence start 0 = write 7-bit device address 7-bit device address adp5589 ack 8-bit register pointer 8-bit read data 00 0 1 0 1 repeat start 1 = read adp5589 ack adp5589 ack no ack stop 09714-027 figure 29. i 2 c single-byte read sequence
adp5589 data sheet rev. b | page 20 of 52 figure 30 shows a typical multibyte read sequence for reading internal registers. the cycle begins with a start condition, followed by the 7-bit device address (0x34), followed by the r/ w bit set to 0 for a write cycle. the adp5589 acknowledges the address byte by pulling the data line low. the address of the register from which data is to be read is sent next. the adp5589 acknowl- edges the register pointer byte by pulling the data line low. a start condition is repeated, followed by the 7-bit device address (0x34), followed by the r/ w bit set to 1 for a read cycle. the adp5589 acknowledges the address byte by pulling the data line low. the 8-bit data is then read. the address pointer is then incremented to read the next data byte, and the host continues to pull the data line low for each byte (master acknowledge) until the n data byte is read. the host pulls the data line high (no acknowledge) after the last byte is read, and a stop condition completes the sequence. start 0 = write 7-bit device address 7-bit device address adp5589 ack 8-bit register pointer read byte 1 read byte 2 read byte n 00 0 1 0 0 0 0 1 repeat start 1 = read adp5589 ack adp5589 ack master ack master ack master ack no ack stop 09714-029 figure 30. i 2 c multibyte read sequence
data sheet adp5589 rev. b | page 21 of 52 r egister map table 6. addr. r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 r man_ id rev_ id 0x01 r /w reserved logic2_int logic1_ int lock_int ovrflow_ int gpi_int event_int 0x02 r logic2_stat logic1_stat lock_stat ec[4:0] 0x03 r event1_state event1_identifier[6:0] 0x04 r event2_state event2_identifier[6:0] 0x05 r event3_state event3_identifier[6:0 ] 0x06 r event4_state event4_identifier[6:0] 0x07 r event5_state event5_identifier[6:0] 0x08 r event6_state event6_identifier[6:0] 0x09 r event7_state event7_identifier[6:0] 0x0a r event8_state event8_identifier[6:0] 0x0b r event9_state event9_ identifier[6:0] 0x0c r event10_state event10_identifier[6:0] 0x0d r event11_state event11_identifier[6:0] 0x0e r event12_state event12_identifier[6:0] 0x0f r event13_state event13_identifier[6:0] 0x10 r event14_state event14_identifier[6:0] 0x11 r event15_state event15_identifier[6:0] 0x12 r event16_state event16_identifier[6:0] 0x13 r gpi_int_stat _a[7:0] 0x14 r gpi_int _stat _b[7:0] 0x15 r reserved gpi_int_stat_c[2:0] 0x16 r gpi_status_a[7:0] 0x17 r gpi_status_b[7:0] 0x18 r reserved gpi_s tatus_c[2:0] 0x19 r/w rpull_config_a[7:0] 0x1a r/w rpull_config_b[7:0] 0x1b r/w rpull_config_c[7:0] 0x1c r/w rpull_config_d[7:0] 0x1d r/w reserved rpull_config_e[5:0] 0x1e r/w gpi_int_level_a[7:0] 0x1f r/w gpi_int_level_b[7:0] 0x20 r/w reserved gpi _int_level_c[2:0] 0x 21 r/w gpi_event_en_a[7:0] 0x 22 r/w gpi_event_en_b[7:0] 0x23 r/w reserved gpi_event_en_c[2:0] 0x24 r/w gpi_interrupt_en_a[7:0] 0x25 r/w gpi_interrupt_en_b[7:0] 0x26 r/w reserved gpi_interrupt_en_c[2:0] 0x27 r/w debounce_dis_a[7:0 ] 0x28 r/w debounce_dis_b[7:0] 0x29 r/w reserved debounce_dis_c[2:0] 0x2a r/w gpo_data_out_a[7:0] 0x2b r/w gpo_data_out_b[7:0] 0x2c r/w reserved gpo_data_out_c[2:0] 0x2d r/w gpo_out_mode_a[7:0] 0x2e r/w gpo_out_mode_b[7:0] 0x2f r/w reserved gpo_out _mode_c[2:0] 0x30 r/w gpio_direction_a[7:0] 0x31 r/w gpio_direction_b[7:0] 0x32 r/w reserved gpio_direction_c[2:0]
adp5589 data sheet rev. b | page 22 of 52 addr. r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x33 r/w unlock1_ state unlock1[6:0] 0x34 r/w unlock2_ state unlock2[6:0] 0x35 r/w ext_lock_ state ext_lock_event[6:0] 0x36 r/w int_ma sk_timer[4:0] unlock_timer[2:0] 0x37 r/w reserved lock_en 0x38 r/w reset1_ event_a level reset1_event_a[6:0] 0x39 r/w reset2_ event_b level reset1_event_b[6:0] 0x3a r/w reset1_ event_b level reset1_event_c[6:0] 0x3b r/w reset1_ event_b level reset2_ev ent_a[6:0] 0x3c r/w reset1_ event_b level reset2_event_b[6:0] 0x3d r/w reset2_pol reset1_pol rst _ passthru_en reset_trigger_time[2:0] reset_pulse_width[1:0] 0x3e r/w pwm_offt_low_byte[7:0] 0x3f r/w pwm_offt_high_byte[7:0] 0x40 r/w pw m_ont_low_byte[7:0] 0x41 r/w pwm_ont_high_byte[7:0] 0x42 r/w reserved pwm_in_and pwm_mode pwm_en 0x43 r/w reserved clk_inv clk_div[4:0] clk_div_en 0x44 r/w reserved ly1_inv lc1_inv lb1_inv la1_inv logic1_sel[2:0] 0x45 r/w ly1_cascade ly2_inv lc2_inv l b2_inv la2_inv logic2_sel[2:0] 0x46 r/w reserved ff2_set ff2_clr ff1_set ff1_clr 0x47 r/w reserved ly2_dbnc_dis logic2_ event_en logic2_int_ level ly1_dbnc_ dis logic1_ event_en logic1_int_ level 0x48 r/w reserved key_poll_time[1:0] 0x49 r/w pin_config _a[7:0] 0x4a r/w pin_config_b[7:0] 0x4b r/w reserved pin_config_c[2:0] 0x4c r/w pull_select c4_extend_ cfg r4_extend_ cfg c6_ extend_cfg r3_extend_cfg[1:0] c9_extend_ cfg r0_extend_ cfg 0x4d r/w osc_en core_freq[1:0] lck_trk_ logic lck_trk_gpi int _cfg rst _cfg 0x4e r/w reserved logic2_ien logic1_ ien lock_ien ovrflow_ ien gpi_ien event_ien
data sheet adp5589 rev. b | page 23 of 52 d etailed r egister d escriptions note: n/a throughout this section means not applicable. note: all registers default to 0000 000 0 unless otherwise specified. id register 0x00 table 7. id bit descriptions bit s name r/w description [ 7: 4] man_id r manufacturer id, default = 0001. [ 3:0] rev _id r rev id . default = 0001 xxxx int_status register 0x01 table 8. int_stat us bit descriptions bit s name r/w description [ 7: 6] n/a reserved . 5 logic2_int r/w 0 = no interrupt. 1 = interrupt due to a general logic 2 condition. write a 1 to this bit to clear it. 4 logic1_int r/w 0 = no interrupt . 1 = interrupt due to a general logic 1 condition. write a 1 to this bit to clear it. 3 lock_int r/w 0 = no interrupt. 1 = interrupt due to a lock/unlock condition. the user can read lock_stat (0x02[5]) to determine if lock_int is due to a lock or unloc k event. if lock_stat = 1, lock_int is due to a lock event. if lock_stat = 0, lock_int is due to an unlock event. write a 1 to this bit to clear it. if lock mode is enabled via the software bit lock_en (0x37[0]), a lock_int is not generated because the p rocessor knows it just enabled lock mode. if lock mode is disabled (while locked) via the software bit lock_en, a lock_int is not generated because the processor knows it just disabled lock mode. 2 ovrflow_int r/w 0 = no interrupt. 1 = interrupt due to an overflow condition. write a 1 to this bit to clear it. 1 gpi_int r/w 0 = no interrupt. 1 = interrupt due to a general gpi condition. this bit is not set by a gpi that has been configured to update the fifo and event count. write a 1 to this bit to clear it. this bit cannot be cleared until all gpi_x_int bits are cleared. 0 event _int r/w 0 = n o interrupt . 1 = i nterrupt due to key event (press/release) , gpi event (gpi programmed for fifo updates) , or logic 1/ logic 2 event (programmed for fifo updates) .wri te a 1 to this bit to clear it. status register 0x02 table 9. status bit descriptions bits name r/w description 7 logic2_stat r 0 = output from logic block 2. (ly2) is low. 1 = output from logic block 2. (ly2) is high. 6 logic1_s tat r 0 = output from logic block 1 (ly1) is low. 1 = output from logic block 1 (ly1) is high. 5 lock_stat r 0 = unlocked. 1 = locked. [ 4:0] ec[4:0] r event count value. indicates how many events are currently stored on the fifo.
adp5589 data sheet rev. b | page 24 of 52 fifo_1 register 0x03 ta ble 10. fifo _1 bit descriptions bits name r/w description 7 event1_state r the seven lower bits of each fifo location contain the event identifier, which can be decoded to reveal the event recorded. table 11 outlines each event number, what it represents, and the i/o pins associated with it. bit 7 is the event 1 state. [6: 0] event1_identifier[6:0] this bit represents the state of the event that is recorded in event1_identifier[6:0]. for key events (event 1 to event 96). 1 = key is pressed. 0 = key is released. for gpi and logic events (event 97 to event 117). 1 = gpi/logic is active. 0 = gpi/logic is inactive. active and inactive states are programmable. table 11. event decoding event no. meaning event no. meaning event no. meaning event no. meaning 0 no event 32 key 32 (r2, c9) 64 key 64 (r5, c8) 96 key 96 (r7 , gnd ) 1 key 1 (r0, c0) 33 key 33 (r2, c10) 65 key 65 (r5, c9) 97 gpi 1 (r0) 2 key 2 (r0, c1) 34 key 34 (r3, c0) 66 key 66 (r5, c10) 98 gpi 2 (r1) 3 key 3 (r0, c2) 35 key 35 (r3, c1) 67 key 67 (r6, c0) 99 gpi 3 (r2) 4 key 4 (r0, c3) 36 key 36 (r3, c2) 68 key 68 (r6, c1) 100 gpi 4 (r3) 5 key 5 (r0, c4) 37 key 37 (r3, c3) 69 key 69 (r6, c2) 101 gpi 5 (r4) 6 key 6 (r0, c5) 38 key 38 (r3, c4) 70 key 70 (r6, c3) 102 gpi 6 (r5) 7 key 7 (r0, c6) 39 key 39 (r3, c5) 71 key 71 (r6, c4) 103 gpi 7 (r6) 8 key 8 (r0, c7) 40 key 40 (r3, c6) 72 key 72 (r6, c5) 104 gpi 8 (r7) 9 key 9 (r0, c8) 41 key 41 (r3, c7) 73 key 73 (r6, c6) 105 gpi 9 (c0) 10 key 10 (r0, c9) 42 key 42 (r3, c8) 74 key 74 (r6, c7) 106 gpi 10 (c1) 11 key 11 (r0, c10) 43 key 43 (r3, c9) 75 key 75 (r6, c8) 107 gpi 11 (c2) 12 key 12 (r1, c0) 44 key 44 (r3, c10) 76 key 76 (r6, c9) 108 gpi 12 (c3) 13 key 13 (r1, c1) 45 key 45 (r4, c0) 77 key 77 (r6, c10) 109 gpi 13 (c4) 14 key 14 (r1, c2) 46 key 46 (r4, c1) 78 key 78 (r7, c0) 110 gpi 14 (c5) 15 key 15 (r1, c3) 47 key 47 (r4, c2) 79 key 79 (r7, c1) 111 gpi 15 (c6) 16 key 16 (r1, c4) 48 key 48 (r4, c3 ) 80 key 80 (r7, c2) 112 gpi 16 (c7) 17 key 17 (r1, c5) 49 key 49 (r4, c4) 81 key 81 (r7, c3) 113 gpi 17 (c8) 18 key 18 (r1, c6) 50 key 50 (r4, c5) 82 key 82 (r7, c4) 114 gpi 18 (c9) 19 key 19 (r1, c7) 51 key 51 (r4, c6) 83 key 83 (r7, c5) 115 gpi 19 (c 10) 20 key 20 (r1, c8) 52 key 52 (r4, c7) 84 key 84 (r7, c6) 116 logic 1 21 key 21 (r1, c9) 53 key 53 (r4, c8) 85 key 85 (r7, c7) 117 logic 2 22 key 22 (r1, c10) 54 key 54 (r4, c9) 86 key 86 (r7, c8) 118 unused 23 key 23 (r2, c0) 55 key 55 (r4, c10) 87 key 87 (r7, c9) 119 unused 24 key 24 (r2, c1) 56 key 56 (r5, c0) 88 key 88 (r7, c10) 120 unused 25 key 25 (r2, c2) 57 key 57 (r5, c1) 89 key 89 (r0 , gnd ) 121 unused 26 key 26 (r2, c3) 58 key 58 (r5, c2) 90 key 90 (r1 , gnd ) 122 unused 27 key 27 (r2, c4 ) 59 key 59 (r5, c3) 91 key 91 (r2 , gnd ) 123 unused 28 key 28 (r2, c5) 60 key 60 (r5, c4) 92 key 92 (r3 , gnd ) 124 unused 29 key 29 (r2, c6) 61 key 61 (r5, c5) 93 key 93 (r4 , gnd ) 125 unused 30 key 30 (r2, c7) 62 key 62 (r5, c6) 94 key 94 (r5 , gnd ) 126 u nused 31 key 31 (r2, c8) 63 key 63 (r5, c7) 95 key 95 (r6 , gnd ) 127 wildcard for unlock
data sheet adp5589 rev. b | page 25 of 52 fifo_2 register 0x04 table 12. fifo_2 bit descriptions bits name r/w description 7 event2_state r refer to table 10. [ 6:0] event2_identifier[6:0] r refer to table 10. fifo_3 register 0x0 5 table 13. fifo_3 bit descriptions bits name r/w description 7 event3_state r refer to table 10 . [ 6: 0] event3_identifier[6:0] r refer to table 10. fifo_ 4 register 0x0 6 table 14. fifo_4 bit descriptions bits name r/w description 7 event4_state r refer to table 10. [ 6:0] event4_identifier[6:0] r refer to table 10. fifo_ 5 register 0x07 table 15. fifo_5 bit descriptions bits name r/w descri ption 7 event5_state r refer to table 10. [ 6 : 0 ] event5_identifier[6:0] r refer to table 10 . fifo_ 6 register 0x0 8 table 16. fifo_6 bit description s bits name r/w description 7 event6_state r refer to table 10. [ 6:0] event6_identifier[6:0] r refer to table 10. fifo_ 7 register 0x0 9 table 17. fifo_7 bit descriptions bits name r/w description 7 event7_state r refer to table 10. [ 6:0] event7_identifier[6:0] r refer to table 10. fifo_ 8 register 0x0a table 18. fifo_8 bit descriptions bits name r/w description 7 event8_state r refer to table 10. [ 6:0] event8_identifier[6:0] r refer to table 10. fifo_ 9 regi ster 0x0 b table 19. fifo_9 bit descriptions bits name r/w description 7 event9_state r refer to table 10. [ 6:0] event9_identifier[6:0] r refer to t able 10.
adp5589 data sheet rev. b | page 26 of 52 fifo_ 10 register 0x0c table 20. fifo_10 bit descriptions bits name r/w description 7 event10_state r refer to table 10. [ 6:0] event10_identifier[6:0] r refer to table 10. fifo_ 11 register 0x0 d table 21. fifo_11 bit descriptions bits name r/w description 7 event11_state r refer to table 10. [ 6:0] event11_identifier[6:0] r refer to table 10. fifo_ 12 register 0x0 e table 22. fifo_12 bit descriptions bits name r/w description 7 event12_state r refer to table 10. [ 6:0] event12_identifier[6:0] r refer to table 10. fifo_ 13 register 0x0f table 23. fifo_13 bit descriptions bits name r/w description 7 event13_state r refer to table 10. [ 6 : 0 ] event13_identifier[6:0] r refer to table 10 . fifo_ 14 register 0x10 table 24. fifo_14 bit descriptions bits name r/w description 7 event14_state r refer to table 10. [ 6: 0] event14_identifier[6:0] r refer to table 10. fifo_ 15 register 0x11 table 25. fifo_15 bit descriptions bits name r/w description 7 even t15_state r refer to table 10. [ 6: 0] event15_identifier[6:0] r refer to table 10. fifo_ 16 register 0x12 table 26. fifo_16 bit descriptions bits n ame r/w description 7 event16_state r refer to table 10. [ 6: 0] event16_identifier[6:0] r refer to table 10.
data sheet adp5589 rev. b | page 27 of 52 gpi_int_stat_a register 0x13 table 27. gpi_int_stat_a bit descriptions bits name r/w description 7 gpi_8_int r 0 = no interrupt. 1 = interrupt due to gpi_8 (r7 pin). cleared on read. 6 gpi_7_int r 0 = no interrupt. 1 = interrupt due to gpi_7 (r6 pin). cleared on read. 5 gpi_6_int r 0 = no interrupt. 1 = interrupt due to gpi_6 (r5 pin). cleared on read. 4 gpi_5_int r 0 = no interrupt. 1 = interrupt due to gpi_5 (r4 pin). cleared on read. 3 gpi_4_int r 0 = no interrupt. 1 = interrupt due to gpi_4 (r3 pin). cleared on read. 2 gpi_3_int r 0 = no interrupt. 1 = interrupt due to gpi_3 (r2 pin). cleared on read. 1 gpi_2_int r 0 = no interrupt. 1 = interrupt due to gpi_2 (r1 pin). cleared on read. 0 gpi_1_int r 0 = no interrupt. 1 = interrupt due to gpi_1 (r0 pin). cleared on read. gpi_int_st at_ b register 0x14 table 28. gpi_int_stat_b bit descriptions bits name r/w description 7 gpi_16_int r 0 = no interrupt. 1 = interrupt due to gpi_16 (c7 pin). cleared on read. 6 gpi_15_int r 0 = no interrupt. 1 = interrupt due to g pi_15 (c6 pin). cleared on read. 5 gpi_14_int r 0 = no interrupt. 1 = interrupt due to gpi_14 (c5 pin). cleared on read. 4 gpi_13_int r 0 = no interrupt. 1 = interrupt due to gpi_13 (c4 pin). cleared on read. 3 gpi_12_int r 0 = no interrupt. 1 = interru pt due to gpi_12 (c3 pin). cleared on read. 2 gpi_11_int r 0 = no interrupt. 1 = interrupt due to gpi_11 (c2 pin). cleared on read. 1 gpi_10_int r 0 = no interrupt. 1 = interrupt due to gpi_10 (c1 pin). cleared on read. 0 gpi_9_int r 0 = no interrupt. 1 = interrupt due to gpi_9 (c0 pin). cleared on read. gpi_int_stat_ c register 0x15 table 29. gpi_int_stat_c bit descriptions bits name r/w description [ 7: 3] reserved. 2 gpi_19_int r 0 = no interrupt. 1 = interrupt due to gpi_19 (c10 pin). cleared on read. 1 gpi_18_int r 0 = no interrupt. 1 = interrupt due to gpi_18 (c9 pin). cleared on read. 0 gpi_17_int r 0 = no interrupt. 1 = interrupt due to gpi_17 (c8 pin). cleared on read.
adp5589 data sheet rev. b | page 28 of 52 gpi_status_a register 0x16 table 30. gpi_status_a bit descriptions bits name r/w description 7 gpi_8_stat r 0 = gpi_8 (r7 pin) is low. 1 = gpi_8 (r7 pin) is high. 6 gpi_7_stat r 0 = gpi_7 (r6 pin) is low. 1 = gpi_7 (r6 pin) is high. 5 gpi_6_stat r 0 = gpi_6 (r5 pin) is low. 1 = gpi_6 (r5 pin) is high. 4 gpi_5_stat r 0 = gpi_5 (r4 pin) is low. 1 = gpi_5 (r4 pin) is high. 3 gpi_4_stat r 0 = gpi_4 (r3 pin) is low. 1 = gpi_4 (r3 pin) is high. 2 gpi_3_stat r 0 = gpi_3 (r2 pin) is low. 1 = gpi_3 (r2 pin) is high. 1 gpi_2_stat r 0 = gpi_2 (r1 pin) is low. 1 = gpi_2 (r1 pin) is high. 0 gpi_1_stat r 0 = gpi_1 (r0 pin) is low. 1 = gpi_1 (r0 pin) is high. gpi_status_ b register 0x1 7 table 31. gpi_status_b bit descriptions bits name r/w description 7 gpi_16_sta t r 0 = gpi_16 (c7 pin) is low. 1 = gpi_16 (c7 pin) is high. 6 gpi_15_stat r 0 = gpi_15 (c6 pin) is low. 1 = gpi_15 (c6 pin) is high. 5 gpi_14_stat r 0 = gpi_14 (c5 pin) is low. 1 = gpi_14 (c5 pin) is high. 4 gpi_13_stat r 0 = gpi_13 (c4 pin) is low. 1 = gpi_13 (c4 pin) is high. 3 gpi_12_stat r 0 = gpi_12 (c3 pin) is low. 1 = gpi_12 (c3 pin) is high. 2 gpi_11_stat r 0 = gpi_11 (c2 pin) is low. 1 = gpi_11 (c2 pin) is high. 1 gpi_10_stat r 0 = gpi_10 (c1 pin) is low. 1 = gpi_10 (c1 pin) is high. 0 gpi_ 9_stat r 0 = gpi_9 (c0 pin) is low. 1 = gpi_9 (c0 pin) is high. gpi_status_c register 0x18 table 32. gpi_status_c bit descriptions bits name r/w description [ 7: 3] reserved. 2 gpi_19_stat r 0 = gpi_19 (c10 pin) is low. 1 = gpi_ 19 (c10 pin) is high. 1 gpi_18_stat r 0 = gpi_18 (c9 pin) is low. 1 = gpi_18 (c9 pin) is high. 0 gpi_17_stat r 0 = gpi_17 (c8 pin) is low. 1 = gpi_17 (c8 pin) is high.
data sheet adp5589 rev. b | page 29 of 52 rpull_ config _ a register 0x1 9 table 33. rpull_config_a bit des criptions bits name r/w description [ 7:6] r3_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable all pull - up/pull - down resistors. [ 5:4 ] r2_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable al l pull - up/pull - down resistors. [ 3:2] r1_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable all pull - up/pull - down resistors. [ 1: 0] r0_pull_cfg r/w 00 = e nable 300 k ? pull -up . 01 = enable 300 k? pull - down . 10 = enable 100 k? pull -up . 11 = disable all pull - up/pull - down resistors . adp5589ac_z - 00- r7, adp5589ac_z -01- r7 default = 0000 0000 adp5589ac_z - 02- r7 default = 0100 0001 rpull_ config _ b register 0x1 a table 34. rpull _ con fig_b bit descriptions bits name r/w description [ 7 :6] r7_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable all pull - up/pull - down resistors. [ 5: 4] r6_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable all pull - up/pull - down resistors. [ 3: 2] r5_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable all pull - up/pull - down resist ors. [ 1: 0] r4_pull_cfg r/w 00 = enable 300 k? pull -up . 01 = enable 300 k? pull - down . 10 = enable 100 k? pull -up . 11 = disable all pull - up/pull - down resistors . adp5589ac_z - 00- r7, adp5589ac_z -01- r7 default = 0000 0000 adp5589ac_z - 02- r7 default = 0000 0001
adp5589 data sheet rev. b | page 30 of 52 rpull_ config _ c register 0x1 b table 35. rpull _ config_c bit descriptions bits name r/w description [ 7 :6] c3_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable all pull - up/pull - down resistors. [ 5: 4 ] c2_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable all pull - up/pull - down resistors. [ 3: 2] c1_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable all pull - up/pull - down resistors. [ 1: 0] c0_pull_cfg r/w 00 = enable 300 k? pull -up . 01 = enable 300 k? pull - down . 10 = enable 100 k? pull -up . 11 = disable all pull - up/pull - down resistors . rpull_ config _ d regi ster 0x1 c table 36. rpull _ config_d bit descriptions bits name r/w description [ 7: 6] c7_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable all pull - up/pull - down resistors . [ 5:4] c6_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable all pull - up/pull - down resistors. [ 3: 2] c5_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k ? pull - up. 11 = disable all pull - up/pull - down resistors. [ 1: 0] c4_pull_cfg r/w 00 = enable 300 k? pull -up . 01 = enable 300 k? pull - down . 10 = enable 100 k? pull -up . 11 = disable all pull - up/pull - down resistors . adp5589ac_z - 00- r7, adp5589ac_z -01- r7 defau lt = 0000 0000 adp5589ac_z - 02- r7 default = 0001 0001
data sheet adp5589 rev. b | page 31 of 52 rpull_config_ e register 0x1d table 37. rpull _ config_e bit descriptions bits name r/w description [ 7: 6] reserved. [ 5:4] c10_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = ena ble 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable all pull - up/pull - down resistors. [ 3: 2] c9_pull_cfg r/w 00 = enable 300 k? pull - up. 01 = enable 300 k? pull - down. 10 = enable 100 k? pull - up. 11 = disable all pull - up/pull - down resistors. [ 1: 0] c8_pull_cfg r/w 00 = enable 300 k? pull -up . 01 = enable 300 k? pull - down . 10 = enable 100 k? pull -up . 11 = disable all pull - up/pull - down resistors . adp5589ac_z - 00 - r7, adp5589ac_z - 01 - r7 default = 0000 0000 adp5589ac_z - 02- r7 default = 0000 0100 gpi_in t_level_a register 0x1 e table 38 . gpi_int_level_a bit descriptions bits name r/w description 7 gpi_8_int_level r/w 0 = gpi_8 interrupt is active low. 1 = gpi_8 interrupt is active high. 6 gpi_7_int_level r/w 0 = gpi_7 interrupt is active low. 1 = gpi_7 interrupt is active high. 5 gpi_6_int_level r/w 0 = gpi_6 interrupt is active low. 1 = gpi_6 interrupt is active high. 4 gpi_5_int_level r/w 0 = gpi_5 interrupt is active low. 1 = gpi_5 interrupt is active high. 3 gpi_4_int_level r/w 0 = gpi_4 interrupt is active low. 1 = gpi_4 interrupt is active high. 2 gpi_3_int_level r/w 0 = gpi_3 interrupt is active low. 1 = gpi_3 interrupt is active high. 1 gpi_2_int_level r/w 0 = gpi_2 interrupt is active low. 1 = gpi_2 interrupt is active high. 0 gpi_1_int_level r/w 0 = gpi_1 interrupt is active low ( gpi_1_int is set whenever r0 is low) . 1 = gpi_1 interrupt is active high (gpi_1_int is set whenever r0 is high) .
adp5589 data sheet rev. b | page 32 of 52 gpi_int_level_ b register 0x1f table 39 . gpi_int_level _b bit descriptions bits name r/w description 7 gpi_16_int_level r/w 0 = gpi_16 interrupt is active low. 1 = gpi_16 interrupt is active high. 6 gpi_15_int_level r/w 0 = gpi_15 interrupt is active low. 1 = gpi_15 interrupt is active high. 5 gpi_14_int_le vel r/w 0 = gpi_14 interrupt is active low. 1 = gpi_14 interrupt is active high. 4 gpi_13_int_level r/w 0 = gpi_13 interrupt is active low. 1 = gpi_13 interrupt is active high. 3 gpi_12_int_level r/w 0 = gpi_12 interrupt is active low. 1 = gpi_12 interru pt is active high. 2 gpi_11_int_level r/w 0 = gpi_11 interrupt is active low. 1 = gpi_11 interrupt is active high. 1 gpi_10_int_level r/w 0 = gpi_10 interrupt is active low. 1 = gpi_10 interrupt is active high. 0 gpi_9_int_level r/w 0 = gpi_9 interrupt is active low . 1 = gpi_9 interrupt is active high . gpi_int_level_c register 0x 20 table 40 . gpi_int_level_c bit descriptions bits name r/w description [ 7: 3] reserved. 2 gpi_19_int_level r/w 0 = gpi_19 interrupt is active low. 1 = gpi_19 interrupt is active high. 1 gpi_18_int_level r/w 0 = gpi_18 interrupt is active low. 1 = gpi_18 interrupt is active high. 0 gpi_17_int_level r/w 0 = gpi_17 interrupt is active low . 1 = gpi_17 interrupt is active high . gpi_event_en_a register 0 x21 table 41. gpi_event_en_a bit descriptions bits name r/w description 7 gpi_8_event_en r/w 0 = disable gpi events. 1 = allow gpi 8 activity to generate events on the fifo. 6 gpi_7_event_en r/w 0 = disable gpi events. 1 = allow g pi 7 activity to generate events on the fifo. 5 gpi_6_event_en r/w 0 = disable gpi events. 1 = allow gpi 6 activity to generate events on the fifo. 4 gpi_5_event_en r/w 0 = disable gpi events. 1 = allow gpi 5 activity to generate events on the fifo. 3 g pi_4_event_en r/w 0 = disable gpi events. 1 = allow gpi 4 activity to generate events on the fifo. 2 gpi_3_event_en r/w 0 = disable gpi events. 1 = allow gpi 3 activity to generate events on the fifo. 1 gpi_2_event_en r/w 0 =disable gpi events. 1 = allow gpi 2 activity to generate events on the fifo. 0 gpi_1_event_en r/w 0 = disable gpi events. 1 = a llow gpi 1 activity to generate events on the fifo . gpis in this mode are considered fifo events and can be used for unlock purposes. gpi acti vity in this mo de cause s event _int interrupts. gpis in this mode do not generate gpi_int interrupts.
data sheet adp5589 rev. b | page 33 of 52 gpi_event_en_ b register 0x2 2 table 42. gpi_event_en_b bit descriptions bits name r/w description 7 gpi_16_event_en r/w 0 = disable gpi events. 1 = allow gpi 16 activity to generate events on the fifo. 6 gpi_15_event_en r/w 0 = disable gpi events. 1 = allow gpi 15 activity to generate events on the fifo. 5 gpi_14_event_en r/w 0 = disable gpi events. 1 = allow gpi 14 activity to generate events on the fifo. 4 gpi_13_event_en r/w 0 = disable gpi events. 1 = allow gpi 13 activity to generate events on the fifo. 3 gpi_12_event_en r/w 0 = disable gpi events. 1 = allow gpi 12 activity to generate events on the fifo. 2 gpi_11_event_en r/w 0 = disable gpi events. 1 = allow gpi 11 activity to generate events on the fifo. 1 gpi_10_event_en r/w 0 = disable gpi events. 1 = allow gpi 10 activity to generate events on the fifo. 0 gpi_9_event_en r/w 0 = disable gpi events. 1 = a llow gpi 9 activity to generat e events on the fifo . gpi_event_en_ c register 0x2 3 table 43. gpi_event_en_c bit descriptions bits name r/w description [ 7: 3] reserved. 2 gpi_19_event_en r/w 0 = disable gpi events. 1 = allow gpi 19 activity to generate events on the fifo. 1 gpi_18_event_en r/w 0 = disable gpi events. 1 = allow gpi 1 8 activity to generate events on the fifo. 0 gpi_17_event_en r/w 0 = disable gpi events. 1 = a llow gpi 17 activity to generate events on the fifo . gpi_ interrupt _en_ a register 0x2 4 table 44. gpi_interrupt_en_a bit descriptions bits name r/w description 7 gpi_8_int_en r/w 0 = gpi_8_int is disable. 1 = gpi_8_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_8_int is set and the gpi interrupt con dition is met. 6 gpi_7_int_en r/w 0 = gpi_7_int is disable. 1 = gpi_7_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_7_int is set and the gpi interrupt condition is met. 5 gpi_6_int_en r/w 0 = gpi_6_int is disable. 1 = gpi_6_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_6_int is set and the gpi interrupt condition is met. 4 gpi_5_int_en r/w 0 = gpi_5_int is disable. 1 = gpi_5_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_5_int is set and the gpi int errupt condition is met. 3 gpi_4_int_en r/w 0 = gpi_4_int is disable. 1 = gpi_4_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_4_int is set and the gpi interrupt condition is met. 2 gpi_3_int_en r/w 0 = gpi_3_int is disable. 1 = gpi_3_i nt enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_3_int is set and the gpi interrupt condition is met. 1 gpi_2_int_en r/w 0 = gpi_2_int is disable. 1 = gpi_2_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_2_int is set and t he gpi interrupt condition is met.
adp5589 data sheet rev. b | page 34 of 52 0 gpi_1_int_en r/w 0 = gpi_1_int is disable. 1 = gpi_1_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_2_int is set and the gpi interrupt condition is met. gpi_ interrupt _en_ b register 0x2 5 table 45. gpi_interrupt_en_b bit descriptions bits name r/w description 7 gpi_16_int_en r/w 0 = gpi_16_int is disabled. 1 = gpi_16_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_16_int is set and the gpi interrupt condition is met. 6 gpi_15_int_en r/w 0 = gpi_15_int is disabled. 1 = gpi_15_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_15_int is set and the gpi interrupt condition is met. 5 gpi_14_int_en r/w 0 = gpi_14_int is disabled. 1 = gpi_14_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_14_int is set and the gpi interrupt condition is met. 4 gpi_13_int_en r/w 0 = gpi_13_int is disabled. 1 = gpi_13_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_13_int is set and the g pi interrupt condition is met. 3 gpi_12_int_en r/w 0 = gpi_12_int is disabled. 1 = gpi_12_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_12_int is set and the gpi interrupt condition is met. 2 gpi_11_int_en r/w 0 = gpi_11_int is disable d. 1 = gpi_11_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_11_int is set and the gpi interrupt condition is met. 1 gpi_10_int_en r/w 0 = gpi_10_int is disabled. 1 = gpi_10_int enable. assert the gpi_int bit (register 0x01, bit 1) if gp i_10_int is set and the gpi interrupt condition is met. 0 gpi_9_int_en r/w 0 = gpi_9_int is disabled. 1 = gpi_9_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_9_int is set and the gpi interrupt condition is met. gpi_ interrupt _en_ c regis ter 0x2 6 table 46. gpi_interrupt_en_c bit descriptions bits name r/w description [ 7: 3] reserved . 2 gpi_19_int_en r/w 0 = gpi_19_int is disabled. 1 = gpi_19_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_19_int is set and the gpi interrupt condition is met. 1 gpi_18_int_en r/w 0 = gpi_18_int is disabled. 1 = gpi_18_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_18_int is set and the gpi interrupt condition is met. 0 gpi_17_int_en r/w 0 = gpi_ 17_int is disabled. 1 = gpi_17_int enable. assert the gpi_int bit (register 0x01, bit 1) if gpi_17_int is set and the gpi interrupt condition is met.
data sheet adp5589 rev. b | page 35 of 52 debounce_dis_a register 0x27 table 47. debounce_dis_a bit descriptions bits name r/w description 7 gpi_8_deb_dis r/w 0 = debounce enabled on gpi 8. 1 = debounce disabled on gpi 8. 6 gpi_7_deb_dis r/w 0 = debounce enabled on gpi 7. 1 = debounce disabled on gpi 7. 5 gpi_6_deb_dis r/w 0 = debounce enabled on gpi 6. 1 = debounce disable d on gpi 6. 4 gpi_5_deb_dis r/w 0 = debounce enabled on gpi 5. 1 = debounce disabled on gpi 5. 3 gpi_4_deb_dis r/w 0 = debounce enabled on gpi 4. 1 = debounce disabled on gpi 4. 2 gpi_3_deb_dis r/w 0 = debounce enabled on gpi 3. 1 = debounce disabled on gpi 3. 1 gpi_2_deb_dis r/w 0 = debounce enabled on gpi 2. 1 = debounce disabled on gpi 2. 0 gpi_1_deb_dis r/w 0 = debounce enabled on gpi 1. 1 = debounce disabled on gpi 1. debounce_dis_ b register 0x2 8 table 48. debounce_dis_b b it descriptions bits name r/w description 7 gpi_16_deb_dis r/w 0 = debounce enabled on gpi 16. 1 = debounce disabled on gpi 16. 6 gpi_15_deb_dis r/w 0 = debounce enabled on gpi 15. 1 = debounce disabled on gpi 15. 5 gpi_14_deb_dis r/w 0 = debounce enabl ed on gpi 14. 1 = debounce disabled on gpi 14. 4 gpi_13_deb_dis r/w 0 = debounce enabled on gpi 13. 1 = debounce disabled on gpi 13. 3 gpi_12_deb_dis r/w 0 = debounce enabled on gpi 12. 1 = debounce disabled on gpi 12. 2 gpi_11_deb_dis r/w 0 = debounce enabled on gpi 11. 1 = debounce disabled on gpi 11. 1 gpi_10_deb_dis r/w 0 = debounce enabled on gpi 10. 1 = debounce disabled on gpi 10. 0 gpi_9_deb_dis r/w 0 = debounce enabled on gpi 9. 1 = debounce disabled on gpi 9.
adp5589 data sheet rev. b | page 36 of 52 debounce_dis_ c register 0x2 9 ta ble 49. debounce_dis_c bit descriptions bits name r/w description [ 7:3] reserved. 2 gpi_19_deb_dis r/w 0 = debounce enabled on gpi 19. 1 = debounce disabled on gpi 19. 1 gpi_18_deb_dis r/w 0 = debounce enabled on gpi 18. 1 = de bounce disabled on gpi 18. 0 gpi_17_deb_dis r/w 0 = debounce enabled on gpi 17. 1 = debounce disabled on gpi 17. gpo_data_out_a register 0x2 a table 50. gpo_data_out_a bit descriptions bits name r/w description 7 gpo_8_data r/w 0 = low. 1 = high. 6 gpo_7_data r/w 0 = low. 1 = high. 5 gpo_6_data r/w 0 = low. 1 = high. 4 gpo_5_data r/w 0 = low. 1 = high. 3 gpo_4_data r/w 0 = low. 1 = high. 2 gpo_3_data r/w 0 = low. 1 = high. 1 gpo_2_data r/w 0 = low. 1 = high. 0 gpo_1_data r/w 0 = low . 1 = high . gpo_data_out_ b register 0x2 b table 51 . gpo_data_out_b bit descriptions bits name r/w description 7 gpo_16_data r/w 0 = low. 1 = high. 6 gpo_15_data r/w 0 = low. 1 = high. 5 gpo_14_data r/w 0 = low. 1 = high. 4 gpo_13_data r/w 0 = low. 1 = high. 3 gpo_12_data r/w 0 = low. 1 = high. 2 gpo_11_data r/w 0 = low. 1 = high. 1 gpo_10_data r/w 0 = low. 1 = high. 0 gpo_9_data r/w 0 = low . 1 = high .
data sheet adp5589 rev. b | page 37 of 52 gpo_data_out_ c register 0x2 c table 52 . gp o_data_out_c bit descriptions bits name r/w description [ 7: 3] reserved. 2 gpo_19_data r/w 0 = low. 1 = high. 1 gpo_18_data r/w 0 = low. 1 = high. 0 gpo_17_data r/w 0 = low . 1 = high . gpo_ out_ mode_a register 0x2 d table 53 . gp o_out_mode_a bit descriptions bits name r/w description 7 gpo_8_ out_mode r/w 0 = push/pull. 1 = open drain. 6 gpo_7_ out_mode r/w 0 = push/pull. 1 = open drain. 5 gpo_6_ out_mode r/w 0 = push/pull. 1 = open drain. 4 gpo_5_ out_mode r/w 0 = push/pull. 1 = open drain. 3 gpo_4_ out_mode r/w 0 = push/pull. 1 = open drain. 2 gpo_3 _out_mode r/w 0 = push/pull. 1 = open drain. 1 gpo_2_ out_mode r/w 0 = push/pull. 1 = open drain. 0 gpo_1_ out_mode r/w 0 = push/pull . 1 = open drain . gpo_ out_ mode_b register 0x2 e ta ble 54 . gpo_out_mode_b bit descriptions bits name r/w description 7 gpo_16_ out_mode r/w 0 = push/pull. 1 = open drain. 6 gpo_15_out_mode r/w 0 = push/pull. 1 = open drain. 5 gpo_14_ out_mode r/w 0 = push/pull. 1 = open drain. 4 g po_13_out_mode r/w 0 = push/pull. 1 = open drain. 3 gpo_12_out_mode r/w 0 = push/pull. 1 = open drain. 2 gpo_11_out_mode r/w 0 = push/pull. 1 = open drain. 1 gpo_10_out_mode r/w 0 = push/pull. 1 = open drain. 0 gpo_9_out_mode r/w 0 = push/pull . 1 = ope n drain .
adp5589 data sheet rev. b | page 38 of 52 gpo_ out_ mode_c register 0x2 f table 55 . gpo_out_mode_c bit descriptions bits name r/w description [ 7: 3] reserved. 2 gpo_19_dir r/w 0 = push/pull. 1 = open drain. 1 gpo_18_dir r/w 0 = push/pull. 1 = open drain. 0 gpo _17_dir r/w 0 = push/pull . 1 = open drain . gpio_direction_a register 0x 30 table 56. gpio_direction_a bit descriptions bits name r/w description 7 gpio_8_dir r/w 0 = gpio 8 is an input. 1 = gpio 8 is an output. 6 gpio_7_dir r/w 0 = gpio 7 is an input. 1 = gpio 7 is an output. 5 gpio_6_dir r/w 0 = gpio 6 is an input. 1 = gpio 6 is an output. 4 gpio_5_dir r/w 0 = gpio 5 is an input. 1 = gpio 5 is an output. 3 gpio_4_dir r/w 0 = gpio 4 is an input. 1 = gpio 4 is an output. 2 gpio_ 3_dir r/w 0 = gpio 3 is an input. 1 = gpio 3 is an output. 1 gpio_2_dir r/w 0 = gpio 2 is an input. 1 = gpio 2 is an output. 0 gpio_1_dir r/w 0 = gpio 1 is an input . 1 = gpio 1 is an output . gpio_direction_b register 0x 31 table 57. gpio_direction_b bit descriptions bits name r/w description 7 gpio_16_dir r/w 0 = gpio 16 is an input. 1 = gpio 16 is an output. 6 gpio_15_dir r/w 0 = gpio 15 is an input. 1 = gpio 15 is an output. 5 gpio_14_dir r/w 0 = gpio 14 is an input. 1 = gpio 14 is an output. 4 gpio_13_dir r/w 0 = gpio 13 is an input. 1 = gpio 13 is an output. 3 gpio_12_dir r/w 0 = gpio 12 is an input. 1 = gpio 12 is an output. 2 gpio_11_dir r/w 0 = gpio 11 is an input. 1 = gpio 11 is an output. 1 gpio_10_dir r/w 0 = gpio 1 0 is an input. 1 = gpio 10 is an output. 0 gpio_9_dir r/w 0 = gpio 9 is an input . 1 = gpio 9 is an output .
data sheet adp5589 rev. b | page 39 of 52 gpio_direction_c register 0x 32 table 58. gpio_direction_c bit descriptions bits name r/w description [ 7:3] reserved. 2 gpio_19_dir r/w 0 = gpio 19 is an input. 1 = gpio 19 is an output. 1 gpio_18_dir r/w 0 = gpio 18 is an input. 1 = gpio 18 is an output. 0 gpio_17_dir r/w 0 = gpio 17 is an input . 1 = gpio 17 is an output . unlock1 register 0x 33 table 59. unlock1 bit descriptions bits name r/w description 7 unlock1_state r/w defines which state the first unlock event should be for key events: 0 = not applicable; releases not used for unlock. 1 = press is used as unlock event. for gpis and logic outputs configured for fifo updates: 0 = inactive event used as reset condition. 1 = active event used as reset condition. [ 6:0] unlock1[6:0] r/w defines the first event that must be detected to unlock the keypad after lock_en has been set. unlock2 reg ister 0x 34 table 60. unlock2 bit descriptions bits name r/w description 7 unlock2_state r/w defines which state the second unlock event should be. for key events: 0 = not applicable; releases not used for unlock. 1 = press is use d as unlock event. for gpis and logic outputs configured for fifo updates: 0 = inactive event used as reset condition. 1 = active event used as reset condition. [ 6:0] unlock2[6:0] r/w defines the second event that must be detected to unlock the keypad aft er lock_en has been set. ext_ lock_event register 0x35 table 61. ext_lock _event bit descriptions bits name r/w description 7 ext_lock_state r/w defines which state the lock event should be. for key events: 0 = not applicable; rel eases not used for unlock. 1 = press is used as unlock event. for gpis and logic outputs configured for fifo updates: 0 = inactive event used as reset condition. 1 = active event used as reset condition. [ 6 : 0 ] ext_lock_event[6:0] r/w defines an event tha t can lock the keypad . when this event is detected, lock_int is set .
adp5589 data sheet rev. b | page 40 of 52 unlock_timers register 0x 36 table 62. unlock_timers bit descriptions bits name r/w description [ 7: 3] int_mask_timer[4:0] r/w if the keypad is locked and this t imer is set, any key event (or gpi/logic event programmed to fifo update) is allowed to generate an event_int interrupt. this timer then begins counting, and no further events generate an interrupt until this timer has expired (or both unlock events have o ccurred). 00000 = disabled. 00001 = 1 sec. 00010 = 2 sec. 11110 = 30 sec. 11111 = 31 sec. [ 2: 0] unlock_timer[2:0] r/w defines the time in which the second unlock event must occur after the first unlock event has occurred. if the second unlock event does not occur within this time (or any other event occurs), the keypad goes back to full lock mode . 000 = disabled . 001 = 1 sec . 010 = 2 sec . 011 = 3 sec . 100 = 4 sec . 101 = 5 sec . 110 = 6 sec . 111 = 7 sec . lock_cfg register 0x 37 table 63. lock_cfg bit descriptions bits name r/w description [ 7:1] reserved. 0 lock_en r/w enable the lock function. reset1_event_a register 0x 38 table 64. reset 1 _event _a bit descriptions bits name r/w description 7 reset1_event_a level r/w defines which level the first reset event should be. for key events: 0 = not applicable; releases not used for reset generation. 1 = press is used as reset event. for gpis and logic outputs configured for fifo updates: 0 = inactive event used as reset condition. 1 = active event used as reset condition. [ 6:0] reset 1 _event_a [6:0] r/w defines an event that can be used to generate the reset1 signal . up to three events can be defined for generating the reset 1 signal , using reset 1 _event_a[6:0], rese t 1 _event_b[6:0], and reset 1 _event_c[6:0] . if one of the registers is 0, that register is not used for reset generation. all reset events must be detected at the same time to trigger the reset . reset1_event_b register 0x 39 table 65. reset 1 _event_b bit descriptions bits name r/w description 7 reset1_event_b level r/w defines which level the second reset event should be. [ 6 : 0 ] reset 1 _event_b [6:0] r/w defines an event that can be used to generate the reset1 signal .
data sheet adp5589 rev. b | page 41 of 52 reset1_event_c register 0x 3a table 66 . reset 1 _event_c bit descriptions bits name r/w description 7 reset1_ev ent_b level r/w defines which level the third reset event should be. [ 6: 0] reset 1 _event_c [6:0] r/w defines an eve nt that can be used to generate the reset1 signal . reset2_event_a register 0x 3b table 67. reset2_event_a bit descriptions bits name r/w description 7 reset 1_event_b level r/w defines which level the first reset event should be. for key events: 0 = no t applicable; releases not used for reset generation. 1 = press is used as reset event. for gpis and logic outputs configured for fifo updates: 0 = inactive event used as reset condition. 1 = active event used as reset condition. [ 6:0] reset2 _event_a[6:0] r/w defines an event that can be used to generate the reset2 signal . up to two events can be defined for generating the reset 2 signal, using reset2_event_a[6:0] and reset2 _event_b[6:0] . if one of the registers is 0, that register is not used for reset ge neration. all reset events must be detected at the same time to trigger the reset . reset2_event_ b register 0x 3c table 68. reset2_event_ b bit descriptions bits name r/w description 7 reset1 _event_b level r/w defines which level the second reset event should be. [ 6:0] reset2_event_b[6:0] r/w defines an event that can be used to generate the reset2 signal . reset_ cfg register 0x 3 d table 69. reset_cfg bit descriptions bits name r/w description 7 reset2_pol r /w sets the polarity of reset2. 0 = reset2 is active low. 1 = reset2 is active high. 6 reset1_pol r/w sets the polarity of reset1. 0 = reset1 is active low. 1 = reset1 is active high. 5 rst _passthru_en r/w allows the rst pin to override (or with) the reset1signal. function not applicable to reset2. [ 4:2 ] reset_trigger_time[2:0] r/w defines the length of time that the reset events must be active before a reset signal is generated. all events must be active at the same time for the same duration. parameter common to both reset1 and reset2. 000 = immediate. 001 = 1.0 sec. 010 = 1.5 sec. 011 = 2.0 sec. 100 = 2.5 sec. 101 = 3.0 sec. 110 = 3.5 sec. 111 = 4.0 sec.
adp5589 data sheet rev. b | page 42 of 52 bits name r/w description [ 1:0] reset_pulse_width[1:0] r/w define s the pulse w idth of the reset signal s . parameter common to both reset1 and reset2. 00 = 500 s . 01 = 1 ms . 10 = 2 ms . 11 = 10 ms . adp5589ac_z - 00- r7, adp5589ac_z -02- r7 default = 0000 0000 adp5589ac_z - 01 - r7 default = 0010 0000 pwm _ offt _ low register 0x 3 e table 70 . pwm_offt_low bit descriptions bits name r/w description [ 7: 0] pwm_offt_low_byte[7:0] r/w lower eight bits of pwm off time . pwm_offt_high register 0x 3f table 71. pwm_offt_high bit descriptions bits name r/w de scription [ 7 : 0 ] pwm_offt_high_byte[7:0] r/w upper eight bits of pwm off time . pwm_ont_low register 0x 40 table 72. pwm_ont_low bit descriptions bits name r/w description [ 7:0] pwm_ont_low_byte[7:0] r/w lower eight bits of pwm on time . pwm_ont_high register 0x 41 table 73 . pwm_ont_high bit descriptions bits name r/w description [ 7:0] pwm_ont_high_byte[7:0] r/w upper eight bits of pwm on time . note that updated pwm times are not latched until this byte is wr itten to . pwm count times are referenced from the internal oscillator . the fastest oscillator setting is 500 khz ( 1 s increments). therefore , max imum on/off time is 1 s ( 2 16 ? 1) = 65.5 ms th is gives pwm frequencies from 500 khz down to 7.6 hz . pwm_c fg register 0x 42 table 74. pwm_cfg bit descriptions bits name r/w description [ 7:3] reserved. 2 pwm_in_and r/w and the internally generated pwm signal with an externally supplied pwm signal (c6) . 1 pwm_mode r/w defines pwm mode . 0 = continuous. 1 = one shot. if a one - shot is performed, the pwm_en bit is automatically cleared. if a second one - shot must be performed, the user must set pwm_en again. 0 pwm_en r/w enable pwm generator .
data sheet adp5589 rev. b | page 43 of 52 clock_div_cfg register 0x 43 table 75. clock_div_cfg bit descriptions bits name r/w description 7 reserved. 6 clk_inv r/w inverts the divided down clock signal. [ 5: 1] clk_div[4:0] r/w defines the divide down scale of the externally supplied clock. 00000 = divide by 1 (pas s - through). 00001 = divide by 2. 00010 = divide by 3. 00011 = divide by 4. 11111 = divide by 32. 0 clk_div_en r/w enable s the clock divider circuit to divide down the externally supplied clock signal . logic_1_cfg register 0x 44 table 76 . logic_1_cfg bit descriptions bits name r/w description 7 reserved. 6 ly1_inv r/w 0 = ly1 output not inverted before passing into logic block 1. 1 = inverts output ly1 from logic block 1. 5 lc1_inv r/w 0 = lc1 input not inverted before passing i nto logic block 1. 1 = inverts input lc1 before passing it into logic block 1. 4 lb1_inv r/w 0 = lb1 input not inverted before passing into logic block 1. 1 = inverts input lb1 before passing it into logic block 1. 3 la1_inv r/w 0 = la1 input not inverte d before passing into logic block 1. 1 = inverts input la1 before passing it into logic block 1. [ 2: 0] logic1_sel[2:0] r/w configure s the digital mux for logic block 1. 000 = o ff/disable . 001 = and1 . 010 = or1 . 011 = xor1 . 100 = ff1. 101 = in_la1 . 110 = in_lb1 . 111 = in_lc1 . logic_2_cfg register 0x 45 table 77 . logic_2_cfg bit descriptions bits name r/w description 7 ly1_cascade r/w 0 = use input la2 for logic block 2. 1 = use output ly1 from logic block 1 instead of la2 as the in put for logic block 2. the r0 pin can be used as gpio or key when cascade is in use. 6 ly2_inv r/w 0 = ly2 input not inverted before passing into logic block 2. 1 = inverts output ly2 from logic block 2. 5 lc2_inv r/w 0 = lc2 input not inverted before pa ssing into logic block 2. 1 = inverts input lc2 before passing it into logic block 2. 4 lb2_inv r/w 0 = lb2 input not inverted before passing into logic block 2. 1 = inverts input lb2 before passing it into logic block 2. 3 la2_inv r/w 0 = la2 input not inverted before passing into logic block 2. 1 = inverts input la2 before passing it into logic block 2.
adp5589 data sheet rev. b | page 44 of 52 bits name r/w description [ 2: 0] logic2_sel[2:0] r/w configure s the digital mux for logic block 2. 000 = o ff/disable . 001 = and2 . 010 = or2 . 011 = xor2 . 100 = ff2. 101 = in_la2 . 110 = in_lb2 . 111 = in_lc2 . logic_ff_cfg register 0x 46 table 78 . logic_ff_cfg bit descriptions bits name r/w description [ 7: 4] r/w reserved. 3 ff2_set r/w 0 = ff2 not set in logic block 2. 1 = set ff2 in logic block 2. 2 ff2_ clr r/w 0 = ff2 not cleared in logic block 2. 1 = clear ff2 in logic block 2. 1 ff1_set r/w 0 = ff1 not set in logic block 1. 1 = set ff1 in logic block 1. 0 ff1_clr r/w 0 = ff1 not cleared in logic block 1. 1 = c lear ff1 in logic block 1. logic_int_ev ent_en register 0x4 7 table 79. logic_int_event_en bit descriptions bits name r/w description [ 7: 6] r/w reserved. 5 ly2_dbnc_dis r/w 0 = output of logic block 2 is debounced before entering the event/interrupt block. 1 = output o f logic block 2 is not debounced before entering the event/interrupt block. use with caution because glitches may generate interrupts prematurely. 4 logic2_event_en r/w 0 = ly2 cannot generate interrupt. 1 = allow ly2 activity to generate events on the fi fo. 3 logic2_int_level r/w configure the logic level of ly2 that generates an interrupt. 0 = ly2 is active low. 1 = ly2 is active high. 2 ly1_dbnc_dis r/w 0 = output of logic block 1 is debounced before entering the event/interrupt block. 1 = output of l ogic block 1 is not debounced before entering the event/interrupt block. use with caution because glitches may generate interrupts prematurely. 1 logic1_event_en r/w 0 = ly1 cannot generate interrupt. 1 = allow ly1 activity to generate events on the fifo. 0 logic1_int_level r/w configure the logic level of ly1 that generate s an interrupt . 0 = ly1 is active low . 1 = ly1 is active high . poll_time_cfg register 0x 48 table 80. poll_ time_cfg bit descriptions bits name r/w description [ 7: 2 ] reserved. [ 1 : 0 ] key_poll_time[1:0] r/w configure time between consecutive scan cycles . 00 = 10 ms . 01 = 20 ms . 10 = 30 ms . 11 = 40 ms .
data sheet adp5589 rev. b | page 45 of 52 pin_config_a register 0x49 table 81. pin_config_a bit descriptions bits name r/w descr iption 7 r7_config r/w 0 = gpio 8. 1 = row 7. 6 r6_config r/w 0 = gpio 7. 1 = row 6. 5 r5_config r/w 0 = gpio 6. 1 = row 5. 4 r4_config r/w 0 = gpio 5 (see r4_extend_cfg in pin_ config _d register 0x4c table 84 f or alternate configuration, reset1). 1 = row 4. 3 r3_config r/w 0 = gpio 4 (see r3_extend_cfg[1:0] in pin_ config _d register 0x4c table 84 for alternate configuration, lc1/pwm_out/clk_out). 1 = row 3. 2 r2_config r/w 0 = gpio 3. 1 = row 2. 1 r1_config r/w 0 = gpio 2. 1 = row 1. 0 r0_config r/w 0 = gpio 1 (see r0_ extend_cfg in pin_ config _d register 0x4c table 84 for alternate configuration, ly1 ) . 1 = row 0 . pin_config_b r egister 0x4a table 82 . pin_config_b bit descriptions bits name r/w description 7 c7_config r/w 0 = gpio 16. 1 = column 7. 6 c6_config r/w 0 = gpio 15 (see c6_extend_cfg in pin_ config _d regi ster 0x4c table 84 for alternate configuration, lc2). 1 = column 6. 5 c5_config r/w 0 = gpio 14. 1 = column 5. 4 c4_config r/w 0 = gpio 13 (see c4_extend_cfg in pin_ config _d register 0x4c table 84 for alternate configuration, reset2). 1 = column 4. 3 c3_config r/w 0 = gpio 12. 1 = column 3. 2 c2_config r/w 0 = gpio 11. 1 = column 2. 1 c1_config r/w 0 = gpio 10. 1 = column 1. 0 c0_config r/w 0 = gpio 9 . 1 = column 0 . pin_config_ c register 0x4 b table 83 . pin_config_c bit descriptions bits name r/w description [ 7: 3 ] reserved. 2 c10_config r/w 0 = gpio 19. 1 = column 10. 1 c9_config r/w 0 = gpio 18 (see c9_extend_cfg in pin_ config _d register 0 x4c table 84 for alternate configuration, ly2). 1 = column 9. 0 c8_config r/w 0 = gpio 17 . 1 = column 8 .
adp5589 data sheet rev. b | page 46 of 52 pin_config_ d register 0x4 c table 84 . pin_config_d bit descriptions bits name r/w description 7 pull_select r/w 0 = 300 k? u sed for row pull - up during key scanning. 1 = 100 k? used for row pull - up during key scanning. 6 c4_extend_cfg r/w 0 = c4 remains configured as gpio 13. 1 = c4 reconfigured as reset2 output. 5 r4_extend_cfg r/w 0 = r4 remains configured as gpio 5. 1 = r4 reconfigured as reset1 output. 4 c6_extend_cfg r/w 0 = c6 remains configured as gpio 15. 1 = c6 reconfigured as lc2 input for logic block 2. [ 3:2 ] r3_extend_cfg[1:0] r/w 00 = r3 remains configured as gpio 4. 01 = r3 reconfigured as lc1 input for logic bl ock 1. 10 = r3 reconfigured as pwm_out/clk_out outputs from pwm and clock divider blocks. 11 = unused. 1 c9_extend_cfg r/w 0 = c9 remains configured as gpio 18. 1 = c9 reconfigured as ly2 output from logic block 2. 0 r0_ extend_cfg r/w 0 = r0 remains conf igured as gpio 1 . 1 = r0 re configured as ly1 output from logic block 1 . adp5589ac_z - 00 - r7, adp5589ac_z - 02- r7 default = 0000 0000 adp5589ac_z - 01 - r7 default = 0010 0000 general_cfg_b register 0x4d table 85 . general_cfg_b bit descri ptions bits name r/w description 7 osc_en r/w 0 = disable internal 1 mhz oscillator. 1 = enable internal 1 mhz oscillator. [ 6:5 ] core_freq[1:0] r/w sets the input clock frequency fed from the base 1 mhz oscillator to the digital core. slower frequencies result in less i dd . however, key and gpi scan times increase. 00 = 50 khz. 01 = 100 khz. 10 = 200 khz. 11 = 500 khz. 4 lck_trk_logic r/w 0 = allow logic outputs (programmed for fifo updates) to be tracked on the fifo if the keypad is locked. 1 = do not tr ack. 3 lck_trk_gpi r/w 0 = allow gpis (programmed for fifo updates) to be tracked on the fifo if the keypad is locked. 1 = do not track. 2 unused 1 int _cfg r/w configure the behavior of the int pin if the user tries to clear it while an interrupt is pending. 0 = int pin remains asserted if an interrupt is pending. 1 = int pin deasserts for 50 s and reasserts if an interrupt is pending. 0 rs t _c fg r/w configure the response adp5589 has to the rst pin . 0 = adp5589 resets if rst is low . 1 = adp5589 does not reset if rst is low .
data sheet adp5589 rev. b | page 47 of 52 int _ en register 0x4e table 86 . int_en bit descriptions bits name r/w description [ 7: 6 ] reserved. 5 logic2_ien r/w 0 = logic 2 interrupt is disabled. 1 = assert the int pin if logic2_int is set. 4 logic1_ien r/w 0 = logic 1 interrupt is disabled. 1 = assert the int pin if logic1_int is set. 3 lock_ien r/w 0 = lock interrupt is disabled. 1 = assert the int pin if lock_int is set. 2 ovrflow_ien r/w 0 = overflow interrupt is disabled. 1 = assert the int pin if ovrflow_int is set. 1 gpi_ien r/w 0 = gpi interrupt is disabled. 1 = assert the int pin if gpi_int is set. 0 event _ien r/w 0 = event interrupt is disabled. 1 = assert the int pin if event _int is set .
adp5589 data sheet rev. b | page 48 of 52 application diagram sda scl rst int vdd sda scl rst int i/o config key scan and decode gpi scan and decode logic1 logic2 clk div pwm reset1 gen reset2 gen i 2 c interface uvlo por oscillator registers vdd gnd host processor kp/logic1 output/gpi/gpo kp/logic1 input/gpi/gpo kp/logic1 input/gpi/gpo kp/logic1 input/gpi/gpo/pwm/clk kp/reset1 output/gpi/gpo vdd r2 r1 r0 r4 r3 r6 r5 r7 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 567891011 4321 16 17 18 19 20 21 22 15141312 27 28 29 30 31 32 33 26252423 38 39 40 41 42 43 44 37363534 49 50 51 52 53 54 55 48474645 60 61 62 63 64 65 66 59585756 71 72 73 74 75 76 77 70696867 82 83 84 85 86 87 88 81807978 09714-030 adp5589 figure 31. typical configuration
data sheet adp5589 rev. b | page 49 of 52 outline dimensions 0.40 bsc 0.50 0.40 0.30 0.25 0.20 0.15 compliant to jedec standards mo-220-wffe. bottom view top view exposed pad p i n 1 i n d i c a t o r 3.60 3.50 sq 3.40 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref 0.20 min coplanarity 0.08 pin 1 indicator 1 24 7 12 13 18 19 6 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 2.30 2.20 sq 2.10 04-13-2012-a figure 32. 24-lead lead frame chip scale package [lfcsp_wq] 3.5 mm 3.5 mm body, very very thin quad (cp-24-11) dimensions shown in millimeters 11-02-2012-a a b c d e 0.560 0.500 0.440 side view 0.230 0.200 0.170 0.300 0.260 0.220 coplanarity 0.05 seating plane 12 3 45 bottom view (ball side up) top view (ball side down) ball a1 identifier 0.40 ref 1.60 ref 2.030 1.990 sq 1.950 figure 33. 25-ball wafer level chip scale package [wlcsp] (cb-25-5) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adp5589acpz-00-r7 ?40c to +85c 24-lead lead frame chip scale package[lfcsp_wq] cp-24-11 adp5589acpz-01-r7 ?40c to +85c 24-lead lead frame chip scale package[lfcsp_wq] cp-24-11 adp5589acpz-02-r7 ?40c to +85c 24-lead lead frame chip scale package[lfcsp_wq] cp-24-11 adp5589acbz-00-r7 ?40c to +85c 25-ball wafer level chip scale package[wlcsp] cb-25-5 adp5589acbz-01-r7 ?40c to +85c 25-ball wafer level chip scale package[wlcsp] cb-25-5 adp5589acbz-02-r7 ?40c to +85c 25-ball wafer level chip scale package[wlcsp] cb-25-5 ADP5589CP-EVALZ evaluation board 1 z = rohs compliant part.
adp5589 data sheet rev. b | page 50 of 52 notes
data sheet adp5589 rev. b | page 51 of 52 notes
adp5589 data sheet rev. b | page 52 of 52 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2011 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their resp ective owners. d09714 - 0 - 1/13(b)

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