View M37516E6HKP_7197325.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose re lating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ship s, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use re nesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of c ontrolled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any fo rm, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics.
regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
7516 group (spec. h) single-chip 8-bit cmos microcomputer mitsubishi microcomputers description the 7516 group (spec. h) is the 8-bit microcomputer based on the 740 family core technology. the 7516 group (spec. h) is designed for the household products and office automation equipment and includes serial i/o functions, 8-bit timer, a-d converter, and i 2 c-bus interface. features basic machine-language instructions ...................................... 71 minimum instruction execution time .................................. 0.5 s (at 8 mhz oscillation frequency) memory size rom ............................................................... 16 k to 24 k bytes ram ................................................................... 512 to 640 bytes programmable input/output ports ............................................ 36 interrupts ................................................. 17 sources, 16 vectors timers ............................................................................. 8-bit ? 4 serial i/o1 ................... 8-bit ? 1 (uart or clock-synchronized) serial i/o2 ................................... 8-bit ? 1(clock-synchronized) multi-master i 2 c-bus interface (option) ...................... 1 channel pwm ............................................................................... 8-bit ? 1 a-d converter ............................................... 10-bit ? 6 channels watchdog timer ............................................................ 16-bit ? 1 pin configuration (top view) fig. 1 m37516mxh-xxxkp pin configuration clock generating circuit ..................................... built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) power source voltage in high-speed mode .................................................. 4.0 to 5.5 v (at 8 mhz oscillation frequency) in high-speed mode .................................................. 2.7 to 5.5 v (at 4 mhz oscillation frequency) in middle-speed mode ............................................... 2.7 to 5.5 v (at 8 mhz oscillation frequency) in low-speed mode .................................................... 2.7 to 5.5 v (at 32 khz oscillation frequency) power dissipation in high-speed mode .......................................................... 34 mw (at 8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ............................................................ 60 w (at 32 khz oscillation frequency, at 3 v power source voltage) operating temperature range .................................... ?0 to 85? application office automation equipment, fa equipment, household products, consumer electronics, etc. 22 12 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 21 20 19 18 17 16 15 14 33 32 31 30 29 28 27 26 25 24 23 13 m37516mxh-xxxkp packa g e t yp e : 44pjx-a p1 7 /(led 7 ) p1 2 /(led 2 ) p1 3 /(led 3 ) p1 4 /(led 4 ) p1 5 /(led 5 ) p1 6 /(led 6 ) v ss x out x in p0 0 /s in2 p0 1 /s out2 p0 2 /s clk2 p0 3 /s rdy2 p0 4 p0 5 p0 6 p1 1 /(led 1 ) p0 7 p1 0 /(led 0 ) reset p2 0 /x cout p2 1 /x cin p4 4 /int 3 /pwm p3 5 /an 5 p3 4 /an 4 p3 1 /an 1 p3 0 /an 0 v cc av ss p3 3 /an 3 p3 2 /an 2 v ref p4 5 p4 2 /int 1 p4 1 /int 0 p4 0 /cntr 1 p2 7 /cntr 0 /s rdy1 p2 6 /s clk1 p2 5 /scl 2 /t x d p2 3 /scl 1 p2 2 /sda 1 cnv ss p2 4 /sda 2 /r x d p4 3 /int 2 /s cmp2
2 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) functional block diagram fig.2 functional block diagram functional block int 0 cntr 0 cntr 1 v ref av ss ram rom cpu a x y s pc h pc l ps v ss 17 reset 14 v cc 40 11 cnv ss 41 42 x in 15 16 si/o1(8) x out x cin x cout p2(8) p3(6) p4(6) int 3 36 38 35 37 39 p1(8) p0(8) 26 27 28 29 30 31 32 33 pwm (8) x cin x cout si/o2(8) i 2 c(8) 44 2 4 13 43 34 79 1 3 81 0 1 2 56 20 22 25 21 23 24 18 19 main-clock input main-clock output sub-clock input sub-clock output clock generating circuit watchdog timer reset a-d converter (10) i/o port p4 i/o port p3 i/o port p2 i/o port p1 i/o port p0 prescaler 12 (8) timer 1 (8) timer 2 (8) timer x (8) timer y (8) prescaler x (8) prescaler y (8) reset input
3 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) table 1 pin description v cc , v ss cnv ss v ref avss reset x in x out p0 0 /s in2 p0 1 /s out2 p0 2 /s clk2 p0 3 /s rdy2 p0 4 p0 7 p1 0 p1 7 p2 0 /x cout p2 1 /x cin p2 2 /sda 1 p2 3 /scl 1 p2 4 /sda 2 /rxd p2 5 /scl 2 /txd p2 6 /s clk p2 7 /cntr 0 / s rdy1 p3 0 /an 0 p3 5 /an 5 p4 0 /cntr 1 p4 1 /int 0 p4 2 /int 1 p4 3 /int 2 /s cmp2 p4 4 /int 3 /pwm p4 5 functions name pin apply voltage of 2.7 v 5.5 v to vcc, and 0 v to vss. this pin controls the operation mode of the chip. normally connected to v ss . reference voltage input pin for a-d converter. analog power source input pin for a-d converter. connect to vss. reset input pin for active l . input and output pins for the clock generating circuit. connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level. cmos 3-state output structure. p1 0 to p1 7 (8 bits) are enabled to output large current for led drive. power source cnv ss input reference voltage input analog power source input reset input clock input clock output i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 function except a port function sub-clock generating circuit i/o pins (connect a resonator) i 2 c-bus interface function pins i 2 c-bus interface function pin/ serial i/o1 function pins serial i/o1 function pin serial i/o1 function pin/ timer x function pin serial i/o2 function pin a-d converter input pin timer y function pin interrupt input pins interrupt input pin/s cmp2 output pin interrupt input pin/pwm output pin 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level. p2 2 to p2 5 can be switched between cmos compat- ible input level or smbus input level in the i 2 c-bus interface function. p2 0 , p2 1 , p2 4 to p2 7 : cmos 3-state output structure. p2 4 , p2 5 : n-channel open-drain structure in the i 2 c- bus interface function. p2 2 , p2 3 : n-channel open-drain structure. 8-bit cmos i/o port with the same function as port p0. cmos compatible input level. cmos 3-state output structure. 8-bit cmos i/o port with the same function as port p0. cmos compatible input level. cmos 3-state output structure.
4 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) part numbering fig. 3 part numbering m37516 m 6 h xxx kp product name package type kp : 44pjx-a rom number omitted in one time prom version shipped in blank and flash memory version. rom/prom size 1 2 3 4 5 6 7 8 : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used as a user s rom area. memory type m : mask rom version e : one time prom version differences of functions : standard omitted in one time prom version shipped in blank and flash memory version. h : partial specification changed version : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes 9 a b c d e f
5 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) group expansion mitsubishi plans to expand the 7516 group (spec. h) as follows. memory type support for mask rom and one time prom versions. memory size mask rom size ................................................. 16 k to 24 k bytes one time prom size ..................................................... 24 k bytes ram size .............................................................. 512 to 640 bytes packages 44pjx-a ............................................... 44-pin plastic-molded qfn fig. 4 memory expansion plan memory expansion plan 32k 28k 24k 20k 16k 12k 8k 384 512 640 768 896 1024 1152 1280 1408 1536 2048 rom exteranal rom size (bytes) ram size ( b y tes ) aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaa aaaaaaa m37516m6h/e6h mass production aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa m37516m4h mass production as of oct. 2002
6 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) currently planning products are listed below. ram size (bytes) remarks package table 2 support products product name 16384 (16254) rom size (bytes) rom size for user in ( ) m37516m4h-xxxkp 44pjx-a mask rom version one time prom version (blank) 512 m37516m6h-xxxkp M37516E6HKP 24576 (24446) 640 as of oct. 2002
7 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) functional description central processing unit (cpu) the 7516 group (spec. h) uses the standard 740 family instruc- tion set. refer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for de- tails on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 6. store registers other than those described in figure 6 with pro- gram when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 5 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counterpc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
8 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) table 3 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 6 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p r e t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i ( p s )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 i n t e r r u p t s e r v i c e r o u t i n e p o p c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) ( s ) ( s ) 1 ( p c l )m ( s ) ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) p o p r e t u r n a d d r e s s f r o m s t a c k i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0
9 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed between accumulator and memory. when the t flag is 1 , direct arithmetic operations and direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 4 set and clear instructions of each bit of processor status register set instruction clear instruction c flag z flag i flag d flag b flag t flag v flag n flag sec clc _ _ sei cli sed cld _ _ set clt clv _ _ _ [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic.
10 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit, etc. the cpu mode register is allocated at address 003b 16 . fig. 7 structure of cpu mode register c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 ) b 7 b 0 fix this bit to 1 . s t a c k p a g e s e l e c t i o n b i t 0 : 0 p a g e 1 : 1 p a g e p r o c e s s o r m o d e b i t s b 1 b 0 00 : s i n g l e - c h i p m o d e 01 : 10 : n o t a v a i l a b l e 11 : port x c switch bit 0 : i/o port function (stop oscillating) 1 : x cin x cout oscillating function main clock (x in x out ) stop bit 0 : oscillating 1 : stopped main clock division ratio selection bits b7 b6 0 0 : = f(x in )/2 (high-speed mode) 0 1 : = f(x in )/8 (middle-speed mode) 1 0 : = f(x cin )/2 (low-speed mode) 1 1 : not available 1
11 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 8 memory map diagram 0100 16 0000 16 0040 16 ff00 16 ffdc 16 fffe 16 ffff 16 yyyy 16 zzzz 16 ram rom sfr area not used interrupt vector area reserved rom area ( 128 bytes ) zero page special page reserved rom area product name m37516m4h m37516m6h/e6h xxxx 16 ram size rom size rom size (bytes) 16384 24576 address yyyy 16 c000 16 a000 16 rom area address zzzz 16 c080 16 a080 16 ram size (bytes) address xxxx 16 023f 16 02bf 16 ram area 512 640 512 bytes 640 bytes 16 kbytes 24 kbytes reserved area 0440 16
12 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 9 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) transmit/receive buffer register (tb/rb) serial i/o1 status register (siosts) serial i/o1 control register (siocon) uart control register (uartcon) baud rate generator (brg) interrupt control register 2 (icon2) a-d conversion low-order register (adl) prescaler y (prey) timer y (ty) a-d control register (adcon) a-d conversion high-order register (adh) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) prescaler 12 (pre12) timer 2 (t2) prescaler x (prex) timer x (tx) timer 1 (t1) timer xy mode register (tm) i 2 c data shift register (s0) i 2 c address register (s0d) i 2 c status register (s1) i 2 c control register (s1d) i 2 c clock control register (s2) i 2 c start/stop condition control register (s2d) misrg watchdog timer control register (wdtcon) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) timer count source selection register (tcss) reserved ? reserved ? reserved ? ? reserved : do not write an y data to the reserved area. serial i/o2 control register 1 (sio2con1) serial i/o2 control register 2 (sio2con2) serial i/o2 register (sio2) reserved ?
13 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) pin name input/output i/o structure non-port function ref.no. table 5 i/o port function related sfrs i/o ports the i/o ports have direction registers which determine the input/ output direction of each individual pin. each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin becomes an output pin. if data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. port p0 port p1 port p3 input/output, individual bits cmos compatible input level cmos 3-state output sub-clock generating circuit cpu mode register (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) port p2 port p4 cmos compatible input level cmos/smbus input level (when selecting i 2 c-bus interface function) n-channel open-drain output cmos compatible input level cmos/smbus input level (when selecting i 2 c-bus interface function) cmos 3-state output n-channel open-drain output (when selecting i 2 c-bus interface function) cmos compatible input level cmos 3-state output i 2 c-bus interface func- tion i/o i 2 c-bus interface func- tion i/o serial i/o1 function i/o serial i/o1 function i/o i 2 c control register i 2 c control register serial i/o1 control register serial i/o1 control register serial i/o1 control register timer xy mode register a-d control register timer xy mode register interrupt edge selection register interrupt edge selection register serial i/o2 control register interrupt edge selection register pwm control register external interrupt input pwm output p0 0 /s in2 p0 1 /s out2 p0 2 /s clk2 p0 3 /s rdy2 p0 4 p0 7 p1 0 p1 7 p2 0 /x cout p2 1 /x cin p2 2 /sda 1 p2 3 /scl 1 serial i/o2 control register serial i/o2 function i/o p2 4 /sda 2 /rxd p2 5 /scl 2 /txd p2 6 /s clk (13) p2 7 /cntr 0 / s rdy1 serial i/o1 function i/o timer x function i/o a-d conversion input timer y function i/o external interrupt input p3 0 /an 0 p3 5 /an 5 p4 0 /cntr 1 p4 1 /int 0 p4 2 /int 1 p4 3 /int 2 /s cmp2 external interrupt input s cmp2 output p4 4 /int 3 /pwm p4 5 (14) (15) (16) (17) (18) (5)
14 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 10 port block diagram (1) (5) ports p0 4 p0 7 , p1, p4 5 (7) port p2 1 sda/scl pin selection bit (8) port p2 2 (4) port p0 3 (1) port p0 0 (6) port p2 0 port p2 1 (2) port p0 1 p0 1 /s out2 p-channel output disable bit (3) port p0 2 p0 2 /s clk2 p-channel output disable bit direction register data bus port latch direction register data bus port latch data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register serial i/o2 input serial i/o2 transmit completion signal serial i/o2 port selection bit serial i/o2 output s rdy2 output enable bit serial i/o2 ready output serial i/o2 synchronous clock selection bit serial i/o2 port selection bit serial i/o2 external clock input serial i/o2 clock output port x c switch bit port x c switch bit oscillator sda output sda input i 2 c-bus interface enable bit port x c switch bit sub-clock generating circuit input
15 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 11 port block diagram (2) (9) port p2 3 (10) port p2 4 (12) port p2 6 (11) port p2 5 (14) ports p3 0 p3 5 (13) port p2 7 (15) port p4 0 (16) ports p4 1 , p4 2 data bus port latch direction register sda/scl pin selection bit i 2 c-bus interface enable bit scl output scl input sda output sda input sda/scl pin selection bit i 2 c-bus interface enable bit data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register serial i/o1 input serial i/o1 enable bit receive enable bit serial i/o1 enable bit serial i/o1 mode selection bit serial i/o1 enable bit serial i/o1 synchronous clock selection bit external clock input serial i/o1 clock output p-channel output disable bit serial i/o1 enable bit transmit enable bit sda/scl pin selection bit i 2 c-bus interface enable bit scl input serial i/o1 output scl output cntr 0 interrupt input pulse output mode timer output serial ready output a-d converter input analog input pin selection bit interrupt input cntr 1 interrupt input pulse output mode timer output pulse output mode serial i/o1 enable bit serial i/o1 mode selection bit s rdy1 output enable bit
16 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 12 port block diagram (3) ( 1 8 ) p o r t p 4 4 p w m o u t p u t e n a b l e b i t p w m o u t p u t ( 1 7 ) p o r t p 4 3 d a t a b u s port latch d i r e c t i o n r e g i s t e r d a t a b u s port latc h direction re g ister s e r i a l i / o 2 i n p u t / o u t p u t c o m p a r i s o n s i g n a l c o n t r o l b i t s e r i a l i / o 2 i n p u t / o u t p u t c o m p a r i s o n s i g n a l o u t p u t i n t e r r u p t i n p u t interrupt input
17 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) interrupts interrupts occur by 17 sources among 17 sources: seven external, nine internal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the in- terrupt disable flag is 0 . interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts except the brk in- struction interrupt. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. notes when setting the followings, the interrupt request bit may be set to 1 . when setting external interrupt active edge related register: interrupt edge selection register (address 3a 16 ) i 2 c start/stop condition control register (address 30 16 ) timer xy mode register (address 23 16 ) when switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated related register: interrupt edge selection register (address 3a 16 ) when not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to 0 (disabled). ? set the interrupt edge select bit or the interrupt source select bit. ? set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to 1 (enabled).
18 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) interrupt request generating conditions remarks interrupt source low fffc 16 high fffd 16 priority 1 table 6 interrupt vector addresses and priority notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. vector addresses (note 1) reset (note 2) int 0 scl, sda int 1 int 2 int 3 serial i/o2 i 2 c timer x timer y timer 1 timer 2 serial i/o1 reception serial i/o1 transmission cntr 0 cntr 1 a-d converter brk instruction at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at detection of either rising or falling edge of int 2 input at detection of either rising or falling edge of int 3 input at completion of serial i/o2 data reception/transmission at completion of data transfer at completion of serial i/o1 data reception at completion of serial i/o1 transfer shift or when transmis- sion buffer is empty at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) stp release timer underflow at detection of either rising or falling edge of scl or sda input at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at completion of a-d conversion at brk instruction execution external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) switch by serial i/o2/int 3 interrupt source bit fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdc 16 ffdd 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 valid when serial i/o1 is selected valid when serial i/o1 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) non-maskable software interrupt
19 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 13 interrupt control fig. 14 structure of interrupt-related registers i n t e r r u p t d i s a b l e f l a g ( i ) i n t e r r u p t r e q u e s t i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t b r k i n s t r u c t i o n r e s e t b 7 b 0 b7 b0 b7 b0 b 7 b 0 b 7 b 0 i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r int 0 active edge selection bit int 1 active edge selection bit int 2 active edge selection bit int 3 active edge selection bit serial i/o2 / int 3 interrupt source bit 0 : int 3 interrupt selected 1 : serial i/o2 interrupt selected not used (returns 0 when read) ( i n t e d g e : a d d r e s s 0 0 3 a 1 6 ) 0 : falling edge active 1 : rising edge active interrupt request register 1 i n t 0 i n t e r r u p t r e q u e s t b i t s c l / s d a i n t e r r u p t r e q u e s t b i t i n t 1 i n t e r r u p t r e q u e s t b i t i n t 2 i n t e r r u p t r e q u e s t b i t i n t 3 / s e r i a l i / o 2 i n t e r r u p t r e q u e s t b i t i 2 c i n t e r r u p t r e q u e s t b i t t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r y i n t e r r u p t r e q u e s t b i t 0 : no interrupt request issued 1 : interrupt request issued ( i r e q 1 : a d d r e s s 0 0 3 c 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 t i m e r 1 i n t e r r u p t r e q u e s t b i t t i m e r 2 i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 r e c e p t i o n i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t i n t e r r u p t r e q u e s t b i t c n t r 0 i n t e r r u p t r e q u e s t b i t c n t r 1 i n t e r r u p t r e q u e s t b i t a d c o n v e r t e r i n t e r r u p t r e q u e s t b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) (ireq2 : address 003d 16 ) 0 : no interrupt request issued 1 : interrupt request issued interrupt control register 1 i n t 0 i n t e r r u p t e n a b l e b i t s c l / s d a i n t e r r u p t e n a b l e b i t i n t 1 i n t e r r u p t e n a b l e b i t i n t 2 i n t e r r u p t e n a b l e b i t i n t 3 / s e r i a l i / o 2 i n t e r r u p t e n a b l e b i t i 2 c i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t t i m e r y i n t e r r u p t e n a b l e b i t ( i c o n 1 : a d d r e s s 0 0 3 e 1 6 ) interrupt control register 2 timer 1 interrupt enable bit timer 2 interrupt enable bit serial i/o1 reception interrupt enable bit serial i/o1 transmit interrupt enable bit cntr 0 interrupt enable bit cntr 1 interrupt enable bit ad converter interrupt enable bit not used (returns 0 when read) (do not write 1 to this bit.) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d
20 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) timers the 7516 group (spec. h) has four timers: timer x, timer y, timer 1, and timer 2. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are count down. when the timer reaches 00 16 , an un- derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit corresponding to that timer is set to 1 . timer x and timer y timer x and timer y can each select in one of four operating modes by setting the timer xy mode register. (1) timer mode the timer counts the count source selected by timer count source selection bit. (2) pulse output mode the timer counts the count source selected by timer count source selection bit. whenever the contents of the timer reach 00 16 , the signal output from the cntr 0 (or cntr 1 ) pin is inverted. if the cntr 0 (or cntr 1 ) active edge selection bit is 0 , output begins at h . if it is 1 , output starts at l . when using a timer in this mode, set the corresponding port p2 7 ( or port p4 0 ) direction register to out- put mode. (3) event counter mode operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the cntr 0 or cntr 1 pin. when the cntr 0 (or cntr 1 ) active edge selection bit is 0 , the rising edge of the cntr 0 (or cntr 1 ) pin is counted. when the cntr 0 (or cntr 1 ) active edge selection bit is 1 , the falling edge of the cntr 0 (or cntr 1 ) pin is counted. (4) pulse width measurement mode if the cntr 0 (or cntr 1 ) active edge selection bit is 0 , the timer counts the selected signals by the count source selection bit while the cntr 0 (or cntr 1 ) pin is at h . if the cntr 0 (or cntr 1 ) ac- tive edge selection bit is 1 , the timer counts it while the cntr 0 (or cntr 1 ) pin is at l . the count can be stopped by setting 1 to the timer x (or timer y) count stop bit in any mode. the corresponding interrupt request bit is set each time a timer underflows. fig. 15 structure of timer xy mode register note when switching the count source by the timer 12, x and y count source bits, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. therefore, select the timer count source before set the value to the prescaler and the timer. when timer x/timer y underflow while executing the instruction which sets 1 to the timer x/timer y count stop bits, the timer x/ timer y interrupt request bits are set to 1 . timer x/timer y in- terrupts are received if these interrupts are enabled at this time. the timing which interrupt is accepted has a case after the in- struction which sets 1 to the count stop bit, and a case after the next instruction according to the timing of the timer under- flow. when this interrupt is unnecessary, set 0 (disabled) to the interrupt enable bit and then set 1 to the count stop bit. fig. 16 structure of timer count source selection register timer 1 and timer 2 the count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. the out- put of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. t i m e r x c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r x y m o d e r e g i s t e r ( t m : a d d r e s s 0 0 2 3 1 6 ) t i m e r y o p e r a t i n g m o d e b i t s 0 0 : t i m e r m o d e 0 1 : p u l s e o u t p u t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h m e a s u r e m e n t m o d e cntr 1 active edge selection bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b 7 c n t r 0 a c t i v e e d g e s e l e c t i o n b i t 0 : i n t e r r u p t a t f a l l i n g e d g e c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e 1 : i n t e r r u p t a t r i s i n g e d g e c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e b 0 t i m e r x o p e r a t i n g m o d e b i t s 0 0 : t i m e r m o d e 0 1 : p u l s e o u t p u t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h m e a s u r e m e n t m o d e b 1 b 0 b5b4 t i m e r y c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( t c s s : a d d r e s s 0 0 2 8 1 6 ) b 7 b 0 t i m e r x c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 a t l o w - s p e e d m o d e ) 1 : f ( x i n ) / 2 ( f ( x c i n ) / 2 a t l o w - s p e e d m o d e ) t i m e r y c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 a t l o w - s p e e d m o d e ) 1 : f ( x i n ) / 2 ( f ( x c i n ) / 2 a t l o w - s p e e d m o d e ) t i m e r 1 2 c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 a t l o w - s p e e d m o d e ) 1 : f ( x c i n ) n o t u s e d ( r e t u r n s 0 w h e n r e a d )
21 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 17 block diagram of timer x, timer y, timer 1, and timer 2 q q 1 0 p 2 7 / c n t r 0 / s r d y 1 q q p4 0 /cntr 1 0 1 r r 1 0 0 1 t t p r e s c a l e r x l a t c h ( 8 ) prescaler x (8) t i m e r x l a t c h ( 8 ) timer x (8) t o t i m e r x i n t e r r u p t r e q u e s t b i t toggle flip-flop t i m e r x c o u n t s t o p b i t p u l s e w i d t h m e a s u r e m e n t m o d e e v e n t c o u n t e r m o d e t o c n t r 0 i n t e r r u p t r e q u e s t b i t pulse output mode p o r t p 2 7 l a t c h port p2 7 direction register cntr 0 active edge selection bit timer x latch write pulse pulse output mode t i m e r m o d e p u l s e o u t p u t m o d e prescaler y latch (8) prescaler y (8) t i m e r y l a t c h ( 8 ) timer y (8) t o t i m e r y i n t e r r u p t r e q u e s t b i t t o g g l e f l i p - f l o p t i m e r y c o u n t s t o p b i t to cntr 1 interrupt request bit pulse output mode p o r t p 4 0 l a t c h port p4 0 direction register c n t r 1 a c t i v e e d g e s e l e c t i o n b i t timer y latch write pulse pulse output mode timer mode pulse output mod e data bus d a t a b u s prescaler 12 latch (8) p r e s c a l e r 1 2 ( 8 ) timer 1 latch (8) timer 1 (8) data bus timer 2 latch (8) timer 2 (8) to timer 2 interrupt request bit t o t i m e r 1 i n t e r r u p t r e q u e s t b i t c n t r 0 a c t i v e e d g e s e l e c t i o n b i t c n t r 1 a c t i v e e d g e s e l e c t i o n b i t p u l s e w i d t h m e a s u r e - m e n t m o d e event counter mode f(x cin ) t i m e r 1 2 c o u n t s o u r c e s e l e c t i o n b i t f ( x i n ) / 1 6 f(x in )/2 timer y count source selection bit f(x in )/16 f ( x i n ) / 2 t i m e r x c o u n t s o u r c e s e l e c t i o n b i t f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 a t l o w - s p e e d m o d e ) ( f ( x c i n ) / 2 a t l o w - s p e e d m o d e ) (f(x cin )/16 at low-speed mode) (f(x cin )/2 at low-speed mode) ( f ( x c i n ) / 1 6 a t l o w - s p e e d m o d e )
22 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) serial i/o serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register (bit 6 of address 001a 16 ) to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. fig. 18 block diagram of clock synchronous serial i/o1 fig. 19 operation of clock synchronous serial i/o1 function 1/4 1/4 f/f p2 6 /s clk serial i/o1 status register serial i/o1 control register p2 7 /s rdy1 p2 4 /r x d p2 5 /t x d x in receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector transmit buffer register data bus address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit shift register d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd serial input rxd write pulse to receive/transmit buffer register (address 0018 16 ) overrun error (oe) detection notes 1: as the transmit interrupt (ti), either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes 1 . receive enable signal s rdy1
23 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode selection bit (b6) of the serial i/o1 control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 20 block diagram of uart serial i/o1 x i n 1 / 4 o e p efe 1/16 1/16 d a t a b u s r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r receive buffer full flag (rbf) receive interrupt request (ri) b a u d r a t e g e n e r a t o r f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) address 001c 16 st/sp/pa generator t r a n s m i t b u f f e r r e g i s t e r d a t a b u s transmit shift register address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) address 0019 16 s t d e t e c t o r sp detector u a r t c o n t r o l r e g i s t e r a d d r e s s 0 0 1 b 1 6 character length selection bit a d d r e s s 0 0 1 a 1 6 brg count source selection bit transmit interrupt source selection bit serial i/o1 synchronous clock selection bit c l o c k c o n t r o l c i r c u i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s s e r i a l i / o 1 c o n t r o l r e g i s t e r p2 6 /s cl k serial i/o1 status register p 2 4 / r x d p 2 5 / t x d
24 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 21 operation of uart serial i/o1 function [transmit buffer register/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0 . [serial i/o1 status register (siosts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to 1 , the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [serial i/o1 control register (siocon)] 001a 16 the serial i/o1 control register consists of eight control bits for the serial i/o1 function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is al- ways valid and sets the output structure of the p2 5 /t x d pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes 1 (at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes 1, can be selected to occur depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes 1. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes serial output t x d serial input r x d receive buffer read signal
25 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) notes on serial i/o1 1. when using the serial i/o1, clear the i 2 c-bus interface enable bit to 0 or the sda/scl interrupt pin selection bit to 0 . 2. when setting the transmit enable bit of serial i/o1 to 1 , the serial i/o1 transmit interrupt request bit is automatically set to 1 . when not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. ? set the serial i/o1 transmit interrupt enable bit to 0 (dis- abled). ? set the transmit enable bit to 1 . ? set the serial i/o1 transmit interrupt request bit to 0 after 1 or more instructions have been executed. ? set the serial i/o1 transmit interrupt enable bit to 1 (en- abled). fig. 22 structure of serial i/o1 control registers b 7 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s e r i a l i / o 1 s t a t u s r e g i s t e r serial i/o1 control register b 7 b 0 b 0 brg count source selection bit (css) 0: f(x in ) 1: f(x in )/4 serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o1 is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o1 is selected, external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p2 7 pin operates as ordinary i/o pin 1: p2 7 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p2 4 to p2 7 operate as ordinary i/o pins) 1: serial i/o1 enabled (pins p2 4 to p2 7 operate as serial i/o1 pins) b 7 u a r t c o n t r o l r e g i s t e r c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) 0 : 8 b i t s 1 : 7 b i t s p a r i t y e n a b l e b i t ( p a r e ) 0 : p a r i t y c h e c k i n g d i s a b l e d 1 : p a r i t y c h e c k i n g e n a b l e d p a r i t y s e l e c t i o n b i t ( p a r s ) 0 : e v e n p a r i t y 1 : o d d p a r i t y s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) 0 : 1 s t o p b i t 1 : 2 s t o p b i t s p 2 5 / t x d p - c h a n n e l o u t p u t d i s a b l e b i t ( p o f f ) 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n d r a i n o u t p u t ( i n o u t p u t m o d e ) n o t u s e d ( r e t u r n 1 w h e n r e a d ) b 0 (siosts : address 0019 16 ) (siocon : address 001a 16 ) ( u a r t c o n : a d d r e s s 0 0 1 b 1 6 )
26 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) serial i/o2 the serial i/o2 can be operated only as the clock synchronous type. as a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial i/o2 synchronous clock selection bit (b6) of serial i/o2 control register 1. the internal clock incorporates a dedicated divider and permits se- lecting 6 types of clock by the internal synchronous clock selection bits (b2, b1, b0) of serial i/o2 control register 1. regarding s out2 and s clk2 being output pins, either cmos output format or n-channel open-drain output format can be selected by the p0 1 /s out2 , p0 2 /s clk2 p-channel output disable bit (b7) of serial i/o2 control register 1. when the internal clock has been selected, a transfer starts by a write signal to the serial i/o2 register (address 0017 16 ). after comple- tion of data transfer, the level of the s out2 pin goes to high imped- ance automatically but bit 7 of the serial i/o2 control register 2 is not set to 1 automatically. when the external clock has been selected, the contents of the serial i/o2 register is continuously sifted while transfer clocks are input. accordingly, control the clock externally. note that the s out2 pin does not go to high impedance after completion of data transfer. to cause the s out2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial i/o2 control reg- ister 2 to 1 when s clk2 is h after completion of data transfer. after the next data transfer is started (the transfer clock falls), bit 7 of the serial i/o2 control register 2 is set to 0 and the s out2 pin is put into the active state. regardless of the internal clock to external clock, the interrupt re- quest bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. in case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial i/o2 register becomes a fractional number of bits close to msb if the transfer direction selection bit of serial i/o2 control regis- ter 1 is lsb first, or a fractional number of bits close to lsb if the transfer direction selection bit is msb first. for the remaining bits, the previously received data is shifted. at transmit operation using the clock synchronous serial i/o, the s cmp2 signal can be output by comparing the state of the transmit pin s out2 with the state of the receive pin s in2 in synchronization with a rise of the transfer clock. if the output level of the s out2 pin is equal to the input level to the s in2 pin, l is output from the s cmp2 pin. if not, h is output. at this time, an int 2 interrupt request can also be gener- ated. select a valid edge by bit 2 of the interrupt edge selection reg- ister (address 003a 16 ). [serial i/o2 control registers 1, 2 (sio2con1 / sio2con2)] 0015 16, 0016 16 the serial i/o2 control registers 1 and 2 are containing various se- lection bits for serial i/o2 control as shown in figure 23. fig. 23 structure of serial i/o2 control registers 1, 2 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 ( s i o 2 c o n 1 : a d d r e s s 0 0 1 5 1 6 ) s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 ( s i o 2 c o n 2 : a d d r e s s 0 0 1 6 1 6 ) b7 b0 optional transfer bits b2 b1 b0 0 0 0: 1 bit 0 0 1: 2 bit 0 1 0: 3 bit 0 1 1: 4 bit 1 0 0: 5 bit 1 0 1: 6 bit 1 1 0: 7 bit 1 1 1: 8 bit not used ( returns "0" when read) serial i/o2 i/o comparison signal control bit 0: p4 3 i/o 1: s cmp2 output s out2 pin control bit (p0 1 ) 0: output active 1: output high-impedance i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s b 2 b 1 b 0 0 0 0 : f ( x i n ) / 8 ( f ( x c i n ) / 8 i n l o w - s p e e d m o d e ) 0 0 1 : f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 i n l o w - s p e e d m o d e ) 0 1 0 : f ( x i n ) / 3 2 ( f ( x c i n ) / 3 2 i n l o w - s p e e d m o d e ) 0 1 1 : f ( x i n ) / 6 4 ( f ( x c i n ) / 6 4 i n l o w - s p e e d m o d e ) 1 1 0 : f ( x i n ) / 1 2 8 f ( x c i n ) / 1 2 8 i n l o w - s p e e d m o d e ) 1 1 1 : f ( x i n ) / 2 5 6 ( f ( x c i n ) / 2 5 6 i n l o w - s p e e d m o d e ) s e r i a l i / o 2 p o r t s e l e c t i o n b i t 0 : i / o p o r t 1 : s o u t 2 , s c l k 2 o u t p u t p i n s r d y 2 o u t p u t e n a b l e b i t 0 : p 0 3 p i n i s n o r m al i / o p i n 1 : p 0 3 p i n i s s r d y 2 o u t p u t p i n t r a n s f e r d i r e c t i o n s e l e c t i o n b i t 0 : l s b f i r s t 1 : m s b f i r s t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k p 0 1 / s o u t 2 , p 0 2 / s c l k 2 p - c h a n n e l o u t p u t d i s a b l e b i t 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n - d r a i n o u t p u t ( i n o u t p u t m o d e ) b 7 b 0
27 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 24 block diagram of serial i/o2 fig. 25 timing chart of serial i/o2 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 t r a n s f e r c l o c k ( n o t e 1 ) s e r i a l i / o 2 o u t p u t s o u t 2 s e r i a l i / o 2 i n p u t s i n 2 r e c e i v e e n a b l e s i g n a l s r d y 2 w r i t e - i n s i g n a l t o s e r i a l i / o 2 r e g i s t e r ( n o t e 2 ) s e r i a l i / o 2 i n t e r r u p t r e q u e s t b i t s e t . 1 : w h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s a t r a n s f e r c l o c k , t h e f ( x i n ) c l o c k d i v i s i o n ( f ( x c i n ) i n l o w - s p e e d m o d e ) c a n b e s e l e c t e d b y s e t t i n g b i t s 0 t o 2 o f s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 . 2 : w h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s a t r a n s f e r c l o c k , t h e s o u t 2 p i n h a s h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n . n o t e s x in 1 0 0 1 0 1 s r d y 2 s c l k 2 0 1 1/8 1/16 1 / 3 2 1 / 6 4 1 / 1 2 8 1 / 2 5 6 1 0 x cin 1 0 0 0 0 1 data bus serial i/o2 interrupt request s e r i a l i / o 2 p o r t s e l e c t i o n b i t s e r i a l i / o c o u n t e r 2 ( 3 ) s e r i a l i / o 2 r e g i s t e r ( 8 ) s y n c h r o n o u s c i r c u i t s e r i a l i / o 2 p o r t s e l e c t i o n b i t serial i/o2 synchronous clock selection bit s r d y 2 o u t p u t e n a b l e b i t e x t e r n a l c l o c k internal synchronous clock selection bits d i v i d e r optional transfer bits (3) p0 2 /s clk2 p 0 1 / s o u t 2 p0 0 /s in2 p 0 2 l a t c h p 0 1 l a t c h p 0 3 l a t c h p 0 3 / s r d y 2 p4 3 /s cmp2 /int 2 serial i/o2 i/o comparison signal control bit p4 3 latch q d main clock division ratio selection bits (note) note: either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of cpu mode register.
28 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 26 s cmp2 output operation s c l k 2 s i n 2 s o u t 2 s c m p 2 j u d g e m e n t o f i / o d a t a c o m p a r i s o n
29 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at = 4 mhz) table 7 multi-master i 2 c-bus interface functions item format communication mode system clock = f(x in )/2 (high-speed mode) = f(x in )/8 (middle-speed mode) multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchro- nous functions, is useful for the multi-master serial communications. figure 27 shows a block diagram of the multi-master i 2 c-bus in- terface and table 7 lists the multi-master i 2 c-bus interface functions. this multi-master i 2 c-bus interface consists of the i 2 c address register, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register, the i 2 c start/stop condition control register and other control circuits. when using the multi-master i 2 c-bus interface, set 1 mhz or more to . note: mitsubishi electric corporation assumes no responsibility for in- fringement of any third-party s rights or originating in the use of the connection control function between the i 2 c-bus interface and the ports scl 1 , scl 2 , sda 1 and sda 2 with the bit 6 of i 2 c control regis- ter (002e 16 ). fig. 27 block diagram of multi-master i 2 c-bus interface ? : purchase of mitsubishi electric corporations i 2 c components conveys a license under the philips i 2 c patent rights to use these components an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. scl clock frequency i 2 c address register b 7b0 s a d 6s a d 5sad 4 sad 3 sad2 sad1 s a d 0r w b noise elimination circui t a d d r e s s c o m p a r a t o r b7 i 2 c data shift register b0 d a t a c o n t r o l c i r c u i t system clock ( ) interrupt generating circuit i n t e r r u p t r e q u e s t s i g n a l ( i i c i r q ) b7 mst trx bb pin a l a a s a d 0 lrb b 0 s1 b 7b 0 tis s 10bit sad a l s b c 2b c 1b c 0 s1d bi t counte r bb circuit clock control circuit n o i s e e l i m i n a t i o n c i r c u i t b 7b0 ac k a c k b i t fast mode c c r 4c c r 3 c c r 2 ccr1 ccr 0 i nterna l d ata b us cl oc k di v i s i on s 0 s2 s0d a l c i r c u i t e s 0 sis i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r sip ssc 4 s s c 3 s s c 2 ssc1 s s c 0 i 2 c c l o c k c o n t r o l r e g i s t e r i 2 c status register s 2 d tsel i 2 c c l o c k c o n t r o l r e g i s t e r s1d i c control register 2 serial data (s da ) serial clock (s cl )
30 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) [i 2 c data shift register (s0)] 002b 16 the i 2 c data shift register (s0 : address 002b 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted by one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted by one bit to the left. the minimum 2 machine cycles are required from the rising of the s cl clock until input to this register. the i 2 c data shift register is in a write enable status only when the i 2 c-bus interface enable bit (es0 bit : bit 3 of address 002e 16 ) of the i 2 c control register is 1 . the bit counter is reset by a write in- struction to the i 2 c data shift register. when both the es0 bit and the mst bit of the i 2 c status register (address 002d 16 ) are 1, the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift register is always enabled re- gardless of the es0 bit value. [i 2 c address register (s0d)] 002c 16 the i 2 c address register (address 002c 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the start condition is de- tected. ?it 0: read/write bit (rwb) this is not used in the 7-bit addressing mode. in the 10-bit ad- dressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rwb) of the i 2 c address reg- ister. the rwb bit is cleared to 0 automatically when the stop condi- tion is detected. ?its 1 to 7: slave address (sad0?ad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. fig. 28 structure of i 2 c address register s a d 6 sad5 s a d 4s a d 3s a d 2 sad1 sad 0 rwb s l a v e a d d r e s s i 2 c a d d r e s s r e g i s t e r ( s 0 d : a d d r e s s 0 0 2 c 1 6 ) r e a d / w r i t e b i t b7 b 0
31 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) table 8 set values of i 2 c clock control register and scl frequency fig. 29 structure of i 2 c clock control register scl frequency (note 1) (at = 4 mhz, unit : khz) setting value of ccr4 ccr0 standard clock mode setting disabled setting disabled setting disabled high-speed clock mode ccr4 0 0 0 0 0 0 0 1 1 1 ccr3 0 0 0 0 0 0 0 1 1 1 ccr2 0 0 0 0 1 1 1 1 1 1 ccr1 0 0 1 1 0 0 1 0 1 1 ccr0 0 1 0 1 0 1 0 1 0 1 setting disabled setting disabled setting disabled 34.5 33.3 32.3 100 83.3 333 250 400 (note 3) 166 (note 2) (note 2) [i 2 c clock control register (s2)] 002f 16 the i 2 c clock control register (address 002f 16 ) is used to set ack control, scl mode and scl frequency. ?its 0 to 4: scl frequency control bits (ccr0?cr4) these bits control the scl frequency. refer to table 8. ?it 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the standard clock mode is selected. when the bit is set to 1, the high-speed clock mode is selected. when connecting the bus of the high-speed mode i 2 c bus stan- dard (maximum 400 kbits/s), use 8 mhz or more oscillation frequency f(x in ) and 2 division clock. ?it 6: ack bit (ack bit) this bit sets the sda status when an ack clock ? is generated. when this bit is set to 0, the ack return mode is selected and sda goes to l at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is selected. the sda is held in the h status at the occurrence of an ack clock. however, when the slave address agree with the address data in the reception of address data at ack bit = 0, the sda is auto- matically made l (ack is returned). if there is a disagreement between the slave address and the address data, the sda is auto- matically made h (ack is not returned). ? ack clock: clock for acknowledgment ?it 7: ack clock bit (ack) this bit specifies the mode of acknowledgment which is an ac- knowledgment response of data transfer. when this bit is set to 0, the no ack clock mode is selected. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is selected and the master generates an ack clock each completion of each 1-byte data transfer. the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (makes sda h ) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transfer. if data is written during transfer, the i 2 c clock generator is reset, so that data cannot be transferred normally. a c k a c k b i t fast mode c c r 4c c r 3 c c r 2ccr1c c r 0 i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 : a d d r e s s 0 0 2 f 1 6 ) b7 b0 s c l f r e q u e n c y c o n t r o l b i t s r e f e r t o t a b l e 8 . s c l m o d e s p e c i f i c a t i o n b i t 0 : s t a n d a r d c l o c k m o d e 1 : h i g h - s p e e d c l o c k d a c k b i t 0 : a c k i s r e t u r n e d . 1 : a c k i s n o t t d a c k c l o c k b i t 0 : n o a c k c l o c k 1 : a c k c l o c k 500/ccr value (note 3) 1000/ccr value (note 3) 17.2 16.6 16.1 notes 1: duty of s cl clock output is 50 %. the duty becomes 35 to 45 % only when the high-speed clock mode is selected and ccr value = 5 (400 khz, at = 4 mhz). h duration of the clock fluctuates from 4 to +2 machine cycles in the standard clock mode, and fluctuates from 2 to +2 machine cycles in the high-speed clock mode. in the case of negative fluctuation, the frequency does not increase because l duration is extended instead of h duration reduction. these are value when s cl clock synchronization by the synchro- nous function is not performed. ccr value is the decimal notation value of the s cl frequency control bits ccr4 to ccr0. 2: each value of s cl frequency exceeds the limit at = 4 mhz or more. when using these setting value, use of 4 mhz or less. 3: the data formula of s cl frequency is described below: /(8 ? ccr value) standard clock mode /(4 ? ccr value) high-speed clock mode (ccr value 5) /(2 ? ccr value) high-speed clock mode (ccr value = 5) do not set 0 to 2 as ccr value regardless of frequency. set 100 khz (max.) in the standard clock mode and 400 khz (max.) in the high-speed clock mode to the s cl frequency by set- ting the s cl frequency control bits ccr4 to ccr0.
32 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 31 structure of i 2 c control register [i 2 c control register (s1d)] 002e 16 the i 2 c control register (address 002e 16 ) controls data communi- cation format. ?its 0 to 2: bit counter (bc0?c2) these bits decide the number of bits for the next 1-byte data to be transmitted. the i 2 c interrupt request signal occurs immediately after the number of count specified with these bits (ack clock is added to the number of count when ack clock is selected by ack clock bit (bit 7 of address 002f 16 )) have been transferred, and bc0 to bc2 are returned to 000 2 . also when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. ?it 3: i 2 c interface enable bit (es0) this bit enables to use the multi-master i 2 c-bus interface. when this bit is set to 0, the use disable status is provided, so that the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when es0 = 0, the following is performed. pin = 1, bb = 0 and al = 0 are set (which are bits of the i 2 c status register at address 002d 16 ). writing data to the i 2 c data shift register (address 002b 16 ) is dis- abled. ?it 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that address data is recognized. when a match is found between a slave address and address data as a result of comparison or when a general call (refer to i 2 c status register, bit 1) is received, transfer processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recognized. ?it 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address regis- ter (address 002c 16 ) are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, and all the bits of the i 2 c address register are compared with address data. ?it 6: sda/scl pin selection bit this bit selects the input/output pins of scl and sda of the multi- master i 2 c-bus interface. ?it 7: i 2 c-bus interface pin input level selection bit this bit selects the input level of the scl and sda pins of the multi-master i 2 c-bus interface. fig. 30 sda/scl pin selection bit s c l s d a multi-master i c-bus interface 2 t s e l s c l 1 / p 2 3 s c l 2 / t x d / p 2 5 s d a 1 / p 2 2 s d a 2 / r x d / p 2 4 t s e l t s e l t s e l b7 tiss tsel 10 bit sad als es0 bc2 bc1 bc0 b0 sda/scl pin selection bit 0 : connect to ports p2 2 , p2 3 1 : connect to ports p2 4 , p2 5 i 2 c control register (s1d : address 002e 16 ) bit counter (number of transmit/receive bits) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 i 2 c-bus interface enable bit 0 : disabled 1 : enabled data format selection bit 0 : addressing format 1 : free data format addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format i 2 c-bus interface pin input level selection bit 0 : cmos input 1 : smbus input
33 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) ?it 4: scl pin low hold bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the pin bit changes from 1 to 0. at the same time, an interrupt request signal occurs to the cpu. the pin bit is set to 0 in synchronization with a falling of the last clock (in- cluding the ack clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 33 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in one of the following conditions: executing a write instruction to the i 2 c data shift register (ad- dress 002b 16 ). (this is the only condition which the prohibition of the internal clock is released and data can be communicated ex- cept for the start condition detection.) when the es0 bit is 0 at reset when writing 1 to the pin bit by software the conditions in which the pin bit is set to 0 are shown below: immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) immediately after completion of 1-byte data reception in the slave reception mode, with als = 0 and immediately af- ter completion of slave address agreement or general call address reception in the slave reception mode, with als = 1 and immediately af- ter completion of address data reception ?it 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. the bb flag is set/reset by the scl, sda pins input signal regardless of master/slave. this flag is set to 1 by detecting the start condition, and is set to 0 by detecting the stop condition. the condition of these detecting is set by the start/stop condition setting bits (ssc4 ssc0) of the i 2 c start/stop condition control register (address 0030 16 ). when the es0 bit of the i 2 c control register (address 002e 16 ) is 0 or reset, the bb flag is set to 0. for the writing function to the bb flag, refer to the sections start condition generating method and stop condition gen- erating method described later. [i 2 c status register (s1)] 002d 16 the i 2 c status register (address 002d 16 ) controls the i 2 c-bus in- terface status. the low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. set 0000 2 to the low-order 4 bits, because these bits become the reserved bits at writing. ?it 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 002b 16 ). ?it 1: general call detecting flag (ad0) when the als bit is 0 , this bit is set to 1 when a general call ? whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives con- trol data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start condition, or reset. ? general call: the master transmits the general call address 00 16 to all slaves. ?it 2: slave address comparison flag (aas) this flag indicates a comparison result of address data when the als bit is 0 . ? in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions: the address data immediately after occurrence of a start condition agrees with the slave address stored in the high-or- der 7 bits of the i 2 c address register (address 002c 16 ). a general call is received. ? in the slave receive mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition: when the address data is compared with the i 2 c address reg- ister (8 bits consisting of slave address and rwb bit), the first bytes agree. ? this bit is set to 0 by executing a write instruction to the i 2 c data shift register (address 002b 16 ) when es0 is set to 1 or reset. ?it 3: arbitration lost ? detecting flag (al) in the master transmission mode, when the sda is made l by any other device, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immediately after transmission of the byte whose arbitration was lost is completed, the mst bit is set to 0. the arbitration lost can be detected only in the master transmission mode. when ar- bitration is lost during slave address transmission, the trx bit is set to 0 and the reception mode is set. consequently, it becomes possible to detect the agreement of its own slave address and ad- dress data transmitted by another master device. ? arbitration lost : the status in which communication as a master is dis- abled.
34 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 33 interrupt request signal generating timing fig. 32 structure of i 2 c status register ?it 6: communication mode specification bit (transfer direc- tion specification bit: trx) this bit decides a direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a transmitting device is received. when the bit is 1, the transmis- sion mode is selected and address data and control data are output onto the sda in synchronization with the clock generated on the s cl . this bit is set/reset by software and hardware. about set/reset by hardware is described below. this bit is set to 1 by hardware when all the following conditions are satisfied: when als is 0 in the slave reception mode or the slave transmission mode when the r/w bit reception is 1 this bit is set to 0 in one of the following conditions: when arbitration lost is detected. when a stop condition is detected. when writing 1 to this bit by software is invalid by the start condition duplication preventing function (note) . with mst = 0 and when a start condition is detected. with mst = 0 and when ack non-return is detected. at reset ?it 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are generated. additionally, the clocks required for data communi- cation are generated on the scl. this bit is set to 0 in one of the following conditions. immediately after completion of 1-byte data transfer when arbi- tration lost is detected when a stop condition is detected. writing 1 to this bit by software is invalid by the start condi- tion duplication preventing function (note) . at reset note: start condition duplication preventing function the mst, trx, and bb bits is set to 1 at the same time after con- firming that the bb flag is 0 in the procedure of a start condition occurrence. however, when a start condition by another master device occurs and the bb flag is set to 1 immediately after the con- tents of the bb flag is confirmed, the start condition duplication preventing function makes the writing to the mst and trx bits in- valid. the duplication preventing function becomes valid from the rising of the bb flag to reception completion of slave address. s c l p i n iicir q b 7 m s t b 0 i 2 c status register (s1 : address 002d 16 ) last receive bit (note) 0 : last bit = 0 1 : last bit = 1 g e n e r a l c a l l d e t e c t i n g f l a g ( n o t e ) 0 :n o g e n e r a l c a l l d e t e c t e d 1 :g e n e r a l c a l l d e t e c t e d s l a v e a d d r e s s c o m p a r i s o n f l a g ( n o t e ) 0 : a d d r e s s d i s a g r e e m e n t 1 : a d d r e s s a g r e e m e n t a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( n o t e ) 0 :n o t d e t e c t e d 1 :d e t e c t e d s c l p i n l o w h o l d b i t 0 : s c l p i n l o w h o l d 1 : s c l p i n l o w r e l e a s e bus busy flag 0 : bus free 1 : bus busy c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s 0 0 :s l a v e r e c e i v e m o d e 0 1 :s l a v e t r a n s m i t m o d e 1 0 :m a s t e r r e c e i v e m o d e 1 1 :m a s t e r t r a n s m i t m o d e t r xb bp i na la a sa d 0l r b n o t e : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n o t b e w r i t t e n . w r i t e 0 t o t h e s e b i t s a t w r i t i n g .
35 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 36 start condition detecting timing diagram start/stop condition detecting operation the start/stop condition detection operations are shown in figures 36, 37, and table 11. the start/stop condition is set by the start/stop condition set bit. the start/stop condition can be detected only when the input signal of the s cl and s da pins satisfy three conditions: s cl re- lease time, setup time, and hold time (see table 11). the bb flag is set to 1 by detecting the start condition and is reset to 0 by detecting the stop condition. the bb flag set/reset timing is different in the standard clock mode and the high-speed clock mode. refer to table 11, the bb flag set/ reset time. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal iicirq occurs to the cpu. start condition generating method when writing 1 to the mst, trx, and bb bits of the i 2 c status register (address 002d 16 ) at the same time after writing the slave address to the i 2 c data shift register (address 002b 16 ) with the condition in which the es0 bit of the i 2 c control register (address 002e 16 ) and the bb flag are 0 , a start condition occurs. after that, the bit counter becomes 000 2 and an s cl for 1 byte is out- put. the start condition generating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 34, the start condition generating timing diagram, and table 9, the start condition generating timing table. stop condition generating method when the es0 bit of the i 2 c control register (address 002e 16 ) is 1, write 1 to the mst and trx bits, and write 0 to the bb bit of the i 2 c status register (address 002d 16 ) simultaneously. then a stop condition occurs. the stop condition generating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 35, the stop condition generating timing diagram, and table 10, the stop condition generating timing table. fig. 34 start condition generating timing diagram fig. 35 stop condition generating timing diagram table 10 stop condition generating timing table item setup time hold time standard clock mode 5.0 s (20 cycles) 4.5 s (18 cycles) note: absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. high-speed clock mode 3.0 s (12 cycles) 2.5 s (10 cycles) table 9 start condition generating timing table item setup time hold time standard clock mode 5.0 s (20 cycles) 5.0 s (20 cycles) note: absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. high-speed clock mode 2.5 s (10 cycles) 2.5 s (10 cycles) table 11 start condition/stop condition detecting conditions note: unit : cycle number of system clock ssc value is the decimal notation value of the start/stop condi- tion set bits ssc4 to ssc0. do not set 0 or an odd number to ssc value. the value in parentheses is an example when the i 2 c start/ stop condition control register is set to 18 16 at = 4 mhz. fig. 37 stop condition detecting timing diagram s cl release time standard clock mode high-speed clock mode 4 cycles (1.0 s) 2 cycles (1.0 s) 2 cycles (0.5 s) 3.5 cycles (0.875 s) ssc value + 1 2 ssc value + 1 2 ssc value 1 2 setup time hold time bb flag set/ reset time ssc value + 1 cycle (6.25 s) cycle < 4.0 s (3.125 s) cycle < 4.0 s (3.125 s) + 2 cycles (3.375 s) i 2 c s t a t u s r e g i s t e r w r i t e s i g n a l h o l d t i m e setup time s c l s d a i 2 c s t a t u s r e g i s t e r w r i t e s i g n a l hold time setup time s c l s da h o l d t i m e setup time s cl s da bb flag s cl release time b b f l a g r e s e t t i m e h o l d t i m e s e t u p t i m e s cl s da bb flag s cl release time b b f l a g r e s e t t i m e
36 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) [i 2 c start/stop condition control register (s2d)] 0030 16 the i 2 c start/stop condition control register (address 0030 16 ) controls start/stop condition detection. bits 0 to 4: start/stop condition set bit (ssc4 ssc0) scl release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(x in ) because these time are measured by the internal system clock. accordingly, set the proper value to the start/stop condition set bits (ssc4 to ssc0) in considered of the system clock frequency. refer to table 11. do not set 00000 2 or an odd number to the start/stop condi- tion set bit (ssc4 to ssc0). refer to table 12, the recommended set value to start/stop condition set bits (ssc4 ssc0) for each oscillation frequency. bit 5: scl/sda interrupt pin polarity selection bit (sip) an interrupt can occur when detecting the falling or rising edge of the scl or sda pin. this bit selects the polarity of the scl or sda pin interrupt pin. bit 6: scl/sda interrupt pin selection bit (sis) this bit selects the pin of which interrupt becomes valid between the scl pin and the sda pin. note: when changing the setting of the s cl /s da interrupt pin polarity se- lection bit, the s cl /s da interrupt pin selection bit, or the i 2 c-bus interface enable bit es0, the s cl /s da interrupt request bit may be set. when selecting the s cl /s da interrupt source, disable the inter- rupt before the s cl /s da interrupt pin polarity selection bit, the s cl / s da interrupt pin selection bit, or the i 2 c-bus interface enable bit es0 is set. reset the request bit to 0 after setting these bits, and enable the interrupt. address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective address communication formats are described below. ? 7-bit addressing format to adapt the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 002e 16 ) to 0. the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c address register (address 002c 16 ). at the time of this comparison, address com- parison of the rwb bit of the i 2 c address register (address 002c 16 ) is not performed. for the data transmission format when the 7-bit addressing format is selected, refer to figure 39, (1) and (2). ? 10-bit addressing format to adapt the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 002e 16 ) to 1. an address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the i 2 c address register (address 002c 16 ). at the time of this comparison, an address comparison between the rwb bit of the i 2 c address register (address 002c 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit addressing mode, the rwb bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is pro- cessed as an address data bit. when the first-byte address data agree with the slave address, the aas bit of the i 2 c status register (address 002d 16 ) is set to 1. after the second-byte address data is stored into the i 2 c data shift register (address 002b 16 ), perform an address com- parison between the second-byte data and the slave address by software. when the address data of the 2 bytes agree with the slave address, set the rwb bit of the i 2 c address register (address 002c 16 ) to 1 by software. this processing can make the 7-bit slave address and r/w data agree, which are re- ceived after a restart condition is detected, with the value of the i 2 c address register (address 002c 16 ). for the data trans- mission format when the 10-bit addressing format is selected, refer to figure 39, (3) and (4).
37 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) start/stop condition control register oscillation frequency f(x in ) (mhz) fig. 39 address data communication format fig. 38 structure of i 2 c start/stop condition control register note: do not set an odd number to the start/stop condition set bit (ssc4 to ssc0). table 12 recommended set value to start/stop condition set bits (ssc4 ssc0) for each oscillation frequency main clock divide ratio system clock (mhz) scl release time ( s) setup time ( s) hold time ( s) 8 8 4 2 2 8 2 2 xxx11010 xxx11000 xxx00100 xxx01100 xxx01010 xxx00100 3.375 s (13.5 cycles) 3.125 s (12.5 cycles) 2.5 s (2.5 cycles) 3.25 s (6.5 cycles) 2.75 s (5.5 cycles) 2.5 s (2.5 cycles) 6.75 s (27 cycles) 6.25 s (25 cycles) 5.0 s (5 cycles) 6.5 s (13 cycles) 5.5 s (11 cycles) 5.0 s (5 cycles) 3.375 s (13.5 cycles) 3.125 s (12.5 cycles) 2.5 s (2.5 cycles) 3.25 s (6.5 cycles) 2.75 s (5.5 cycles) 2.5 s (2.5 cycles) 4 1 2 1 b 7b 0 i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r s t a r t / s t o p c o n d i t i o n s e t b i t s c l / s d a i n t e r r u p t p i n p o l a r i t y s e l e c t i o n b i t 0 :f a l l i n g e d g e a c t i v e 1 :r i s i n g e d g e a c t i v e s c l / s d a i n t e r r u p t p i n s e l e c t i o n b i t 0 :s d a v a l i d 1 :s c l v a l i d r e s e r v e d d o n o t w r i t e 1 t o t h i s b i t . s i s s i p s s c 4s s c 3s s c 2s s c 1s s c 0 ( s 2 d : a d d r e s s 0 0 3 0 1 6 ) s s l a v e a d d r e s sr / w a d a t a a/a p a d a t a 7 b i t s 0 1 t o 8 b i t s 1 to 8 bits ( 1 ) a m a s t e r - t r a n s m i t t e r t r a n s n m i t s d a t a t o a s l a v e - r e c e i v e r s s l a v e a d d r e s sr / w a d a t a a p a d a t a 7 b i t s 1 1 t o 8 b i t s1 t o 8 b i t s ( 2 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r 7 b i t s 0 8 b i t s ( 3 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r w i t h a 1 0 - b i t a d d r e s s 1 t o 8 b i t s1 t o 8 b i t s s r / w a s l a v e a d d r e s s 1 s t 7 b i t s s l a v e a d d r e s s 2 n d b y t e s a ad a t a data p a / a 7 b i t s 0 8 b i t s ( 4 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r w i t h a 1 0 - b i t a d d r e s s s : s t a r t c o n d i t i o n a : a c k b i t s r : r e s t a r t c o n d i t i o n p : s t o p c o n d i t i o n r / w : r e a d / w r i t e b i t 7 b i t s 1 1 t o 8 b i t s1 t o 8 b i t s s r / w a s l a v e a d d r e s s 1 s t 7 b i t s s l a v e a d d r e s s 2 n d b y t e s a s r slave address 1st 7 bits r / w a d a t a d a t a p a : master to slave : slave to master a
38 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. ? set a slave address in the high-order 7 bits of the i 2 c address register (address 002c 16 ) and 0 into the rwb bit. ? set the ack return mode and scl = 100 khz by setting 85 16 in the i 2 c clock control register (address 002f 16 ). ? set 00 16 in the i 2 c status register (address 002d 16 ) so that transmission/reception mode can become initializing condition. ? set a communication enable status by setting 08 16 in the i 2 c control register (address 002e 16 ). ? confirm the bus free condition by the bb flag of the i 2 c status register (address 002d 16 ). ? set the address data of the destination of transmission in the high-order 7 bits of the i 2 c data shift register (address 002b 16 ) and set 0 in the least significant bit. ? set f0 16 in the i 2 c status register (address 002d 16 ) to gener- ate a start condition. at this time, an scl for 1 byte and an ack clock automatically occur. ? set transmit data in the i 2 c data shift register (address 002b 16 ). at this time, an scl and an ack clock automatically occur. ? when transmitting control data of more than 1 byte, repeat step ? . ? set d0 16 in the i 2 c status register (address 002d 16 ) to gener- ate a stop condition if ack is not returned from slave reception side or transmission ends. example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode and using the addressing format is shown below. ? set a slave address in the high-order 7 bits of the i 2 c address register (address 002c 16 ) and 0 in the rwb bit. ? set the no ack clock mode and scl = 400 khz by setting 25 16 in the i 2 c clock control register (address 002f 16 ). ? set 00 16 in the i 2 c status register (address 002d 16 ) so that transmission/reception mode can become initializing condition. ? set a communication enable status by setting 08 16 in the i 2 c control register (address 002e 16 ). ? when a start condition is received, an address comparison is performed. ? when all transmitted addresses are 0 (general call): ad0 of the i 2 c status register (address 002d 16 ) is set to 1 and an interrupt request signal occurs. when the transmitted addresses agree with the address set in ? : aas of the i 2 c status register (address 002d 16 ) is set to 1 and an interrupt request signal occurs. in the cases other than the above ad0 and aas of the i 2 c sta- tus register (address 002d 16 ) are set to 0 and no interrupt request signal occurs. ? set dummy data in the i 2 c data shift register (address 002b 16 ). ? when receiving control data of more than 1 byte, repeat step ? . ? when a stop condition is detected, the communication ends.
39 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) precautions when using multi-master i 2 c- bus interface (1) read-modify-write instruction the precautions when the read-modify-write instruction such as seb, clb etc. is executed for each register of the multi-master i 2 c-bus interface are described below. i 2 c data shift register (s0: address 002b 16 ) when executing the read-modify-write instruction for this regis- ter during transfer, data may become a value not intended. i 2 c address register (s0d: address 002c 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the stop condition, data may become a value not intended. it is because h/w changes the read/write bit (rwb) at the above timing. i 2 c status register (s1: address 002d 16 ) do not execute the read-modify-write instruction for this register because all bits of this register are changed by h/w. i 2 c control register (s1d: address 002e 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the start condition or at completing the byte transfer, data may become a value not intended. because h/w changes the bit counter (bc0-bc2) at the above timing. i 2 c clock control register (s2: address 002f 16 ) the read-modify-write instruction can be executed for this regis- ter. i 2 c start/stop condition control register (s2d: address 0030 16 ) the read-modify-write instruction can be executed for this regis- ter. (2) start condition generating procedure using multi-master 1. procedure example (the necessary conditions of the generat- ing procedure are described in items 2 to 5 below. lda (taking out of slave address value) sei (interrupt disabled) bbs 5, s1, busbusy (bb flag confirming and branch process) busfree: sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of start condition generating) cli (interrupt enabled) busbusy: cli (interrupt enabled) 2. use branch on bit set of bbs 5, $002d, for the bb flag confirming and branch process. 3. use sta $2b, stx $2b or sty $2b of the zero page ad- dressing instruction for writing the slave address value to the i 2 c data shift register. 4. execute the branch instruction of item 2 and the store instruc- tion of item 3 continuously, as shown in the procedure example above. 5. disable interrupts during the following three process steps: bb flag confirming writing of slave address value trigger of start condition generating when the condition of the bb flag is bus busy, enable interrupts immediately. (3) restart condition generating procedure 1. procedure example (the necessary conditions for the proce- dure are described in items 2 to 4 below.) execute the following procedure when the pin bit is 0. ldm #$00, s1 (select slave receive mode) lda (take out of slave address value) sei (disable interrupt) sta s0 (write slave address value) ldm #$f0, s1 ( trigger restart condition generation ) cli (enable interrupt) 2. select the slave receive mode when the pin bit is 0. do not write 1 to the pin bit. neither 0 nor 1 is specified as input to the bb bit. the trx bit becomes 0 and the s da pin is released. 3. the s cl pin is released by writing the slave address value to the i 2 c data shift register. 4. disable interrupts during the following two process steps: write slave address value trigger restart condition generation (4) writing to i 2 c status register do not execute an instruction to set the pin bit to 1 from 0 and an instruction to set the mst and trx bits to 0 from 1 simulta- neously. because it may enter the state that the s cl pin is released and the s da pin is released after about one machine cycle. do not execute an instruction to set the mst and trx bits to 0 from 1 simultaneously when the pin bit is 1. because it may become the same as above. (5) process of after stop condition generating do not write data in the i 2 c data shift register s0 and the i 2 c sta- tus register s1 until the bus busy flag bb becomes 0 after generating the stop condition in the master mode. because the stop condition waveform might not be normally generated. reading to the above registers do not have the problem.
40 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) pulse width modulation (pwm) the 7516 group (spec. h) has a pwm function with an 8-bit reso- lution, based on a signal that is the clock input x in or that clock input divided by 2. data setting the pwm output pin also functions as port p4 4 . set the pwm period by the pwm prescaler, and set the h term of output pulse by the pwm register. if the value in the pwm prescaler is n and the value in the pwm register is m (where n = 0 to 255 and m = 0 to 255) : pwm period = 255 ? (n+1) / f(x in ) = 31.875 ? (n+1) s (when f(x in ) = 8 mhz,count source selection bit = 0 ) output pulse h term = pwm period ? m / 255 = 0.125 ? (n+1) ? m s (when f(x in ) = 8 mhz,count source selection bit = 0 ) fig. 40 timing of pwm period fig. 41 block diagram of pwm function pwm operation when bit 0 (pwm enable bit) of the pwm control register is set to 1 , operation starts by initializing the pwm output circuit, and pulses are output starting at an h . if the pwm register or pwm prescaler is updated during pwm output, the pulses will change in the cycle after the one in which the change was made. 31.875 ? m ? (n+1) 255 s t = [ 3 1 . 8 7 5 ? ( n + 1 ) ] s pwm output m: contents of pwm register n : contents of pwm prescaler t : pwm period (when f(x in ) = 8 mhz, count source selection bit = 0 ) d a t a b u s count source selection bit 0 1 p w m p r e s c a l e r p r e - l a t c h p w m r e g i s t e r p r e - l a t c h pwm prescaler latch pwm register latch transfer control circuit p w m r e g i s t e r 1 / 2 x in p o r t p 4 4 l a t c h p w m e n a b l e b i t port p4 4 p w m p r e s c a l e r ( x c i n a t l o w - s p e e d m o d e )
41 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 42 structure of pwm control register fig. 43 pwm output timing when pwm register or pwm prescaler is changed note the pwm starts after the pwm function enable bit is set to enable and l level is output from the pwm pin. the length of this l level output is as follows: sec (count source selection bit = 0, where n is the value set in the prescaler) sec (count source selection bit = 1, where n is the value set in the prescaler) n+1 2 f(x in ) n+1 f(x in ) p w m c o n t r o l r e g i s t e r ( p w m c o n : a d d r e s s 0 0 1 d 1 6 ) p w m f u n c t i o n e n a b l e b i t c o u n t s o u r c e s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) b 7 b 0 0 : p w m d i s a b l e d 1 : p w m e n a b l e d 0 : f ( x i n ) ( f ( x c i n ) a t l o w - s p e e d m o d e ) 1 : f ( x i n ) / 2 ( f ( x c i n ) / 2 a t l o w - s p e e d m o d e ) abc b t c t 2 = p w m o u t p u t p w m r e g i s t e r w r i t e s i g n a l p w m p r e s c a l e r w r i t e s i g n a l (changes h term from a to b .) (changes pwm period from t to t2 .) when the contents of the pwm register or pwm prescaler have changed, the pwm output will change from the next period after the change. t t t2
42 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) a-d converter [a-d conversion registers (adl, adh)] 0035 16 , 0036 16 the a-d conversion registers are read-only registers that store the result of an a-d conversion. do not read these registers during an a-d conversion. [ad control register (adcon)] 0034 16 the ad control register controls the a-d conversion process. bits 0 to 2 select a specific analog input pin. bit 4 indicates the completion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion and changes to 1 when an a-d conversion ends. writing 0 to this bit starts the a-d conversion. comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref into 1024 and outputs the divided voltages. channel selector the channel selector selects one of ports p3 0 /an 0 to p3 5 /an 5 and inputs the voltage to the comparator. comparator and control circuit the comparator and control circuit compare an analog input volt- age with the comparison voltage, and the result is stored in the a-d conversion registers. when an a-d conversion is completed, the control circuit sets the a-d conversion completion bit and the a-d interrupt request bit to 1 . note that because the comparator consists of a capacitor cou- pling, set f(x in ) to 500 khz or more during an a-d conversion. when the a-d converter is operated at low-speed mode, f(x in ) and f(x cin ) do not have the lower limit of frequency, because of the a-d converter has a built-in self-oscillation circuit. fig. 44 structure of ad control register fig. 45 structure of a-d conversion registers fig. 46 block diagram of a-d converter ad control register (adcon : address 0034 16 ) analog input pin selection bits b2 b1 b0 0 0 0: p3 0 /an 0 0 0 1: p3 1 /an 1 0 1 0: p3 2 /an 2 0 1 1: p3 3 /an 3 1 0 0: p3 4 /an 4 1 0 1: p3 5 /an 5 1 1 0: setting disabled 1 1 1: setting disabled not used (returns 0 when read) a-d conversion completion bit 0: conversion in progress 1: conversion completed not used (returns 0 when read) b7 b0 10-bit reading (read address 0036 16 before 0035 16 ) (address 0036 16 ) (address 0035 16 ) 8-bit reading (read only address 0035 16 ) (address 0035 16 ) b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b0 b9 b7 b0 note : the high-order 6 bits of address 0036 16 become 0 at reading. b9 b8 b7 b6 b5 b4 b3 b2 b7 b0 channel selector a-d control circuit a-d conversion low-order register resistor ladder v ref av ss comparator a-d interrupt request b7 b0 3 10 p3 0 /an 0 p3 1 /an 1 p3 2 /an 2 p3 3 /an 3 p3 4 /an 4 data bus ad control register a-d conversion high-order register (address 0034 16 ) (address 0036 16 ) (address 0035 16 ) p3 5 /an 5
43 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. standard operation of watchdog timer when any data is not written into the watchdog timer control reg- ister (address 0039 16 ) after reset, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 0039 16 ) and an internal reset occurs at an underflow of the watch- dog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 16 ) may be started before an underflow. when the watchdog timer control reg- ister (address 0039 16 ) is read, the values of the high-order 6 bits of the watchdog timer h, stp instruction disable bit, and watch- dog timer h count source selection bit are read. initial value of watchdog timer at reset or writing to the watchdog timer control register (address 0039 16 ), each watchdog timer h and l are set to ff 16 . fig. 48 structure of watchdog timer control register watchdog timer h count source selection bit operation bit 7 of the watchdog timer control register (address 0039 16 ) per- mits selecting a watchdog timer h count source. when this bit is set to 0 , the count source becomes the underflow signal of watchdog timer l. the detection time is set to 131.072 ms at f(x in ) = 8 mhz frequency and 32.768 s at f(x cin ) = 32 khz frequency. when this bit is set to 1 , the count source becomes the signal divided by 16 for f(x in ) (or f(x cin )). the detection time in this case is set to 512 s at f(x in ) = 8 mhz frequency and 128 ms at f(x cin ) = 32 khz frequency. this bit is cleared to 0 after reset. operation of stp instruction disable bit bit 6 of the watchdog timer control register (address 0039 16 ) per- mits disabling the stp instruction when the watchdog timer is in operation. when this bit is 0 , the stp instruction is enabled. when this bit is 1 , the stp instruction is disabled, once the stp instruction is executed, an internal reset occurs. when this bit is set to 1 , it cannot be rewritten to 0 by program. this bit is cleared to 0 after reset. fig. 47 block diagram of watchdog timer x in data bus x cin 1 0 0 0 0 1 main clock division ratio selection bits (note) 0 1 1 / 1 6 watchdog timer h count source selection bit r e s e t c i r c u i t stp instruction disable bit w a t c h d o g t i m e r h ( 8 ) f f 1 6 i s s e t w h e n w a t c h d o g t i m e r c o n t r o l r e g i s t e r i s w r i t t e n t o . i n t e r n a l r e s e t r e s e t w a t c h d o g t i m e r l ( 8 ) n o t e : a n y o n e o f h i g h - s p e e d , m i d d l e - s p e e d o r l o w - s p e e d m o d e i s s e l e c t e d b y b i t s 7 a n d 6 o f t h e c p u m o d e r e g i s t e r . stp instruction ff 16 is set when watchdog timer control register is written to. b 0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/16 or f(x cin )/16 w a t c h d o g t i m e r h ( f o r r e a d - o u t o f h i g h - o r d e r 6 b i t ) watchdog timer control register (wdtcon : address 0039 16 ) b 7
44 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec.h) reset circuit to reset the microcomputer, reset pin must be held at an l level for 20 cycles or more of x in . then the reset pin is returned to an h level (the power source voltage must be between 2.7 v and 5.5 v, and the oscillation must be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.54 v for v cc of 2.7 v. fig. 50 reset sequence fig. 49 reset circuit example (note) 0 . 2 v c c 0v 0v p o w e r o n v c c r e s e t v c c r e s e t p o w e r s o u r c e v o l t a g e d e t e c t i o n c i r c u i t p o w e r s o u r c e v o l t a g e r e s e t i n p u t v o l t a g e n o t e : r e s e t r e l e a s e v o l t a g e ; v c c = 2 . 7 v r e s e t d a t a a d d r e s s s y n c x i n : 8 t o 1 3 c l o c k c y c l e s x i n ? ? ? ? ? f f f cf f f d a d h , l ? ? ? ? ? ad l a d h 1: the frequency relation of f(x in ) and f( ) is f(x in ) = 8 f( ). 2: the question marks (?) indicate an undefined state that depends on the previous state. 3: all signals except x in and reset are internals. r e s e t a d d r e s s f r o m t h e v e c t o r t a b l e . n o t e s r e s e t o u t
45 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec.h) fig. 51 internal status at reset 000 x 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 f f 1 6 0 1 1 6 0 0 1 6 0 0 1 6 f f 1 6 f f 1 6 f f 1 6 f f 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 a - d c o n t r o l r e g i s t e r ( a d c o n ) a - d c o n v e r s i o n l o w - o r d e r r e g i s t e r ( a d l ) a - d c o n v e r s i o n h i g h - o r d e r r e g i s t e r ( a d h ) m i s r g w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n ) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) c p u m o d e r e g i s t e r ( c p u m ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) p r o c e s s o r s t a t u s r e g i s t e r p r o g r a m c o u n t e r n o t e : x : n o t f i x e d s i n c e t h e i n i t i a l v a l u e s f o r o t h e r t h a n a b o v e m e n t i o n e d r e g i s t e r s a n d r a m c o n t e n t s a r e i n d e f i n i t e a t r e s e t , t h e y m u s t b e s e t . ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 1 0 ) ( 1 1 ) ( 1 2 ) ( 1 3 ) ( 1 4 ) ( 1 5 ) ( 1 6 ) ( 1 7 ) ( 1 8 ) ( 1 9 ) ( 2 0 ) ( 2 1 ) ( 2 2 ) ( 2 3 ) ( 2 4 ) ( 2 5 ) ( 2 6 ) ( 2 7 ) ( 2 8 ) ( 2 9 ) ( 3 0 ) ( 3 1 ) ( 3 2 ) ( 3 3 ) ( 3 4 ) ( 3 5 ) ( 3 6 ) a d d r e s sr e g i s t e r c o n t e n t s p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 ( s i o 2 c o n 1 ) s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 ( s i o 2 c o n 2 ) s e r i a l i / o 2 r e g i s t e r ( s i o 2 ) t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r ( t b / r b ) s e r i a l i / o 1 s t a t u s r e g i s t e r ( s i o s t s ) s e r i a l i / o 1 c o n t r o l r e g i s t e r ( s i o c o n ) u a r t c o n t r o l r e g i s t e r ( u a r t c o n ) b a u d r a t e g e n e r a t o r ( b r g ) p w m c o n t r o l r e g i s t e r ( p w m c o n ) p w m p r e s c a l e r ( p r e p w m ) p w m r e g i s t e r ( p w m ) p r e s c a l e r 1 2 ( p r e 1 2 ) t i m e r 1 ( t 1 ) t i m e r 2 ( t 2 ) t i m e r x y m o d e r e g i s t e r ( t m ) p r e s c a l e r x ( p r e x ) t i m e r x ( t x ) p r e s c a l e r y ( p r e y ) t i m e r y ( t y ) t i m e r c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( t c s s ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c a d d r e s s r e g i t e r ( s 0 d ) i 2 c s t a t u s r e g i s t e r ( s 1 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i 2 c s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r ( s 2 d ) 00000111 10000000 x x x x x x x x 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 b 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 e 1 6 0 0 2 f 1 6 0 0 3 0 1 6 11100000 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) (48) (49) register contents 0 0 3 4 1 6 0 0 3 5 1 6 0 0 3 6 1 6 0 0 3 8 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 ( p s ) ( p c h ) ( p c l ) a d d r e s s 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 xx x x x1 x x f f f d 1 6 c o n t e n t s f f f c 1 6 c o n t e n t s 00111111 01001000 00010000 x x x x x x x x x x 000000 000 0 100 x x x xx x x x xx x x x
46 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec.h) clock generating circuit the 7516 group (spec h) has two built-in oscillation circuits: main clock x in -x out oscillation circuit and sub clock x cin -x cout oscil- lation circuit. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the cir- cuit constants in accordance with the resonator manufacturer s recommended values. no external resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal clock is the frequency of x in divided by 8. after re- set is released, this mode is selected. (2) high-speed mode the internal clock is half the frequency of x in . (3) low-speed mode the internal clock is half the frequency of x cin . note if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub-clock to stabilize, especially immediately af- ter power on and at returning from the stop mode. when switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(x in ) > 3 f(x cin ). (4) low power dissipation mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to 1. when the main clock x in is restarted (by setting the main clock stop bit to 0 ), set sufficient time for oscillation to stabilize. the sub-clock x cin -x cout oscillation circuit can not directly input clocks that are generated externally. accordingly, make sure to cause an external resonator to oscillate. oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at an h level, and x in and x cin oscillation stops. when the oscillation stabilizing time set after stp instruction released bit is 0, the prescaler 12 is set to ff 16 and timer 1 is set to 01 16 . when the oscillation stabilizing time set after stp instruction released bit is 1, set the sufficient time for oscillation of used oscillator to stabi- lize since nothing is set to the prescaler 12 and timer 1. either x in or x cin divided by 16 is input to the prescaler 12 as count source. oscillator restarts when an external interrupt is re- ceived, but the internal clock is not supplied to the cpu (remains at h ) until timer 1 underflows. the internal clock is supplied for the first time, when timer 1 underflows. this ensures time for the clock oscillation using the ceramic resonators to be stabilized. when the oscillator is restarted by reset, apply l level to the fig. 52 ceramic resonator circuit fig. 53 external clock input circuit reset pin until the oscillation is stable since a wait time will not be generated. (2) wait mode if the wit instruction is executed, the internal clock stops at an h level, but the oscillator does not stop. the internal clock re- starts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. to ensure that the interrupts will be received to release the stp or wit state, their interrupt enable bits must be set to 1 before ex- ecuting of the stp or wit instruction. when releasing the stp state, the prescaler 12 and timer 1 will start counting the clock x in divided by 16. accordingly, set the timer 1 interrupt enable bit to 0 before executing the stp instruc- tion. note when using the oscillation stabilizing time set after stp instruction released bit set to 1 , evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. x c i n x c o u t x i n x o u t c i n c o u t c c i n c c o u t r f r d x c i n x c o u t x i n x o u t c c i n c c o u t r f r d o p e n e x t e r n a l o s c i l l a t i o n c i r c u i t v c c v s s
47 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec.h) fig. 54 structure of misrg notes on middle-speed mode automatic switch set bit when the middle-speed mode automatic switch set bit is set to 1 while operating in the low-speed mode, by detecting the rising/fall- ing edge of the scl or sda pin, x in oscillation automatically starts and the mode is automatically switched to the middle-speed mode. the timing which changes from the low-speed mode to the middle-speed mode can be set as 4.5 to 5.5 cycle, or 6.5 to 7.5 cycle in the low-speed mode by the middle-speed mode automatic switch waiting time set bit. select according to the oscillation start characteristic of the x in oscillator to be used. fig. 55 system clock generating circuit block diagram (single-chip mode) misrg (misrg : address 0038 16 ) o s c i l l a t i o n s t a b i l i z i n g t i m e s e t a f t e r s t p i n s t r u c t i o n r e l e a s e d b i t 0 : a u t o m a t i c a l l y s e t 0 1 1 6 t o t i m e r 1 , f f 1 6 t o p r e s c a l e r 1 2 1 : a u t o m a t i c a l l y s e t n o t h i n g b 7 b 0 notes 1: while operating in the low-speed mode, the mode can be automatically switched to the middle-speed mode by the scl/sda interrupt. 2: when the mode is automatically switched from the low-speed mode to the middle-speed mode, the value of cpu mode register (address 003b 16 ) changes. n o t u s e d ( r e t u r n 0 w h e n r e a d ) m i d d l e - s p e e d m o d e a u t o m a t i c s w i t c h s t a r t b i t ( d e p e n d i n g o n p r o g r a m ) 0 : i n v a l i d 1 : a u t o m a t i c s w i t c h s t a r t (note 2) middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles m i d d l e - s p e e d m o d e a u t o m a t i c s w i t c h s e t b i t 0 : n o t s e t a u t o m a t i c a l l y 1 : a u t o m a t i c s w i t c h i n g e n a b l e (notes 1, 2) w i t i n s t r u c t i o n stp instruction t i m i n g ( i n t e r n a l c l o c k ) s r q s t p i n s t r u c t i o n s r q m a i n c l o c k s t o p b i t s r q 1 / 2 1/4 x in x out x c o u t x c i n i n t e r r u p t r e q u e s t r e s e t i n t e r r u p t d i s a b l e f l a g l 1 / 2 p o r t x c s w i t c h b i t 1 0 low-speed mode h i g h - s p e e d o r m i d d l e - s p e e d m o d e middle-speed mode high-speed or low-speed mode m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s ( n o t e 1 ) n o t e s 1 : a n y o n e o f h i g h - s p e e d , m i d d l e - s p e e d o r l o w - s p e e d m o d e i s s e l e c t e d b y b i t s 7 a n d 6 o f t h e c p u m o d e r e g i s t e r . w h e n l o w - s p e e d m o d e i s s e l e c t e d , s e t p o r t x c s w i t c h b i t ( b 4 ) t o 1 . 2 : w h e n b i t 0 o f m i s r g = 0 m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s ( n o t e 1 ) ff 16 01 16 p r e s c a l e r 1 2 timer 1 reset or stp instruction (note 2) r e s e t timer 12 count source selection bit
48 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec.h) fig. 56 state transitions of system clock c m 4 : p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n ( s t o p o s c i l l a t i n g ) 1 : x c i n - x c o u t o s c i l l a t i n g f u n c t i o n c m 5 : m a i n c l o c k ( x i n - x o u t ) s t o p b i t 0 : o p e r a t i n g 1 : s t o p p e d c m 7 , c m 6 : m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b 7 b 6 0 0 : = f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) 0 1 : = f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) 1 0 : = f ( x c i n ) / 2 ( l o w - s p e e d m o d e ) 1 1 : n o t a v a i l a b l e n o t e s r e s e t c m 4 1 0 c m 4 0 1 c m 6 1 0 c m 4 1 0 c m 6 1 0 c m 7 1 0 c m 4 1 0 c m 5 1 0 cm 6 1 0 cm 6 1 0 cpu mode register b7 b 4 c m 7 0 1 c m 6 1 0 ( c p u m : a d d r e s s 0 0 3 b 1 6 ) c m 7 = 0 c m 6 = 1 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) m i d d l e - s p e e d m o d e ( f ( ) = 1 m h z ) c m 7 = 0 c m 6 = 1 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) m i d d l e - s p e e d m o d e ( f ( ) = 1 m h z ) c m 7 = 0 c m 6 = 0 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) high-speed mode (f( ) = 4 mhz) c m 7 = 1 c m 6 = 0 c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) low-speed mode (f( )=16 khz) cm 7 = 1 cm 6 = 0 cm 5 = 1 (8 mhz stopped) cm 4 = 1 (32 khz oscillating) l o w - s p e e d m o d e ( f ( ) = 1 6 k h z ) cm 7 = 0 cm 6 = 0 cm 5 = 0 (8 mhz oscillating) cm 4 = 1 (32 khz oscillating) high-speed mode (f( ) = 4 mhz) 1 : s w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( d o n o t s w i t c h b e t w e e n t h e m o d e s d i r e c t l y w i t h o u t a n a l l o w . ) 2 : t h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d . 3 : t i m e r o p e r a t e s i n t h e w a i t m o d e . 4 : w h e n b i t 0 o f m i s r g i s 0 a n d t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 1 m s o c c u r s b y c o n n e c t i n g t i m e r 1 i n m i d d l e / h i g h - s p e e d m o d e . 5 : w h e n b i t 0 o f m i s r g i s 0 a n d t h e s t o p m o d e i s e n d e d , t h e f o l l o w i n g i s p e r f o r m e d . ( 1 ) a f t e r t h e c l o c k i s r e s t a r t e d , a d e l a y o f a p p r o x i m a t e l y 2 5 0 m s o c c u r s i n l o w - s p e e d m o d e i f t i m e r 1 2 c o u n t s o u r c e s e l e c t i o n b i t i s 0 . ( 2 ) a f t e r t h e c l o c k i s r e s t a r t e d , a d e l a y o f a p p r o x i m a t e l y 1 6 m s o c c u r s i n l o w - s p e e d m o d e i f t i m e r 1 2 c o u n t s o u r c e s e l e c t i o n b i t i s 1 . 6 : w a i t u n t i l o s c i l l a t i o n s t a b i l i z e s a f t e r o s c i l l a t i n g t h e m a i n c l o c k x i n b e f o r e t h e s w i t c h i n g f r o m t h e l o w - s p e e d m o d e t o m i d d l e / h i g h - s p e e d m o d e . 7 : t h e e x a m p l e a s s u m e s t h a t 8 m h z i s b e i n g a p p l i e d t o t h e x i n p i n a n d 3 2 k h z t o t h e x c i n p i n . i n d i c a t e s t h e i n t e r n a l c l o c k .
49 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before perform- ing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1 , then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: the data transfer instruction (lda, etc.) the operation instruction when the index x mode flag (t) is 1 the addressing mode which uses the value of a direction regis- ter as an index the bit-test instruction (bbc or bbs, etc.) to a direction register the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in serial i/o1 (clock synchronous mode), if the receive side is us- ing an external clock and it is to output the s rdy1 signal, set the transmit enable bit, the receive enable bit, and the s rdy1 output enable bit to 1. serial i/o1 continues to output the final bit from the t x d pin after transmission is completed. s out2 pin for serial i/o2 goes to high impedance after transmis- sion is completed. when an external clock is used as synchronous clock in serial i/o1 or serial i/o2, write transmission data to the transmit buffer register or serial i/o2 register while the transfer clock is h. a-d converter the comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) in the middle/high-speed mode is at least on 500 khz during an a-d conversion. do not execute the stp instruction or the wit instruction during an a-d conversion. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock is half of the x in frequency in high-speed mode. notes on usage handling of source pins in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (v cc pin) and gnd pin (v ss pin) and between power source pin (v cc pin) and analog power source input pin (av ss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 f 0.1 f is recom- mended. eprom version/one time prom version the cnvss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnvss pin and vss pin or vcc pin with 1 to 10 k ? resistance. the mask rom version track of cnvss pin has no operational in- terference even if it is connected to vss pin or vcc pin via a resistor. electric characteristic differences between mask rom and one time prom version mcus there are differences in electric characteristics, operation margin, noise immunity, and noise radiation between mask rom and one time prom version mcus due to the differences in the manufac- turing processes. when manufacturing an application system with one time prom version and then switching to use of the mask rom version, per- form sufficient evaluations for the commercial samples of the mask rom version.
50 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1. mask rom order confirmation form ? 2. mark specification form ? 3. data to be written to rom, in eprom form (three identical cop- ies) or one floppy disk. data required for one time prom programming orders the following are necessary when ordering a prom programming service: 1. rom programming confirmation form ? 2. mark specification form ? (only special mark with customers trade mark logo) 3. data to be programmed to prom, in eprom form (three iden- tical copies) or one floppy disk. ? for the mask rom confirmation and the mark specifications, re- fer to the ?itsubishi mcu technical information?homepage (http://www.infomicom.maec.co.jp/indexe.htm). rom programming method the built-in prom of the blank one time prom version and buit- in eprom version can be read or programmed with a general-purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. table 13 programming adapter package 44pjx-a name of programming adapter pca7446 the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 57 is recommended to verify programming. fig. 57 programming and testing of one time prom version programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer f u n c t i o n a l c h e c k i n t a r g e t d e v i c e the screening temperature is far highe r than the storage temperature. neve r expose to 150 c exceeding 100 hours. caution :
51 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) v cc v ss v ref av ss v ia v ih v ih v ih v ih v ih v ih v il v il v il v il v il electrical characteristics table 14 absolute maximum ratings power source voltage input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 , p2 1, p2 4 ?2 7 , p3 0 ?3 5 , p4 0 ?4 5 , v ref input voltage p2 2 , p2 3 input voltage reset, x in input voltage output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 , p2 1, p2 4 ?2 7 , p3 0 ?3 5 , p4 0 ?4 5 , x out output voltage p2 2 , p2 3 power dissipation operating temperature storage temperature v cc v i v i v i v i v o v o p d t opr t stg symbol parameter conditions ratings ?.3 to 6.5 ?.3 to v cc +0.3 ?.3 to 5.8 ?.3 to v cc +0.3 ?.3 to v cc +0.3 ?.3 to 13 ?.3 to v cc +0.3 ?.3 to 5.8 300 ?0 to 85 ?0 to 125 v v v v v v v mw ? ? unit t a = 25 ? all voltages are based on v ss . output transistors are cut off. 5.5 5.5 v cc v cc v cc 5.8 v cc 5.8 v cc v cc 0.2v cc 0.3v cc 0.6 0.2v cc 0.16v cc power source voltage (at 8 mhz) power source voltage (at 4 mhz) power source voltage a-d convert reference voltage analog power source voltage analog input voltage an 0 ?n 5 ??input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 5 , p4 0 ?4 5 ??input voltage (when i 2 c-bus input level is selected) sda 1 , scl 1 ??input voltage (when i 2 c-bus input level is selected) sda 2 , scl 2 ??input voltage (when smbus input level is selected) sda 1 , scl 1 ??input voltage (when smbus input level is selected) sda 2 , scl 2 ??input voltage reset, x in , cnv ss ??input voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 5 , p4 0 ?4 5 ??input voltage (when i 2 c-bus input level is selected) sda 1 , sda 2 , scl 1 , scl 2 ??input voltage (when smbus input level is selected) sda 1 , sda 2 , scl 1 , scl 2 ??input voltage reset, cnv ss ??input voltage x in symbol parameter limits min. v v v v v v v v v v v v v v v v unit table 15 recommended operating conditions (1) (v cc = 2.7 to 5.5 v, t a = ?0 to 85 ?, unless otherwise noted) 4.0 2.7 2.0 av ss 0.8v cc 0.7v cc 0.7v cc 1.4 1.4 0.8v cc 0 0 0 0 0 5.0 5.0 0 0 typ. max. ?0 ?0 80 120 80 ?0 ?0 40 60 40 ??total peak output current p0 0 ?0 7 , p1 0 ?1 7 , p3 0 ?3 5 (note) ??total peak output current p2 0 , p2 1 , p2 4 ?2 7 , p4 0 ?4 5 (note) ??total peak output current p0 0 ?0 7 , p3 0 ?3 5 (note) ??total peak output current p1 0 ?1 7 (note) ??total peak output current p2 0 ?2 7 ,p4 0 ?4 5 (note) ??total average output current p0 0 ?0 7 , p1 0 ?1 7 , p3 0 ?3 5 (note) ??total average output current p2 0 , p2 1 , p2 4 ?2 7 , p4 0 ?4 5 (note) ??total average output current p0 0 ?0 7 , p3 0 ?3 5 (note) ??total average output current p1 0 ?1 7 (note) ??total average output current p2 0 ?2 7 ,p4 0 ?4 5 (note) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) ma ma ma ma ma ma ma ma ma ma note : the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. m37516m4h, m37516m6h m37516e6h
52 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) table 16 recommended operating conditions (2) (v cc = 2.7 to 5.5 v, t a = 20 to 85 c, unless otherwise noted) 10 h peak output current p0 0 p0 7 , p1 0 p1 7 , p2 0 , p2 1 , p2 4 p2 7 , p3 0 p3 5 , p4 0 p4 5 (note 1) l peak output current p0 0 p0 7 , p2 0 p2 7 , p3 0 p3 5 , p4 0 p4 5 (note 1) l peak output current p1 0 p1 7 (note 1) h average output current p0 0 p0 7 , p1 0 p1 7 , p2 0 , p2 1 , p2 4 p2 7 , p3 0 p3 5 , p4 0 p4 5 (note 2) l average output current p0 0 p0 7 , p2 0 p2 7 , p3 0 p3 5 , p4 0 p4 5 (note 2) l peak output current p1 0 p1 7 (note 2) internal clock oscillation frequency (v cc = 4.0 to 5.5v) (note 3) internal clock oscillation frequency (v cc = 2.7 to 5.5v) (note 3) i oh(peak) symbol parameter limits min. ma unit typ. max. notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) are average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50%. i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) f(x in ) 10 20 5 5 8 4 15 ma ma ma ma ma mhz mhz
53 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) table 17 electrical characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted) h output voltage p0 0 p0 7 , p1 0 p1 7 , p2 0 , p2 1, p2 4 p2 7 , p3 0 p3 5 , p4 0 p4 5 (note) l output voltage p0 0 p0 7 , p2 0 p2 7 , p3 0 p3 5 , p4 0 p4 5 l output voltage p1 0 p1 7 hysteresis cntr 0 , cntr 1 , int 0 int 3 hysteresis rxd, s clk hysteresis reset h input current p0 0 p0 7 , p1 0 p1 7 , p2 0 , p2 1, p2 4 p2 7 , p3 0 p3 5 , p4 0 p4 5 h input current reset, cnv ss h input current x in l input current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 p3 0 p3 5 , p4 0 p4 5 l input current reset,cnv ss l input current x in ram hold voltage limits v v v v v v parameter min. typ. max. symbol unit note: p2 5 is measured when the p2 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . i oh = 10 ma v cc = 4.0 5.5 v i oh = 1.0 ma v cc = 2.7 5.5 v i ol = 10 ma v cc = 4.0 5.5 v i ol = 1.0 ma v cc = 2.7 5.5 v i ol = 20 ma v cc = 4.0 5.5 v i ol = 10 ma v cc = 2.7 5.5 v v i = v cc v i = v cc v i = v cc v i = v ss v i = v ss v i = v ss when clock stopped v cc 2.0 v cc 1.0 test conditions 0.4 0.5 0.5 2.0 1.0 2.0 1.0 v oh v ol v ol v t+ v t v t+ v t v t+ v t i ih i ih i ih i il i il i il v ram 2.0 4 4 5.0 5.0 5.0 5.0 5.5 v v v a a a a a a v
54 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) table 18 electrical characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted) power source current limits parameter min. typ. max. symbol unit high-speed mode f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off high-speed mode f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off low-speed mode (v cc = 3 v) f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off low-speed mode (v cc = 3 v) f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off middle-speed mode f(x in ) = 8 mhz f(x cin ) = stopped output transistors off middle-speed mode f(x in ) = 8 mhz (in wit state) f(x cin ) = stopped output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz test conditions 13 i cc ta = 25 c ta = 85 c 6.8 ma all oscillation stopped (in stp state) output transistors off 1.6 ma a a a a ma ma a a a 60 20 20 5.0 4.0 1.5 200 40 55 10.0 7.0 1.0 10 800 0.1
55 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) bit lsb tc( ) s k ? a a a resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current a-d port input current min. 50 typ. 40 35 150 0.5 max. 10 4 61 200 5.0 5.0 high-speed mode, middle-speed mode low-speed mode v ref = 5.0 v table 19 a-d converter characteristics (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = 20 to 85 c, f(x in ) = 8 mhz, f(x cin ) = 32 khz, unless otherwise noted) unit limits parameter t conv r ladder i vref i i(ad) test conditions symbol v ref on v ref off
56 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) timing requirements table 20 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted) reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 clock input set up time serial i/o1 clock input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 clock input set up time serial i/o2 clock input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (r x d-s clk1 ) t h (s clk1 -r x d) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 -s clk2 ) t h (s clk2 -s in2 ) limits x in cycles ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 20 125 50 50 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 typ. max. symbol unit note : when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart). table 21 timing requirements (2) (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted) reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 clock input set up time serial i/o1 clock input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 clock input set up time serial i/o2 clock input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (r x d-s clk1 ) t h (s clk1 -r x d) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 -s clk2 ) t h (s clk2 -s in2 ) limits x in cycles ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 20 250 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 typ. max. symbol unit note : when f(x in ) = 4 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart).
57 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) table 22 switching characteristics 1 (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time (note 2) serial i/o2 output valid time (note 2) serial i/o2 clock output falling time cmos output rising time (note 3) cmos output falling time (note 3) t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 -t x d) t v (s clk1 -t x d) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 -s out2 ) t v (s clk2 -s out2 ) t f (s clk2 ) t r (cmos) t f (cmos) limits ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. t c (s clk1 )/2 30 t c (s clk1 )/2 30 30 t c (s clk2 )/2 160 t c (s clk2 )/2 160 0 typ. 10 10 max. 140 30 30 200 30 30 30 symbol unit notes 1: for t wh (s clk1 ), t wl (s clk1 ), when the p2 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2: when the p0 1 /s out2 and p0 2 /s clk2 p-channel output disable bit of the serial i/o2 control register (bit 7 of address 0015 16 ) is 0 . 3: the x out pin is excluded. table 23 switching characteristics 2 (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = 20 to 85 c, unless otherwise noted) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time (note 2) serial i/o2 output valid time (note 2) serial i/o2 clock output falling time cmos output rising time (note 3) cmos output falling time (note 3) t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 -t x d) t v (s clk1 -t x d) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 -s out2 ) t v (s clk2 -s out2 ) t f (s clk2 ) t r (cmos) t f (cmos) limits ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. t c (s clk1 )/2 50 t c (s clk1 )/2 50 30 t c (s clk2 )/2 240 t c (s clk2 )/2 240 0 typ. 20 20 symbol unit notes 1: for t wh (s clk1 ), t wl (s clk1 ), when the p2 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2: when the p0 1 /s out2 and p0 2 /s clk2 p-channel output disable bit of the serial i/o2 control register (bit 7 of address 0015 16 ) is 0 . 3: the x out pin is excluded. max. 350 50 50 400 50 50 50 test conditions fig. 59 test conditions fig. 59
58 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) symbol parameter unit multi-master i 2 c-bus bus line characteristics table 24 multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition hold time for scl clock = 0 rising time of both scl and sda signals data hold time hold time for scl clock = 1 falling time of both scl and sda signals data setup time setup time for repeated start condition setup time for stop condition t buf t hd;sta t low t r t hd;dat t high t f t su;dat t su;sta t su;sto min. max. min. max. s s s ns s s ns ns s s standard clock mode high-speed clock mode note: c b = total capacitance of 1 bus line fig. 58 timing diagram of multi-master i 2 c-bus 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 300 0.9 300 t buf t hd:sta t hd:dat t low t r t f t high t su:dat t su:sta t hd:sta t su:sto scl p s sr p sda s : start condition sr : restart condition p : stop condition
59 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 59 circuit for measuring output switching characteris- tics (1) measurement output pin 100pf cmos output
60 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) fig. 60 timing diagram t c(cntr) 0.2v cc t wl(int) 0.8v cc t wh(int) 0.2v cc 0.8v cc t w(reset) reset 0.2v cc t wl(cntr) 0.8v cc t wh(cntr) 0.2v cc 0.2v cc 0.8v cc 0.8v cc 0.2v cc t wl(x in ) 0.8v cc t wh(x in ) t c(x in ) x in t f t r t d(s clk1 -t x d), t d(s clk2 -s out2 ) t v(s clk1 -t x d), t v(s clk2 -s out2 ) t c(s clk1 ), t c(s clk2 ) t wl(s clk1 ), t wl(s clk2 ) t wh(s clk1 ), t wh(s clk2 ) t h(s clk1 - r x d), t h(s clk2 - s in2 ) t su(r x d - s clk1 ), t su(s in2 - s clk2 ) t x d s out2 r x d s in2 s clk1 s clk2 int 0 to int 3 cntr 0 cntr 1
single-chip 8-bit cmos microcomputer mitsubishi microcomputers 7516 group (spec. h) ? 2002 mitsubishi electric corp. new publication, effective oct. 2002. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents info rmation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these ma terials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
revision history 7516 group (spec. h) data sheet rev. date description page summary (1/1) 1.0 10/21/02 first edition

▲Up To Search▲

Price & Availability of M37516E6HKP

	To Download M37516E6HKP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .