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1 revision 1.1 fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89480/mb89480l series mb89485/485l/p485/p485l/pv480 description the mb89480 series has been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit, single-chip microcontrollers. in addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as 21-bit time-base timer, watch prescaler, pwc timer, pwm timer, 8/16-bit timer/counter, 6-bit ppg, lcd controller/driver, external interrupt 1 (edge), external interrupt 2 (level), 10-bit a/d converter, uart/sio, buzzer, watchdog timer reset. the mb89480 series is designed suitable for lcd remote controller as well as in a wide range of applications for consumer product. *: f 2 mc stands for fujitsu flexible microcontroller. features ? package used qfp package and sh-dip package for mb89p485/p485l, mb89485/485l mqfp package for mb89pv480 high-speed operating capability at low voltage minimum execution time: 0.32 s/12.5mhz (continued) package (mqp-64c-p01) 64-pin ceramic mqfp (fpt-64p-m09) 64-pin plastic qfp (mqp-64c-p01) (fpt-64p-m09) (dip-64p-m01) (dip-64p-m01) 64-pin plastic sh-dip
2 mb89480/480l series (continued) f 2 mc-8l family cpu core six timers pwc timer (also usable as a interval timer) pwm timer 8/16-bit timer/counter x 2 21-bit timebase timer watch prescaler programmable pulse generator 6-bit ppg with program-selectable pulse width and period external interrupts edge detection (selectable edge) : 4 channels low-level interrupt (wake-up function) : 8 channels a/d converter (4 channels) 10-bit successive approximation type uart/sio synchronous/asynchronous data transfer capable lcd controller/driver max. 31 segments output x 4 commons booster for lcd driving (selected by mask option) buzzer 7 frequency types are selectable by software low-power consumption modes stop mode (oscillation stops to minimize the current consumption.) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.) watch mode (everything except the watch prescaler stops to reduce the power comsumption to an extremely low level.) subclock mode watch dog timer reset i/o ports: max. 42 channels product lineup mb89485l mb89485 mb89p485l mb89p485 mb89pv480 classification mass production products (mask rom product) otp piggy-back rom size 16k x 8-bit (internal rom) 16k x 8-bit (internal prom with read protection * 2 ) 32k x 8-bit (external rom)* 1 ram size 512 x 8 bits 1k 8 bits *1 : use mbm27c256a as the external rom. *2 : read protection feature is selected by part number, detail please refer to mask options. multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. instruction set optimized for controllers part number parameter
3 mb89480/480l series mb89485l mb89485 mb89p485l mb89p485 mb89pv480 cpu functions number of instructions: : 136 instruction bit length: : 8 bits instruction length: : 1 to 3 bytes data bit length: : 1, 8, 16 bits minimum execution time: : 0.32 s/12.5 mhz minimum interrupt processing time: : 2.88 s/12.5 mhz ports i/o ports (cmos) : 11 pins n-channel open drain i/o ports : 28 pins output ports (n-channel open drain) : 2 pins input port : 1 pin total : 42 pins 21-bit time-based timer interrupt period (0.66ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 mhz watchdog timer reset period (167.8 ms to 335.5 ms) at 12.5 mhz pulse width count timer 2 channels 8-bit one-shot timer operation (supports underflow output, operating clock period: 1, 4, 32 tinst, external) 8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst, external) 8-bit pulse width measurement operation (supports continuous measurement, h width, l width, rising edge to rising edge, falling edge to falling edge measurement and both edge measurement) pwm timer 8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst, external) 8-bit resolution pwm operation 6- bit programmable pulse generator can generate square pulse with programmable period. 8/16-bit timer/ counter 11,12 can be operated either as a 2-channel 8-bit timer/counter (timer 11 and timer 12, each with its own independent operating clock cycle), or as one 16-bit timer/counter in timer 11 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable 8/16-bit timer/ counter 21,22 can be operated either as a 2-channel 8-bit timer/counter (timer 21 and timer 22, each with its own independent operating clock cycle), or as one 16-bit timer/counter in timer 21 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable external interrupt 4 independent channels (selectable edge, interrupt vector, request flag) 8 channels (low level interrupt) a/d converter 10-bit resolution 4 channels a/d conversion function (conversion time: 60 tinst ) supports repeated activation by internal clock. lcd controller/driver common output: 4 (max.) segment output: 31 (max.) (selected resistor ladder) 26 (max.) (selected booster) bias power supply pins: 4 lcd display ram size: 31 4 bits dividing resistor/booster: selected by mask option uart/sio synchronous/asynchronous data transfer capable (max. baud rate: 97.656 kbps at 12.5 mhz) (7 and 8 bits with parity bit ; 8 and 9 bits without parity bit) buzzer output 7 frequency types are selectable by software. part number parameter
4 mb89480/480l series note: 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock. package and corresponding products o : availabe x : not available differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: the stack area, etc., is set at the upper limit of the ram. 2. current consumption for the mb89pv480, add the current consumed by the eprom mounted in the piggy-back socket. when operating at low speed, the current consumed by the one-time prom product is greater than that for the mask rom product. however, the current consumption are roughly the same in sleep or stop mode. for more information, see ? electrical characteristics. ? 3. oscillation stabilization time after power-on reset for mb89pv480,mb89p485l and mb89485l, there is no power-on stabilization time after power-on reset. for mb89p485, there is power-on stabilization time after power-on reset. for mb89485, the power-on stabilization time can be selected. for more information, refer to ? mask option ? . mb89485l mb89485 mb89p485l mb89p485 mb89pv480 standby mode sleep mode, stop mode, watch mode, subclock mode. process cmos operating voltage 2.2v ~ 3.6v 2.2v ~ 5.5v 2.7v ~ 3.6v 3.5v ~ 5.5v 2.7v ~ 5.5v device package mb89485/485l mb89p485/p485l mb89pv480 dip-64p-m01 o o x fpt-64p-m09 oox mqp-64c-p01 xxo part number parameter
5 mb89480/480l series pin assignment com0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 p40/seg8 p41/seg9 p42/seg10 p43/seg11 p44/seg12 p45/seg13 p46/seg14 p47/seg15 p50/seg16 p51/seg17 p52/seg18 p53/seg19 p54/seg20 p55/seg21 p56/seg22 p57 p10/seg23/int10 p11/seg24/int11 p12/seg25/int12 p13/seg26/int13 x0a x1a c * 2 vss vcc com1 p30/com2 p31/com3 v3 p27/v2/ec1 p26/v1/to1 v0/seg0 p25/c0/ec2 * 1 p24/c1/to2 * 1 p23/si p22/so p21/sck p20/pwm p00/int20 p01/int21 p02/int22 p03/int23 * 1 p04/int24 * 1 p05/int25 /pwc p06/int26 /ppg p07/int27 /buz avss avcc p17/seg30/an3 * 1 p16/seg29/an2 * 1 p15/seg28/an1 * 1 p14/seg27/an0 * 1 rst mode x1 x0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 (dip-64p-m01) *1: if booster is selected, ec2 and to2 will be redirected to p03/int23 and p04/int24 respectively. segment output of p17/seg30/an3 - p14/seg27/an0 will be disabled. *2: for product other than mb89p485, pin 31 is nc pin. (top view)
6 mb89480/480l series (fpt-64p-m09) *1: if booster is selected, ec2 and to2 will be redirected to p03/int23 and p04/int24 respectively. segment output of p17/seg30/an3 - p14/seg27/an0 will be disabled. *2: for product other than mb89p485, pin 23 is nc pin. p40/seg8 p41/seg9 p42/seg10 p43/seg11 p44/seg12 p45/seg13 p46/seg14 p47/seg15 p50/seg16 p51/seg17 p52/seg18 p53/seg19 p54/seg20 p55/seg21 p56/seg22 p57 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p10/seg23/int10 p11/seg24/int11 p12/seg25/int12 p13/seg26/int13 x0a x1a * 2 c vss x0 x1 mode rst * 1 p14/seg27/an0 * 1 p15/seg28/an1 * 1 p16/seg29/an2 * 1 p17/seg30/an3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p25/c0/ec2 * 1 p24/c1/to2 * 1 p23/si p22/so p21/sck p20/pwm p00/int20 p01/int21 p02/int22 p03/int23 * 1 p04/int24 * 1 p05/int25 /pwc p06/int26 /ppg p07/int27 /buz avss avcc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg7 seg6 seg5 seg4 seg3 seg2 seg1 com0 vcc com1 p30/com2 p31/com3 v3 p27/v2/ec1 p26/v1/to1 v0/seg0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (top view)
7 mb89480/480l series seg7 p40/seg8 p41/seg9 p42/seg10 p43/seg11 p44/seg12 p45/seg13 p46/seg14 p47/seg15 p50/seg16 p51/seg17 p52/seg18 p53/seg19 p54/seg20 p55/seg21 p56/seg22 p57 p10/seg23/int10 p11/seg24/int11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg6 seg5 seg4 seg3 seg2 seg1 com0 vcc com1 p30/com2 p31/com3 v3 p27/v2/ec1 64 63 62 61 60 59 58 57 56 55 54 53 52 p12/seg25/int12 p13/seg26/int13 x0a x1a *2 c vss x0 x1 mode rst *1 p14/seg27/an0 *1 p15/seg28/an1 *1 p16/seg29/an2 20 21 22 23 24 25 26 27 28 29 30 31 32 85 86 87 88 89 90 91 92 93 77 76 75 74 73 72 71 70 69 94 95 96 65 66 67 68 84 83 82 81 80 79 78 (top view) (mqp-64c-p01) *1: if booster is selected, ec2 and to2 will be redirected to p03/int23 and p04/int24 respectively. segment output of p17/seg30/an3 - p14/seg27/an0 will be disabled. *2: pin 24 is nc pin. pin assignment on package top n.c.: as connected internally, do not use. pin no. pin symbol pin no. pin symbol pin no. pin symbo l pin no. pin symbol 65 n.c. 73 a2 81 n.c. 89 oe 66 v pp 74 a1 82 o4 90 n.c. 67 a12 75 a0 83 o5 91 a11 68 a7 76 n.c. 84 o6 92 a9 69 a6 77 o1 85 o7 93 a8 70 a5 78 o2 86 o8 94 a13 71 a4 79 o3 87 ce 95 a14 72 a3 80 v ss 88 a10 96 v cc p26/v1/to1 v0/seg0 p25/c0/ec2 * 1 p24/c1/to2 * 1 p23/si p22/so p21/sck p20/pwm p00/int20 p01/int21 p02/int22 p03/int23 * 1 p04/int24 * 1 p05/int25 /pwc p06/int26 /ppg p07/int27 /buz avss avcc p17/seg30/an3 * 1
8 mb89480/480l series pin description (continued) pin number pin name i/o circuit type function sh-dip *1 mqfp *2 qfp *3 33 26 25 x0 a connection pins for a crystal or other oscillator. an external clock can be connected to x0. in this case, leave x1 open. 34 27 26 x1 29 22 21 x0a a connection pins for a crystal or other oscillator. an external clock can be connected to x0a. in this case, leave x1a open. 30 23 22 x1a 35 28 27 mode b input pins for setting the memory access mode. connect directly to v ss . 36 29 28 rst c reset i/o pin. the pin is a n-ch open-drain type with pull- up resistor and a hysteresis input. the pin outputs a ? l ? level when an internal reset request is present. inputting an ? l ? level initializes internal circuits. 50 ~ 48 43 ~ 41 42 ~ 40 p00/int20 ~ p02/int22 d general-purpose cmos i/o port. a hysteresis input. the pin is shared with external interrupt 2 input. 47 40 39 p03/int23 d general-purpose cmos i/o port. a hysteresis input. the pin is shared with external interrupt 2 input, and shared with 8/16-bit timer/counter 21, 22 input when booster is selected. 46 39 38 p04/int24 d general-purpose cmos i/o port. a hysteresis input. the pin is shared with external interrupt 2 input, and shared with 8/16-bit timer/counter 21, 22 output when booster is selected. 45 38 37 p05/int25 / pwc d general-purpose cmos i/o port. a hysteresis input. the pin is shared with external interrupt 2 input, and pwc input. 44 37 36 p06/int26 / ppg d general-purpose cmos i/o port. a hysteresis input. the pin is shared with external interrupt 2 input, and 6-bit ppg output. 43 36 35 p07/int27 / buz d general-purpose cmos i/o port. a hysteresis input. the pin is shared with external interrupt 2 input and buzzer output. 25 ~ 28 18 ~ 21 17 ~ 20 p10/seg23/ int10 ~ p13/seg26/ int13 f / k general-purpose n-ch open-drain i/o port. a hysteresis input. the pin is shared with external interrupt 1 input and lcd segment output. 37 ~ 40 30 ~ 33 29 ~ 32 p14/seg27/ an0 ~ p17/seg30/ an3 g / k general-purpose n-ch open-drain i/o port. an analog input. the pin is shared with a/d converter input and lcd segment output. lcd segment output will be disabled when booster is selected. *1: dip-64p-m01 *2: mqp-64c-p01 *3: fpt-64p-m09
9 mb89480/480l series (continued) (continued) pin number pin name i/o circuit type function sh-dip *1 mqfp *2 qfp *3 51 44 43 p20/pwm e general-purpose cmos i/o port. the pin is shared with pwm output. 52 45 44 p21/sck e general-purpose cmos i/o port. the pin is shared with uart/sio clock i/o. 53 46 45 p22/so e general-purpose cmos i/o port. the pin is shared with uart/sio data output. 54 47 46 p23/si d general-purpose cmos i/o port. the pin is shared with uart/sio data input. 55 48 47 p24/c1/to2 h general-purpose cmos i/o port. the pin is shared with 8/16-bit timer 21,22 output (it is redirected to p04/int24 when booster is selected), and as a capacitor connecting pin when booster is selected. 56 49 48 p25/c0/ec2 f general-purpose cmos i/o port. a hysteresis input. the pin is shared with 8/16-bit timer 21,22 input (it is redirected to p03/int23 when booster is selected), and as a capacitor connecting pin when booster is selected. 58 51 50 p26/v1/to1 h general-purpose cmos i/o port. the pin is shared with 8/16-bit timer 11,12 output, and lcd power driving pin. 59 52 51 p27/v2/ec1 f general-purpose cmos i/o port. a hysteresis input. the pin is shared with 8/16-bit timer 11,12 input, and lcd power driving pin. 62 55 54 p30/com2 i / k general-purpose n-ch open-drain output port. the pin is shared with the lcd common output 61 54 53 p31/com3 i / k general-purpose n-ch open-drain output port. the pin is shared with the lcd common output 9 ~ 16 2 ~ 9 1 ~ 8 p40/seg8 ~ p47/seg15 h / k general-purpose n-ch open-drain i/o port. the pin is shared with lcd segment output. 17 ~ 23 10 ~ 16 9 ~ 15 p50/seg16 ~ p56/seg22 h / k general-purpose n-ch open-drain i/o port. the pin is shared with lcd segment output. 24 17 16 p57 j general-purpose cmos input port. *1: dip-64p-m01 *2: mqp-64c-p01 *3: fpt-64p-m09
10 mb89480/480l series (continued) *1: dip-64p-m01 *2: mqp-64c-p01 *3: fpt-64p-m09 *4: when mb89485/485l, mb89p485l or mb89pv480 is used, this pin will become a n.c. pin. when mb89p485 is used, connect this pin to an external 0.1uf capacitor to ground. pin number pin name i/o circuit type function sh-dip *1 mqfp *2 qfp *3 2 ~ 8 59 ~ 64, 1 58 ~ 64 seg1 ~ seg7 k lcd segment output only pins. 1, 63 58, 56 57, 55 com0 ~ com1 k lcd common output only pins. 60 53 52 v3 ? lcd driving power supply pin. 57 50 49 v0/seg0 ? / k lcd driving power supply pin when booster is selected. lcd segment output when booster is not selected. 31 24 23 c ? capacitor connection pin * 4 64 57 56 v cc ? power supply pin (+3v or +5v). 32 25 24 v ss ? power supply pin (gnd). 41 34 33 av cc ? a/d converter power supply pin. 42 35 34 av ss ? a/d converter power supply pin. use at the same voltage level as v ss .
11 mb89480/480l series ? external eprom socket (mb89pv480 only) *1: mqp-64c-p01 pin numbe pin name i/o function mqfp* 1 95 94 67 91 88 92 93 68 69 70 71 72 73 74 75 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins. 86 85 84 83 82 79 78 77 o8 o7 o6 o5 o4 o3 o2 o1 i data input pins. 65 76 81 90 n.c. ? internally connected pins. always leave open. 66 v pp o ? h ? level output pin. 80 v ss o power supply pin (gnd). 87 ce o chip enable pin for the eprom. outputs ? h ? in standby mode. 89 oe o output enable pin for the eprom. always outputs ? l ? . 96 v cc o power supply pin for the eprom.
12 mb89480/480l series i/o circuit type (continued) circuit class circuit remarks a main/sub clock circuit b hysteresis input the pull-down resistor approx. 50k ?. (not available in mb89p485/ p485l) c the pull-up resistance (p- channel) approx. 50 k ? . hysteresis input d cmos output cmos input hysteresis input selectable pull-up resistor approx. 50 k ? e cmos output cmos input selectable pull-up resistor approx. 50 k ? x1 (x1a) x0 (x0a) nch pch pch nch stop mode control signal pch nch r pch nch r port resources pull-up resistor register pch nch r port pull-up resistor register
13 mb89480/480l series (continued) f n-ch open-drain output cmos input hysteresis input g n-ch open-drain output cmos input analog input h n-ch open-drain output cmos input i n-ch open-drain output j cmos input k lcd segment output nch port resources nch port analog input nch port nch port n-ch p-ch p-ch n-ch
14 mb89480/480l series handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on ? 1. absolute maximum ratings ? in ? electrical characteristics ? is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc ) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = v cc and av ss = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode.
15 mb89480/480l series programming otprom in mb89p485/p485l with serial programmer 1. programming the otprom with serial programmer all otp products can be programmed with serial programmer 2. programming the otprom to program the otprom using eprom programmer af200 (manufacturer: yokogawa digital computer corp.). inquiry : yokogawa digital computer corp. : tel (81)-42-333-6224 to program the otprom using fujitsu mcu programmer mb91919-001. inquiry : fujitsu microelectronics asia pte ltd. : tel (65)-2810770 fax (65)-2810220 3. programming adaptor for otprom to program the otprom using fujitsu mcu programmer mb91919-001, use the programming adapter listed below. inquiry : fujitsu microelectronics asia pte ltd. : tel (65)-2810770 fax (65)-2810220 4. otprom content protection for product with otprom content protection feature (mb89p485-103, mb89p485-104), otprom content can be read using serial programmer if the otprom content protection mechanism is not activated. one predefined area of the otprom (fffc h ) is assigned to be used for preventing the read access of otprom content. if the protection code "00 h " is written in this address (fffc h ), the otprom content cannot be read by any serial programmer. note: the program written into the otprom cannot be verified once the otprom protection code is written ("00 h " in fffc h ). it is advised to write the otprom protection code at last. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. package compatible socker adaptor dip-64p-m01 mb91919-812 fpt-64p-m09 mb91919-813
16 mb89480/480l series programming otprom in mb89p485/p485l with general purpose eprom programmer 1. programming otprom with general purpose eprom programmer only products without protection feature (i.e. mb89p485/p485l-101 and mb89p485/p485l-102) can be pro- grammed with general purpose eprom programmer. product with protection feature (i.e. mb89p485/p485l- 103 and mb89p485/p485l-104) cannot be programmed with general purpose programmer. 2. rom writer adapters and recommended rom writers the following shows rom writer adapters and recommended rom writers. contact information minato electronics co., ltd.: phone 045-591-5611 3. memory space memory map of piggyback/evaluation device 4. writing data to the eprom (1) set the eprom writer for the cu50-otp (device code: t.b.d). (2) load the program data to the eprom writer. (3) write data using the eprom writer. package name applicable adapter model recommended writer maker and writer fujitsu microelectronics asia pte ltd. minato electronics co., ltd. model1890a dip-64p-m01 mb91919-604 under evaluation fpt-64p-m09 mb91919-605 under evaluation address normal operating mode corresponding addresses on the eprom programmer c000h 7fffh 0000h 0080h 0280h c000h ffffh i/o ram not available prom 16kbyte eprom 16kbyte
17 mb89480/480l series 4. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times.
18 mb89480/480l series programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c256a-20tvm 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel 81-3-3986-0403 3. memory space memory space in each mode is diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c256. (2) load program data into the eprom programmer at 0000 h to 7fff h . (3) program to 0000 h to 7fff h with the eprom programmer. package adapter socket part number lcc-32 (rectangle) rom-32lc-28dp-s address normal operating mode corresponding addresses on the eprom programmer 0000h 7fffh 0000h 0080h 0480h 8000h ffffh i/o ram not available prom 32kb eprom 32kb
19 mb89480/480l series block diagram main clock clock controller sub-clock ram (512 bytes / 1k bytes) f 2 mc-8l cpu rom (16k bytes / 32k bytes) other pins vcc, vss, mode, c * 2 internal data bus 21-bit timebase uart/sio port 0 port 1 x0 x1 p07/int27 /buz p21/sck p22/so p23/si timer x0a x1a port 3 n-ch open-drain output port 2 buzzer output 4 lcd controller/driver 32 4-bit display ram (16 bytes) 8-bit pwm timer port 4 and port 5 * 4 n-ch open-drain i/o port p10/seg23/int10 to p13/seg26/int13 seg1 t0 seg7 7 com0 to com1 2 v3 v0/seg0 * 3 8 p30/com2 p31/com3 reset circuit (watchdog timer) rst external interrupt 2 (egde) 4 4 16 p56/seg22 to p54/seg20 oscillator oscillator watch prescaler 8/16-bit timer/counter 21,22 cmos i/o port * 4 port 2 * 4 8/16-bit timer/counter 11,12 booster 2 2 p20/pwm p24/c1/to2 * 1 p25/c0/ec2 * 1 p26/v1/to1 p27/v2/ec1 cmos i/o port external interrupt 2 (level) 8 8-bit p05/int25 /pwc pwc timer 6-bit ppg p06/int26 /ppg p04/int24 * 1 p02/int22 p03/int23 * 1 to p00/int20 10-bit a/d converter p14/seg27/an0 * 1 to p17/seg30/an3 * 1 avcc avss 4 *1: if booster is selected, ec2 and to2 will be redirected to p03/int23 and p04/int24 respectively. segment output of p14/seg27/an0 to p17/seg30/an3 will be disabled. *2: for product other than mb89p485, c pin is nc pin. *3: if booster is selected, it serves as v0. if booster is not selected, it serves as seg0. *4: p20 to p23 are cmos i/o ports. p24 to p27 are n-ch open-drain i/o ports. p57 is input-only port. n-ch open-drain i/o port p57 3 p53/seg19 to p50/seg16 4 p47/seg15 to p44/seg12 4 p43/seg11 to p40/seg8 4
20 mb89480/480l series cpu core 1. memory space the microcontrollers of the mb89480 series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89480 series is structured as illustrated below. memory space mb89p485/p485l general- purpose registers i/o ram rom 0000 h 0080 h 0100 h 0280 h ffff h 0200 h vacant mb89485/485l general- purpose registers i/o ram rom 0000 h 0080 h 0100 h 0280 h ffff h 0200 h vacant mb89pv480 general- purpose registers i/o ram 0000 h 0080 h 0100 h ffff h 0200 h 0480 h rom external (32k) 8000 h vacant c000 h c000 h ffc0 h ffc0 h ffc0 h vector table (reset, interrupt, vector call instruction)
21 mb89480/480l series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator. when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy vacancy vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr
22 mb89480/480l series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to 1. interrupt is prohibited when the flag is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-flag: set when an arithmetic operation results in 0. cleared otherwise. v-flag: set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. c-flag: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? 0 ? a15 ? 0 ? a14 ? 0 ? a13 ? 0 ? a12 ? 0 ? a11 ? 0 ? a10 ? 0 ? a9 ? 1 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
23 mb89480/480l series the following general-purpose registers are provided: general-purpose registers: an 8-bit resister for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers. up to a total of 32 banks can be used on the mb89480 series. the bank currently in use is indicated by the register bank pointer (rp). register bank configuration this address = 0100 h + 8 (rp) memory area 32 banks r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7
24 mb89480/480l series i/o map (continued) address register name register description read/write initial value 00 h pdr0 port 0 data register r/w xxxxxxxx b 01 h ddr0 port 0 data direction register w* 00000000 b 02 h pdr1 port 1 data register r/w xxxxxxxx b 03 h ddr1 port 1 data direction register w* 00000000 b 04 h pdr2 port 2 data register r/w 00000000 b 05 h (reserved) 06 h ddr2 port 2 data direction register r/w 00000000 b 07 h sycc system clock control register r/w x-1mm100 b 08 h stbc standby control register r/w 00010xxx b 09 h wdtc watchdog timer control register w* 0---xxxx b 0a h tbtc timebase timer control register r/w 00---000 b 0b h wpcr watch prescaler control register r/w 00--0000 b 0c h pdr3 port 3 data register r/w ------11 b 0d h (reserved) 0e h rsfr reset flag register r xxxx---- b 0f h (reserved) 10 h pdr4 port 4 data register r/w 11111111 b 11 h (reserved) 12 h pdr5 port 5 data register r/w x1111111 b 13 h (reserved) 14 h to 1f h (reserved) 20 h smc1 uart/sio mode control register 1 r/w 00000000 b 21 h smc2 uart/sio mode control register 2 r/w 00000000 b 22 h src uart/sio rate control register r/w xxxxxxxx b 23 h ssd uart/sio status/data register r 00001--- b 24 h sidr/sodr uart/sio data register r/w xxxxxxxx b 25 h eic1 external interrupt 1 control register 1 r/w 00000000 b 26 h eic2 external interrupt 1 control register 2 r/w 00000000 b 27 h eie2 external interrupt 2 enable register r/w 00000000 b 28 h eif2 external interrupt 2 flag register r/w -------0 b 29 h to 2b h (reserved) 2c h adc1 a/d control register 1 r/w -0000000 b 2d h adc2 a/d control register 2 r/w -0000001 b 2e h addh a/d data register (upper byte) r ------xx b 2f h addl a/d data register (lower byte) r xxxxxxxx b 30 h aden a/d input enable register r/w 1111---- b 31 h pcr1 pwc control register 1 r/w 0-0--000 b 32 h pcr2 pwc control register 2 r/w 00000000 b 33 h plbr pwc reload buffer register r/w xxxxxxxx b
25 mb89480/480l series (continued) * bit manipulation instruction cannot be used. read/write access symbols r/w : readable and writable r : read-only w : write-only initial value symbols 0: the initial value of this bit is ? 0 ? . 1: the initial value of this bit is ? 1 ? . x: the initial value of this bit is undefined. - : unused bit. m: the initial value of this bit is determined by mask option. address register name register description read/write initial value 34 h cntr pwm timer control register r/w 0-000000 b 35 h comr pwm timer compare register w* xxxxxxxx b 36 h t4cr timer 22 control register r/w 000000x0 b 37 h t3cr timer 21 control register r/w 000000x0 b 38 h t4dr timer 22 data register r/w xxxxxxxx b 39 h t3dr timer 21 data register r/w xxxxxxxx b 3a h t2cr timer 12 control register r/w 000000x0 b 3b h t1cr timer 11 control register r/w 000000x0 b 3c h t2dr timer 12 data register r/w xxxxxxxx b 3d h t1dr timer 11 data register r/w xxxxxxxx b 3e h ppgc1 ppg control register 1 r/w 00000000 b 3f h ppgc2 ppg control register 2 r/w 0-000000 b 40 h buzr buzzer control register r/w -----000 b 41 to 5d h (reserved) 5e h lcr1 lcd controller control register 1 r/w 00010000 b 5f h lcr2 lcd controller control register 2 r/w -0000000 b 60 to 6f h vram lcd data ram r/w xxxxxxxx b 70 h purc0 port 0 pull up resistor control register r/w 11111111 b 71 h (reserved) 72 h purc2 port 2 pull up resistor control register r/w ----1111 b 73 h to 76 h (reserved) 77 h (reserved) 78 h (reserved) 79 h (reserved) 7a h (reserved) 7b h ilr1 interrupt level setting register 1 w* 11111111 b 7c h ilr2 interrupt level setting register 2 w* 11111111 b 7d h ilr3 interrupt level setting register 3 w* 11111111 b 7e h ilr4 interrupt level setting register 4 w* 11111111 b 7f h (reserved)
26 mb89480/480l series electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) precautions: permanent device damage may occur if the above ? absolute maximum ratings ? are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc av cc v ss ? 0.3 v ss + 6.0 v mb89pv480, mb89p485, mb89485 av cc must not exceed v cc v cc av cc v ss ? 0.3 v ss + 4.0 v mb89p485l, mb89485l av cc must not exceed v cc lcd power supply voltage v0 to v3 v ss ? 0.3 v ss + 6.0 v input voltage v i v ss ? 0.3 v cc + 0.3 v p00 to p07, p10 to p17, p20 to p27, p40 to p47, p50 to p57 output voltage v o v ss ? 0.3 v cc + 0.3 v p00 to p07, p10 to p17, p20 to p27, p30 to p31, p40 to p47, p50 to p56 ? l ? level maximum output current i ol ? 15 ma ? l ? level average output current i olav ? 4ma average value (operating current operating rate) ? l ? level total maximum output current i ol ? 100 ma ? l ? level total average output current i olav ? 40 ma average value (operating current operating rate) ? h ? level maximum output current i oh ? ? 15 ma ? h ? level average output current i ohav ? ? 4ma average value (operating current operating rate) ? h ? level total maximum output current i oh ? ? 50 ma ? h ? level total average output current i ohav ? ? 20 ma average value (operating current operating rate) power consumption p d ? 300 mw operating temperature t a ? 40 +85 c storage temperature tstg ? 55 +150 c
27 mb89480/480l series 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values depend on the operating conditions and the analog assurance range. see figure 1,2 and ? 5. a/d converter electrical characteristics. ? figure 1 operating voltage vs. main clock operating frequency (mb89p485/485) parameter symbol value unit remarks min. max. power supply voltage v cc av cc 2.2* 5.5 v operation assurance range mb89485 3.5* 5.5 v operation assurance range mb89p485 2.7* 5.5 v operation assurance range mb89pv480 1.5 5.5 v retains the ram state in stop mode mb89485, mb89p485, mb89pv480 2.2* 3.6 v operation assurance range mb89485l, mb89p485l 1.5 3.6 v retains the ram state in stop mode lcd power supply voltage v0 to v3 vss vcc v operating temperature t a ? 40 +85 c 2.0 4.0 5.0 3.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 operating voltage (v) 4.0 2.0 1.0 0.4 1.33 0.8 0.66 0.57 0.50 0.44 main clock operating freq. (mhz) min execution time (inst. cycle) ( s) 3.5 2.7 11.0 12.0 12.5 0.36 0.33 0.32 analog accuracy assurance range : vcc = avcc =4.5v~5.5v 5.5 2.2 4.5 note : the shaded area is not assured for mb89p485
28 mb89480/480l series figure 2 operating voltage vs. main clock operating frequency (mb89p485l/485l) figure 3 operating voltage vs. main clock operating frequency (mb89pv480) figure 1,2 and 3 indicate the operating frequency of the external oscillator at an instruction cycle of 4/f ch . since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 2.0 3.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 operating voltage (v) 4.0 2.0 1.0 0.4 1.33 0.8 0.66 0.57 0.50 0.44 3.6 2.7 11.0 12.0 12.5 0.36 0.33 0.32 analog accuracy assurance range : vcc = avcc =2.7v~3.6v 2.2 min execution time (inst. cycle) ( s) main clock operating freq. (mhz) note : the shaded area is not assured for mb89p485l 4.0 5.0 3.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 operating voltage (v) 4.0 2.0 1.0 0.4 1.33 0.8 0.66 0.57 0.50 0.44 main clock operating freq. (mhz) min execution time (inst. cycle) ( s) 3.5 2.7 11.0 12.0 12.5 0.36 0.33 0.32 analog accuracy assurance range : vcc = avcc =4.5v~5.5v 5.5 4.5
29 mb89480/480l series 3. dc characteristics av cc = v cc = 5.0 v for mb89pv480, mb89p485, mb89485 av cc = v cc = 3.0 v for mb89p485l, mb89485l (av ss = v ss = 0.0 v, t a = ? 40 c to +85 c) (continued) parameter symbol pin condition value unit remarks min. typ. max. ? h ? level input voltage v ih p00 ~ p07, p10 ~ p17, p20 ~ p27, p40 ~ p47, p50 ~ p57 ? 0.7 v cc ? v cc + 0.3 v v ihs rst , mode, ec1, ec2, pwc, sck, si, int10 ~ int13, int20 ~ int27 ? 0.8 v cc ? v cc + 0.3 v ? l ? level input voltage v il p00 ~ p07, p10 ~ p17, p20 ~ p27, p40 ~ p47, p50 ~ p57 ? v ss ? 0.3 ? 0.3 v cc v v ils rst , mode, ec1, ec2, pwc, sck, si, int10 ~ int13, int20 ~ int27 ? v ss ? 0.3 ? 0.2 v cc v open-drain output pin application voltage v d p10 ~ p17, p24 ~ p27, p30 ~ p31, p40 ~ p47, p50 ~ p56 ? v ss ? 0.3 ? v cc + 0.3 v product without booster v3 product with booster ? h ? level output voltage v oh p00 ~ p07, p20 ~ p23 i oh = ? 2.0ma 4.0 ?? v mb89pv480 mb89p485 mb89485 2.2 ?? v mb89p485l mb89485l ? l ? level output voltage v ol p00 ~ p07, p10 ~ p17, p20 ~ p27, p30 ~ p31, p40 ~ p47, p50 ~ p56, rst i ol = 4.0 ma ?? 0.4 v input leakage current i li p00 ~ p07, p10 ~ p17, p20 ~ p27, p40 ~ p47, p50 ~ p57 0.45 v < v i < v cc -5 ? + 5 a without pull-up resister open-drain output leakage current i lod p10 ~ p17, p24 ~ p27, p30 ~ p31, p40 ~ p47, p50 ~ p56 0.45 v < v i < v cc -5 ? + 5 a
30 mb89480/480l series (continued) (continued) parameter symbol pin condition value unit remarks min. typ. max. pull-down resistance r down mode v i = v cc 25 50 100 k ? except mb89p485, mb89p485l pull-up resistance r pull p00 ~ p07, p20 ~ p23, rst v i = 0.0 v 25 50 100 k ? when pull-up resistor is selected (except rst ) common output impedance r vcom com0 to com3 v1 to v3 = +3.0 v ?? 2.5 k ? mb89p485l, mb89485l v1 to v3 = +5.0 v mb89pv480, mb89p485, mb89485 segment output impedance r vseg seg0 to seg30 v1 to v3 = +3.0 v ?? 15 k ? mb89p485l, mb89485l v1 to v3 = +5.0 v mb89pv480, mb89p485, mb89485 lcd divided resistance r lcd ? between v cc and v ss 300 500 750 k ? lcd controller/ driver leakage current i lcdl v0 to v3, com0 to com3, seg0 to seg30 ??? 1 a booster for lcd driving output voltage v v3 v3 v1 = 1.5v 4.3 4.5 4.7 v products with booster only v v2 v2 v1 = 1.5v 2.9 3.0 3.1 v reference input voltage for lcd driving v v1 v1 i in = 0 a1.41.51.7 v reference voltage input impedance r rin v1 ? 8.5 9.8 11 k ? input capacitance c in other than v cc ,v ss ,av cc ,av ss f=1mhz ? 10 ? pf
31 mb89480/480l series (continued) parameter symbol pin condition value unit remarks min. typ. max. power supply current i cc1 v cc f ch = 12.5mhz t inst = 0.32 s main clock run mode ? 813ma i cc2 f ch = 12.5mhz t inst = 5.12 s main clock run mode ? 0.7 3 ma i ccs1 f ch = 12.5mhz t inst = 0.32 s main clock sleep mode ? 2.5 5 ma i ccs2 f ch = 12.5mhz t inst = 5.12 s main clock sleep mode ? 0.4 2 ma i ccl f cl = 32.768khz subclock mode ? 50 85 a except mb89p485 ? 54 91 a mb89p485 i ccls f cl = 32.768khz subclock sleep mode ? 15 30 a except mb89p485 ? 19 36 a mb89p485 i cct f cl = 32.768khz watch mode main clock stop mode ? 1.6 15 a except mb89p485 ? 5.6 21 a mb89p485 i cch ta=+25 0 c subclock stop mode ? 310 a i a av cc ta=+25 0 c ? 46ma a/d converting i ah ? 15 a a/d stop
32 mb89480/480l series 4. ac characteristics (1) reset timing v cc = 5.0 v for mb89pv480, mb89p485, mb89485 v cc = 3.0 v for mb89p485l, mb89485l (av ss = v ss = 0.0 v, t a = ? 40 c to +85 c) note: t hcyl is the oscillation cycle (1/f c ) to input to the x0 pin. the mcu operation is not guaranteed when the "l" pulse width is shorter than t zlzh . (2) power-on reset (av ss = v ss = 0.0 v, t a = ? 40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. rapid changes in power supply voltage may cause a power-on reset. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst ? l ? pulse width t zlzh ? 48 t hcyl ? ns parameter symbol condition value unit remarks min. max. power supply rising time t r ? ? 50 ms power supply cut-off time t off 1 ? ms due to repeated operations t zlzh 0.2 v cc 0.2 v cc rst 0.2 v 0.2 v 0.2 v t r v cc t off vth vth = 3.5 v for mb89pv480, mb89p485 and mb89485 vth = 1.8 v for mb89p485l and mb89485l
33 mb89480/480l series (3) clock timing (av ss = v ss = 0.0 v, t a = ? 40 c to +85 c) parameter symbol pin value unit remarks min. typ. max. clock frequency f ch x0, x1 1 ? 12.5 mhz f cl x0a, x1a ? 32.768 ? khz clock cycle time t hcyl x0, x1 80 ? 1000 ns t lcyl x0a, x1a ? 30.5 ? s input clock pulse width p wh p wl x0 20 ?? ns external clock p whl p wll x0a ? 15.2 ? s input clock rising/falling time t cr t cf x0, x0a ?? 10 ns 0.2 v cc 0.8 v cc x0 0.2 v cc t cr p wh t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic reasonator is used when an external clock is used open t hcyl p wl f ch c1 c2 f ch x0 and x1 timing and conditions main clock conditions
34 mb89480/480l series (4) instruction cycle parameter symbol value unit remarks instruction cycle (minimum execution time) t inst 4/f ch , 8/f ch , 16/f ch , 64/f ch s (4/f ch )t inst = 0.32 s when operating at f ch = 12.5 mhz 2/f cl s t inst = 61.036 s when operating at f cl = 32.768 khz x0a x1a c 0 c 1 rd open when a crystal or ceramic oscillator is used when subclock is not used x0a x1a f cl 0.8 v cc t lcyl 0.2 v cc p whl p wll t cf t cr x0a open when an external clock is used f cl x0a x1a subclock timing and conditions subclock conditions
35 mb89480/480l series (5) serial i/o timing v cc = 5.0 v for mb89pv480, mb89p485, mb89485 ,v cc = 3.0 v for mb89p485l, mb89485l (av ss = v ss = 0.0 v, t a = ? 40 c to +85 c) * : for information on t inst , see ? (4) instruction cycle. ? parameter symbol pin condition value unit min. max. serial clock cycle time t scyc sck internal shift clock mode 2 t inst * ? s sck so time t slov sck, so ? 200 200 ns valid si sck t ivsh si, sck 1/2 t inst * ? ns sck valid si hold time t shix sck, si 1/2 t inst * ? ns serial clock ? h ? pulse width t shsl sck external shift clock mode 1 t inst * ? s serial clock ? l ? pulse width t slsh 1 t inst * ? s sck so time t slov sck, so 0 200 ns valid si sck t ivsh si, sck 1/2 t inst * ? ns sck valid si hold time t shix sck, si 1/2 t inst * ? ns 0.2 v cc 0.8 v cc t slsh 2.4 v 0.2 v cc 0.8 v cc 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc sck so si 0.2 v cc t shsl t shix t ivsh t slov external clock operation 0.8 v 2.4 v t scyc 2.4 v 0.2 v cc t shix 0.8 v 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck so si t slov internal clock operation
36 mb89480/480l series (6) peripheral input timing v cc = 5.0 v for mb89pv480, mb89p485, mb89485 v cc = 3.0 v for mb89p485l, mb89485l (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = ? 40 c to +85 c) * : for information on t inst, see ? (4) instruction cycle. ? parameter symbol pin value unit remarks min. max. peripheral input ? h ? pulse width 1 t ilih1 int10 ~ 13, int20 ~ int27 , ec1, ec2, pwc 2 t inst * ? s peripheral input ? l ? pulse width 1 t ihil1 2 t inst * ? s 0.2 v cc 0.8 v cc t ihil1 0.8 v cc int10 to 13, int20 to 27, ec1, ec2, pwc 0.2 v cc t ilih1
37 mb89480/480l series 5. a/d converter electrical characteristics (1) a/d converter electrical characteristics ( av cc = v cc = 4.5 v ~ 5.5 v for mb89pv480, mb89p485, mb89485, av cc = v cc = 2.7 v ~ 3.6 v for mb89p485l, mb89485l, av ss = v ss = 0.0 v, t a = ? 40 c to +85 c) * : for information on t inst , see "(4) instruction cycle" in "4. ac characteristics". (2) a/d converter glossary resolution analog changes that are identifiable with the a/d converter when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. linearity error (unit: lsb) the deviation of the straight line connecting the zero transition point ("00 0000 0000" ? "00 0000 0001") with the full-scale transition point ("11 1111 1111" ? "11 1111 1110") from actual conversion characteristics. differential linearity error (unit: lsb) the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value. total error (unit: lsb) the difference between theoretical and actual conversion values. parameter symbol pin value unit remarks min. typ. max. resolution ? ? ? 10 ? bit to t a l e r r o r ?? 3.0 lsb linearity error ?? 2.5 lsb differential linearity error ?? 1.9 lsb zero transition voltage v ot av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb lsb full-scale transition voltage v fst av cc ? 3.5 lsb av cc ? 1.5 lsb av cc + 0.5 lsb lsb a/d mode conversion time ??? 60 tinst* s analog port input current i ain an0 to an3 ?? 10 a analog input voltage v ain av ss ? av cc v
38 mb89480/480l series 0.5 lsb 1 lsb analog input av ss 1.5 lsb theoretical i/o characteristics 3ff 3fe 3fd 004 003 002 001 av cc theoretical value analog input av ss v nt actual conversion value total error 3ff 3fe 3fd 004 003 002 001 av cc {1 lsb n + v ot } v fst v ot actual conversion value total error = v nt ? {1 lsb n + 0.5 lsb} 1 lsb 1 lsb = v fst ? v ot 1022 digital output digital output (v) analog input av ss linearity error 3ff 3fe 3fd 004 003 002 001 av cc theoretical value analog input av ss v nt v (n + 1)t actual conversion value differential linearity error n + 1 n n ? 1 n ? 2 av cc v nt v ot (actual measurement) actual conversion value actual conversion value differential linearity error = 1 lsb v (n + 1)t ? v nt digital output digital output linearity error = v nt ? {1 lsb n + v ot } 1 lsb ? 1 {1 lsb n + v ot } actual conversion value v fst (actual measurement) theoretical value analog input av ss zero transition error 004 003 002 001 theoretical value analog input actual conversion value full-scale transition error av cc actual conversion value digital output digital output actual conversion value actual conversion value v ot (actual measurement) v fst (actual measurement) 3ff 3fe 3fd 3fc
39 mb89480/480l series (3) notes on using a/d converter input impedance of the analog input pins the a/d converter used for the mb89470 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for 16 instruction cycles after activation a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low . note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 f for the analog input pin. error the smaller the |avr - av ss |, the greater the error would become relatively. mb89485 mb89pv480 mb89485l mb89p485 mb89p485l r: analog input equivalent resistance 2.2 k ? 7.1 k ? 2.6 k ? 2.8 k ? c: analog input equivalent capacitance 45 pf 48.3 pf 28 pf 46 pf analog input pin sample hold circuit if the analog input impedance is too low, it is recommended to connect an external capacitor of approx. 0.1 f. comparator r c analog channel selector close for 16 instruction cycles after activating a/d conversion. analog input circuit model
40 mb89480/480l series instructions execution instructions can be divided into the following four groups: transfer arithmetic operation branch others table 1 lists symbols used for notation of instructions. (continued) table 1 instruction symbols symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
41 mb89480/480l series (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: number of instructions #: number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? ? ? indicates no change. dh is the 8 upper bits of operation description data. al and ah must become the contents of al and ah immediately before the instruction is executed. 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
42 mb89480/480l series notes: ? during byte transfer to a, t a is restricted to low bytes. ? operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) table 2 transfer instructions (48 instructions) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) (a) ( (ix) +off ) (a) (ext) (a) ( (ep) ) (a) (ri) (a) (a) d8 (a) (dir) (a) ( (ix) +off) (a) (ext) (a) ( (a) ) (a) ( (ep) ) (a) (ri) (dir) d8 ( (ix) +off ) d8 ( (ep) ) d8 (ri) d8 (dir) (ah),(dir + 1) (al) ( (ix) +off) (ah), ( (ix) +off + 1) (al) (ext) (ah), (ext + 1) (al) ( (ep) ) (ah),( (ep) + 1) (al) (ep) (a) (a) d16 (ah) (dir), (al) (dir + 1) (ah) ( (ix) +off), (al) ( (ix) +off + 1) (ah) (ext), (al) (ext + 1) (ah) ( (a) ), (al) ( (a) ) + 1) (ah) ( (ep) ), (al) ( (ep) + 1) (a) (ep) (ep) d16 (ix) (a) (a) (ix) (sp) (a) (a) (sp) ( (a) ) (t) ( (a) ) (th),( (a) + 1) (tl) (ix) d16 (a) (ps) (ps) (a) (sp) d16 (ah) ? (al) (dir): b 1 (dir): b 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) (pc) ? ? ? ? ? al al al al al al al ? ? ? ? ? ? ? ? ? al al al al al al ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? al al ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ah ah ah ah ah ah ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ah ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dh dh dh dh dh dh dh ? ? dh ? dh ? ? ? dh ? ? al ? ? ? dh dh dh dh dh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? ? + + ? ? + + ? ? + + ? ? + + ? ? + + ? ? + + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? ? + + ? ? + + ? ? + + ? ? + + ? ? + + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + + + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
43 mb89480/480l series (continued) table 3 arithmetic operation instructions (62 instructions) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) (a) + (ri) + c (a) (a) + d8 + c (a) (a) + (dir) + c (a) (a) + ( (ix) +off) + c (a) (a) + ( (ep) ) + c (a) (a) + (t) + c (al) (al) + (tl) + c (a) (a) ? (ri) ? c (a) (a) ? d8 ? c (a) (a) ? (dir) ? c (a) (a) ? ( (ix) +off) ? c (a) (a) ? ( (ep) ) ? c (a) (t) ? (a) ? c (al) (tl) ? (al) ? c (ri) (ri) + 1 (ep) (ep) + 1 (ix) (ix) + 1 (a) (a) + 1 (ri) (ri) ? 1 (ep) (ep) ? 1 (ix) (ix) ? 1 (a) (a) ? 1 (a) (al) (tl) (a) (t) / (al),mod (t) (a) (a) (t) (a) (a) (t) (a) (a) ? (t) (tl) ? (al) (t) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ep) ) (a) ? ( (ix) +off) (a) ? (ri) decimal adjust for addition decimal adjust for subtraction (a) (al) ? (tl) (a) (al) ? d8 (a) (al) ? (dir) (a) (al) ? ( (ep) ) (a) (al) ? ( (ix) +off) (a) (al) ? (ri) (a) (al) (tl) (a) (al) d8 (a) (al) (dir) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dh ? ? ? ? ? ? dh ? ? ? ? dh ? ? ? dh dh 00 dh dh dh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ? ? ? ? ? ? ? ? ? + + ? ? + + + ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? ? ? + + r ? + + r ? + + r ? + + + + + + + + + + ? + + + ? + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r ? + + r ? + + r ? + + r ? + + r ? + + r ? + + r ? + + r ? + + r ? 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c a c
44 mb89480/480l series (continued) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) (al) ( (ep) ) (a) (al) ( (ix) +off) (a) (al) (ri) (a) (al) (tl) (a) (al) d8 (a) (al) (dir) (a) (al) ( (ep) ) (a) (al) ( (ix) +off) (a) (al) (ri) (dir) ? d8 ( (ep) ) ? d8 ( (ix) + off) ? d8 (ri) ? d8 (sp) (sp) + 1 (sp) (sp) ? 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + r ? + + r ? + + r ? + + r ? + + r ? + + r ? + + r ? + + r ? + + r ? + + + + + + + + + + + + + + + + ? ? ? ? ? ? ? ? 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 table 4 branch instructions (17 instructions) mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc pc + rel if z = 0 then pc pc + rel if c = 1 then pc pc + rel if c = 0 then pc pc + rel if n = 1 then pc pc + rel if n = 0 then pc pc + rel if v ? n = 1 then pc pc + rel if v ? n = 0 then pc pc + rei if (dir: b) = 0 then pc pc + rel if (dir: b) = 1 then pc pc + rel (pc) (a) (pc) ext vector call subroutine call (pc) (a),(a) (pc) + 1 return from subrountine return form interrupt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r ? ? ? s ? ? ? ? ? ? ? ? 40 50 41 51 00 81 91 80 90
45 mb89480/480l series instruction map 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor @a,ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel h l
46 mb89480/480l series mask options no. part number mb89485 mb89485l mb89p485 mb89p485l mb89pv480 specifying procedure specify when ordering masking setting not possible setting not possible 1 booster selection (ksv) internal resistor ladder booster selectable 101: internal resistor ladder 102: booster 101: internal resistor ladder 102: booster 2 selection of otprom content protection feature no protection feature with protection feature -- 101/102: no protection 103/104: with protection -- 3 selection of oscillation stabilization time (osc) the initial value of the oscillation stabilization time for the main clock can be set by selecting the values of the wtm1 and wtm0 bits on the right. selectable osc 1 : 2 14 /f ch 2 : 2 17 /f ch 3 : 2 18 /f ch fixed to oscillation stabilization time of 2 18 /f ch fixed to oscillation stabilization time of 2 18 /f ch 4 selection of power-on stabilization time nil 2 17 /f ch selectable fixed to nil 2 17 /f ch fixed to nil fixed to nil
47 mb89480/480l series ordering information part number package remarks mb89485pfm mb89p485pfm-101 mb89p485pfm-102 mb89p485pfm-103 mb89p485pfm-104 mb89485lpfm mb89p485lpfm-101 mb89p485lpfm-102 mb89p485lpfm-103 mb89p485lpfm-104 64-pin plastic qfp (fpt-64p-m09) 101: with internal resistor ladder, without con- tent protection 102: with booster, with- out content protec- tion 103: with internal resistor ladder, with content protection 104: with booster, with content protection mb89485p-sh mb89p485p-sh-101 mb89p485p-sh-102 mb89p485p-sh-103 mb89p485p-sh-104 mb89485lp-sh mb89p485lp-sh-101 mb89p485lp-sh-102 mb89p485lp-sh-103 MB89P485LP-SH-104 64-pin plastic sh-dip (dip-64p-m01) mb89pv480cf-101 mb89pv480cf-102 64-pin ceramic mqfp (mqp-64c-p01)
48 mb89480/480l series package dimensions c 2001 fujitsu limited d64001s-c-4-5 58.00 +0.22 ? 0.55 +.009 ? .022 2.283 17.000.25 (.669.010) 3.30 +0.20 ? 0.30 .130 ? .012 +.008 +.028 ? .008 .195 ? 0.20 +0.70 4.95 +.016 ? .008 .0543 ? 0.20 +0.40 1.378 1.778(.0700) 0.470.10 (.019.004) 1.00 +0.50 ? 0 .039 ? .0 +.020 +.020 ? .007 .028 ? 0.19 +0.50 0.70 19.05(.750) (.011.004) 0.270.10 0~15 index-2 index-1 m 0.25(.010) dimensions in mm (inches) 64-pin plastic sh-dip dip-64p-m01 64-pin plastic lqfp fpt-64p-m09 dimensions in mm (inches) c 2001 fujitsu limited f64018s-c-2-4 0.65(.026) 0.10(.004) 116 17 32 49 64 33 48 12.000.10(.472.004)sq 14.000.20(.551.008)sq index 0.320.05 (.013.002) m 0.13(.005) 0.1450.055 (.0057.0022) "a" .059 ? .004 +.008 ? 0.10 +0.20 1.50 0~8 0.25(.010) (mounting height) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) details of "a" part (stand off) 0.10(.004)
49 mb89480/480l series mqp-64c-p01 64-pin ceramic mqfp
mb89480/480l series memo
51 mb89480/480l series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: (044) 754-3763 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. complete information sufficient for construction purposes is not necessarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu assumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.

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